target/linux/generic/backport-5.15/746-v5.16-04-net-phy-at803x-better-describe-debug-regs.patch

   1 From 67999555ff42e91de7654488d9a7735bd9e84555 Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Sun, 10 Oct 2021 00:46:18 +0200
   4 Subject: net: phy: at803x: better describe debug regs
   5
   6 Give a name to known debug regs from Documentation instead of using
   7 unknown hex values.
   8
   9 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  10 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  11 Signed-off-by: David S. Miller <davem@davemloft.net>
  12 ---
  13  drivers/net/phy/at803x.c | 30 +++++++++++++++---------------
  14  1 file changed, 15 insertions(+), 15 deletions(-)
  15
  16 --- a/drivers/net/phy/at803x.c
  17 +++ b/drivers/net/phy/at803x.c
  18 @@ -86,12 +86,12 @@
  19  #define AT803X_PSSR                    0x11    /*PHY-Specific Status Register*/
  20  #define AT803X_PSSR_MR_AN_COMPLETE     0x0200
  21
  22 -#define AT803X_DEBUG_REG_0                     0x00
  23 +#define AT803X_DEBUG_ANALOG_TEST_CTRL          0x00
  24  #define QCA8327_DEBUG_MANU_CTRL_EN             BIT(2)
  25  #define QCA8337_DEBUG_MANU_CTRL_EN             GENMASK(3, 2)
  26  #define AT803X_DEBUG_RX_CLK_DLY_EN             BIT(15)
  27
  28 -#define AT803X_DEBUG_REG_5                     0x05
  29 +#define AT803X_DEBUG_SYSTEM_CTRL_MODE          0x05
  30  #define AT803X_DEBUG_TX_CLK_DLY_EN             BIT(8)
  31
  32  #define AT803X_DEBUG_REG_HIB_CTRL              0x0b
  33 @@ -100,7 +100,7 @@
  34
  35  #define AT803X_DEBUG_REG_3C                    0x3C
  36
  37 -#define AT803X_DEBUG_REG_3D                    0x3D
  38 +#define AT803X_DEBUG_REG_GREEN                 0x3D
  39  #define   AT803X_DEBUG_GATE_CLK_IN1000         BIT(6)
  40
  41  #define AT803X_DEBUG_REG_1F                    0x1F
  42 @@ -274,25 +274,25 @@ static int at803x_read_page(struct phy_d
  43
  44  static int at803x_enable_rx_delay(struct phy_device *phydev)
  45  {
  46 -       return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
  47 +       return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,
  48                                      AT803X_DEBUG_RX_CLK_DLY_EN);
  49  }
  50
  51  static int at803x_enable_tx_delay(struct phy_device *phydev)
  52  {
  53 -       return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
  54 +       return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,
  55                                      AT803X_DEBUG_TX_CLK_DLY_EN);
  56  }
  57
  58  static int at803x_disable_rx_delay(struct phy_device *phydev)
  59  {
  60 -       return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
  61 +       return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
  62                                      AT803X_DEBUG_RX_CLK_DLY_EN, 0);
  63  }
  64
  65  static int at803x_disable_tx_delay(struct phy_device *phydev)
  66  {
  67 -       return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
  68 +       return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
  69                                      AT803X_DEBUG_TX_CLK_DLY_EN, 0);
  70  }
  71
  72 @@ -1208,9 +1208,9 @@ static int qca83xx_config_init(struct ph
  73         switch (switch_revision) {
  74         case 1:
  75                 /* For 100M waveform */
  76 -               at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_0, 0x02ea);
  77 +               at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
  78                 /* Turn on Gigabit clock */
  79 -               at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x68a0);
  80 +               at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
  81                 break;
  82
  83         case 2:
  84 @@ -1218,8 +1218,8 @@ static int qca83xx_config_init(struct ph
  85                 fallthrough;
  86         case 4:
  87                 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
  88 -               at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x6860);
  89 -               at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_5, 0x2c46);
  90 +               at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
  91 +               at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
  92                 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
  93                 break;
  94         }
  95 @@ -1230,7 +1230,7 @@ static int qca83xx_config_init(struct ph
  96          */
  97         if (phydev->drv->phy_id == QCA8327_A_PHY_ID ||
  98             phydev->drv->phy_id == QCA8327_B_PHY_ID)
  99 -               at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
 100 +               at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
 101                                       QCA8327_DEBUG_MANU_CTRL_EN, 0);
 102
 103         /* Following original QCA sourcecode set port to prefer master */
 104 @@ -1248,12 +1248,12 @@ static void qca83xx_link_change_notify(s
 105         /* Set DAC Amplitude adjustment to +6% for 100m on link running */
 106         if (phydev->state == PHY_RUNNING) {
 107                 if (phydev->speed == SPEED_100)
 108 -                       at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
 109 +                       at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
 110                                               QCA8327_DEBUG_MANU_CTRL_EN,
 111                                               QCA8327_DEBUG_MANU_CTRL_EN);
 112         } else {
 113                 /* Reset DAC Amplitude adjustment */
 114 -               at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
 115 +               at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
 116                                       QCA8327_DEBUG_MANU_CTRL_EN, 0);
 117         }
 118  }
 119 @@ -1300,7 +1300,7 @@ static int qca83xx_suspend(struct phy_de
 120                 phy_modify(phydev, MII_BMCR, mask, 0);
 121         }
 122
 123 -       at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_3D,
 124 +       at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
 125                               AT803X_DEBUG_GATE_CLK_IN1000, 0);
 126
 127         at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,