generic: 5.15: copy config and patch from 5.10
[openwrt/staging/stintel.git] / target / linux / generic / backport-5.15 / 758-net-next-net-dsa-qca8k-add-additional-MIB-counter-and-.patch
1 From c126f118b330ccf0db0dda4a4bd6c729865a205f Mon Sep 17 00:00:00 2001
2 From: Ansuel Smith <ansuelsmth@gmail.com>
3 Date: Mon, 22 Nov 2021 16:23:45 +0100
4 Subject: net: dsa: qca8k: add additional MIB counter and make it dynamic
5
6 We are currently missing 2 additionals MIB counter present in QCA833x
7 switch.
8 QC832x switch have 39 MIB counter and QCA833X have 41 MIB counter.
9 Add the additional MIB counter and rework the MIB function to print the
10 correct supported counter from the match_data struct.
11
12 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
13 Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
14 Signed-off-by: David S. Miller <davem@davemloft.net>
15 ---
16 drivers/net/dsa/qca8k.c | 23 ++++++++++++++++++++---
17 drivers/net/dsa/qca8k.h | 4 ++++
18 2 files changed, 24 insertions(+), 3 deletions(-)
19
20 --- a/drivers/net/dsa/qca8k.c
21 +++ b/drivers/net/dsa/qca8k.c
22 @@ -70,6 +70,8 @@ static const struct qca8k_mib_desc ar832
23 MIB_DESC(1, 0x9c, "TxExcDefer"),
24 MIB_DESC(1, 0xa0, "TxDefer"),
25 MIB_DESC(1, 0xa4, "TxLateCol"),
26 + MIB_DESC(1, 0xa8, "RXUnicast"),
27 + MIB_DESC(1, 0xac, "TXUnicast"),
28 };
29
30 /* The 32bit switch registers are accessed indirectly. To achieve this we need
31 @@ -1605,12 +1607,16 @@ qca8k_phylink_mac_link_up(struct dsa_swi
32 static void
33 qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
34 {
35 + const struct qca8k_match_data *match_data;
36 + struct qca8k_priv *priv = ds->priv;
37 int i;
38
39 if (stringset != ETH_SS_STATS)
40 return;
41
42 - for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
43 + match_data = of_device_get_match_data(priv->dev);
44 +
45 + for (i = 0; i < match_data->mib_count; i++)
46 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
47 ETH_GSTRING_LEN);
48 }
49 @@ -1620,12 +1626,15 @@ qca8k_get_ethtool_stats(struct dsa_switc
50 uint64_t *data)
51 {
52 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
53 + const struct qca8k_match_data *match_data;
54 const struct qca8k_mib_desc *mib;
55 u32 reg, i, val;
56 u32 hi = 0;
57 int ret;
58
59 - for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
60 + match_data = of_device_get_match_data(priv->dev);
61 +
62 + for (i = 0; i < match_data->mib_count; i++) {
63 mib = &ar8327_mib[i];
64 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
65
66 @@ -1648,10 +1657,15 @@ qca8k_get_ethtool_stats(struct dsa_switc
67 static int
68 qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
69 {
70 + const struct qca8k_match_data *match_data;
71 + struct qca8k_priv *priv = ds->priv;
72 +
73 if (sset != ETH_SS_STATS)
74 return 0;
75
76 - return ARRAY_SIZE(ar8327_mib);
77 + match_data = of_device_get_match_data(priv->dev);
78 +
79 + return match_data->mib_count;
80 }
81
82 static int
83 @@ -2146,14 +2160,17 @@ static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
84 static const struct qca8k_match_data qca8327 = {
85 .id = QCA8K_ID_QCA8327,
86 .reduced_package = true,
87 + .mib_count = QCA8K_QCA832X_MIB_COUNT,
88 };
89
90 static const struct qca8k_match_data qca8328 = {
91 .id = QCA8K_ID_QCA8327,
92 + .mib_count = QCA8K_QCA832X_MIB_COUNT,
93 };
94
95 static const struct qca8k_match_data qca833x = {
96 .id = QCA8K_ID_QCA8337,
97 + .mib_count = QCA8K_QCA833X_MIB_COUNT,
98 };
99
100 static const struct of_device_id qca8k_of_match[] = {
101 --- a/drivers/net/dsa/qca8k.h
102 +++ b/drivers/net/dsa/qca8k.h
103 @@ -21,6 +21,9 @@
104 #define PHY_ID_QCA8337 0x004dd036
105 #define QCA8K_ID_QCA8337 0x13
106
107 +#define QCA8K_QCA832X_MIB_COUNT 39
108 +#define QCA8K_QCA833X_MIB_COUNT 41
109 +
110 #define QCA8K_BUSY_WAIT_TIMEOUT 2000
111
112 #define QCA8K_NUM_FDB_RECORDS 2048
113 @@ -279,6 +282,7 @@ struct ar8xxx_port_status {
114 struct qca8k_match_data {
115 u8 id;
116 bool reduced_package;
117 + u8 mib_count;
118 };
119
120 enum {