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116f6cf5d65dccd2bc73884229ce575747abd3f1
[openwrt/staging/stintel.git] / target / linux / generic / files / drivers / net / phy / mvsw61xx.c
1 /*
2 * Marvell 88E61xx switch driver
3 *
4 * Copyright (c) 2014 Claudio Leite <leitec@staticky.com>
5 * Copyright (c) 2014 Nikita Nazarenko <nnazarenko@radiofid.com>
6 *
7 * Based on code (c) 2008 Felix Fietkau <nbd@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License v2 as published by the
11 * Free Software Foundation
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/list.h>
18 #include <linux/mii.h>
19 #include <linux/phy.h>
20 #include <linux/of.h>
21 #include <linux/of_mdio.h>
22 #include <linux/delay.h>
23 #include <linux/switch.h>
24 #include <linux/device.h>
25 #include <linux/platform_device.h>
26
27 #include "mvsw61xx.h"
28
29 MODULE_DESCRIPTION("Marvell 88E61xx Switch driver");
30 MODULE_AUTHOR("Claudio Leite <leitec@staticky.com>");
31 MODULE_AUTHOR("Nikita Nazarenko <nnazarenko@radiofid.com>");
32 MODULE_LICENSE("GPL v2");
33 MODULE_ALIAS("platform:mvsw61xx");
34
35 /*
36 * Register access is done through direct or indirect addressing,
37 * depending on how the switch is physically connected.
38 *
39 * Direct addressing: all port and global registers directly
40 * accessible via an address/register pair
41 *
42 * Indirect addressing: switch is mapped at a single address,
43 * port and global registers accessible via a single command/data
44 * register pair
45 */
46
47 static int
48 mvsw61xx_wait_mask_raw(struct mii_bus *bus, int addr,
49 int reg, u16 mask, u16 val)
50 {
51 int i = 100;
52 u16 r;
53
54 do {
55 r = bus->read(bus, addr, reg);
56 if ((r & mask) == val)
57 return 0;
58 } while (--i > 0);
59
60 return -ETIMEDOUT;
61 }
62
63 static u16
64 r16(struct mii_bus *bus, bool indirect, int base_addr, int addr, int reg)
65 {
66 u16 ind_addr;
67
68 if (!indirect)
69 return bus->read(bus, addr, reg);
70
71 /* Indirect read: First, make sure switch is free */
72 mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD,
73 MV_INDIRECT_INPROGRESS, 0);
74
75 /* Load address and request read */
76 ind_addr = MV_INDIRECT_READ | (addr << MV_INDIRECT_ADDR_S) | reg;
77 bus->write(bus, base_addr, MV_INDIRECT_REG_CMD,
78 ind_addr);
79
80 /* Wait until it's ready */
81 mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD,
82 MV_INDIRECT_INPROGRESS, 0);
83
84 /* Read the requested data */
85 return bus->read(bus, base_addr, MV_INDIRECT_REG_DATA);
86 }
87
88 static void
89 w16(struct mii_bus *bus, bool indirect, int base_addr, int addr,
90 int reg, u16 val)
91 {
92 u16 ind_addr;
93
94 if (!indirect) {
95 bus->write(bus, addr, reg, val);
96 return;
97 }
98
99 /* Indirect write: First, make sure switch is free */
100 mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD,
101 MV_INDIRECT_INPROGRESS, 0);
102
103 /* Load the data to be written */
104 bus->write(bus, base_addr, MV_INDIRECT_REG_DATA, val);
105
106 /* Wait again for switch to be free */
107 mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD,
108 MV_INDIRECT_INPROGRESS, 0);
109
110 /* Load address, and issue write command */
111 ind_addr = MV_INDIRECT_WRITE | (addr << MV_INDIRECT_ADDR_S) | reg;
112 bus->write(bus, base_addr, MV_INDIRECT_REG_CMD,
113 ind_addr);
114 }
115
116 /* swconfig support */
117
118 static inline u16
119 sr16(struct switch_dev *dev, int addr, int reg)
120 {
121 struct mvsw61xx_state *state = get_state(dev);
122
123 return r16(state->bus, state->is_indirect, state->base_addr, addr, reg);
124 }
125
126 static inline void
127 sw16(struct switch_dev *dev, int addr, int reg, u16 val)
128 {
129 struct mvsw61xx_state *state = get_state(dev);
130
131 w16(state->bus, state->is_indirect, state->base_addr, addr, reg, val);
132 }
133
134 static int
135 mvsw61xx_wait_mask_s(struct switch_dev *dev, int addr,
136 int reg, u16 mask, u16 val)
137 {
138 int i = 100;
139 u16 r;
140
141 do {
142 r = sr16(dev, addr, reg) & mask;
143 if (r == val)
144 return 0;
145 } while (--i > 0);
146
147 return -ETIMEDOUT;
148 }
149
150 static int
151 mvsw61xx_get_port_mask(struct switch_dev *dev,
152 const struct switch_attr *attr, struct switch_val *val)
153 {
154 struct mvsw61xx_state *state = get_state(dev);
155 char *buf = state->buf;
156 int port, len, i;
157 u16 reg;
158
159 port = val->port_vlan;
160 reg = sr16(dev, MV_PORTREG(VLANMAP, port)) & MV_PORTS_MASK;
161
162 len = sprintf(buf, "0x%04x: ", reg);
163
164 for (i = 0; i < MV_PORTS; i++) {
165 if (reg & (1 << i))
166 len += sprintf(buf + len, "%d ", i);
167 else if (i == port)
168 len += sprintf(buf + len, "(%d) ", i);
169 }
170
171 val->value.s = buf;
172
173 return 0;
174 }
175
176 static int
177 mvsw61xx_get_port_qmode(struct switch_dev *dev,
178 const struct switch_attr *attr, struct switch_val *val)
179 {
180 struct mvsw61xx_state *state = get_state(dev);
181
182 val->value.i = state->ports[val->port_vlan].qmode;
183
184 return 0;
185 }
186
187 static int
188 mvsw61xx_set_port_qmode(struct switch_dev *dev,
189 const struct switch_attr *attr, struct switch_val *val)
190 {
191 struct mvsw61xx_state *state = get_state(dev);
192
193 state->ports[val->port_vlan].qmode = val->value.i;
194
195 return 0;
196 }
197
198 static int
199 mvsw61xx_get_pvid(struct switch_dev *dev, int port, int *val)
200 {
201 struct mvsw61xx_state *state = get_state(dev);
202
203 *val = state->ports[port].pvid;
204
205 return 0;
206 }
207
208 static int
209 mvsw61xx_set_pvid(struct switch_dev *dev, int port, int val)
210 {
211 struct mvsw61xx_state *state = get_state(dev);
212
213 if (val < 0 || val >= MV_VLANS)
214 return -EINVAL;
215
216 state->ports[port].pvid = (u16)val;
217
218 return 0;
219 }
220
221 static int
222 mvsw61xx_get_port_status(struct switch_dev *dev,
223 const struct switch_attr *attr, struct switch_val *val)
224 {
225 struct mvsw61xx_state *state = get_state(dev);
226 char *buf = state->buf;
227 u16 status, speed;
228 int len;
229
230 status = sr16(dev, MV_PORTREG(STATUS, val->port_vlan));
231 speed = (status & MV_PORT_STATUS_SPEED_MASK) >>
232 MV_PORT_STATUS_SPEED_SHIFT;
233
234 len = sprintf(buf, "link: ");
235 if (status & MV_PORT_STATUS_LINK) {
236 len += sprintf(buf + len, "up, speed: ");
237
238 switch (speed) {
239 case MV_PORT_STATUS_SPEED_10:
240 len += sprintf(buf + len, "10");
241 break;
242 case MV_PORT_STATUS_SPEED_100:
243 len += sprintf(buf + len, "100");
244 break;
245 case MV_PORT_STATUS_SPEED_1000:
246 len += sprintf(buf + len, "1000");
247 break;
248 }
249
250 len += sprintf(buf + len, " Mbps, duplex: ");
251
252 if (status & MV_PORT_STATUS_FDX)
253 len += sprintf(buf + len, "full");
254 else
255 len += sprintf(buf + len, "half");
256 } else {
257 len += sprintf(buf + len, "down");
258 }
259
260 val->value.s = buf;
261
262 return 0;
263 }
264
265 static int
266 mvsw61xx_get_port_speed(struct switch_dev *dev,
267 const struct switch_attr *attr, struct switch_val *val)
268 {
269 u16 status, speed;
270
271 status = sr16(dev, MV_PORTREG(STATUS, val->port_vlan));
272 speed = (status & MV_PORT_STATUS_SPEED_MASK) >>
273 MV_PORT_STATUS_SPEED_SHIFT;
274
275 val->value.i = 0;
276
277 if (status & MV_PORT_STATUS_LINK) {
278 switch (speed) {
279 case MV_PORT_STATUS_SPEED_10:
280 val->value.i = 10;
281 break;
282 case MV_PORT_STATUS_SPEED_100:
283 val->value.i = 100;
284 break;
285 case MV_PORT_STATUS_SPEED_1000:
286 val->value.i = 1000;
287 break;
288 }
289 }
290
291 return 0;
292 }
293
294 static int mvsw61xx_get_vlan_ports(struct switch_dev *dev,
295 struct switch_val *val)
296 {
297 struct mvsw61xx_state *state = get_state(dev);
298 int i, j, mode, vno;
299
300 vno = val->port_vlan;
301
302 if (vno <= 0 || vno >= dev->vlans)
303 return -EINVAL;
304
305 for (i = 0, j = 0; i < dev->ports; i++) {
306 if (state->vlans[vno].mask & (1 << i)) {
307 val->value.ports[j].id = i;
308
309 mode = (state->vlans[vno].port_mode >> (i * 4)) & 0xf;
310 if (mode == MV_VTUCTL_EGRESS_TAGGED)
311 val->value.ports[j].flags =
312 (1 << SWITCH_PORT_FLAG_TAGGED);
313 else
314 val->value.ports[j].flags = 0;
315
316 j++;
317 }
318 }
319
320 val->len = j;
321
322 return 0;
323 }
324
325 static int mvsw61xx_set_vlan_ports(struct switch_dev *dev,
326 struct switch_val *val)
327 {
328 struct mvsw61xx_state *state = get_state(dev);
329 int i, mode, pno, vno;
330
331 vno = val->port_vlan;
332
333 if (vno <= 0 || vno >= dev->vlans)
334 return -EINVAL;
335
336 state->vlans[vno].mask = 0;
337 state->vlans[vno].port_mode = 0;
338 state->vlans[vno].port_sstate = 0;
339
340 if(state->vlans[vno].vid == 0)
341 state->vlans[vno].vid = vno;
342
343 for (i = 0; i < val->len; i++) {
344 pno = val->value.ports[i].id;
345
346 state->vlans[vno].mask |= (1 << pno);
347 if (val->value.ports[i].flags &
348 (1 << SWITCH_PORT_FLAG_TAGGED))
349 mode = MV_VTUCTL_EGRESS_TAGGED;
350 else
351 mode = MV_VTUCTL_EGRESS_UNTAGGED;
352
353 state->vlans[vno].port_mode |= mode << (pno * 4);
354 state->vlans[vno].port_sstate |=
355 MV_STUCTL_STATE_FORWARDING << (pno * 4 + 2);
356 }
357
358 /*
359 * DISCARD is nonzero, so it must be explicitly
360 * set on ports not in the VLAN.
361 */
362 for (i = 0; i < dev->ports; i++)
363 if (!(state->vlans[vno].mask & (1 << i)))
364 state->vlans[vno].port_mode |=
365 MV_VTUCTL_DISCARD << (i * 4);
366
367 return 0;
368 }
369
370 static int mvsw61xx_get_vlan_port_based(struct switch_dev *dev,
371 const struct switch_attr *attr, struct switch_val *val)
372 {
373 struct mvsw61xx_state *state = get_state(dev);
374 int vno = val->port_vlan;
375
376 if (vno <= 0 || vno >= dev->vlans)
377 return -EINVAL;
378
379 if (state->vlans[vno].port_based)
380 val->value.i = 1;
381 else
382 val->value.i = 0;
383
384 return 0;
385 }
386
387 static int mvsw61xx_set_vlan_port_based(struct switch_dev *dev,
388 const struct switch_attr *attr, struct switch_val *val)
389 {
390 struct mvsw61xx_state *state = get_state(dev);
391 int vno = val->port_vlan;
392
393 if (vno <= 0 || vno >= dev->vlans)
394 return -EINVAL;
395
396 if (val->value.i == 1)
397 state->vlans[vno].port_based = true;
398 else
399 state->vlans[vno].port_based = false;
400
401 return 0;
402 }
403
404 static int mvsw61xx_get_vid(struct switch_dev *dev,
405 const struct switch_attr *attr, struct switch_val *val)
406 {
407 struct mvsw61xx_state *state = get_state(dev);
408 int vno = val->port_vlan;
409
410 if (vno <= 0 || vno >= dev->vlans)
411 return -EINVAL;
412
413 val->value.i = state->vlans[vno].vid;
414
415 return 0;
416 }
417
418 static int mvsw61xx_set_vid(struct switch_dev *dev,
419 const struct switch_attr *attr, struct switch_val *val)
420 {
421 struct mvsw61xx_state *state = get_state(dev);
422 int vno = val->port_vlan;
423
424 if (vno <= 0 || vno >= dev->vlans)
425 return -EINVAL;
426
427 state->vlans[vno].vid = val->value.i;
428
429 return 0;
430 }
431
432 static int mvsw61xx_get_enable_vlan(struct switch_dev *dev,
433 const struct switch_attr *attr, struct switch_val *val)
434 {
435 struct mvsw61xx_state *state = get_state(dev);
436
437 val->value.i = state->vlan_enabled;
438
439 return 0;
440 }
441
442 static int mvsw61xx_set_enable_vlan(struct switch_dev *dev,
443 const struct switch_attr *attr, struct switch_val *val)
444 {
445 struct mvsw61xx_state *state = get_state(dev);
446
447 state->vlan_enabled = val->value.i;
448
449 return 0;
450 }
451
452 static int mvsw61xx_vtu_program(struct switch_dev *dev)
453 {
454 struct mvsw61xx_state *state = get_state(dev);
455 u16 v1, v2, s1, s2;
456 int i;
457
458 /* Flush */
459 mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP),
460 MV_VTUOP_INPROGRESS, 0);
461 sw16(dev, MV_GLOBALREG(VTU_OP),
462 MV_VTUOP_INPROGRESS | MV_VTUOP_PURGE);
463
464 /* Write VLAN table */
465 for (i = 1; i < dev->vlans; i++) {
466 if (state->vlans[i].mask == 0 ||
467 state->vlans[i].vid == 0 ||
468 state->vlans[i].port_based == true)
469 continue;
470
471 mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP),
472 MV_VTUOP_INPROGRESS, 0);
473
474 /* Write per-VLAN port state into STU */
475 s1 = (u16) (state->vlans[i].port_sstate & 0xffff);
476 s2 = (u16) ((state->vlans[i].port_sstate >> 16) & 0xffff);
477
478 sw16(dev, MV_GLOBALREG(VTU_VID), MV_VTU_VID_VALID);
479 sw16(dev, MV_GLOBALREG(VTU_SID), i);
480 sw16(dev, MV_GLOBALREG(VTU_DATA1), s1);
481 sw16(dev, MV_GLOBALREG(VTU_DATA2), s2);
482 sw16(dev, MV_GLOBALREG(VTU_DATA3), 0);
483
484 sw16(dev, MV_GLOBALREG(VTU_OP),
485 MV_VTUOP_INPROGRESS | MV_VTUOP_STULOAD);
486 mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP),
487 MV_VTUOP_INPROGRESS, 0);
488
489 /* Write VLAN information into VTU */
490 v1 = (u16) (state->vlans[i].port_mode & 0xffff);
491 v2 = (u16) ((state->vlans[i].port_mode >> 16) & 0xffff);
492
493 sw16(dev, MV_GLOBALREG(VTU_VID),
494 MV_VTU_VID_VALID | state->vlans[i].vid);
495 sw16(dev, MV_GLOBALREG(VTU_SID), i);
496 sw16(dev, MV_GLOBALREG(VTU_FID), 0);
497 sw16(dev, MV_GLOBALREG(VTU_DATA1), v1);
498 sw16(dev, MV_GLOBALREG(VTU_DATA2), v2);
499 sw16(dev, MV_GLOBALREG(VTU_DATA3), 0);
500
501 sw16(dev, MV_GLOBALREG(VTU_OP),
502 MV_VTUOP_INPROGRESS | MV_VTUOP_LOAD);
503 mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP),
504 MV_VTUOP_INPROGRESS, 0);
505 }
506
507 return 0;
508 }
509
510 static void mvsw61xx_vlan_port_config(struct switch_dev *dev, int vno)
511 {
512 struct mvsw61xx_state *state = get_state(dev);
513 int i, mode;
514
515 for (i = 0; i < dev->ports; i++) {
516 if (!(state->vlans[vno].mask & (1 << i)))
517 continue;
518
519 mode = (state->vlans[vno].port_mode >> (i * 4)) & 0xf;
520
521 if(mode != MV_VTUCTL_EGRESS_TAGGED)
522 state->ports[i].pvid = state->vlans[vno].vid;
523
524 if (state->vlans[vno].port_based)
525 state->ports[i].mask |= state->vlans[vno].mask;
526 else
527 state->ports[i].qmode = MV_8021Q_MODE_SECURE;
528 }
529 }
530
531 static int mvsw61xx_update_state(struct switch_dev *dev)
532 {
533 struct mvsw61xx_state *state = get_state(dev);
534 int i;
535 u16 reg;
536
537 if (!state->registered)
538 return -EINVAL;
539
540 /*
541 * Set 802.1q-only mode if vlan_enabled is true.
542 *
543 * Without this, even if 802.1q is enabled for
544 * a port/VLAN, it still depends on the port-based
545 * VLAN mask being set.
546 *
547 * With this setting, port-based VLANs are still
548 * functional, provided the VID is not in the VTU.
549 */
550 reg = sr16(dev, MV_GLOBAL2REG(SDET_POLARITY));
551
552 if (state->vlan_enabled)
553 reg |= MV_8021Q_VLAN_ONLY;
554 else
555 reg &= ~MV_8021Q_VLAN_ONLY;
556
557 sw16(dev, MV_GLOBAL2REG(SDET_POLARITY), reg);
558
559 /*
560 * Set port-based VLAN masks on each port
561 * based only on VLAN definitions known to
562 * the driver (i.e. in state).
563 *
564 * This means any pre-existing port mapping is
565 * wiped out once our driver is initialized.
566 */
567 for (i = 0; i < dev->ports; i++) {
568 state->ports[i].mask = 0;
569 state->ports[i].qmode = MV_8021Q_MODE_DISABLE;
570 }
571
572 for (i = 0; i < dev->vlans; i++)
573 mvsw61xx_vlan_port_config(dev, i);
574
575 for (i = 0; i < dev->ports; i++) {
576 reg = sr16(dev, MV_PORTREG(VLANID, i)) & ~MV_PVID_MASK;
577 reg |= state->ports[i].pvid;
578 sw16(dev, MV_PORTREG(VLANID, i), reg);
579
580 state->ports[i].mask &= ~(1 << i);
581
582 reg = sr16(dev, MV_PORTREG(VLANMAP, i)) & ~MV_PORTS_MASK;
583 reg |= state->ports[i].mask;
584 sw16(dev, MV_PORTREG(VLANMAP, i), reg);
585
586 reg = sr16(dev, MV_PORTREG(CONTROL2, i)) &
587 ~MV_8021Q_MODE_MASK;
588 reg |= state->ports[i].qmode << MV_8021Q_MODE_SHIFT;
589 sw16(dev, MV_PORTREG(CONTROL2, i), reg);
590 }
591
592 mvsw61xx_vtu_program(dev);
593
594 return 0;
595 }
596
597 static int mvsw61xx_apply(struct switch_dev *dev)
598 {
599 return mvsw61xx_update_state(dev);
600 }
601
602 static int mvsw61xx_reset(struct switch_dev *dev)
603 {
604 struct mvsw61xx_state *state = get_state(dev);
605 int i;
606 u16 reg;
607
608 /* Disable all ports before reset */
609 for (i = 0; i < dev->ports; i++) {
610 reg = sr16(dev, MV_PORTREG(CONTROL, i)) &
611 ~MV_PORTCTRL_FORWARDING;
612 sw16(dev, MV_PORTREG(CONTROL, i), reg);
613 }
614
615 reg = sr16(dev, MV_GLOBALREG(CONTROL)) | MV_CONTROL_RESET;
616
617 sw16(dev, MV_GLOBALREG(CONTROL), reg);
618 if (mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(CONTROL),
619 MV_CONTROL_RESET, 0) < 0)
620 return -ETIMEDOUT;
621
622 for (i = 0; i < dev->ports; i++) {
623 state->ports[i].qmode = 0;
624 state->ports[i].mask = 0;
625 state->ports[i].pvid = 0;
626
627 /* Force flow control off */
628 reg = sr16(dev, MV_PORTREG(PHYCTL, i)) & ~MV_PHYCTL_FC_MASK;
629 reg |= MV_PHYCTL_FC_DISABLE;
630 sw16(dev, MV_PORTREG(PHYCTL, i), reg);
631
632 /* Set port association vector */
633 sw16(dev, MV_PORTREG(ASSOC, i), (1 << i));
634 }
635
636 for (i = 0; i < dev->vlans; i++) {
637 state->vlans[i].port_based = false;
638 state->vlans[i].mask = 0;
639 state->vlans[i].vid = 0;
640 state->vlans[i].port_mode = 0;
641 state->vlans[i].port_sstate = 0;
642 }
643
644 state->vlan_enabled = 0;
645
646 mvsw61xx_update_state(dev);
647
648 /* Re-enable ports */
649 for (i = 0; i < dev->ports; i++) {
650 reg = sr16(dev, MV_PORTREG(CONTROL, i)) |
651 MV_PORTCTRL_FORWARDING;
652 sw16(dev, MV_PORTREG(CONTROL, i), reg);
653 }
654
655 return 0;
656 }
657
658 enum {
659 MVSW61XX_ENABLE_VLAN,
660 };
661
662 enum {
663 MVSW61XX_VLAN_PORT_BASED,
664 MVSW61XX_VLAN_ID,
665 };
666
667 enum {
668 MVSW61XX_PORT_MASK,
669 MVSW61XX_PORT_QMODE,
670 MVSW61XX_PORT_STATUS,
671 MVSW61XX_PORT_LINK,
672 };
673
674 static const struct switch_attr mvsw61xx_global[] = {
675 [MVSW61XX_ENABLE_VLAN] = {
676 .id = MVSW61XX_ENABLE_VLAN,
677 .type = SWITCH_TYPE_INT,
678 .name = "enable_vlan",
679 .description = "Enable 802.1q VLAN support",
680 .get = mvsw61xx_get_enable_vlan,
681 .set = mvsw61xx_set_enable_vlan,
682 },
683 };
684
685 static const struct switch_attr mvsw61xx_vlan[] = {
686 [MVSW61XX_VLAN_PORT_BASED] = {
687 .id = MVSW61XX_VLAN_PORT_BASED,
688 .type = SWITCH_TYPE_INT,
689 .name = "port_based",
690 .description = "Use port-based (non-802.1q) VLAN only",
691 .get = mvsw61xx_get_vlan_port_based,
692 .set = mvsw61xx_set_vlan_port_based,
693 },
694 [MVSW61XX_VLAN_ID] = {
695 .id = MVSW61XX_VLAN_ID,
696 .type = SWITCH_TYPE_INT,
697 .name = "vid",
698 .description = "Get/set VLAN ID",
699 .get = mvsw61xx_get_vid,
700 .set = mvsw61xx_set_vid,
701 },
702 };
703
704 static const struct switch_attr mvsw61xx_port[] = {
705 [MVSW61XX_PORT_MASK] = {
706 .id = MVSW61XX_PORT_MASK,
707 .type = SWITCH_TYPE_STRING,
708 .description = "Port-based VLAN mask",
709 .name = "mask",
710 .get = mvsw61xx_get_port_mask,
711 .set = NULL,
712 },
713 [MVSW61XX_PORT_QMODE] = {
714 .id = MVSW61XX_PORT_QMODE,
715 .type = SWITCH_TYPE_INT,
716 .description = "802.1q mode: 0=off/1=fallback/2=check/3=secure",
717 .name = "qmode",
718 .get = mvsw61xx_get_port_qmode,
719 .set = mvsw61xx_set_port_qmode,
720 },
721 [MVSW61XX_PORT_STATUS] = {
722 .id = MVSW61XX_PORT_STATUS,
723 .type = SWITCH_TYPE_STRING,
724 .description = "Return port status",
725 .name = "status",
726 .get = mvsw61xx_get_port_status,
727 .set = NULL,
728 },
729 [MVSW61XX_PORT_LINK] = {
730 .id = MVSW61XX_PORT_LINK,
731 .type = SWITCH_TYPE_INT,
732 .description = "Get link speed",
733 .name = "link",
734 .get = mvsw61xx_get_port_speed,
735 .set = NULL,
736 },
737 };
738
739 static const struct switch_dev_ops mvsw61xx_ops = {
740 .attr_global = {
741 .attr = mvsw61xx_global,
742 .n_attr = ARRAY_SIZE(mvsw61xx_global),
743 },
744 .attr_vlan = {
745 .attr = mvsw61xx_vlan,
746 .n_attr = ARRAY_SIZE(mvsw61xx_vlan),
747 },
748 .attr_port = {
749 .attr = mvsw61xx_port,
750 .n_attr = ARRAY_SIZE(mvsw61xx_port),
751 },
752 .get_port_pvid = mvsw61xx_get_pvid,
753 .set_port_pvid = mvsw61xx_set_pvid,
754 .get_vlan_ports = mvsw61xx_get_vlan_ports,
755 .set_vlan_ports = mvsw61xx_set_vlan_ports,
756 .apply_config = mvsw61xx_apply,
757 .reset_switch = mvsw61xx_reset,
758 };
759
760 /* end swconfig stuff */
761
762 static int mvsw61xx_probe(struct platform_device *pdev)
763 {
764 struct mvsw61xx_state *state;
765 struct device_node *np = pdev->dev.of_node;
766 struct device_node *mdio;
767 char *model_str;
768 u32 val;
769 int err;
770
771 state = kzalloc(sizeof(*state), GFP_KERNEL);
772 if (!state)
773 return -ENOMEM;
774
775 mdio = of_parse_phandle(np, "mii-bus", 0);
776 if (!mdio) {
777 dev_err(&pdev->dev, "Couldn't get MII bus handle\n");
778 err = -ENODEV;
779 goto out_err;
780 }
781
782 state->bus = of_mdio_find_bus(mdio);
783 if (!state->bus) {
784 dev_err(&pdev->dev, "Couldn't find MII bus from handle\n");
785 err = -ENODEV;
786 goto out_err;
787 }
788
789 state->is_indirect = of_property_read_bool(np, "is-indirect");
790
791 if (state->is_indirect) {
792 if (of_property_read_u32(np, "reg", &val)) {
793 dev_err(&pdev->dev, "Switch address not specified\n");
794 err = -ENODEV;
795 goto out_err;
796 }
797
798 state->base_addr = val;
799 } else {
800 state->base_addr = MV_BASE;
801 }
802
803 state->model = r16(state->bus, state->is_indirect, state->base_addr,
804 MV_PORTREG(IDENT, 0)) & MV_IDENT_MASK;
805
806 switch(state->model) {
807 case MV_IDENT_VALUE_6171:
808 model_str = MV_IDENT_STR_6171;
809 break;
810 case MV_IDENT_VALUE_6172:
811 model_str = MV_IDENT_STR_6172;
812 break;
813 case MV_IDENT_VALUE_6176:
814 model_str = MV_IDENT_STR_6176;
815 break;
816 default:
817 dev_err(&pdev->dev, "No compatible switch found at 0x%02x\n",
818 state->base_addr);
819 err = -ENODEV;
820 goto out_err;
821 }
822
823 platform_set_drvdata(pdev, state);
824 dev_info(&pdev->dev, "Found %s at %s:%02x\n", model_str,
825 state->bus->id, state->base_addr);
826
827 dev_info(&pdev->dev, "Using %sdirect addressing\n",
828 (state->is_indirect ? "in" : ""));
829
830 if (of_property_read_u32(np, "cpu-port-0", &val)) {
831 dev_err(&pdev->dev, "CPU port not set\n");
832 err = -ENODEV;
833 goto out_err;
834 }
835
836 state->cpu_port0 = val;
837
838 if (!of_property_read_u32(np, "cpu-port-1", &val))
839 state->cpu_port1 = val;
840 else
841 state->cpu_port1 = -1;
842
843 state->dev.vlans = MV_VLANS;
844 state->dev.cpu_port = state->cpu_port0;
845 state->dev.ports = MV_PORTS;
846 state->dev.name = model_str;
847 state->dev.ops = &mvsw61xx_ops;
848 state->dev.alias = dev_name(&pdev->dev);
849
850 err = register_switch(&state->dev, NULL);
851 if (err < 0)
852 goto out_err;
853
854 state->registered = true;
855
856 return 0;
857 out_err:
858 kfree(state);
859 return err;
860 }
861
862 static int
863 mvsw61xx_remove(struct platform_device *pdev)
864 {
865 struct mvsw61xx_state *state = platform_get_drvdata(pdev);
866
867 if (state->registered)
868 unregister_switch(&state->dev);
869
870 kfree(state);
871
872 return 0;
873 }
874
875 static const struct of_device_id mvsw61xx_match[] = {
876 { .compatible = "marvell,88e6171" },
877 { .compatible = "marvell,88e6172" },
878 { .compatible = "marvell,88e6176" },
879 { }
880 };
881 MODULE_DEVICE_TABLE(of, mvsw61xx_match);
882
883 static struct platform_driver mvsw61xx_driver = {
884 .probe = mvsw61xx_probe,
885 .remove = mvsw61xx_remove,
886 .driver = {
887 .name = "mvsw61xx",
888 .of_match_table = of_match_ptr(mvsw61xx_match),
889 .owner = THIS_MODULE,
890 },
891 };
892
893 static int __init mvsw61xx_module_init(void)
894 {
895 return platform_driver_register(&mvsw61xx_driver);
896 }
897 late_initcall(mvsw61xx_module_init);
898
899 static void __exit mvsw61xx_module_exit(void)
900 {
901 platform_driver_unregister(&mvsw61xx_driver);
902 }
903 module_exit(mvsw61xx_module_exit);
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