mvebu: fix RxAlignErr and RxFcsErr

diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.c b/target/linux/generic/files/drivers/net/phy/ar8216.c
index 850bcefb74e26e8cffa62fa0993533c40300339f..329fb5b582774283b75dc91676265e3edf699c99 100644 (file)
--- a/target/linux/generic/files/drivers/net/phy/ar8216.c
+++ b/target/linux/generic/files/drivers/net/phy/ar8216.c
@@ -202,6 +202,8 @@ ar8xxx_phy_init(struct ar8xxx_priv *priv)
        int i;
        struct mii_bus *bus;
 
+       pr_err("%s\n", __PRETTY_FUNCTION__);
+
        bus = priv->sw_mii_bus ?: priv->mii_bus;
        for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
                if (priv->chip->phy_fixup)
@@ -216,6 +218,11 @@ ar8xxx_phy_init(struct ar8xxx_priv *priv)
        }
 
        ar8xxx_phy_poll_reset(bus);
+
+       pr_err("ar8xxx_phy_init: setting custom registers\n");
+
+       ar8xxx_write(priv, 0x002c, 0x7e3f003f);
+       ar8xxx_write(priv, 0x0004, 0x00000500);
 }
 
 u32
@@ -720,6 +727,8 @@ ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 static int
 ar8216_hw_init(struct ar8xxx_priv *priv)
 {
+       pr_err("%s\n", __PRETTY_FUNCTION__);
+
        if (priv->initialized)
                return 0;
 
@@ -746,6 +755,8 @@ static void
 __ar8216_init_port(struct ar8xxx_priv *priv, int port,
                   bool cpu_ge, bool flow_en)
 {
+       pr_err("%s\n", __PRETTY_FUNCTION__);
+
        /* Enable port learning and tx */
        ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
                AR8216_PORT_CTRL_LEARN |
@@ -764,13 +775,16 @@ __ar8216_init_port(struct ar8xxx_priv *priv, int port,
                        AR8216_PORT_STATUS_DUPLEX);
        } else {
                ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
-                       AR8216_PORT_STATUS_LINK_AUTO);
+                       AR8216_PORT_STATUS_LINK_AUTO |
+                       AR8216_PORT_STATUS_FLOW_CONTROL);
        }
 }
 
 static void
 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 {
+       pr_err("%s\n", __PRETTY_FUNCTION__);
+
        __ar8216_init_port(priv, port, ar8xxx_has_gige(priv),
                           chip_is_ar8316(priv));
 }
@@ -1038,6 +1052,9 @@ ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 {
        u32 egress, ingress;
        u32 pvid;
+       u32 t;
+
+       pr_err("%s\n", __PRETTY_FUNCTION__);
 
        if (priv->vlan) {
                pvid = priv->vlan_id[priv->pvid[port]];
@@ -1069,11 +1086,19 @@ ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
                   AR8236_PORT_VLAN2_MEMBER,
                   (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
                   (members << AR8236_PORT_VLAN2_MEMBER_S));
+
+       t = ar8xxx_read(priv, AR8216_REG_PORT_CTRL(port));
+       pr_err("Port %i control register: %llx\n", port, t);
+
+       t = ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
+       pr_err("Port %i status register: %llx\n", port, t);
 }
 
 static void
 ar8236_init_globals(struct ar8xxx_priv *priv)
 {
+       pr_err("%s\n", __PRETTY_FUNCTION__);
+
        /* enable jumbo frames */
        ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
                   AR8316_GCTRL_MTU, 9018 + 8 + 2);
@@ -1360,6 +1385,9 @@ ar8xxx_sw_hw_apply(struct switch_dev *dev)
        const struct ar8xxx_chip *chip = priv->chip;
        u8 portmask[AR8X16_MAX_PORTS];
        int i, j;
+       u32 t;
+
+       pr_err("%s\n", __PRETTY_FUNCTION__);
 
        mutex_lock(&priv->reg_mutex);
        /* flush all vlan translation unit entries */
@@ -1408,6 +1436,13 @@ ar8xxx_sw_hw_apply(struct switch_dev *dev)
                ar8xxx_set_age_time(priv, chip->reg_arl_ctrl);
 
        mutex_unlock(&priv->reg_mutex);
+
+       t = ar8xxx_read(priv, 0x002c);
+       pr_err("ar8xxx_phy_init: 0x002c: %llx\n", t);
+
+       t = ar8xxx_read(priv, 0x0004);
+       pr_err("ar8xxx_phy_init: 0x0004: %llx\n", t);
+
        return 0;
 }
 

diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-oc200.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-oc200.dts
index 521de7a900b4f365feeb81af2f44718ba2d60bf6..690c09816272244a59c8454a18a8fa08830031de 100755 (executable)
--- a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-oc200.dts
+++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-oc200.dts
@@ -126,6 +126,23 @@
                                enable-active-high;
                        };
 
+
+                       bm: bm@c0000 {
+                               compatible = "marvell,armada-380-neta-bm";
+                               reg = <0xc0000 0xac>;
+                               clocks = <&sb_periph_clk 9>;
+                               internal-mem = <&bm_bppi>;
+                               status = "okay";
+                       };
+
+                       bm_bppi: bm-bppi {
+                               compatible = "mmio-sram";
+                               reg = <0xc8000 0x1000>;
+                               clocks = <&sb_periph_clk 9>;
+                               no-memory-wc;
+                               status = "okay";
+                       };
+
                        eip97: eip97@90000 {
                                status = "okay";
                        };
@@ -226,10 +243,14 @@
 &eth0 {
        phy-mode = "rgmii";
        status = "okay";
+       buffer-manager = <&bm>;
+       bm,pool-long = <1>;
+       bm,pool-short = <3>;
 
        fixed-link {
                speed = <100>;
                full-duplex;
+               //pause;
        };
 
 };

diff --git a/target/linux/mvebu/patches-5.15/999-mvneta-debug.patch b/target/linux/mvebu/patches-5.15/999-mvneta-debug.patch
new file mode 100644 (file)
index 0000000..65556b7
--- /dev/null
+++ b/target/linux/mvebu/patches-5.15/999-mvneta-debug.patch
@@ -0,0 +1,37 @@
+diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
+index ccb2abd18d6c..3d1849c2ed24 100644
+--- a/drivers/net/ethernet/marvell/mvneta.c
++++ b/drivers/net/ethernet/marvell/mvneta.c
+@@ -3534,7 +3534,7 @@ static void mvneta_mac_config(struct phylink_config *config, unsigned int mode,
+       /* Even though it might look weird, when we're configured in
+        * SGMII or QSGMII mode, the RGMII bit needs to be set.
+        */
+-      new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII;
++      new_ctrl2 &= ~MVNETA_GMAC2_PORT_RGMII;
+ 
+       if (state->interface == PHY_INTERFACE_MODE_QSGMII ||
+           state->interface == PHY_INTERFACE_MODE_SGMII ||
+@@ -4498,6 +4498,8 @@ static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
+ /* Power up the port */
+ static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
+ {
++      u32 val;
++
+       /* MAC Cause register should be cleared */
+       mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
+ 
+@@ -4507,6 +4509,14 @@ static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
+           !phy_interface_mode_is_rgmii(phy_mode))
+               return -EINVAL;
+ 
++      val = mvreg_read(pp, 0x243c);
++      pr_err("mvneta: register 0x243c original value: %llx\n", val);
++
++      val |= BIT(28)|BIT(29)|BIT(30);
++      pr_err("mvneta: register 0x243c modified value: %llx\n", val);
++
++      mvreg_write(pp, 0x243c, val);
++
+       return 0;
+ }
+