openwrt/target/linux/brcm-2.4/patches/008-b44_bcm47xx_support.patch

   1 diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
   2 --- linux.old/drivers/net/b44.c 2006-02-12 13:49:59.000000000 +0100
   3 +++ linux.dev/drivers/net/b44.c 2006-03-06 22:37:14.000000000 +0100
   4 @@ -1,7 +1,9 @@
   5  /* b44.c: Broadcom 4400 device driver.
   6   *
   7   * Copyright (C) 2002 David S. Miller (davem@redhat.com)
   8 - * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
   9 + * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
  10 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
  11 + * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
  12   *
  13   * Distribute under GPL.
  14   */
  15 @@ -25,6 +27,41 @@
  16
  17  #include "b44.h"
  18
  19 +#include <typedefs.h>
  20 +#include <bcmdevs.h>
  21 +#include <bcmutils.h>
  22 +#include <osl.h>
  23 +#include <bcmutils.h>
  24 +#include <bcmnvram.h>
  25 +#include <sbconfig.h>
  26 +#include <sbchipc.h>
  27 +#include <sflash.h>
  28 +
  29 +#ifdef CONFIG_BCM947XX
  30 +#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
  31 +
  32 +static inline void e_aton(char *str, char *dest)
  33 +{
  34 +       int i = 0;
  35 +       u16 *d = (u16 *) dest;
  36 +
  37 +       if (str == NULL) {
  38 +               memset(dest, 0, 6);
  39 +               return;
  40 +       }
  41 +
  42 +       for (;;) {
  43 +               dest[i++] = (char) simple_strtoul(str, NULL, 16);
  44 +               str += 2;
  45 +               if (!*str++ || i == 6)
  46 +                       break;
  47 +       }
  48 +}
  49 +
  50 +static int instance = 0;
  51 +#endif
  52 +
  53 +
  54  #define DRV_MODULE_NAME                "b44"
  55  #define PFX DRV_MODULE_NAME    ": "
  56  #define DRV_MODULE_VERSION     "0.93"
  57 @@ -75,7 +112,7 @@
  58         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  59
  60  MODULE_AUTHOR("David S. Miller (davem@redhat.com)");
  61 -MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
  62 +MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
  63  MODULE_LICENSE("GPL");
  64  MODULE_PARM(b44_debug, "i");
  65  MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
  66 @@ -89,6 +126,8 @@
  67           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  68         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
  69           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  70 +       { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4713,
  71 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  72         { }     /* terminate list with empty entry */
  73  };
  74
  75 @@ -113,11 +152,13 @@
  76                 udelay(10);
  77         }
  78         if (i == timeout) {
  79 +#ifdef DEBUG
  80                 printk(KERN_ERR PFX "%s: BUG!  Timeout waiting for bit %08x of register "
  81                        "%lx to %s.\n",
  82                        bp->dev->name,
  83                        bit, reg,
  84                        (clear ? "clear" : "set"));
  85 +#endif
  86                 return -ENODEV;
  87         }
  88         return 0;
  89 @@ -236,6 +277,8 @@
  90         udelay(1);
  91  }
  92
  93 +static int b44_4713_instance;
  94 +
  95  static int ssb_core_unit(struct b44 *bp)
  96  {
  97  #if 0
  98 @@ -258,6 +301,9 @@
  99                 break;
 100         };
 101  #endif
 102 +       if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
 103 +               return b44_4713_instance++;
 104 +       else
 105         return 0;
 106  }
 107
 108 @@ -267,6 +313,28 @@
 109                 == SBTMSLOW_CLOCK);
 110  }
 111
 112 +static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
 113 +{
 114 +       u32 val;
 115 +
 116 +       bw32(B44_CAM_CTRL, (CAM_CTRL_READ |
 117 +                           (index << CAM_CTRL_INDEX_SHIFT)));
 118 +
 119 +       b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
 120 +
 121 +       val = br32(B44_CAM_DATA_LO);
 122 +
 123 +       data[2] = (val >> 24) & 0xFF;
 124 +       data[3] = (val >> 16) & 0xFF;
 125 +       data[4] = (val >> 8) & 0xFF;
 126 +       data[5] = (val >> 0) & 0xFF;
 127 +
 128 +       val = br32(B44_CAM_DATA_HI);
 129 +
 130 +       data[0] = (val >> 8) & 0xFF;
 131 +       data[1] = (val >> 0) & 0xFF;
 132 +}
 133 +
 134  static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
 135  {
 136         u32 val;
 137 @@ -287,7 +355,7 @@
 138
 139  static inline void __b44_disable_ints(struct b44 *bp)
 140  {
 141 -       bw32(B44_IMASK, 0);
 142 +       bw32(B44_IMASK, ISTAT_TO); /* leave the timeout interrupt active */
 143  }
 144
 145  static void b44_disable_ints(struct b44 *bp)
 146 @@ -303,14 +371,14 @@
 147         bw32(B44_IMASK, bp->imask);
 148  }
 149
 150 -static int b44_readphy(struct b44 *bp, int reg, u32 *val)
 151 +static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
 152  {
 153         int err;
 154
 155         bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
 156         bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
 157                              (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
 158 -                            (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 159 +                            (phy_addr << MDIO_DATA_PMD_SHIFT) |
 160                              (reg << MDIO_DATA_RA_SHIFT) |
 161                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
 162         err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 163 @@ -319,23 +387,42 @@
 164         return err;
 165  }
 166
 167 -static int b44_writephy(struct b44 *bp, int reg, u32 val)
 168 +static int b44_readphy(struct b44 *bp, int reg, u32 *val)
 169 +{
 170 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 171 +               return 0;
 172 +
 173 +       return __b44_readphy(bp, bp->phy_addr, reg, val);
 174 +}
 175 +
 176 +static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
 177  {
 178         bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
 179         bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
 180                              (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
 181 -                            (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 182 +                            (phy_addr << MDIO_DATA_PMD_SHIFT) |
 183                              (reg << MDIO_DATA_RA_SHIFT) |
 184                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
 185                              (val & MDIO_DATA_DATA)));
 186         return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 187  }
 188
 189 +static int b44_writephy(struct b44 *bp, int reg, u32 val)
 190 +{
 191 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 192 +               return 0;
 193 +
 194 +       return __b44_writephy(bp, bp->phy_addr, reg, val);
 195 +}
 196 +
 197  static int b44_phy_reset(struct b44 *bp)
 198  {
 199         u32 val;
 200         int err;
 201
 202 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 203 +               return 0;
 204 +
 205         err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
 206         if (err)
 207                 return err;
 208 @@ -406,6 +493,23 @@
 209         u32 val;
 210         int err;
 211
 212 +
 213 +       /*
 214 +        * workaround for bad hardware design in Linksys WAP54G v1.0
 215 +        * see https://dev.openwrt.org/ticket/146
 216 +        * check and reset bit "isolate"
 217 +        */
 218 +       if ((bp->pdev->device == PCI_DEVICE_ID_BCM4713) &&
 219 +                       (atoi(nvram_get("boardnum")) == 2) &&
 220 +                       (__b44_readphy(bp, 0, MII_BMCR, &val) == 0) &&
 221 +                       (val & BMCR_ISOLATE) &&
 222 +                       (__b44_writephy(bp, 0, MII_BMCR, val & ~BMCR_ISOLATE) != 0)) {
 223 +               printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
 224 +       }
 225 +
 226 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 227 +               return 0;
 228 +
 229         if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
 230                 goto out;
 231         if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
 232 @@ -498,6 +602,19 @@
 233  {
 234         u32 bmsr, aux;
 235
 236 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
 237 +               bp->flags |= B44_FLAG_100_BASE_T;
 238 +               bp->flags |= B44_FLAG_FULL_DUPLEX;
 239 +               if (!netif_carrier_ok(bp->dev)) {
 240 +                       u32 val = br32(B44_TX_CTRL);
 241 +                       val |= TX_CTRL_DUPLEX;
 242 +                       bw32(B44_TX_CTRL, val);
 243 +                       netif_carrier_on(bp->dev);
 244 +                       b44_link_report(bp);
 245 +               }
 246 +               return;
 247 +       }
 248 +
 249         if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
 250             !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
 251             (bmsr != 0xffff)) {
 252 @@ -765,6 +882,25 @@
 253         return received;
 254  }
 255
 256 +
 257 +static inline void __b44_reset(struct b44 *bp)
 258 +{
 259 +       spin_lock_irq(&bp->lock);
 260 +       b44_halt(bp);
 261 +       b44_init_rings(bp);
 262 +       b44_init_hw(bp);
 263 +       spin_unlock_irq(&bp->lock);
 264 +
 265 +       b44_enable_ints(bp);
 266 +       netif_wake_queue(bp->dev);
 267 +}
 268 +
 269 +static inline void __b44_set_timeout(struct b44 *bp, int timeout)
 270 +{
 271 +       /* Set timeout for Rx to two seconds after the last Tx */
 272 +       bw32(B44_GPTIMER, timeout ? 2 * 125000000 : 0);
 273 +}
 274 +
 275  static int b44_poll(struct net_device *netdev, int *budget)
 276  {
 277         struct b44 *bp = netdev->priv;
 278 @@ -772,13 +908,13 @@
 279
 280         spin_lock_irq(&bp->lock);
 281
 282 -       if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
 283 +       if (bp->istat & ISTAT_TX) {
 284                 /* spin_lock(&bp->tx_lock); */
 285                 b44_tx(bp);
 286                 /* spin_unlock(&bp->tx_lock); */
 287         }
 288         spin_unlock_irq(&bp->lock);
 289 -
 290 +
 291         done = 1;
 292         if (bp->istat & ISTAT_RX) {
 293                 int orig_budget = *budget;
 294 @@ -796,24 +932,18 @@
 295                         done = 0;
 296         }
 297
 298 -       if (bp->istat & ISTAT_ERRORS) {
 299 -               spin_lock_irq(&bp->lock);
 300 -               b44_halt(bp);
 301 -               b44_init_rings(bp);
 302 -               b44_init_hw(bp);
 303 -               netif_wake_queue(bp->dev);
 304 -               spin_unlock_irq(&bp->lock);
 305 -               done = 1;
 306 -       }
 307 -
 308         if (done) {
 309                 netif_rx_complete(netdev);
 310                 b44_enable_ints(bp);
 311         }
 312
 313 +       if ((bp->core_unit == 1) && (bp->istat & (ISTAT_TX | ISTAT_RX)))
 314 +               __b44_set_timeout(bp, (bp->istat & ISTAT_TX) ? 1 : 0);
 315 +
 316         return (done ? 0 : 1);
 317  }
 318
 319 +
 320  static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 321  {
 322         struct net_device *dev = dev_id;
 323 @@ -832,6 +962,18 @@
 324          */
 325         istat &= imask;
 326         if (istat) {
 327 +               /* Workaround for the WL-500g WAN port hang */
 328 +               if (istat & (ISTAT_TO | ISTAT_ERRORS)) {
 329 +                       /*
 330 +                        * no rx before the watchdog timeout
 331 +                        * reset the interface
 332 +                        */
 333 +                       __b44_reset(bp);
 334 +               }
 335 +
 336 +               if ((bp->core_unit == 1) && (bp->istat & (ISTAT_TX | ISTAT_RX)))
 337 +                       __b44_set_timeout(bp, (bp->istat & ISTAT_TX) ? 1 : 0);
 338 +
 339                 handled = 1;
 340                 if (netif_rx_schedule_prep(dev)) {
 341                         /* NOTE: These writes are posted by the readback of
 342 @@ -848,6 +990,7 @@
 343                 bw32(B44_ISTAT, istat);
 344                 br32(B44_ISTAT);
 345         }
 346 +
 347         spin_unlock_irqrestore(&bp->lock, flags);
 348         return IRQ_RETVAL(handled);
 349  }
 350 @@ -859,16 +1002,7 @@
 351         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
 352                dev->name);
 353
 354 -       spin_lock_irq(&bp->lock);
 355 -
 356 -       b44_halt(bp);
 357 -       b44_init_rings(bp);
 358 -       b44_init_hw(bp);
 359 -
 360 -       spin_unlock_irq(&bp->lock);
 361 -
 362 -       b44_enable_ints(bp);
 363 -
 364 +       __b44_reset(bp);
 365         netif_wake_queue(dev);
 366  }
 367
 368 @@ -1092,6 +1226,8 @@
 369  /* bp->lock is held. */
 370  static void b44_chip_reset(struct b44 *bp)
 371  {
 372 +       unsigned int sb_clock;
 373 +
 374         if (ssb_is_core_up(bp)) {
 375                 bw32(B44_RCV_LAZY, 0);
 376                 bw32(B44_ENET_CTRL, ENET_CTRL_DISABLE);
 377 @@ -1105,9 +1241,10 @@
 378                 bw32(B44_DMARX_CTRL, 0);
 379                 bp->rx_prod = bp->rx_cons = 0;
 380         } else {
 381 -               ssb_pci_setup(bp, (bp->core_unit == 0 ?
 382 -                                  SBINTVEC_ENET0 :
 383 -                                  SBINTVEC_ENET1));
 384 +               /*if (bp->pdev->device != PCI_DEVICE_ID_BCM4713)*/
 385 +                       ssb_pci_setup(bp, (bp->core_unit == 0 ?
 386 +                                       SBINTVEC_ENET0 :
 387 +                                       SBINTVEC_ENET1));
 388         }
 389
 390         ssb_core_reset(bp);
 391 @@ -1115,6 +1252,11 @@
 392         b44_clear_stats(bp);
 393
 394         /* Make PHY accessible. */
 395 +       if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
 396 +               sb_clock = 100000000; /* 100 MHz */
 397 +       else
 398 +               sb_clock = 62500000; /* 62.5 MHz */
 399 +
 400         bw32(B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
 401                              (0x0d & MDIO_CTRL_MAXF_MASK)));
 402         br32(B44_MDIO_CTRL);
 403 @@ -1215,6 +1357,8 @@
 404         struct b44 *bp = dev->priv;
 405         int err;
 406
 407 +       netif_carrier_off(dev);
 408 +
 409         err = b44_alloc_consistent(bp);
 410         if (err)
 411                 return err;
 412 @@ -1235,9 +1379,10 @@
 413         bp->timer.expires = jiffies + HZ;
 414         bp->timer.data = (unsigned long) bp;
 415         bp->timer.function = b44_timer;
 416 -       add_timer(&bp->timer);
 417 +       b44_timer((unsigned long) bp);
 418
 419         b44_enable_ints(bp);
 420 +       netif_start_queue(dev);
 421
 422         return 0;
 423
 424 @@ -1628,7 +1773,7 @@
 425                 u32 mii_regval;
 426
 427                 spin_lock_irq(&bp->lock);
 428 -               err = b44_readphy(bp, data->reg_num & 0x1f, &mii_regval);
 429 +               err = __b44_readphy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
 430                 spin_unlock_irq(&bp->lock);
 431
 432                 data->val_out = mii_regval;
 433 @@ -1641,7 +1786,7 @@
 434                         return -EPERM;
 435
 436                 spin_lock_irq(&bp->lock);
 437 -               err = b44_writephy(bp, data->reg_num & 0x1f, data->val_in);
 438 +               err = __b44_writephy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
 439                 spin_unlock_irq(&bp->lock);
 440
 441                 return err;
 442 @@ -1668,21 +1813,52 @@
 443  static int __devinit b44_get_invariants(struct b44 *bp)
 444  {
 445         u8 eeprom[128];
 446 +       u8 buf[32];
 447         int err;
 448 +       unsigned long flags;
 449
 450 -       err = b44_read_eeprom(bp, &eeprom[0]);
 451 -       if (err)
 452 -               goto out;
 453 -
 454 -       bp->dev->dev_addr[0] = eeprom[79];
 455 -       bp->dev->dev_addr[1] = eeprom[78];
 456 -       bp->dev->dev_addr[2] = eeprom[81];
 457 -       bp->dev->dev_addr[3] = eeprom[80];
 458 -       bp->dev->dev_addr[4] = eeprom[83];
 459 -       bp->dev->dev_addr[5] = eeprom[82];
 460 -
 461 -       bp->phy_addr = eeprom[90] & 0x1f;
 462 -       bp->mdc_port = (eeprom[90] >> 14) & 0x1;
 463 +       if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) {
 464 +#ifdef CONFIG_BCM947XX
 465 +               sprintf(buf, "et%dmacaddr", instance - 1);
 466 +               e_aton(nvram_get(buf), bp->dev->dev_addr);
 467 +
 468 +               sprintf(buf, "et%dphyaddr", instance - 1);
 469 +               bp->phy_addr = B44_PHY_ADDR_NO_PHY;
 470 +#else
 471 +               /*
 472 +                * BCM47xx boards don't have a EEPROM. The MAC is stored in
 473 +                * a NVRAM area somewhere in the flash memory. As we don't
 474 +                * know the location and/or the format of the NVRAM area
 475 +                * here, we simply rely on the bootloader to write the
 476 +                * MAC into the CAM.
 477 +                */
 478 +               spin_lock_irqsave(&bp->lock, flags);
 479 +               __b44_cam_read(bp, bp->dev->dev_addr, 0);
 480 +               spin_unlock_irqrestore(&bp->lock, flags);
 481 +
 482 +               /*
 483 +                * BCM47xx boards don't have a PHY. Usually there is a switch
 484 +                * chip with multiple PHYs connected to the PHY port.
 485 +                */
 486 +               bp->phy_addr = B44_PHY_ADDR_NO_PHY;
 487 +#endif
 488 +               bp->dma_offset = 0;
 489 +       } else {
 490 +               err = b44_read_eeprom(bp, &eeprom[0]);
 491 +               if (err)
 492 +                       return err;
 493 +
 494 +               bp->dev->dev_addr[0] = eeprom[79];
 495 +               bp->dev->dev_addr[1] = eeprom[78];
 496 +               bp->dev->dev_addr[2] = eeprom[81];
 497 +               bp->dev->dev_addr[3] = eeprom[80];
 498 +               bp->dev->dev_addr[4] = eeprom[83];
 499 +               bp->dev->dev_addr[5] = eeprom[82];
 500 +
 501 +               bp->phy_addr = eeprom[90] & 0x1f;
 502 +               bp->dma_offset = SB_PCI_DMA;
 503 +               bp->mdc_port = (eeprom[90] >> 14) & 0x1;
 504 +       }
 505
 506         /* With this, plus the rx_header prepended to the data by the
 507          * hardware, we'll land the ethernet header on a 2-byte boundary.
 508 @@ -1692,13 +1868,12 @@
 509         bp->imask = IMASK_DEF;
 510
 511         bp->core_unit = ssb_core_unit(bp);
 512 -       bp->dma_offset = ssb_get_addr(bp, SBID_PCI_DMA, 0);
 513
 514         /* XXX - really required?
 515            bp->flags |= B44_FLAG_BUGGY_TXPTR;
 516           */
 517 -out:
 518 -       return err;
 519 +
 520 +       return 0;
 521  }
 522
 523  static int __devinit b44_init_one(struct pci_dev *pdev,
 524 @@ -1710,6 +1885,10 @@
 525         struct b44 *bp;
 526         int err, i;
 527
 528 +#ifdef CONFIG_BCM947XX
 529 +       instance++;
 530 +#endif
 531 +
 532         if (b44_version_printed++ == 0)
 533                 printk(KERN_INFO "%s", version);
 534
 535 @@ -1819,11 +1998,17 @@
 536
 537         pci_save_state(bp->pdev, bp->pci_cfg_state);
 538
 539 -       printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
 540 +       printk(KERN_INFO "%s: Broadcom %s 10/100BaseT Ethernet ", dev->name,
 541 +               (pdev->device == PCI_DEVICE_ID_BCM4713) ? "47xx" : "4400");
 542         for (i = 0; i < 6; i++)
 543                 printk("%2.2x%c", dev->dev_addr[i],
 544                        i == 5 ? '\n' : ':');
 545
 546 +       /* Initialize phy */
 547 +       spin_lock_irq(&bp->lock);
 548 +       b44_chip_reset(bp);
 549 +       spin_unlock_irq(&bp->lock);
 550 +
 551         return 0;
 552
 553  err_out_iounmap:
 554 diff -urN linux.old/drivers/net/b44.h linux.dev/drivers/net/b44.h
 555 --- linux.old/drivers/net/b44.h 2006-02-12 13:49:59.000000000 +0100
 556 +++ linux.dev/drivers/net/b44.h 2006-01-24 20:52:08.000000000 +0100
 557 @@ -229,8 +229,6 @@
 558  #define  SBIPSFLAG_IMASK4      0x3f000000 /* Which sbflags --> mips interrupt 4 */
 559  #define  SBIPSFLAG_ISHIFT4     24
 560  #define B44_SBTPSFLAG  0x0F18UL /* SB Target Port OCP Slave Flag */
 561 -#define  SBTPS_NUM0_MASK       0x0000003f
 562 -#define  SBTPS_F0EN0           0x00000040
 563  #define B44_SBADMATCH3 0x0F60UL /* SB Address Match 3 */
 564  #define B44_SBADMATCH2 0x0F68UL /* SB Address Match 2 */
 565  #define B44_SBADMATCH1 0x0F70UL /* SB Address Match 1 */
 566 @@ -461,6 +459,8 @@
 567  };
 568
 569  #define B44_MCAST_TABLE_SIZE   32
 570 +#define B44_PHY_ADDR_NO_PHY    30
 571 +#define B44_MDC_RATIO          5000000
 572
 573  /* SW copy of device statistics, kept up to date by periodic timer
 574   * which probes HW values.  Must have same relative layout as HW
 575 diff -urN linux.old/include/linux/pci_ids.h linux.dev/include/linux/pci_ids.h
 576 --- linux.old/include/linux/pci_ids.h   2006-02-12 13:49:59.000000000 +0100
 577 +++ linux.dev/include/linux/pci_ids.h   2006-01-24 20:52:08.000000000 +0100
 578 @@ -1735,6 +1735,7 @@
 579  #define PCI_DEVICE_ID_TIGON3_5901_2    0x170e
 580  #define PCI_DEVICE_ID_BCM4401          0x4401
 581  #define PCI_DEVICE_ID_BCM4401B0                0x4402
 582 +#define PCI_DEVICE_ID_BCM4713          0x4713
 583
 584  #define PCI_VENDOR_ID_ENE              0x1524
 585  #define PCI_DEVICE_ID_ENE_1211         0x1211