openwrt/target/linux/image/generic/lzma-loader/src/start.S

   1 #include <asm/asm.h>
   2 #include <asm/regdef.h>
   3
   4 #define KSEG0           0x80000000
   5
   6 #define C0_CONFIG       $16
   7 #define C0_TAGLO        $28
   8 #define C0_TAGHI        $29
   9
  10 #define CONF1_DA_SHIFT  7                       /* D$ associativity */
  11 #define CONF1_DA_MASK   0x00000380
  12 #define CONF1_DA_BASE   1
  13 #define CONF1_DL_SHIFT  10                      /* D$ line size */
  14 #define CONF1_DL_MASK   0x00001c00
  15 #define CONF1_DL_BASE   2
  16 #define CONF1_DS_SHIFT  13                      /* D$ sets/way */
  17 #define CONF1_DS_MASK   0x0000e000
  18 #define CONF1_DS_BASE   64
  19 #define CONF1_IA_SHIFT  16                      /* I$ associativity */
  20 #define CONF1_IA_MASK   0x00070000
  21 #define CONF1_IA_BASE   1
  22 #define CONF1_IL_SHIFT  19                      /* I$ line size */
  23 #define CONF1_IL_MASK   0x00380000
  24 #define CONF1_IL_BASE   2
  25 #define CONF1_IS_SHIFT  22                      /* Instruction cache sets/way */
  26 #define CONF1_IS_MASK   0x01c00000
  27 #define CONF1_IS_BASE   64
  28
  29 #define Index_Invalidate_I      0x00
  30 #define Index_Writeback_Inv_D   0x01
  31
  32 LEAF(_start)
  33
  34         .set    mips32
  35         .set noreorder
  36
  37         /* set up stack */
  38         li      sp, 0xa0000000 + RAMSIZE - 16
  39
  40
  41         /* At this point we need to invalidate dcache and */
  42         /* icache before jumping to new code */
  43
  44 1:      /* Get cache sizes */
  45         mfc0    s0,C0_CONFIG,1
  46
  47         li      s1,CONF1_DL_MASK
  48         and     s1,s0
  49         beq     s1,zero,nodc
  50         nop
  51
  52         srl     s1,CONF1_DL_SHIFT
  53         li      t0,CONF1_DL_BASE
  54         sll     s1,t0,s1                /* s1 has D$ cache line size */
  55
  56         li      s2,CONF1_DA_MASK
  57         and     s2,s0
  58         srl     s2,CONF1_DA_SHIFT
  59         addiu   s2,CONF1_DA_BASE        /* s2 now has D$ associativity */
  60
  61         li      t0,CONF1_DS_MASK
  62         and     t0,s0
  63         srl     t0,CONF1_DS_SHIFT
  64         li      s3,CONF1_DS_BASE
  65         sll     s3,s3,t0                /* s3 has D$ sets per way */
  66
  67         multu   s2,s3                   /* sets/way * associativity */
  68         mflo    t0                      /* total cache lines */
  69
  70         multu   s1,t0                   /* D$ linesize * lines */
  71         mflo    s2                      /* s2 is now D$ size in bytes */
  72
  73         /* Initilize the D$: */
  74         mtc0    zero,C0_TAGLO
  75         mtc0    zero,C0_TAGHI
  76
  77         li      t0,KSEG0                /* Just an address for the first $ line */
  78         addu    t1,t0,s2                /*  + size of cache == end */
  79
  80 1:      cache   Index_Writeback_Inv_D,0(t0)
  81         bne     t0,t1,1b
  82         addu    t0,s1
  83
  84 nodc:
  85         /* Now we get to do it all again for the I$ */
  86
  87         move    s3,zero                 /* just in case there is no icache */
  88         move    s4,zero
  89
  90         li      t0,CONF1_IL_MASK
  91         and     t0,s0
  92         beq     t0,zero,noic
  93         nop
  94
  95         srl     t0,CONF1_IL_SHIFT
  96         li      s3,CONF1_IL_BASE
  97         sll     s3,t0                   /* s3 has I$ cache line size */
  98
  99         li      t0,CONF1_IA_MASK
 100         and     t0,s0
 101         srl     t0,CONF1_IA_SHIFT
 102         addiu   s4,t0,CONF1_IA_BASE     /* s4 now has I$ associativity */
 103
 104         li      t0,CONF1_IS_MASK
 105         and     t0,s0
 106         srl     t0,CONF1_IS_SHIFT
 107         li      s5,CONF1_IS_BASE
 108         sll     s5,t0                   /* s5 has I$ sets per way */
 109
 110         multu   s4,s5                   /* sets/way * associativity */
 111         mflo    t0                      /* s4 is now total cache lines */
 112
 113         multu   s3,t0                   /* I$ linesize * lines */
 114         mflo    s4                      /* s4 is cache size in bytes */
 115
 116         /* Initilize the I$: */
 117         mtc0    zero,C0_TAGLO
 118         mtc0    zero,C0_TAGHI
 119
 120         li      t0,KSEG0                /* Just an address for the first $ line */
 121         addu    t1,t0,s4                /*  + size of cache == end */
 122
 123 1:      cache   Index_Invalidate_I,0(t0)
 124         bne     t0,t1,1b
 125         addu    t0,s3
 126 noic:
 127         /* jump to main */
 128         move    a0,s3                   /* icache line size */
 129         move    a1,s4                   /* icache size */
 130         move    a2,s1                   /* dcache line size */
 131         jal     entry
 132         move    a3,s2                   /* dcache size */
 133
 134         .set reorder
 135 END(_start)
 136