openwrt/toolchain/gdb/patches/830-arm_gcc4.patch

   1 diff -ur gdb-6.3/sim/arm/iwmmxt.c gdb-6.3-owrt/sim/arm/iwmmxt.c
   2 --- gdb-6.3/sim/arm/iwmmxt.c    2003-03-27 18:13:33.000000000 +0100
   3 +++ gdb-6.3-owrt/sim/arm/iwmmxt.c       2006-04-12 15:06:03.000000000 +0200
   4 @@ -2114,7 +2114,7 @@
   5
   6           s = (signed long) a * (signed long) b;
   7
   8 -         (signed long long) t += s;
   9 +         t = t + (ARMdword) s;
  10          }
  11        else
  12          {
  13 @@ -2130,7 +2130,7 @@
  14      wR [BITS (12, 15)] = 0;
  15
  16    if (BIT (21))        /* Signed.  */
  17 -    (signed long long) wR[BITS (12, 15)] += (signed long long) t;
  18 +    wR[BITS (12, 15)] += t;
  19    else
  20      wR [BITS (12, 15)] += t;
  21
  22 @@ -2166,7 +2166,7 @@
  23           b = wRHALF (BITS (0, 3), i * 2);
  24           b = EXTEND16 (b);
  25
  26 -         (signed long) s1 = a * b;
  27 +         s1 = (ARMdword) (a * b);
  28
  29           a = wRHALF (BITS (16, 19), i * 2 + 1);
  30           a = EXTEND16 (a);
  31 @@ -2174,7 +2174,7 @@
  32           b = wRHALF (BITS (0, 3), i * 2 + 1);
  33           b = EXTEND16 (b);
  34
  35 -         (signed long) s2 = a * b;
  36 +         s2 = (ARMdword) (a * b);
  37          }
  38        else                     /* Unsigned.  */
  39          {
  40 @@ -2183,12 +2183,12 @@
  41           a = wRHALF (BITS (16, 19), i * 2);
  42           b = wRHALF (BITS ( 0,  3), i * 2);
  43
  44 -         (unsigned long) s1 = a * b;
  45 +         s1 = (ARMdword) (a * b);
  46
  47           a = wRHALF (BITS (16, 19), i * 2 + 1);
  48           b = wRHALF (BITS ( 0,  3), i * 2 + 1);
  49
  50 -         (signed long) s2 = a * b;
  51 +         s2 = (ARMdword) a * b;
  52          }
  53
  54        r |= (ARMdword) ((s1 + s2) & 0xffffffff) << (i ? 32 : 0);
  55 @@ -2914,9 +2914,9 @@
  56
  57      case Dqual:
  58        if (shift > 63)
  59 -       r = (wR [BITS (16, 19)] & 0x8000000000000000) ? 0xffffffffffffffff : 0;
  60 +       r = (wR [BITS (16, 19)] & 0x8000000000000000ULL) ? 0xffffffffffffffffULL : 0;
  61        else
  62 -       r = ((signed long long) (wR[BITS (16, 19)] & 0xffffffffffffffff) >> shift);
  63 +       r = ((signed long long) (wR[BITS (16, 19)] & 0xffffffffffffffffULL) >> shift);
  64        SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
  65        SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
  66        break;
  67 @@ -2985,7 +2985,7 @@
  68        if (shift > 63)
  69         r = 0;
  70        else
  71 -       r = (wR [BITS (16, 19)] & 0xffffffffffffffff) >> shift;
  72 +       r = (wR [BITS (16, 19)] & 0xffffffffffffffffULL) >> shift;
  73
  74        SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
  75        SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
  76 @@ -3287,7 +3287,7 @@
  77        r = wRWORD (BITS (16, 19), 1);
  78
  79        if (BIT (21) && NBIT32 (r))
  80 -       r |= 0xffffffff00000000;
  81 +       r |= 0xffffffff00000000ULL;
  82
  83        SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
  84        SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
  85 @@ -3354,7 +3354,7 @@
  86        r = wRWORD (BITS (16, 19), 0);
  87
  88        if (BIT (21) && NBIT32 (r))
  89 -       r |= 0xffffffff00000000;
  90 +       r |= 0xffffffff00000000ULL;
  91
  92        SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
  93        SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);