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[openwrt/staging/wigyori.git] / package / boot / uboot-kirkwood / patches / 007-nsa310-uboot-generic.patch
1
2 arm: kirkwood: add ZyXEL NSA310 device
3
4 This patch add ZyXEL NSA310 1-Bay Media Server
5
6 The ZyXEL NSA310 device is a Kirkwood based NAS:
7
8 - SoC: Marvell 88F6702 1200Mhz
9 - SDRAM memory: 256MB DDR2 400Mhz
10 - Gigabit ethernet: PHY Realtek
11 - Flash memory: 128MB
12 - 1 Power button
13 - 1 Power LED (blue)
14 - 5 Status LED (green/red)
15 - 1 Copy/Sync button
16 - 1 Reset button
17 - 2 SATA II port (1 internal and 1 external eSata)
18 - 2 USB 2.0 ports (1 front and 1 back)
19 - Smart fan
20
21 Signed-off-by: Alberto Bursi <alberto.bursi@outlook.it>
22
23 NOTE: this patch is ready for upstream, LEDE-specific parts are in
24 another patch
25
26 diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
27 index 9205b1e..819bd3b 100644
28 --- a/arch/arm/mach-kirkwood/Kconfig
29 +++ b/arch/arm/mach-kirkwood/Kconfig
30 @@ -53,6 +53,9 @@ config TARGET_GOFLEXHOME
31 config TARGET_NAS220
32 bool "BlackArmor NAS220"
33
34 +config TARGET_NSA310
35 + bool "Zyxel NSA310 Board"
36 +
37 config TARGET_NSA310S
38 bool "Zyxel NSA310S"
39
40 @@ -77,6 +80,7 @@ source "board/raidsonic/ib62x0/Kconfig"
41 source "board/Seagate/dockstar/Kconfig"
42 source "board/Seagate/goflexhome/Kconfig"
43 source "board/Seagate/nas220/Kconfig"
44 +source "board/zyxel/nsa310/Kconfig"
45 source "board/zyxel/nsa310s/Kconfig"
46
47 endif
48 diff --git a/board/zyxel/nsa310/Kconfig b/board/zyxel/nsa310/Kconfig
49 new file mode 100644
50 index 0000000..145ade6
51 --- /dev/null
52 +++ b/board/zyxel/nsa310/Kconfig
53 @@ -0,0 +1,12 @@
54 +if TARGET_NSA310
55 +
56 +config SYS_BOARD
57 + default "nsa310"
58 +
59 +config SYS_VENDOR
60 + default "zyxel"
61 +
62 +config SYS_CONFIG_NAME
63 + default "nsa310"
64 +
65 +endif
66 diff --git a/board/zyxel/nsa310/MAINTAINERS b/board/zyxel/nsa310/MAINTAINERS
67 new file mode 100644
68 index 0000000..d09f1ab
69 --- /dev/null
70 +++ b/board/zyxel/nsa310/MAINTAINERS
71 @@ -0,0 +1,6 @@
72 +NSA310 BOARD
73 +M: Alberto Bursi <alberto.bursi@outlook.it>
74 +S: Maintained
75 +F: board/zyxel/nsa310/
76 +F: include/configs/nsa310.h
77 +F: configs/nsa310_defconfig
78 diff --git a/board/zyxel/nsa310/Makefile b/board/zyxel/nsa310/Makefile
79 new file mode 100644
80 index 0000000..dfe93cc
81 --- /dev/null
82 +++ b/board/zyxel/nsa310/Makefile
83 @@ -0,0 +1,12 @@
84 +#
85 +# (C) Copyright 2015 bodhi <mibodhi@gmail.com>
86 +#
87 +# Based on
88 +# (C) Copyright 2009
89 +# Marvell Semiconductor <www.marvell.com>
90 +# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
91 +#
92 +# SPDX-License-Identifier: GPL-2.0+
93 +#
94 +
95 +obj-y := nsa310.o
96 diff --git a/board/zyxel/nsa310/kwbimage.cfg b/board/zyxel/nsa310/kwbimage.cfg
97 new file mode 100644
98 index 0000000..f60e1d2
99 --- /dev/null
100 +++ b/board/zyxel/nsa310/kwbimage.cfg
101 @@ -0,0 +1,166 @@
102 +#
103 +# Copyright (C) 2013 Rafal Kazmierowski
104 +#
105 +# Based on guruplug.c originally written by
106 +# Siddarth Gore <gores@marvell.com>
107 +# (C) Copyright 2009
108 +# Marvell Semiconductor <www.marvell.com>
109 +#
110 +# See file CREDITS for list of people who contributed to this
111 +# project.
112 +#
113 +# This program is free software; you can redistribute it and/or
114 +# modify it under the terms of the GNU General Public License as
115 +# published by the Free Software Foundation; either version 2 of
116 +# the License, or (at your option) any later version.
117 +#
118 +# This program is distributed in the hope that it will be useful,
119 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
120 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
121 +# GNU General Public License for more details.
122 +#
123 +# You should have received a copy of the GNU General Public License
124 +# along with this program; if not, write to the Free Software
125 +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
126 +# MA 02110-1301 USA
127 +#
128 +# Refer docs/README.kwimage for more details about how-to configure
129 +# and create kirkwood boot image
130 +#
131 +
132 +# Boot Media configurations
133 +BOOT_FROM nand
134 +#BOOT_FROM uart
135 +NAND_ECC_MODE default
136 +NAND_PAGE_SIZE 0x0800
137 +
138 +# SOC registers configuration using bootrom header extension
139 +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
140 +
141 +# Configure RGMII-0 interface pad voltage to 1.8V
142 +DATA 0xFFD100e0 0x1b1b1b9b
143 +
144 +#Dram initalization for SINGLE x16 CL=5 @ 400MHz
145 +DATA 0xFFD01400 0x43010c30 # DDR Configuration register
146 +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
147 +# bit23-14: zero
148 +# bit24: 1= enable exit self refresh mode on DDR access
149 +# bit25: 1 required
150 +# bit29-26: zero
151 +# bit31-30: 01
152 +
153 +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
154 +# bit 4: 0=addr/cmd in smame cycle
155 +# bit 5: 0=clk is driven during self refresh, we don't care for APX
156 +# bit 6: 0=use recommended falling edge of clk for addr/cmd
157 +# bit14: 0=input buffer always powered up
158 +# bit18: 1=cpu lock transaction enabled
159 +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
160 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
161 +# bit30-28: 3 required
162 +# bit31: 0=no additional STARTBURST delay
163 +
164 +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
165 +# bit3-0: TRAS lsbs
166 +# bit7-4: TRCD
167 +# bit11- 8: TRP
168 +# bit15-12: TWR
169 +# bit19-16: TWTR
170 +# bit20: TRAS msb
171 +# bit23-21: 0x0
172 +# bit27-24: TRRD
173 +# bit31-28: TRTP
174 +
175 +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
176 +# bit6-0: TRFC
177 +# bit8-7: TR2R
178 +# bit10-9: TR2W
179 +# bit12-11: TW2W
180 +# bit31-13: zero required
181 +
182 +DATA 0xFFD01410 0x0000000c # DDR Address Control
183 +# bit1-0: 01, Cs0width=x8
184 +# bit3-2: 10, Cs0size=1Gb
185 +# bit5-4: 01, Cs1width=x8
186 +# bit7-6: 10, Cs1size=1Gb
187 +# bit9-8: 00, Cs2width=nonexistent
188 +# bit11-10: 00, Cs2size =nonexistent
189 +# bit13-12: 00, Cs3width=nonexistent
190 +# bit15-14: 00, Cs3size =nonexistent
191 +# bit16: 0, Cs0AddrSel
192 +# bit17: 0, Cs1AddrSel
193 +# bit18: 0, Cs2AddrSel
194 +# bit19: 0, Cs3AddrSel
195 +# bit31-20: 0 required
196 +
197 +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
198 +# bit0: 0, OpenPage enabled
199 +# bit31-1: 0 required
200 +
201 +DATA 0xFFD01418 0x00000000 # DDR Operation
202 +# bit3-0: 0x0, DDR cmd
203 +# bit31-4: 0 required
204 +
205 +DATA 0xFFD0141C 0x00000652 # DDR Mode
206 +# bit2-0: 2, BurstLen=2 required
207 +# bit3: 0, BurstType=0 required
208 +# bit6-4: 4, CL=5
209 +# bit7: 0, TestMode=0 normal
210 +# bit8: 0, DLL reset=0 normal
211 +# bit11-9: 6, auto-precharge write recovery ????????????
212 +# bit12: 0, PD must be zero
213 +# bit31-13: 0 required
214 +
215 +DATA 0xFFD01420 0x00000004 # DDR Extended Mode
216 +# bit0: 0, DDR DLL enabled
217 +# bit1: 0, DDR drive strenght normal
218 +# bit2: 0, DDR ODT control lsd (disabled)
219 +# bit5-3: 000, required
220 +# bit6: 1, DDR ODT control msb, (disabled)
221 +# bit9-7: 000, required
222 +# bit10: 0, differential DQS enabled
223 +# bit11: 0, required
224 +# bit12: 0, DDR output buffer enabled
225 +# bit31-13: 0 required
226 +
227 +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
228 +# bit2-0: 111, required
229 +# bit3 : 1 , MBUS Burst Chop disabled
230 +# bit6-4: 111, required
231 +# bit7 : 0
232 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
233 +# bit9 : 0 , no half clock cycle addition to dataout
234 +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
235 +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
236 +# bit15-12: 1111 required
237 +# bit31-16: 0 required
238 +
239 +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
240 +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
241 +
242 +
243 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
244 +#DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
245 +# bit0: 1, Window enabled
246 +# bit1: 0, Write Protect disabled
247 +# bit3-2: 00, CS0 hit selected
248 +# bit23-4: ones, required
249 +# bit31-24: 0x0F, Size (i.e. 256MB)
250 +
251 +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
252 +DATA 0xFFD0150C 0x00000000 # CS[2]n Size, window disabled KAZ z 400db
253 +DATA 0xFFD01514 0x00000000 # CS[3]n Size, window disabled
254 +
255 +DATA 0xFFD0151C 0x00000000 # DDR ODT Control (Low)
256 +DATA 0xFFD01494 0x00120012 # DDR ODT Control (High) KAZ z nowy STATIC_SDRAM_ODT_CTRL_LOW
257 +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
258 +# bit3-2: 01, ODT1 active NEVER!
259 +# bit31-4: zero, required
260 +
261 +DATA 0xFFD01498 0x00000000 # CPU ODT Control KAZ STATIC_SDRAM_ODT_CTRL_HI
262 +DATA 0xFFD0149C 0x0000E403 # DDR Initialization Control KAZ STATIC_SDRAM_DUNIT_ODT_CTRL
263 +DATA 0xFFD01480 0x00000001 # DDR Initialization Control
264 +#bit0=1, enable DDR init upon this register write
265 +
266 +# End of Header extension
267 +DATA 0x0 0x0
268 diff --git a/board/zyxel/nsa310/nsa310.c b/board/zyxel/nsa310/nsa310.c
269 new file mode 100644
270 index 0000000..eee3f1a
271 --- /dev/null
272 +++ b/board/zyxel/nsa310/nsa310.c
273 @@ -0,0 +1,190 @@
274 +/*
275 + * Copyright (C) 2013 Rafal Kazmierowski
276 + *
277 + * Based on NSA320.c Peter Schildmann <linux@schildmann.info>
278 + * originally written by
279 + * Marvell Semiconductor <www.marvell.com>
280 + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
281 + *
282 + * See file CREDITS for list of people who contributed to this
283 + * project.
284 + *
285 + * This program is free software; you can redistribute it and/or
286 + * modify it under the terms of the GNU General Public License as
287 + * published by the Free Software Foundation; either version 2 of
288 + * the License, or (at your option) any later version.
289 + *
290 + * This program is distributed in the hope that it will be useful,
291 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
292 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
293 + * GNU General Public License for more details.
294 + *
295 + * You should have received a copy of the GNU General Public License
296 + * along with this program; if not, write to the Free Software
297 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
298 + * MA 02110-1301 USA
299 + */
300 +
301 +#include <common.h>
302 +#include <miiphy.h>
303 +#include <asm/arch/cpu.h>
304 +#include <asm/arch/soc.h>
305 +#include <asm/arch/mpp.h>
306 +#include <asm/io.h>
307 +#include "nsa310.h"
308 +
309 +DECLARE_GLOBAL_DATA_PTR;
310 +
311 +int board_early_init_f(void)
312 +{
313 + /*
314 + * default gpio configuration
315 + * There are maximum 64 gpios controlled through 2 sets of registers
316 + * the below configuration configures mainly initial LED status
317 + */
318 + mvebu_config_gpio(NSA310_VAL_LOW, NSA310_VAL_HIGH,
319 + NSA310_OE_LOW, NSA310_OE_HIGH);
320 +
321 + /* Multi-Purpose Pins Functionality configuration */
322 + /* (all LEDs & power off active high) */
323 + static const u32 kwmpp_config[] = {
324 + MPP0_NF_IO2,
325 + MPP1_NF_IO3,
326 + MPP2_NF_IO4,
327 + MPP3_NF_IO5,
328 + MPP4_NF_IO6,
329 + MPP5_NF_IO7,
330 + MPP6_SYSRST_OUTn,
331 + MPP7_GPO,
332 + MPP8_TW_SDA, /* PCF8563 RTC chip */
333 + MPP9_TW_SCK, /* connected to TWSI */
334 + MPP10_UART0_TXD,
335 + MPP11_UART0_RXD,
336 + MPP12_GPO, /* SATA2 LED (green) */
337 + MPP13_GPIO, /* SATA2 LED (red) */
338 + MPP14_GPIO, /* MCU DATA pin (in) */
339 + MPP15_GPIO, /* USB LED (green) */
340 + MPP16_GPIO, /* MCU CLK pin (out) */
341 + MPP17_GPIO, /* MCU ACT pin (out) */
342 + MPP18_NF_IO0,
343 + MPP19_NF_IO1,
344 + MPP20_GPIO,
345 + MPP21_GPIO, /* USB LED (red)-Power*/
346 + MPP22_GPIO,
347 + MPP23_GPIO,
348 + MPP24_GPIO,
349 + MPP25_GPIO,
350 + MPP26_GPIO,
351 + MPP27_GPIO,
352 + MPP28_GPIO, /* SYS LED (green) */
353 + MPP29_GPIO, /* SYS LED (red) */
354 + MPP30_GPIO,
355 + MPP31_GPIO,
356 + MPP32_GPIO,
357 + MPP33_GPIO,
358 + MPP34_GPIO,
359 + MPP35_GPIO,
360 + MPP36_GPIO, /* Reset button */
361 + MPP37_GPIO, /* Copy button */
362 + MPP38_GPIO, /* VID B0 */
363 + MPP39_GPIO, /* COPY LED (green) */
364 + MPP40_GPIO, /* COPY LED (red) */
365 + MPP41_GPIO, /* SATA1 LED (green) */
366 + MPP42_GPIO, /* SATA1 LED (red) */
367 + MPP43_GPIO, /* HTP pin */
368 + MPP44_GPIO, /* Buzzer */
369 + MPP45_GPIO, /* VID B1 */
370 + MPP46_GPIO, /* Power button */
371 + MPP47_GPIO, /* Power resume data */
372 + MPP48_GPIO, /* Power off */
373 + MPP49_GPIO, /* Power resume clock */
374 + 0
375 + };
376 + kirkwood_mpp_conf(kwmpp_config,NULL);
377 + return 0;
378 +}
379 +
380 +int board_init(void)
381 +{
382 + /* address of boot parameters */
383 + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
384 +
385 + return 0;
386 +}
387 +
388 +#ifdef CONFIG_RESET_PHY_R
389 +/* Configure and enable MV88E1318 PHY */
390 +void reset_phy(void)
391 +{
392 + u16 reg;
393 + u16 devadr;
394 + char *name = "egiga0";
395 +
396 + if (miiphy_set_current_dev(name))
397 + return;
398 +
399 + /* command to read PHY dev address */
400 + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
401 + printf("Err..%s could not read PHY dev address\n",
402 + __FUNCTION__);
403 + return;
404 + }
405 +
406 + /* Set RGMII delay */
407 + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 2);
408 + miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, &reg);
409 + reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL);
410 + miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg);
411 + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
412 +
413 + /* reset the phy */
414 + miiphy_reset(name, devadr);
415 +
416 + printf("MV88E1318 PHY initialized on %s\n", name);
417 +}
418 +#endif /* CONFIG_RESET_PHY_R */
419 +
420 +#ifdef CONFIG_SHOW_BOOT_PROGRESS
421 +void show_boot_progress(int val)
422 +{
423 + struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
424 + u32 dout0 = readl(&gpio0->dout);
425 + u32 blen0 = readl(&gpio0->blink_en);
426 +
427 + struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
428 + u32 dout1 = readl(&gpio1->dout);
429 + u32 blen1 = readl(&gpio1->blink_en);
430 +
431 + switch (val) {
432 + case BOOTSTAGE_ID_DECOMP_IMAGE:
433 + writel(blen0 & ~(SYS_GREEN_LED | SYS_RED_LED), &gpio0->blink_en);
434 + writel((dout0 & ~SYS_GREEN_LED) | SYS_RED_LED, &gpio0->dout);
435 + break;
436 + case BOOTSTAGE_ID_RUN_OS:
437 + writel(dout0 & ~SYS_RED_LED, &gpio0->dout);
438 + writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en);
439 + break;
440 + case BOOTSTAGE_ID_NET_START:
441 + writel(dout1 & ~COPY_RED_LED, &gpio1->dout);
442 + writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en);
443 + break;
444 + case BOOTSTAGE_ID_NET_LOADED:
445 + writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en);
446 + writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout);
447 + break;
448 + case -BOOTSTAGE_ID_NET_NETLOOP_OK:
449 + case -BOOTSTAGE_ID_NET_LOADED:
450 + writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout);
451 + writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en);
452 + break;
453 + default:
454 + if (val < 0) {
455 + /* error */
456 + printf("Error occured, error code = %d\n", -val);
457 + writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout);
458 + writel(blen0 | SYS_RED_LED, &gpio0->blink_en);
459 + }
460 + break;
461 + }
462 +}
463 +#endif
464 diff --git a/board/zyxel/nsa310/nsa310.h b/board/zyxel/nsa310/nsa310.h
465 new file mode 100644
466 index 0000000..6634a4f
467 --- /dev/null
468 +++ b/board/zyxel/nsa310/nsa310.h
469 @@ -0,0 +1,56 @@
470 +/*
471 + * Copyright (C) 2013 Rafal Kazmierowski
472 + *
473 + * Based on Peter Schildmann <linux@schildmann.info>
474 + * and guruplug.h originally written by
475 + * Siddarth Gore <gores@marvell.com>
476 + * (C) Copyright 2009
477 + * Marvell Semiconductor <www.marvell.com>
478 + *
479 + * See file CREDITS for list of people who contributed to this
480 + * project.
481 + *
482 + * This program is free software; you can redistribute it and/or
483 + * modify it under the terms of the GNU General Public License as
484 + * published by the Free Software Foundation; either version 2 of
485 + * the License, or (at your option) any later version.
486 + *
487 + * This program is distributed in the hope that it will be useful,
488 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
489 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
490 + * GNU General Public License for more details.
491 + *
492 + * You should have received a copy of the GNU General Public License
493 + * along with this program; if not, write to the Free Software
494 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
495 + * MA 02110-1301 USA
496 + */
497 +
498 +#ifndef __NSA310_H
499 +#define __NSA310_H
500 +
501 +/* GPIO's */
502 +#define SYS_GREEN_LED (1 << 28)
503 +#define SYS_RED_LED (1 << 29)
504 +#define SATA1_GREEN_LED (1 << 41)
505 +#define SATA1_RED_LED (1 << 42)
506 +#define SATA2_GREEN_LED (1 << 12)
507 +#define SATA2_RED_LED (1 << 13)
508 +#define USB_GREEN_LED (1 << 15)
509 +#define USB_RED_LED (1 << 21)
510 +#define COPY_GREEN_LED (1 << 39)
511 +#define COPY_RED_LED (1 << 40)
512 +
513 +#define NSA310_OE_LOW (0)
514 +#define NSA310_VAL_LOW (SYS_GREEN_LED)
515 +#define NSA310_OE_HIGH ((COPY_GREEN_LED | COPY_RED_LED | \
516 + SATA1_GREEN_LED | SATA1_RED_LED))
517 +#define NSA310_VAL_HIGH (0)
518 +
519 +/* PHY related */
520 +#define MV88E1318_MAC_CTRL_REG 21
521 +#define MV88E1318_PGADR_REG 22
522 +#define MV88E1318_RGMII_TXTM_CTRL (1 << 4)
523 +#define MV88E1318_RGMII_RXTM_CTRL (1 << 5)
524 +
525 +#endif /* __NSA310_H */
526 diff --git a/configs/nsa310_defconfig b/configs/nsa310_defconfig
527 new file mode 100644
528 index 0000000..d26ef35
529 --- /dev/null
530 +++ b/configs/nsa310_defconfig
531 @@ -0,0 +1,22 @@
532 +CONFIG_ARM=y
533 +CONFIG_KIRKWOOD=y
534 +CONFIG_TARGET_NSA310=y
535 +CONFIG_IDENT_STRING="\nZyXEL NSA310 1-Bay Power Media Server"
536 +CONFIG_BOOTDELAY=3
537 +CONFIG_SYS_PROMPT="NSA310> "
538 +# CONFIG_CMD_IMLS is not set
539 +# CONFIG_CMD_FLASH is not set
540 +CONFIG_SYS_NS16550=y
541 +CONFIG_CMD_FDT=y
542 +CONFIG_OF_LIBFDT=y
543 +CONFIG_CMD_SETEXPR=y
544 +CONFIG_CMD_DHCP=y
545 +CONFIG_CMD_MII=y
546 +CONFIG_CMD_PING=y
547 +CONFIG_CMD_USB=y
548 +CONFIG_CMD_EXT2=y
549 +CONFIG_CMD_FAT=y
550 +CONFIG_EFI_PARTITION=y
551 +CONFIG_CMD_UBI=y
552 +CONFIG_USB=y
553 +CONFIG_USB_STORAGE=y
554 diff --git a/include/configs/nsa310.h b/include/configs/nsa310.h
555 new file mode 100644
556 index 0000000..86ef825
557 --- /dev/null
558 +++ b/include/configs/nsa310.h
559 @@ -0,0 +1,144 @@
560 +/* Copyright (C) 2015-2016 bodhi <mibodhi@gmail.com>
561 + *
562 + * Based on
563 + * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info>
564 + *
565 + * Based on guruplug.h originally written by
566 + * Siddarth Gore <gores@marvell.com>
567 + * (C) Copyright 2009
568 + * Marvell Semiconductor <www.marvell.com>
569 + *
570 + * See file CREDITS for list of people who contributed to this
571 + * project.
572 + *
573 + * This program is free software; you can redistribute it and/or
574 + * modify it under the terms of the GNU General Public License as
575 + * published by the Free Software Foundation; either version 2 of
576 + * the License, or (at your option) any later version.
577 + *
578 + * This program is distributed in the hope that it will be useful,
579 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
580 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
581 + * GNU General Public License for more details.
582 + *
583 + * You should have received a copy of the GNU General Public License
584 + * along with this program; if not, write to the Free Software
585 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
586 + * MA 02110-1301 USA
587 + */
588 +
589 +#ifndef _CONFIG_NSA310_H
590 +#define _CONFIG_NSA310_H
591 +
592 +/*
593 + * High Level Configuration Options (easy to change)
594 + */
595 +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
596 +#define CONFIG_KW88F6281 /* SOC Name */
597 +#define CONFIG_MACH_NSA310 /* Machine type */
598 +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
599 +
600 +/*
601 + * Misc Configuration Options
602 + */
603 +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progess display (LED's) */
604 +
605 +/*
606 + * Commands configuration
607 + */
608 +#define CONFIG_CMD_ENV
609 +#define CONFIG_CMD_IDE
610 +#define CONFIG_CMD_NAND
611 +#define CONFIG_CMD_DATE
612 +#define CONFIG_SYS_LONGHELP
613 +#define CONFIG_PREBOOT
614 +#define CONFIG_SYS_HUSH_PARSER
615 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
616 +
617 +/*
618 + * mv-common.h should be defined after CMD configs since it used them
619 + * to enable certain macros
620 + */
621 +#include "mv-common.h"
622 +
623 +/*
624 + * Environment variables configurations
625 + */
626 +#ifdef CONFIG_CMD_NAND
627 +#define CONFIG_ENV_IS_IN_NAND 1
628 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
629 +#else
630 +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
631 +#endif
632 +
633 +/* max 4k env size is enough, but in case of nand
634 + * it has to be rounded to sector size
635 + */
636 +#define CONFIG_ENV_SIZE 0x20000 /* 128k */
637 +#define CONFIG_ENV_ADDR 0xc0000
638 +#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here */
639 +
640 +/*
641 + * Default environment variables
642 + */
643 +#define CONFIG_BOOTCOMMAND \
644 + "ubi part ubi; " \
645 + "ubi read 0x800000 kernel; " \
646 + "bootm 0x800000"
647 +
648 +#define CONFIG_MTDPARTS \
649 + "mtdparts=orion_nand:" \
650 + "0x0c0000(uboot)," \
651 + "0x80000(uboot_env)," \
652 + "0x7ec0000(ubi)\0"
653 +
654 +#define CONFIG_EXTRA_ENV_SETTINGS \
655 + "console=console=ttyS0,115200\0" \
656 + "mtdids=nand0=orion_nand\0" \
657 + "mtdparts="CONFIG_MTDPARTS \
658 + "bootargs_root=\0"
659 +
660 +/*
661 + * Ethernet Driver configuration
662 + */
663 +#ifdef CONFIG_CMD_NET
664 +#define CONFIG_NETCONSOLE
665 +#define CONFIG_NET_MULTI
666 +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
667 +#define CONFIG_PHY_BASE_ADR 0x1
668 +#define CONFIG_PHY_GIGE
669 +#define CONFIG_RESET_PHY_R
670 +#endif /* CONFIG_CMD_NET */
671 +
672 +/*
673 + * SATA Driver configuration
674 + */
675 +#ifdef CONFIG_MVSATA_IDE
676 +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
677 +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
678 +#endif /* CONFIG_MVSATA_IDE */
679 +
680 +/*
681 + * File system
682 + */
683 +#define CONFIG_CMD_EXT4
684 +#define CONFIG_CMD_JFFS2
685 +#define CONFIG_JFFS2_NAND
686 +#define CONFIG_JFFS2_LZO
687 +#define CONFIG_CMD_UBIFS
688 +#define CONFIG_RBTREE
689 +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
690 +#define CONFIG_MTD_PARTITIONS
691 +#define CONFIG_CMD_MTDPARTS
692 +#define CONFIG_LZO
693 +
694 +/*
695 + * Date Time
696 + */
697 +#ifdef CONFIG_CMD_DATE
698 +#define CONFIG_RTC_MV
699 +#define CONFIG_CMD_SNTP
700 +#define CONFIG_CMD_DNS
701 +#endif /* CONFIG_CMD_DATE */
702 +
703 +#endif /* _CONFIG_NSA310_H */
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