package/boot/uboot-kirkwood/patches/007-nsa310-uboot-generic.patch

   1
   2 arm: kirkwood: add ZyXEL NSA310 device
   3
   4 This patch add ZyXEL NSA310 1-Bay Media Server
   5
   6 The ZyXEL NSA310 device is a Kirkwood based NAS:
   7
   8 - SoC: Marvell 88F6702 1200Mhz
   9 - SDRAM memory: 256MB DDR2 400Mhz
  10 - Gigabit ethernet: PHY Realtek
  11 - Flash memory: 128MB
  12 - 1 Power button
  13 - 1 Power LED (blue)
  14 - 5 Status LED (green/red)
  15 - 1 Copy/Sync button
  16 - 1 Reset button
  17 - 2 SATA II port (1 internal and 1 external eSata)
  18 - 2 USB 2.0 ports (1 front and 1 back)
  19 - Smart fan
  20
  21 Signed-off-by: Alberto Bursi <alberto.bursi@outlook.it>
  22
  23 NOTE: this patch is ready for upstream, LEDE-specific parts are in
  24       another patch
  25
  26 --- a/arch/arm/mach-kirkwood/Kconfig
  27 +++ b/arch/arm/mach-kirkwood/Kconfig
  28 @@ -56,6 +56,9 @@ config TARGET_GOFLEXHOME
  29  config TARGET_NAS220
  30         bool "BlackArmor NAS220"
  31
  32 +config TARGET_NSA310
  33 +       bool "Zyxel NSA310 Board"
  34 +
  35  config TARGET_NSA310S
  36         bool "Zyxel NSA310S"
  37
  38 @@ -86,6 +89,7 @@ source "board/raidsonic/ib62x0/Kconfig"
  39  source "board/Seagate/dockstar/Kconfig"
  40  source "board/Seagate/goflexhome/Kconfig"
  41  source "board/Seagate/nas220/Kconfig"
  42 +source "board/zyxel/nsa310/Kconfig"
  43  source "board/zyxel/nsa310s/Kconfig"
  44  source "board/alliedtelesis/SBx81LIFKW/Kconfig"
  45  source "board/alliedtelesis/SBx81LIFXCAT/Kconfig"
  46 --- /dev/null
  47 +++ b/board/zyxel/nsa310/Kconfig
  48 @@ -0,0 +1,12 @@
  49 +if TARGET_NSA310
  50 +
  51 +config SYS_BOARD
  52 +       default "nsa310"
  53 +
  54 +config SYS_VENDOR
  55 +       default "zyxel"
  56 +
  57 +config SYS_CONFIG_NAME
  58 +       default "nsa310"
  59 +
  60 +endif
  61 --- /dev/null
  62 +++ b/board/zyxel/nsa310/MAINTAINERS
  63 @@ -0,0 +1,6 @@
  64 +NSA310 BOARD
  65 +M:     Alberto Bursi <alberto.bursi@outlook.it>
  66 +S:     Maintained
  67 +F:     board/zyxel/nsa310/
  68 +F:     include/configs/nsa310.h
  69 +F:     configs/nsa310_defconfig
  70 --- /dev/null
  71 +++ b/board/zyxel/nsa310/Makefile
  72 @@ -0,0 +1,12 @@
  73 +#
  74 +# (C) Copyright 2015 bodhi <mibodhi@gmail.com>
  75 +#
  76 +# Based on
  77 +# (C) Copyright 2009
  78 +# Marvell Semiconductor <www.marvell.com>
  79 +# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  80 +#
  81 +# SPDX-License-Identifier:     GPL-2.0+
  82 +#
  83 +
  84 +obj-y  := nsa310.o
  85 --- /dev/null
  86 +++ b/board/zyxel/nsa310/kwbimage.cfg
  87 @@ -0,0 +1,166 @@
  88 +#
  89 +# Copyright (C) 2013  Rafal Kazmierowski
  90 +#
  91 +# Based on guruplug.c originally written by
  92 +# Siddarth Gore <gores@marvell.com>
  93 +# (C) Copyright 2009
  94 +# Marvell Semiconductor <www.marvell.com>
  95 +#
  96 +# See file CREDITS for list of people who contributed to this
  97 +# project.
  98 +#
  99 +# This program is free software; you can redistribute it and/or
 100 +# modify it under the terms of the GNU General Public License as
 101 +# published by the Free Software Foundation; either version 2 of
 102 +# the License, or (at your option) any later version.
 103 +#
 104 +# This program is distributed in the hope that it will be useful,
 105 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
 106 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 107 +# GNU General Public License for more details.
 108 +#
 109 +# You should have received a copy of the GNU General Public License
 110 +# along with this program; if not, write to the Free Software
 111 +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 112 +# MA 02110-1301 USA
 113 +#
 114 +# Refer docs/README.kwimage for more details about how-to configure
 115 +# and create kirkwood boot image
 116 +#
 117 +
 118 +# Boot Media configurations
 119 +BOOT_FROM      nand
 120 +#BOOT_FROM     uart
 121 +NAND_ECC_MODE  default
 122 +NAND_PAGE_SIZE 0x0800
 123 +
 124 +# SOC registers configuration using bootrom header extension
 125 +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
 126 +
 127 +# Configure RGMII-0 interface pad voltage to 1.8V
 128 +DATA 0xFFD100e0 0x1b1b1b9b
 129 +
 130 +#Dram initalization for SINGLE x16 CL=5 @ 400MHz
 131 +DATA 0xFFD01400 0x43010c30     # DDR Configuration register
 132 +# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
 133 +# bit23-14: zero
 134 +# bit24: 1= enable exit self refresh mode on DDR access
 135 +# bit25: 1 required
 136 +# bit29-26: zero
 137 +# bit31-30: 01
 138 +
 139 +DATA 0xFFD01404 0x37543000     # DDR Controller Control Low
 140 +# bit 4:    0=addr/cmd in smame cycle
 141 +# bit 5:    0=clk is driven during self refresh, we don't care for APX
 142 +# bit 6:    0=use recommended falling edge of clk for addr/cmd
 143 +# bit14:    0=input buffer always powered up
 144 +# bit18:    1=cpu lock transaction enabled
 145 +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
 146 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
 147 +# bit30-28: 3 required
 148 +# bit31:    0=no additional STARTBURST delay
 149 +
 150 +DATA 0xFFD01408 0x22125451     # DDR Timing (Low) (active cycles value +1)
 151 +# bit3-0:   TRAS lsbs
 152 +# bit7-4:   TRCD
 153 +# bit11- 8: TRP
 154 +# bit15-12: TWR
 155 +# bit19-16: TWTR
 156 +# bit20:    TRAS msb
 157 +# bit23-21: 0x0
 158 +# bit27-24: TRRD
 159 +# bit31-28: TRTP
 160 +
 161 +DATA 0xFFD0140C 0x00000a33     #  DDR Timing (High)
 162 +# bit6-0:   TRFC
 163 +# bit8-7:   TR2R
 164 +# bit10-9:  TR2W
 165 +# bit12-11: TW2W
 166 +# bit31-13: zero required
 167 +
 168 +DATA 0xFFD01410 0x0000000c     #  DDR Address Control
 169 +# bit1-0:   01, Cs0width=x8
 170 +# bit3-2:   10, Cs0size=1Gb
 171 +# bit5-4:   01, Cs1width=x8
 172 +# bit7-6:   10, Cs1size=1Gb
 173 +# bit9-8:   00, Cs2width=nonexistent
 174 +# bit11-10: 00, Cs2size =nonexistent
 175 +# bit13-12: 00, Cs3width=nonexistent
 176 +# bit15-14: 00, Cs3size =nonexistent
 177 +# bit16:    0,  Cs0AddrSel
 178 +# bit17:    0,  Cs1AddrSel
 179 +# bit18:    0,  Cs2AddrSel
 180 +# bit19:    0,  Cs3AddrSel
 181 +# bit31-20: 0 required
 182 +
 183 +DATA 0xFFD01414 0x00000000     #  DDR Open Pages Control
 184 +# bit0:    0,  OpenPage enabled
 185 +# bit31-1: 0 required
 186 +
 187 +DATA 0xFFD01418 0x00000000     #  DDR Operation
 188 +# bit3-0:   0x0, DDR cmd
 189 +# bit31-4:  0 required
 190 +
 191 +DATA 0xFFD0141C 0x00000652     #  DDR Mode
 192 +# bit2-0:   2, BurstLen=2 required
 193 +# bit3:     0, BurstType=0 required
 194 +# bit6-4:   4, CL=5
 195 +# bit7:     0, TestMode=0 normal
 196 +# bit8:     0, DLL reset=0 normal
 197 +# bit11-9:  6, auto-precharge write recovery ????????????
 198 +# bit12:    0, PD must be zero
 199 +# bit31-13: 0 required
 200 +
 201 +DATA 0xFFD01420 0x00000004     #  DDR Extended Mode
 202 +# bit0:    0,  DDR DLL enabled
 203 +# bit1:    0,  DDR drive strenght normal
 204 +# bit2:    0,  DDR ODT control lsd (disabled)
 205 +# bit5-3:  000, required
 206 +# bit6:    1,  DDR ODT control msb, (disabled)
 207 +# bit9-7:  000, required
 208 +# bit10:   0,  differential DQS enabled
 209 +# bit11:   0, required
 210 +# bit12:   0, DDR output buffer enabled
 211 +# bit31-13: 0 required
 212 +
 213 +DATA 0xFFD01424 0x0000F17F     #  DDR Controller Control High
 214 +# bit2-0:  111, required
 215 +# bit3  :  1  , MBUS Burst Chop disabled
 216 +# bit6-4:  111, required
 217 +# bit7  :  0
 218 +# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
 219 +# bit9  :  0  , no half clock cycle addition to dataout
 220 +# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
 221 +# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
 222 +# bit15-12: 1111 required
 223 +# bit31-16: 0    required
 224 +
 225 +DATA 0xFFD01428 0x00085520     # DDR2 ODT Read Timing (default values)
 226 +DATA 0xFFD0147C 0x00008552     # DDR2 ODT Write Timing (default values)
 227 +
 228 +
 229 +DATA 0xFFD01504 0x0FFFFFF1     # CS[0]n Size
 230 +#DATA 0xFFD01500 0x00000000    # CS[0]n Base address to 0x0
 231 +# bit0:    1,  Window enabled
 232 +# bit1:    0,  Write Protect disabled
 233 +# bit3-2:  00, CS0 hit selected
 234 +# bit23-4: ones, required
 235 +# bit31-24: 0x0F, Size (i.e. 256MB)
 236 +
 237 +DATA 0xFFD01508 0x10000000     # CS[1]n Base address to 256Mb
 238 +DATA 0xFFD0150C 0x00000000     # CS[2]n Size, window disabled        KAZ z 400db
 239 +DATA 0xFFD01514 0x00000000     # CS[3]n Size, window disabled
 240 +
 241 +DATA 0xFFD0151C 0x00000000     #  DDR ODT Control (Low)
 242 +DATA 0xFFD01494 0x00120012     #  DDR ODT Control (High)              KAZ  z nowy  STATIC_SDRAM_ODT_CTRL_LOW
 243 +# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
 244 +# bit3-2:  01, ODT1 active NEVER!
 245 +# bit31-4: zero, required
 246 +
 247 +DATA 0xFFD01498 0x00000000     # CPU ODT Control                     KAZ STATIC_SDRAM_ODT_CTRL_HI
 248 +DATA 0xFFD0149C 0x0000E403     # DDR Initialization Control          KAZ STATIC_SDRAM_DUNIT_ODT_CTRL
 249 +DATA 0xFFD01480 0x00000001     # DDR Initialization Control
 250 +#bit0=1, enable DDR init upon this register write
 251 +
 252 +# End of Header extension
 253 +DATA 0x0 0x0
 254 --- /dev/null
 255 +++ b/board/zyxel/nsa310/nsa310.c
 256 @@ -0,0 +1,190 @@
 257 +/*
 258 + * Copyright (C) 2013 Rafal Kazmierowski
 259 + *
 260 + * Based on NSA320.c Peter Schildmann <linux@schildmann.info>
 261 + * originally written by
 262 + * Marvell Semiconductor <www.marvell.com>
 263 + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
 264 + *
 265 + * See file CREDITS for list of people who contributed to this
 266 + * project.
 267 + *
 268 + * This program is free software; you can redistribute it and/or
 269 + * modify it under the terms of the GNU General Public License as
 270 + * published by the Free Software Foundation; either version 2 of
 271 + * the License, or (at your option) any later version.
 272 + *
 273 + * This program is distributed in the hope that it will be useful,
 274 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 275 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 276 + * GNU General Public License for more details.
 277 + *
 278 + * You should have received a copy of the GNU General Public License
 279 + * along with this program; if not, write to the Free Software
 280 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 281 + * MA 02110-1301 USA
 282 + */
 283 +
 284 +#include <common.h>
 285 +#include <miiphy.h>
 286 +#include <asm/arch/cpu.h>
 287 +#include <asm/arch/soc.h>
 288 +#include <asm/arch/mpp.h>
 289 +#include <asm/io.h>
 290 +#include "nsa310.h"
 291 +
 292 +DECLARE_GLOBAL_DATA_PTR;
 293 +
 294 +int board_early_init_f(void)
 295 +{
 296 +       /*
 297 +        * default gpio configuration
 298 +        * There are maximum 64 gpios controlled through 2 sets of registers
 299 +        * the below configuration configures mainly initial LED status
 300 +        */
 301 +       mvebu_config_gpio(NSA310_VAL_LOW, NSA310_VAL_HIGH,
 302 +                      NSA310_OE_LOW, NSA310_OE_HIGH);
 303 +
 304 +       /* Multi-Purpose Pins Functionality configuration */
 305 +       /* (all LEDs & power off active high) */
 306 +       static const u32 kwmpp_config[] = {
 307 +               MPP0_NF_IO2,
 308 +               MPP1_NF_IO3,
 309 +               MPP2_NF_IO4,
 310 +               MPP3_NF_IO5,
 311 +               MPP4_NF_IO6,
 312 +               MPP5_NF_IO7,
 313 +               MPP6_SYSRST_OUTn,
 314 +               MPP7_GPO,
 315 +               MPP8_TW_SDA,    /* PCF8563 RTC chip   */
 316 +               MPP9_TW_SCK,    /* connected to TWSI  */
 317 +               MPP10_UART0_TXD,
 318 +               MPP11_UART0_RXD,
 319 +               MPP12_GPO,              /* SATA2 LED (green)  */
 320 +               MPP13_GPIO,             /* SATA2 LED (red)    */
 321 +               MPP14_GPIO,             /* MCU DATA pin (in)  */
 322 +               MPP15_GPIO,             /* USB LED (green)    */
 323 +               MPP16_GPIO,             /* MCU CLK pin (out)  */
 324 +               MPP17_GPIO,             /* MCU ACT pin (out)  */
 325 +               MPP18_NF_IO0,
 326 +               MPP19_NF_IO1,
 327 +               MPP20_GPIO,
 328 +               MPP21_GPIO,             /* USB LED (red)-Power*/
 329 +               MPP22_GPIO,
 330 +               MPP23_GPIO,
 331 +               MPP24_GPIO,
 332 +               MPP25_GPIO,
 333 +               MPP26_GPIO,
 334 +               MPP27_GPIO,
 335 +               MPP28_GPIO,             /* SYS LED (green)    */
 336 +               MPP29_GPIO,             /* SYS LED (red)      */
 337 +               MPP30_GPIO,
 338 +               MPP31_GPIO,
 339 +               MPP32_GPIO,
 340 +               MPP33_GPIO,
 341 +               MPP34_GPIO,
 342 +               MPP35_GPIO,
 343 +               MPP36_GPIO,             /* Reset button       */
 344 +               MPP37_GPIO,             /* Copy button        */
 345 +               MPP38_GPIO,             /* VID B0             */
 346 +               MPP39_GPIO,             /* COPY LED (green)   */
 347 +               MPP40_GPIO,             /* COPY LED (red)     */
 348 +               MPP41_GPIO,             /* SATA1 LED (green)  */
 349 +               MPP42_GPIO,             /* SATA1 LED (red)    */
 350 +               MPP43_GPIO,             /* HTP pin            */
 351 +               MPP44_GPIO,             /* Buzzer             */
 352 +               MPP45_GPIO,             /* VID B1             */
 353 +               MPP46_GPIO,             /* Power button       */
 354 +               MPP47_GPIO,             /* Power resume data  */
 355 +               MPP48_GPIO,             /* Power off          */
 356 +               MPP49_GPIO,             /* Power resume clock */
 357 +               0
 358 +       };
 359 +       kirkwood_mpp_conf(kwmpp_config,NULL);
 360 +       return 0;
 361 +}
 362 +
 363 +int board_init(void)
 364 +{
 365 +       /* address of boot parameters */
 366 +       gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 367 +
 368 +       return 0;
 369 +}
 370 +
 371 +#ifdef CONFIG_RESET_PHY_R
 372 +/* Configure and enable MV88E1318 PHY */
 373 +void reset_phy(void)
 374 +{
 375 +       u16 reg;
 376 +       u16 devadr;
 377 +       char *name = "egiga0";
 378 +
 379 +       if (miiphy_set_current_dev(name))
 380 +               return;
 381 +
 382 +       /* command to read PHY dev address */
 383 +       if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
 384 +               printf("Err..%s could not read PHY dev address\n",
 385 +                       __FUNCTION__);
 386 +               return;
 387 +       }
 388 +
 389 +       /* Set RGMII delay */
 390 +       miiphy_write(name, devadr, MV88E1318_PGADR_REG, 2);
 391 +       miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, &reg);
 392 +       reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL);
 393 +       miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg);
 394 +       miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
 395 +
 396 +       /* reset the phy */
 397 +       miiphy_reset(name, devadr);
 398 +
 399 +       printf("MV88E1318 PHY initialized on %s\n", name);
 400 +}
 401 +#endif /* CONFIG_RESET_PHY_R */
 402 +
 403 +#ifdef CONFIG_SHOW_BOOT_PROGRESS
 404 +void show_boot_progress(int val)
 405 +{
 406 +       struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
 407 +       u32 dout0 = readl(&gpio0->dout);
 408 +       u32 blen0 = readl(&gpio0->blink_en);
 409 +
 410 +       struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
 411 +       u32 dout1 = readl(&gpio1->dout);
 412 +       u32 blen1 = readl(&gpio1->blink_en);
 413 +
 414 +       switch (val) {
 415 +       case BOOTSTAGE_ID_DECOMP_IMAGE:
 416 +               writel(blen0 & ~(SYS_GREEN_LED | SYS_RED_LED), &gpio0->blink_en);
 417 +               writel((dout0 & ~SYS_GREEN_LED) | SYS_RED_LED, &gpio0->dout);
 418 +               break;
 419 +       case BOOTSTAGE_ID_RUN_OS:
 420 +               writel(dout0 & ~SYS_RED_LED, &gpio0->dout);
 421 +               writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en);
 422 +               break;
 423 +       case BOOTSTAGE_ID_NET_START:
 424 +               writel(dout1 & ~COPY_RED_LED, &gpio1->dout);
 425 +               writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en);
 426 +               break;
 427 +       case BOOTSTAGE_ID_NET_LOADED:
 428 +               writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en);
 429 +               writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout);
 430 +               break;
 431 +       case -BOOTSTAGE_ID_NET_NETLOOP_OK:
 432 +       case -BOOTSTAGE_ID_NET_LOADED:
 433 +               writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout);
 434 +               writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en);
 435 +               break;
 436 +       default:
 437 +               if (val < 0) {
 438 +                       /* error */
 439 +                       printf("Error occured, error code = %d\n", -val);
 440 +                       writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout);
 441 +                       writel(blen0 | SYS_RED_LED, &gpio0->blink_en);
 442 +               }
 443 +               break;
 444 +       }
 445 +}
 446 +#endif
 447 --- /dev/null
 448 +++ b/board/zyxel/nsa310/nsa310.h
 449 @@ -0,0 +1,56 @@
 450 +/*
 451 + * Copyright (C) 2013 Rafal Kazmierowski
 452 + *
 453 + * Based on Peter Schildmann <linux@schildmann.info>
 454 + * and  guruplug.h originally written by
 455 + * Siddarth Gore <gores@marvell.com>
 456 + * (C) Copyright 2009
 457 + * Marvell Semiconductor <www.marvell.com>
 458 + *
 459 + * See file CREDITS for list of people who contributed to this
 460 + * project.
 461 + *
 462 + * This program is free software; you can redistribute it and/or
 463 + * modify it under the terms of the GNU General Public License as
 464 + * published by the Free Software Foundation; either version 2 of
 465 + * the License, or (at your option) any later version.
 466 + *
 467 + * This program is distributed in the hope that it will be useful,
 468 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 469 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 470 + * GNU General Public License for more details.
 471 + *
 472 + * You should have received a copy of the GNU General Public License
 473 + * along with this program; if not, write to the Free Software
 474 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 475 + * MA 02110-1301 USA
 476 + */
 477 +
 478 +#ifndef __NSA310_H
 479 +#define __NSA310_H
 480 +
 481 +/* GPIO's */
 482 +#define SYS_GREEN_LED          (1 << 28)
 483 +#define SYS_RED_LED            (1 << 29)
 484 +#define SATA1_GREEN_LED                (1ULL << 41)
 485 +#define SATA1_RED_LED          (1ULL << 42)
 486 +#define SATA2_GREEN_LED                (1 << 12)
 487 +#define SATA2_RED_LED          (1 << 13)
 488 +#define USB_GREEN_LED          (1 << 15)
 489 +#define USB_RED_LED            (1 << 21)
 490 +#define COPY_GREEN_LED         (1ULL << 39)
 491 +#define COPY_RED_LED           (1ULL << 40)
 492 +
 493 +#define NSA310_OE_LOW   (0)
 494 +#define NSA310_VAL_LOW    (SYS_GREEN_LED)
 495 +#define NSA310_OE_HIGH         (((COPY_GREEN_LED | COPY_RED_LED | \
 496 +                                   SATA1_GREEN_LED | SATA1_RED_LED)) >> 32UL)
 497 +#define NSA310_VAL_HIGH                (0)
 498 +
 499 +/* PHY related */
 500 +#define MV88E1318_MAC_CTRL_REG         21
 501 +#define MV88E1318_PGADR_REG            22
 502 +#define MV88E1318_RGMII_TXTM_CTRL      (1 << 4)
 503 +#define MV88E1318_RGMII_RXTM_CTRL      (1 << 5)
 504 +
 505 +#endif /* __NSA310_H */
 506 --- /dev/null
 507 +++ b/configs/nsa310_defconfig
 508 @@ -0,0 +1,40 @@
 509 +CONFIG_ARM=y
 510 +CONFIG_KIRKWOOD=y
 511 +CONFIG_SYS_TEXT_BASE=0x600000
 512 +CONFIG_TARGET_NSA310=y
 513 +CONFIG_IDENT_STRING="\nZyXEL NSA310 1-Bay Power Media Server"
 514 +CONFIG_NR_DRAM_BANKS=2
 515 +CONFIG_BOOTDELAY=3
 516 +CONFIG_SYS_PROMPT="NSA310> "
 517 +# CONFIG_CMD_IMLS is not set
 518 +# CONFIG_CMD_FLASH is not set
 519 +CONFIG_MVGBE=y
 520 +CONFIG_MII=y
 521 +CONFIG_SYS_NS16550=y
 522 +CONFIG_CMD_FDT=y
 523 +CONFIG_OF_LIBFDT=y
 524 +CONFIG_CMD_SETEXPR=y
 525 +CONFIG_CMD_DHCP=y
 526 +CONFIG_CMD_MII=y
 527 +CONFIG_CMD_PING=y
 528 +CONFIG_CMD_DNS=y
 529 +CONFIG_CMD_SNTP=y
 530 +CONFIG_CMD_USB=y
 531 +CONFIG_CMD_DATE=y
 532 +CONFIG_CMD_EXT2=y
 533 +CONFIG_CMD_EXT4=y
 534 +CONFIG_CMD_FAT=y
 535 +CONFIG_CMD_JFFS2=y
 536 +CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x0c0000(uboot),0x80000(uboot_env),0x7ec0000(ubi)"
 537 +CONFIG_CMD_MTDPARTS=y
 538 +CONFIG_CMD_ENV=y
 539 +CONFIG_CMD_NAND=y
 540 +CONFIG_EFI_PARTITION=y
 541 +CONFIG_ENV_IS_IN_NAND=y
 542 +CONFIG_CMD_UBI=y
 543 +CONFIG_USB=y
 544 +CONFIG_USB_EHCI_HCD=y
 545 +CONFIG_USB_STORAGE=y
 546 +CONFIG_LZMA=y
 547 +CONFIG_LZO=y
 548 +CONFIG_SYS_LONGHELP=y
 549 --- /dev/null
 550 +++ b/include/configs/nsa310.h
 551 @@ -0,0 +1,117 @@
 552 +/* Copyright (C) 2015-2016 bodhi <mibodhi@gmail.com>
 553 + *
 554 + * Based on
 555 + * Copyright (C) 2012  Peter Schildmann <linux@schildmann.info>
 556 + *
 557 + * Based on guruplug.h originally written by
 558 + * Siddarth Gore <gores@marvell.com>
 559 + * (C) Copyright 2009
 560 + * Marvell Semiconductor <www.marvell.com>
 561 + *
 562 + * See file CREDITS for list of people who contributed to this
 563 + * project.
 564 + *
 565 + * This program is free software; you can redistribute it and/or
 566 + * modify it under the terms of the GNU General Public License as
 567 + * published by the Free Software Foundation; either version 2 of
 568 + * the License, or (at your option) any later version.
 569 + *
 570 + * This program is distributed in the hope that it will be useful,
 571 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 572 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 573 + * GNU General Public License for more details.
 574 + *
 575 + * You should have received a copy of the GNU General Public License
 576 + * along with this program; if not, write to the Free Software
 577 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 578 + * MA 02110-1301 USA
 579 + */
 580 +
 581 +#ifndef _CONFIG_NSA310_H
 582 +#define _CONFIG_NSA310_H
 583 +
 584 +/*
 585 + * High Level Configuration Options (easy to change)
 586 + */
 587 +#define CONFIG_FEROCEON_88FR131                /* CPU Core subversion */
 588 +#define CONFIG_KW88F6281               /* SOC Name */
 589 +
 590 +#define CONFIG_SKIP_LOWLEVEL_INIT      /* disable board lowlevel_init */
 591 +
 592 +/*
 593 + * Misc Configuration Options
 594 + */
 595 +#define CONFIG_SHOW_BOOT_PROGRESS 1     /* boot progess display (LED's) */
 596 +
 597 +/*
 598 + * Commands configuration
 599 + */
 600 +#define CONFIG_PREBOOT
 601 +
 602 +/*
 603 + * mv-common.h should be defined after CMD configs since it used them
 604 + * to enable certain macros
 605 + */
 606 +#include "mv-common.h"
 607 +
 608 +/*
 609 + * Environment variables configurations
 610 + */
 611 +#ifdef CONFIG_CMD_NAND
 612 +#define CONFIG_ENV_SECT_SIZE            0x20000         /* 128K */
 613 +#endif
 614 +
 615 +/* max 4k env size is enough, but in case of nand
 616 + * it has to be rounded to sector size
 617 + */
 618 +#define CONFIG_ENV_SIZE                 0x20000         /* 128k */
 619 +#define CONFIG_ENV_ADDR                 0xc0000
 620 +#define CONFIG_ENV_OFFSET               0xc0000 /* env starts here */
 621 +
 622 +/*
 623 + * Default environment variables
 624 + */
 625 +#define CONFIG_BOOTCOMMAND \
 626 +       "ubi part ubi; " \
 627 +       "ubi read 0x800000 kernel; " \
 628 +       "bootm 0x800000"
 629 +
 630 +#define CONFIG_EXTRA_ENV_SETTINGS \
 631 +       "console=console=ttyS0,115200\0"        \
 632 +       "mtdids=nand0=orion_nand\0"             \
 633 +       "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
 634 +       "bootargs_root=\0"
 635 +
 636 +/*
 637 + * Ethernet Driver configuration
 638 + */
 639 +#ifdef CONFIG_CMD_NET
 640 +#define CONFIG_NETCONSOLE
 641 +#define CONFIG_NET_MULTI
 642 +#define CONFIG_MVGBE_PORTS             {1, 0}  /* enable port 0 only */
 643 +#define CONFIG_PHY_BASE_ADR            0x1
 644 +#define CONFIG_RESET_PHY_R
 645 +#endif /* CONFIG_CMD_NET */
 646 +
 647 +/*
 648 + * SATA Driver configuration
 649 + */
 650 +#ifdef CONFIG_MVSATA_IDE
 651 +#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET
 652 +#define CONFIG_SYS_ATA_IDE1_OFFSET      MV_SATA_PORT1_OFFSET
 653 +#endif /* CONFIG_MVSATA_IDE */
 654 +
 655 +/*
 656 + * File system
 657 + */
 658 +#define CONFIG_JFFS2_NAND
 659 +#define CONFIG_JFFS2_LZO
 660 +
 661 +/*
 662 + *  Date Time
 663 + */
 664 +#ifdef CONFIG_CMD_DATE
 665 +#define CONFIG_RTC_MV
 666 +#endif /* CONFIG_CMD_DATE */
 667 +
 668 +#endif /* _CONFIG_NSA310_H */