package/boot/uboot-kirkwood/patches/008-nsa325-uboot-generic.patch

   1 --- a/arch/arm/mach-kirkwood/Kconfig
   2 +++ b/arch/arm/mach-kirkwood/Kconfig
   3 @@ -68,6 +68,9 @@ config TARGET_SBx81LIFKW
   4  config TARGET_SBx81LIFXCAT
   5         bool "Allied Telesis SBx81GP24/SBx81GT24"
   6
   7 +config TARGET_NSA325
   8 +       bool "Zyxel NSA325 board"
   9 +
  10  endchoice
  11
  12  config SYS_SOC
  13 @@ -91,6 +94,7 @@ source "board/Seagate/goflexhome/Kconfig
  14  source "board/Seagate/nas220/Kconfig"
  15  source "board/zyxel/nsa310/Kconfig"
  16  source "board/zyxel/nsa310s/Kconfig"
  17 +source "board/zyxel/nsa325/Kconfig"
  18  source "board/alliedtelesis/SBx81LIFKW/Kconfig"
  19  source "board/alliedtelesis/SBx81LIFXCAT/Kconfig"
  20
  21 --- /dev/null
  22 +++ b/board/zyxel/nsa325/Kconfig
  23 @@ -0,0 +1,12 @@
  24 +if TARGET_NSA325
  25 +
  26 +config SYS_BOARD
  27 +       default "nsa325"
  28 +
  29 +config SYS_VENDOR
  30 +       default "zyxel"
  31 +
  32 +config SYS_CONFIG_NAME
  33 +       default "nsa325"
  34 +
  35 +endif
  36 --- /dev/null
  37 +++ b/board/zyxel/nsa325/MAINTAINERS
  38 @@ -0,0 +1,6 @@
  39 +NSA325 BOARD
  40 +M:     Alberto Bursi <alberto.bursi@outlook.it>
  41 +S:     Maintained
  42 +F:     board/zyxel/nsa325/
  43 +F:     include/configs/nsa325.h
  44 +F:     configs/nsa325_defconfig
  45 --- /dev/null
  46 +++ b/board/zyxel/nsa325/Makefile
  47 @@ -0,0 +1,13 @@
  48 +#
  49 +# (C) Copyright 2015 bodhi <mibodhi@gmail.com>
  50 +#
  51 +# Based on
  52 +# (C) Copyright 2009
  53 +# Marvell Semiconductor <www.marvell.com>
  54 +# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  55 +#
  56 +# SPDX-License-Identifier:     GPL-2.0+
  57 +#
  58 +
  59 +obj-y  := nsa325.o
  60 +
  61 --- /dev/null
  62 +++ b/board/zyxel/nsa325/kwbimage.cfg
  63 @@ -0,0 +1,78 @@
  64 +# Copyright (C) 2015 bodhi <mibodhi@gmail.com>
  65 +#
  66 +# Extracted from Zyxel GPL source for u-boot-1.1.4_NSA325v2
  67 +#
  68 +# See file CREDITS for list of people who contributed to this
  69 +# project.
  70 +#
  71 +# This program is free software; you can redistribute it and/or
  72 +# modify it under the terms of the GNU General Public License as
  73 +# published by the Free Software Foundation; either version 2 of
  74 +# the License, or (at your option) any later version.
  75 +#
  76 +# This program is distributed in the hope that it will be useful,
  77 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  78 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  79 +# GNU General Public License for more details.
  80 +#
  81 +# You should have received a copy of the GNU General Public License
  82 +# along with this program; if not, write to the Free Software
  83 +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  84 +# MA 02110-1301 USA
  85 +#
  86 +# Refer docs/README.kwimage for more details about how-to configure
  87 +# and create kirkwood boot image
  88 +#
  89 +
  90 +# Boot Media configurations
  91 +#BOOT_FROM     uart
  92 +BOOT_FROM       nand
  93 +NAND_ECC_MODE   default
  94 +NAND_PAGE_SIZE  0x0800
  95 +
  96 +# SOC registers configuration using bootrom header extension
  97 +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
  98 +
  99 +# Configure RGMII-0 interface pad voltage to 1.8V
 100 +DATA 0xFFD100e0 0x1b1b1b9b
 101 +
 102 +#Dram initalization
 103 +DATA 0xFFD01400 0x4301503E      # DDR Configuration register
 104 +DATA 0xFFD01404 0xB9843000      # DDR Controller Control Low
 105 +DATA 0xFFD01408 0x33137777      # DDR Timing (Low)
 106 +DATA 0xFFD0140C 0x16000C55      # DDR Timing (High)
 107 +DATA 0xFFD01410 0x04000000      # DDR Address Control
 108 +DATA 0xFFD01414 0x00000000     #  DDR Open Pages Control
 109 +DATA 0xFFD01418 0x00000000     #  DDR Operation
 110 +DATA 0xFFD0141C 0x00000672     #  DDR Mode
 111 +DATA 0xFFD01420 0x00000004     #  DDR Extended Mode
 112 +DATA 0xFFD01424 0x0000F14F     #  DDR Controller Control High
 113 +DATA 0xFFD01428 0x000D6720     # DDR3 ODT Read Timing
 114 +DATA 0xFFD0147C 0x0000B571     # DDR2 ODT Write Timing
 115 +DATA 0xFFD01504 0x1FFFFFF1      # CS[0]n Size
 116 +DATA 0xFFD01508 0x20000000      # CS[1]n Base address to 512Mb
 117 +DATA 0xFFD0150C 0x1FFFFFF4      # CS[1]n Size 512Mb Window enabled for CS1
 118 +DATA 0xFFD01514 0x00000000      # CS[2]n Size, window disabled
 119 +DATA 0xFFD0151C 0x00000000      # CS[3]n Size, window disabled
 120 +DATA 0xFFD01494 0x00120000      #  DDR ODT Control (Low)
 121 +DATA 0xFFD01498 0x00000000      #  DDR ODT Control (High)
 122 +DATA 0xFFD0149C 0x0000E803      # CPU ODT Control
 123 +
 124 +DATA 0xFFD015D0 0x00000630
 125 +DATA 0xFFD015D4 0x00000046
 126 +DATA 0xFFD015D8 0x00000008
 127 +DATA 0xFFD015DC 0x00000000
 128 +DATA 0xFFD015E0 0x00000023
 129 +DATA 0xFFD015E4 0x00203C18
 130 +DATA 0xFFD01620 0x00384800
 131 +DATA 0xFFD01480 0x00000001
 132 +DATA 0xFFD20134 0x66666666
 133 +DATA 0xFFD20138 0x00066666
 134 +
 135 +#Disable nsa325 hardware watchdog to allow successful kwbooting
 136 +DATA 0xFFD10100 0x00004000 # set GPIO 14 to high to disable the watchdog
 137 +DATA 0xFFD10104 0xFFFFBFFF # set GPIO 14 to output (to block any other input to it)
 138 +
 139 +# End of Header extension
 140 +DATA 0x0 0x0
 141 +
 142 --- /dev/null
 143 +++ b/board/zyxel/nsa325/nsa325.c
 144 @@ -0,0 +1,265 @@
 145 +/*
 146 + * Copyright (C) 2015 bodhi <mibodhi@gmail.com>
 147 + *
 148 + * Based on
 149 + * Copyright (C) 2014  Jason Plum <jplum@archlinuxarm.org>
 150 + *
 151 + * Based on nsa320.c originall written by
 152 + * Copyright (C) 2012  Peter Schildmann <linux@schildmann.info>
 153 + *
 154 + * Based on guruplug.c originally written by
 155 + * Siddarth Gore <gores@marvell.com>
 156 + * (C) Copyright 2009
 157 + * Marvell Semiconductor <www.marvell.com>
 158 + *
 159 + * See file CREDITS for list of people who contributed to this
 160 + * project.
 161 + *
 162 + * This program is free software; you can redistribute it and/or
 163 + * modify it under the terms of the GNU General Public License as
 164 + * published by the Free Software Foundation; either version 2 of
 165 + * the License, or (at your option) any later version.
 166 + *
 167 + * This program is distributed in the hope that it will be useful,
 168 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 169 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 170 + * GNU General Public License for more details.
 171 + *
 172 + * You should have received a copy of the GNU General Public License
 173 + * along with this program; if not, write to the Free Software
 174 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 175 + * MA 02110-1301 USA
 176 + */
 177 +
 178 +#include <common.h>
 179 +#include <miiphy.h>
 180 +#include <asm/arch/soc.h>
 181 +#include <asm/arch/mpp.h>
 182 +#include <asm/arch/cpu.h>
 183 +#include <asm/gpio.h>
 184 +#include <asm/io.h>
 185 +#include "nsa325.h"
 186 +#include <asm/arch/gpio.h>
 187 +
 188 +DECLARE_GLOBAL_DATA_PTR;
 189 +
 190 +int board_early_init_f(void)
 191 +{
 192 +       /*
 193 +        * default gpio configuration
 194 +        * There are maximum 64 gpios controlled through 2 sets of registers
 195 +        * the below configuration configures mainly initial LED status
 196 +        */
 197 +       mvebu_config_gpio(NSA325_VAL_LOW, NSA325_VAL_HIGH,
 198 +                      NSA325_OE_LOW, NSA325_OE_HIGH);
 199 +
 200 +       /* Multi-Purpose Pins Functionality configuration */
 201 +       /* (all LEDs & power off active high) */
 202 +       u32 kwmpp_config[] = {
 203 +               MPP0_NF_IO2,
 204 +               MPP1_NF_IO3,
 205 +               MPP2_NF_IO4,
 206 +               MPP3_NF_IO5,
 207 +               MPP4_NF_IO6,
 208 +               MPP5_NF_IO7,
 209 +               MPP6_SYSRST_OUTn,
 210 +               MPP7_GPO,
 211 +               MPP8_TW_SDA,            /* PCF8563 RTC chip   */
 212 +               MPP9_TW_SCK,            /* connected to TWSI  */
 213 +               MPP10_UART0_TXD,
 214 +               MPP11_UART0_RXD,
 215 +               MPP12_GPO,              /* HDD2 LED (green)   */
 216 +               MPP13_GPIO,             /* HDD2 LED (red)     */
 217 +               MPP14_GPIO,             /* MCU DATA pin (in)  */
 218 +               MPP15_GPIO,             /* USB LED (green)    */
 219 +               MPP16_GPIO,             /* MCU CLK pin (out)  */
 220 +               MPP17_GPIO,             /* MCU ACT pin (out)  */
 221 +               MPP18_NF_IO0,
 222 +               MPP19_NF_IO1,
 223 +               MPP20_GPIO,
 224 +               MPP21_GPIO,             /* USB power          */
 225 +               MPP22_GPIO,
 226 +               MPP23_GPIO,
 227 +               MPP24_GPIO,
 228 +               MPP25_GPIO,
 229 +               MPP26_GPIO,
 230 +               MPP27_GPIO,
 231 +               MPP28_GPIO,             /* SYS LED (green)    */
 232 +               MPP29_GPIO,             /* SYS LED (orange)   */
 233 +               MPP30_GPIO,
 234 +               MPP31_GPIO,
 235 +               MPP32_GPIO,
 236 +               MPP33_GPIO,
 237 +               MPP34_GPIO,
 238 +               MPP35_GPIO,
 239 +               MPP36_GPIO,             /* reset button       */
 240 +               MPP37_GPIO,             /* copy button        */
 241 +               MPP38_GPIO,             /* VID B0             */
 242 +               MPP39_GPIO,             /* COPY LED (green)   */
 243 +               MPP40_GPIO,             /* COPY LED (red)     */
 244 +               MPP41_GPIO,             /* HDD1 LED (green)   */
 245 +               MPP42_GPIO,             /* HDD1 LED (red)     */
 246 +               MPP43_GPIO,             /* HTP pin            */
 247 +               MPP44_GPIO,             /* buzzer             */
 248 +               MPP45_GPIO,             /* VID B1             */
 249 +               MPP46_GPIO,             /* power button       */
 250 +               MPP47_GPIO,             /* HDD2 power         */
 251 +               MPP48_GPIO,             /* power off          */
 252 +               0
 253 +       };
 254 +       kirkwood_mpp_conf(kwmpp_config, NULL);
 255 +       return 0;
 256 +}
 257 +
 258 +int board_init(void)
 259 +{
 260 +
 261 +       /* address of boot parameters */
 262 +       gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 263 +
 264 +       /* This disables the hardware watchdog in the mcu on this board. */
 265 +       kw_gpio_set_valid(14, 1);
 266 +       kw_gpio_direction_output(14, 0);
 267 +       kw_gpio_set_value(14, 1);
 268 +
 269 +       return 0;
 270 +}
 271 +
 272 +#ifdef CONFIG_RESET_PHY_R
 273 +/* Configure and enable MV88E1318 PHY */
 274 +void reset_phy(void)
 275 +{
 276 +       u16 reg;
 277 +       u16 devadr;
 278 +       char *name = "egiga0";
 279 +
 280 +       if (miiphy_set_current_dev(name))
 281 +               return;
 282 +
 283 +       /* command to read PHY dev address */
 284 +       if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
 285 +               printf("Err..%s could not read PHY dev address\n",
 286 +                       __FUNCTION__);
 287 +               return;
 288 +       }
 289 +
 290 +       /* Set RGMII delay */
 291 +       miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
 292 +       miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, &reg);
 293 +       reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL);
 294 +       miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg);
 295 +       miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
 296 +
 297 +       /* reset the phy */
 298 +       miiphy_reset(name, devadr);
 299 +
 300 +       /* The ZyXEL NSA325 uses the 88E1310S Alaska (interface identical to 88E1318) */
 301 +       /* and has an MCU attached to the LED[2] via tristate interrupt */
 302 +       reg = 0;
 303 +
 304 +       /* switch to LED register page */
 305 +       miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
 306 +       /* read out LED polarity register */
 307 +       miiphy_read(name, devadr, MV88E1318_LED_POL_REG, &reg);
 308 +       /* clear 4, set 5 - LED2 low, tri-state */
 309 +       reg &= ~(MV88E1318_LED2_4);
 310 +       reg |= (MV88E1318_LED2_5);
 311 +       /* write back LED polarity register */
 312 +       miiphy_write(name, devadr, MV88E1318_LED_POL_REG, reg);
 313 +       /* jump back to page 0, per the PHY chip documenation. */
 314 +       miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
 315 +
 316 +       /* Set the phy back to auto-negotiation mode. Onboard mcu sets it as 10Mbits/s on poweroff for WoL function */
 317 +       miiphy_write(name, devadr, 0x4, 0x1e1);
 318 +       miiphy_write(name, devadr, 0x9, 0x300);
 319 +       /* Downshift */
 320 +       miiphy_write(name, devadr, 0x10, 0x3860);
 321 +       miiphy_write(name, devadr, 0x0, 0x9140);
 322 +
 323 +       printf("MV88E1318 PHY initialized on %s\n", name);
 324 +
 325 +}
 326 +#endif /* CONFIG_RESET_PHY_R */
 327 +
 328 +#ifdef CONFIG_SHOW_BOOT_PROGRESS
 329 +void show_boot_progress(int val)
 330 +{
 331 +       struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
 332 +       u32 dout0 = readl(&gpio0->dout);
 333 +       u32 blen0 = readl(&gpio0->blink_en);
 334 +
 335 +       struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
 336 +       u32 dout1 = readl(&gpio1->dout);
 337 +       u32 blen1 = readl(&gpio1->blink_en);
 338 +
 339 +       switch (val) {
 340 +       case BOOTSTAGE_ID_DECOMP_IMAGE:
 341 +               writel(blen0 & ~(SYS_GREEN_LED | SYS_ORANGE_LED), &gpio0->blink_en);
 342 +               writel((dout0 & ~SYS_GREEN_LED) | SYS_ORANGE_LED, &gpio0->dout);
 343 +               break;
 344 +       case BOOTSTAGE_ID_RUN_OS:
 345 +               writel(dout0 & ~SYS_ORANGE_LED, &gpio0->dout);
 346 +               writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en);
 347 +               break;
 348 +       case BOOTSTAGE_ID_NET_START:
 349 +               writel(dout1 & ~COPY_RED_LED, &gpio1->dout);
 350 +               writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en);
 351 +               break;
 352 +       case BOOTSTAGE_ID_NET_LOADED:
 353 +               writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en);
 354 +               writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout);
 355 +               break;
 356 +       case -BOOTSTAGE_ID_NET_NETLOOP_OK:
 357 +       case -BOOTSTAGE_ID_NET_LOADED:
 358 +               writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout);
 359 +               writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en);
 360 +               break;
 361 +       default:
 362 +               if (val < 0) {
 363 +                       /* error */
 364 +                       printf("Error occured, error code = %d\n", -val);
 365 +                       writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout);
 366 +                       writel(blen0 | SYS_ORANGE_LED, &gpio0->blink_en);
 367 +               }
 368 +               break;
 369 +       }
 370 +}
 371 +#endif
 372 +
 373 +#if defined(CONFIG_KIRKWOOD_GPIO)
 374 +/* Return GPIO button status */
 375 +/*
 376 +un-pressed:
 377 + gpio-36 (Reset Button ) in hi (act lo) - IRQ edge (clear )
 378 + gpio-37 (Copy Button  ) in hi (act lo) - IRQ edge (clear )
 379 + gpio-46 (Power Button ) in lo (act hi) - IRQ edge (clear )
 380 +pressed
 381 + gpio-36 (Reset Button ) in lo (act hi) - IRQ edge (clear )
 382 + gpio-37 (Copy Button  ) in lo (act hi) - IRQ edge (clear )
 383 + gpio-46 (Power Button ) in hi (act lo) - IRQ edge (clear )
 384 +*/
 385 +
 386 +static int
 387 +do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 388 +{
 389 +       if (strcmp(argv[1], "power") == 0) {
 390 +                       kw_gpio_set_valid(BTN_POWER, GPIO_INPUT_OK);
 391 +                       kw_gpio_direction_input(BTN_POWER);
 392 +                       return !kw_gpio_get_value(BTN_POWER);
 393 +       }
 394 +       else if (strcmp(argv[1], "reset") == 0)
 395 +               return kw_gpio_get_value(BTN_RESET);
 396 +       else if (strcmp(argv[1], "copy") == 0)
 397 +               return kw_gpio_get_value(BTN_COPY);
 398 +       else
 399 +               return -1;
 400 +}
 401 +
 402 +
 403 +U_BOOT_CMD(button, 2, 0, do_read_button,
 404 +          "Return GPIO button status 0=off 1=on",
 405 +          "- button power|reset|copy: test buttons states\n"
 406 +);
 407 +
 408 +#endif
 409 +
 410 --- /dev/null
 411 +++ b/board/zyxel/nsa325/nsa325.h
 412 @@ -0,0 +1,77 @@
 413 +/*
 414 + * Copyright (C) 2014  Jason Plum <jplum@archlinuxarm.org>
 415 + *
 416 + * Based on nsa320.h originall written by
 417 + * Copyright (C) 2012  Peter Schildmann <linux@schildmann.info>
 418 + *
 419 + * Based on guruplug.h originally written by
 420 + * Siddarth Gore <gores@marvell.com>
 421 + * (C) Copyright 2009
 422 + * Marvell Semiconductor <www.marvell.com>
 423 + *
 424 + * See file CREDITS for list of people who contributed to this
 425 + * project.
 426 + *
 427 + * This program is free software; you can redistribute it and/or
 428 + * modify it under the terms of the GNU General Public License as
 429 + * published by the Free Software Foundation; either version 2 of
 430 + * the License, or (at your option) any later version.
 431 + *
 432 + * This program is distributed in the hope that it will be useful,
 433 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 434 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 435 + * GNU General Public License for more details.
 436 + *
 437 + * You should have received a copy of the GNU General Public License
 438 + * along with this program; if not, write to the Free Software
 439 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 440 + * MA 02110-1301 USA
 441 + */
 442 +
 443 +#ifndef __NSA325_H
 444 +#define __NSA325_H
 445 +
 446 +/* low GPIO's */
 447 +#define HDD2_GREEN_LED         (1 << 12)
 448 +#define HDD2_RED_LED           (1 << 13)
 449 +#define USB_GREEN_LED          (1 << 15)
 450 +#define USB_POWER              (1 << 21)
 451 +#define SYS_GREEN_LED          (1 << 28)
 452 +#define SYS_ORANGE_LED         (1 << 29)
 453 +
 454 +#define PIN_USB_GREEN_LED      15
 455 +#define PIN_USB_POWER          21
 456 +
 457 +#define NSA325_OE_LOW          (~(HDD2_GREEN_LED | HDD2_RED_LED | \
 458 +                                  USB_GREEN_LED | USB_POWER | \
 459 +                                  SYS_GREEN_LED | SYS_ORANGE_LED))
 460 +#define NSA325_VAL_LOW         (SYS_GREEN_LED | USB_POWER)
 461 +
 462 +/* high GPIO's */
 463 +#define COPY_GREEN_LED         (1 << 7)
 464 +#define COPY_RED_LED           (1 << 8)
 465 +#define HDD1_GREEN_LED         (1 << 9)
 466 +#define HDD1_RED_LED           (1 << 10)
 467 +#define HDD2_POWER          (1 << 15)
 468 +#define WATCHDOG_SIGNAL     (1 << 14)
 469 +
 470 +#define NSA325_OE_HIGH         (~(COPY_GREEN_LED | COPY_RED_LED | \
 471 +                                  HDD1_GREEN_LED | HDD1_RED_LED | HDD2_POWER | WATCHDOG_SIGNAL ))
 472 +#define NSA325_VAL_HIGH                (WATCHDOG_SIGNAL | HDD2_POWER)
 473 +
 474 +/* PHY related */
 475 +#define MV88E1318_PGADR_REG            22
 476 +#define MV88E1318_MAC_CTRL_PG  2
 477 +#define MV88E1318_MAC_CTRL_REG 21
 478 +#define MV88E1318_RGMII_TXTM_CTRL      (1 << 4)
 479 +#define MV88E1318_RGMII_RXTM_CTRL      (1 << 5)
 480 +#define MV88E1318_LED_PG        3
 481 +#define MV88E1318_LED_POL_REG  17
 482 +#define MV88E1318_LED2_4           (1 << 4)
 483 +#define MV88E1318_LED2_5           (1 << 5)
 484 +
 485 +#define BTN_POWER                              46
 486 +#define BTN_RESET                              36
 487 +#define BTN_COPY                               37
 488 +
 489 +#endif /* __NSA325_H */
 490 --- /dev/null
 491 +++ b/configs/nsa325_defconfig
 492 @@ -0,0 +1,40 @@
 493 +CONFIG_ARM=y
 494 +CONFIG_KIRKWOOD=y
 495 +CONFIG_SYS_TEXT_BASE=0x600000
 496 +CONFIG_TARGET_NSA325=y
 497 +CONFIG_IDENT_STRING="\nZyXEL NSA325 2-Bay Power Media Server"
 498 +CONFIG_NR_DRAM_BANKS=2
 499 +CONFIG_BOOTDELAY=3
 500 +CONFIG_SYS_PROMPT="NSA325> "
 501 +# CONFIG_CMD_IMLS is not set
 502 +# CONFIG_CMD_FLASH is not set
 503 +CONFIG_MVGBE=y
 504 +CONFIG_MII=y
 505 +CONFIG_SYS_NS16550=y
 506 +CONFIG_CMD_FDT=y
 507 +CONFIG_OF_LIBFDT=y
 508 +CONFIG_CMD_SETEXPR=y
 509 +CONFIG_CMD_DHCP=y
 510 +CONFIG_CMD_MII=y
 511 +CONFIG_CMD_PING=y
 512 +CONFIG_CMD_DNS=y
 513 +CONFIG_CMD_SNTP=y
 514 +CONFIG_CMD_USB=y
 515 +CONFIG_USB=y
 516 +CONFIG_CMD_DATE=y
 517 +CONFIG_CMD_EXT2=y
 518 +CONFIG_CMD_EXT4=y
 519 +CONFIG_CMD_FAT=y
 520 +CONFIG_CMD_JFFS2=y
 521 +CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x0c0000(uboot),0x80000(uboot_env),0x7ec0000(ubi)"
 522 +CONFIG_CMD_MTDPARTS=y
 523 +CONFIG_CMD_ENV=y
 524 +CONFIG_CMD_NAND=y
 525 +CONFIG_EFI_PARTITION=y
 526 +CONFIG_ENV_IS_IN_NAND=y
 527 +CONFIG_CMD_UBI=y
 528 +CONFIG_USB_EHCI_HCD=y
 529 +CONFIG_USB_STORAGE=y
 530 +CONFIG_LZMA=y
 531 +CONFIG_LZO=y
 532 +CONFIG_SYS_LONGHELP=y
 533 --- /dev/null
 534 +++ b/include/configs/nsa325.h
 535 @@ -0,0 +1,120 @@
 536 +/*
 537 + * (C) Copyright 2016 bodhi <mibodhi@gmail.com>
 538 + *
 539 + * Based on
 540 + * Copyright (C) 2014 Jason Plum <jplum@archlinuxarm.org>
 541 + * Based on
 542 + * Copyright (C) 2012  Peter Schildmann <linux@schildmann.info>
 543 + *
 544 + * Based on guruplug.h originally written by
 545 + * Siddarth Gore <gores@marvell.com>
 546 + * (C) Copyright 2009
 547 + * Marvell Semiconductor <www.marvell.com>
 548 + *
 549 + * See file CREDITS for list of people who contributed to this
 550 + * project.
 551 + *
 552 + * This program is free software; you can redistribute it and/or
 553 + * modify it under the terms of the GNU General Public License as
 554 + * published by the Free Software Foundation; either version 2 of
 555 + * the License, or (at your option) any later version.
 556 + *
 557 + * This program is distributed in the hope that it will be useful,
 558 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 559 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 560 + * GNU General Public License for more details.
 561 + *
 562 + * You should have received a copy of the GNU General Public License
 563 + * along with this program; if not, write to the Free Software
 564 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 565 + * MA 02110-1301 USA
 566 + */
 567 +
 568 +#ifndef _CONFIG_NSA325_H
 569 +#define _CONFIG_NSA325_H
 570 +
 571 +/*
 572 + * High Level Configuration Options (easy to change)
 573 + */
 574 +#define CONFIG_FEROCEON_88FR131        1       /* CPU Core subversion */
 575 +#define CONFIG_KW88F6281       1       /* SOC Name */
 576 +
 577 +#define CONFIG_SKIP_LOWLEVEL_INIT      /* disable board lowlevel_init */
 578 +
 579 +/*
 580 + * Misc Configuration Options
 581 + */
 582 +#define CONFIG_SHOW_BOOT_PROGRESS 1    /* boot progess display (LED's) */
 583 +
 584 +/*
 585 + * Commands configuration
 586 + */
 587 +#define CONFIG_PREBOOT
 588 +
 589 +/*
 590 + * mv-common.h should be defined after CMD configs since it used them
 591 + * to enable certain macros
 592 + */
 593 +#include "mv-common.h"
 594 +
 595 +/*
 596 + *  Environment variables configurations
 597 + */
 598 +#ifdef CONFIG_CMD_NAND
 599 +#define CONFIG_ENV_SECT_SIZE           0x20000         /* 128K */
 600 +#endif
 601 +/*
 602 + * max 4k env size is enough, but in case of nand
 603 + * it has to be rounded to sector size
 604 + */
 605 +#define CONFIG_ENV_SIZE                        0x20000         /* 128k */
 606 +#define CONFIG_ENV_ADDR                        0xc0000
 607 +#define CONFIG_ENV_OFFSET              0xc0000 /* env starts here */
 608 +
 609 +/*
 610 + * Default environment variables
 611 + */
 612 +#define CONFIG_BOOTCOMMAND \
 613 +       "ubi part ubi; " \
 614 +       "ubi read 0x800000 kernel; " \
 615 +       "bootm 0x800000"
 616 +
 617 +#define CONFIG_EXTRA_ENV_SETTINGS \
 618 +       "console=console=ttyS0,115200\0"        \
 619 +       "mtdids=nand0=orion_nand\0"             \
 620 +       "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
 621 +       "bootargs_root=\0"
 622 +
 623 +/*
 624 + * Ethernet Driver configuration
 625 + */
 626 +#ifdef CONFIG_CMD_NET
 627 +#define CONFIG_MVGBE_PORTS             {1, 0}  /* enable port 0 only */
 628 +#define CONFIG_PHY_BASE_ADR            0x1
 629 +#define CONFIG_NETCONSOLE
 630 +#endif /* CONFIG_CMD_NET */
 631 +
 632 +/*
 633 + * SATA Driver configuration
 634 + */
 635 +#ifdef CONFIG_MVSATA_IDE
 636 +#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET
 637 +#define CONFIG_SYS_ATA_IDE1_OFFSET      MV_SATA_PORT1_OFFSET
 638 +#endif /* CONFIG_MVSATA_IDE */
 639 +
 640 +/*
 641 + * File system
 642 + */
 643 +#define CONFIG_JFFS2_NAND
 644 +#define CONFIG_JFFS2_LZO
 645 +
 646 +/*
 647 + *  Date Time
 648 + */
 649 +#ifdef CONFIG_CMD_DATE
 650 +#define CONFIG_RTC_MV
 651 +#endif /* CONFIG_CMD_DATE */
 652 +
 653 +#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */
 654 +
 655 +#endif /* _CONFIG_NSA325_H */