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uboot-kirkwood: update to 2019.01
[openwrt/staging/wigyori.git] / package / boot / uboot-kirkwood / patches / 010-pogoplug_v4.patch
1 --- a/arch/arm/mach-kirkwood/Kconfig
2 +++ b/arch/arm/mach-kirkwood/Kconfig
3 @@ -25,6 +25,9 @@ config TARGET_LSXL
4 config TARGET_POGO_E02
5 bool "pogo_e02 Board"
6
7 +config TARGET_POGOPLUGV4
8 + bool "Pogoplug V4 Board"
9 +
10 config TARGET_DNS325
11 bool "dns325 Board"
12
13 @@ -83,6 +86,7 @@ source "board/Marvell/guruplug/Kconfig"
14 source "board/Marvell/sheevaplug/Kconfig"
15 source "board/buffalo/lsxl/Kconfig"
16 source "board/cloudengines/pogo_e02/Kconfig"
17 +source "board/cloudengines/pogoplugv4/Kconfig"
18 source "board/d-link/dns325/Kconfig"
19 source "board/iomega/iconnect/Kconfig"
20 source "board/keymile/km_arm/Kconfig"
21 --- a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h
22 +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h
23 @@ -15,6 +15,6 @@
24 #define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE
25
26 /* TCLK Core Clock defination */
27 -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
28 +#define CONFIG_SYS_TCLK 166666667 /* 166MHz */
29
30 #endif /* _CONFIG_KW88F6192_H */
31 --- a/arch/arm/mach-kirkwood/include/mach/mpp.h
32 +++ b/arch/arm/mach-kirkwood/include/mach/mpp.h
33 @@ -216,10 +216,12 @@
34 #define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 )
35 #define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 )
36 #define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 )
37 +#define MPP33_SATA1_ACTn MPP( 33, 0x5, 0, 1, 0, 1, 1, 1 )
38
39 #define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 )
40 #define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 )
41 #define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 )
42 +#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 1, 1, 1 )
43
44 #define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 )
45 #define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 )
46 --- /dev/null
47 +++ b/board/cloudengines/pogoplugv4/Kconfig
48 @@ -0,0 +1,12 @@
49 +if TARGET_POGOPLUGV4
50 +
51 +config SYS_BOARD
52 + default "pogoplugv4"
53 +
54 +config SYS_VENDOR
55 + default "cloudengines"
56 +
57 +config SYS_CONFIG_NAME
58 + default "pogoplugv4"
59 +
60 +endif
61 --- /dev/null
62 +++ b/board/cloudengines/pogoplugv4/MAINTAINERS
63 @@ -0,0 +1,6 @@
64 +POGOPLUGV4 BOARD
65 +M: Alberto Bursi <alberto.bursi@outlook.it>
66 +S: Maintained
67 +F: board/cloudengines/pogoplugv4/
68 +F: include/configs/pogoplugv4.h
69 +F: configs/pogoplugv4_defconfig
70 --- /dev/null
71 +++ b/board/cloudengines/pogoplugv4/Makefile
72 @@ -0,0 +1,11 @@
73 +#
74 +# (C) Copyright 2009 bodhi <mibodhi@gmail.com>
75 +#
76 +# Based on
77 +# Marvell Semiconductor <www.marvell.com>
78 +# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
79 +#
80 +# SPDX-License-Identifier: GPL-2.0+
81 +#
82 +
83 +obj-y := pogoplugv4.o
84 --- /dev/null
85 +++ b/board/cloudengines/pogoplugv4/kwbimage.cfg
86 @@ -0,0 +1,167 @@
87 +#
88 +# Copyright (C) 2012
89 +# David Purdy <david.c.purdy@gmail.com>
90 +#
91 +# Based on Kirkwood support:
92 +# (C) Copyright 2009
93 +# Marvell Semiconductor <www.marvell.com>
94 +# Written-by: Prafulla Wadaskar <prafulla <at> marvell.com>
95 +#
96 +# See file CREDITS for list of people who contributed to this
97 +# project.
98 +#
99 +# This program is free software; you can redistribute it and/or
100 +# modify it under the terms of the GNU General Public License as
101 +# published by the Free Software Foundation; either version 2 of
102 +# the License, or (at your option) any later version.
103 +#
104 +# This program is distributed in the hope that it will be useful,
105 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
106 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
107 +# GNU General Public License for more details.
108 +#
109 +# You should have received a copy of the GNU General Public License
110 +# along with this program; If not, see <http://www.gnu.org/licenses/>.
111 +#
112 +# Refer docs/README.kwimage for more details about how-to configure
113 +# and create kirkwood boot image
114 +#
115 +
116 +# Boot Media configurations (DONE)
117 +BOOT_FROM nand
118 +NAND_ECC_MODE default
119 +NAND_PAGE_SIZE 0x0800
120 +
121 +# SOC registers configuration using bootrom header extension
122 +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
123 +
124 +# Configure RGMII-0 interface pad voltage to 1.8V (SHOULD BE SAME)
125 +DATA 0xffd100e0 0x1b1b1b9b
126 +
127 +#Dram initalization for SINGLE x16 CL=3 @ 200MHz (need CL=3 @ 200MHz?)
128 +DATA 0xffd01400 0x43000618 # DDR Configuration register
129 +# bit13-0: 0x200 (200 DDR2 clks refresh rate)
130 +# bit23-14: zero
131 +# bit24: 1= enable exit self refresh mode on DDR access
132 +# bit25: 1 required
133 +# bit29-26: zero
134 +# bit31-30: 01
135 +
136 +DATA 0xffd01404 0x34143000 # DDR Controller Control Low
137 +# bit 4: 0=addr/cmd in smame cycle
138 +# bit 5: 0=clk is driven during self refresh, we don't care for APX
139 +# bit 6: 0=use recommended falling edge of clk for addr/cmd
140 +# bit14: 0=input buffer always powered up
141 +# bit18: 1=cpu lock transaction enabled
142 +# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
143 +# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
144 +# bit30-28: 3 required
145 +# bit31: 0=no additional STARTBURST delay
146 +
147 +DATA 0xffd01408 0x11012227 # DDR Timing (Low) (active cycles value +1)
148 +# bit3-0: TRAS lsbs
149 +# bit7-4: TRCD
150 +# bit11- 8: TRP
151 +# bit15-12: TWR
152 +# bit19-16: TWTR
153 +# bit20: TRAS msb
154 +# bit23-21: 0x0
155 +# bit27-24: TRRD
156 +# bit31-28: TRTP
157 +
158 +DATA 0xffd0140c 0x00000819 # DDR Timing (High)
159 +# bit6-0: TRFC
160 +# bit8-7: TR2R
161 +# bit10-9: TR2W
162 +# bit12-11: TW2W
163 +# bit31-13: zero required
164 +
165 +DATA 0xffd01410 0x00000001 # DDR Address Control (changed to Dockstar vals)
166 +# bit1-0: 00, Cs0width=x16
167 +# bit3-2: 10, Cs0size=512Mb
168 +# bit5-4: 00, Cs2width=nonexistent
169 +# bit7-6: 00, Cs1size =nonexistent
170 +# bit9-8: 00, Cs2width=nonexistent
171 +# bit11-10: 00, Cs2size =nonexistent
172 +# bit13-12: 00, Cs3width=nonexistent
173 +# bit15-14: 00, Cs3size =nonexistent
174 +# bit16: 0, Cs0AddrSel
175 +# bit17: 0, Cs1AddrSel
176 +# bit18: 0, Cs2AddrSel
177 +# bit19: 0, Cs3AddrSel
178 +# bit31-20: 0 required
179 +
180 +DATA 0xffd01414 0x00000000 # DDR Open Pages Control
181 +# bit0: 0, OpenPage enabled
182 +# bit31-1: 0 required
183 +
184 +DATA 0xffd01418 0x00000000 # DDR Operation
185 +# bit3-0: 0x0, DDR cmd
186 +# bit31-4: 0 required
187 +
188 +DATA 0xffd0141c 0x00000632 # DDR Mode
189 +# bit2-0: 2, BurstLen=2 required
190 +# bit3: 0, BurstType=0 required
191 +# bit6-4: 4, CL=5 (<===== change to CL=3 ?)
192 +# bit7: 0, TestMode=0 normal
193 +# bit8: 0, DLL reset=0 normal
194 +# bit11-9: 6, auto-precharge write recovery ????????????
195 +# bit12: 0, PD must be zero
196 +# bit31-13: 0 required
197 +
198 +DATA 0xffd01420 0x00000040 # DDR Extended Mode
199 +# bit0: 0, DDR DLL enabled
200 +# bit1: 0, DDR drive strenght normal
201 +# bit2: 0, DDR ODT control lsd (disabled)
202 +# bit5-3: 000, required
203 +# bit6: 1, DDR ODT control msb, (disabled)
204 +# bit9-7: 000, required
205 +# bit10: 0, differential DQS enabled
206 +# bit11: 0, required
207 +# bit12: 0, DDR output buffer enabled
208 +# bit31-13: 0 required
209 +
210 +DATA 0xffd01424 0x0000F07F # DDR Controller Control High
211 +# bit2-0: 111, required
212 +# bit3 : 1 , MBUS Burst Chop disabled
213 +# bit6-4: 111, required
214 +# bit7 : 0
215 +# bit8 : 0 , no sample stage
216 +# bit9 : 0 , no half clock cycle addition to dataout
217 +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
218 +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
219 +# bit15-12: 1111 required
220 +# bit31-16: 0 required
221 +
222 +DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
223 +DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
224 +
225 +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
226 +DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
227 +# bit0: 1, Window enabled
228 +# bit1: 0, Write Protect disabled
229 +# bit3-2: 00, CS0 hit selected
230 +# bit23-4: ones, required
231 +# bit31-24: 0x07, Size (i.e. 128MB)
232 +
233 +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
234 +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
235 +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
236 +
237 +DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) (DONE)
238 +# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
239 +# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
240 +# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
241 +# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
242 +
243 +DATA 0xffd01498 0x00000000 # DDR ODT Control (High) (DONE)
244 +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
245 +# bit3-2: 01, ODT1 active NEVER!
246 +# bit31-4: zero, required
247 +
248 +DATA 0xffd0149c 0x0000e803 # CPU ODT Control (DONE)
249 +DATA 0xffd01480 0x00000001 # DDR Initialization Control (DONE)
250 +#bit0=1, enable DDR init upon this register write
251 +
252 +# End of Header extension
253 +DATA 0x0 0x0
254 --- /dev/null
255 +++ b/board/cloudengines/pogoplugv4/pogoplugv4.c
256 @@ -0,0 +1,223 @@
257 +/*
258 + * Copyright (C) 2016 bodhi <mibodhi@gmail.com>
259 + * Copyright (C) 2014 bodhi <mibodhi@gmail.com>
260 + *
261 + * Based on
262 + *
263 + * Copyright (C) 2014 <ebbes.ebbes@gmail.com>
264 + *
265 + * Copyright (C) 2012
266 + * David Purdy <david.c.purdy@gmail.com>
267 + *
268 + * Based on Kirkwood support:
269 + * (C) Copyright 2009
270 + * Marvell Semiconductor <www.marvell.com>
271 + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
272 + *
273 + * See file CREDITS for list of people who contributed to this
274 + * project.
275 + *
276 + * This program is free software; you can redistribute it and/or
277 + * modify it under the terms of the GNU General Public License as
278 + * published by the Free Software Foundation; either version 2 of
279 + * the License, or (at your option) any later version.
280 + *
281 + * This program is distributed in the hope that it will be useful,
282 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
283 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
284 + * GNU General Public License for more details.
285 + *
286 + * You should have received a copy of the GNU General Public License
287 + * along with this program; If not, see <http://www.gnu.org/licenses/>.
288 + */
289 +
290 +#include <common.h>
291 +#include <miiphy.h>
292 +#include <asm/arch/cpu.h>
293 +#include <asm/arch/soc.h>
294 +#include <asm/arch/mpp.h>
295 +#include <asm/io.h>
296 +#include "pogoplugv4.h"
297 +#include <asm/arch/gpio.h>
298 +
299 +#ifdef CONFIG_KIRKWOOD_MMC
300 +#include <kirkwood_mmc.h>
301 +#endif /* CONFIG_KIRKWOOD_MMC */
302 +
303 +
304 +DECLARE_GLOBAL_DATA_PTR;
305 +
306 +int board_early_init_f(void)
307 +{
308 + /*
309 + * default gpio configuration
310 + * There are maximum 64 gpios controlled through 2 sets of registers
311 + * the below configuration configures mainly initial LED status
312 + */
313 + mvebu_config_gpio(POGOPLUGV4_OE_VAL_LOW,
314 + POGOPLUGV4_OE_VAL_HIGH,
315 + POGOPLUGV4_OE_LOW, POGOPLUGV4_OE_HIGH);
316 +
317 + /* Multi-Purpose Pins Functionality configuration */
318 + u32 kwmpp_config[] = {
319 + MPP0_NF_IO2,
320 + MPP1_NF_IO3,
321 + MPP2_NF_IO4,
322 + MPP3_NF_IO5,
323 + MPP4_NF_IO6,
324 + MPP5_NF_IO7,
325 + MPP6_SYSRST_OUTn,
326 + MPP7_GPO,
327 + MPP8_TW_SDA,
328 + MPP9_TW_SCK,
329 + MPP10_UART0_TXD,
330 + MPP11_UART0_RXD,
331 + MPP12_SD_CLK,
332 + MPP13_SD_CMD,
333 + MPP14_SD_D0,
334 + MPP15_SD_D1,
335 + MPP16_SD_D2,
336 + MPP17_SD_D3,
337 + MPP18_NF_IO0,
338 + MPP19_NF_IO1,
339 + MPP20_SATA1_ACTn,
340 + MPP21_SATA0_ACTn,
341 + MPP22_GPIO, /* Green LED */
342 + MPP23_GPIO,
343 + MPP24_GPIO, /* Red LED */
344 + MPP25_GPIO,
345 + MPP26_GPIO,
346 + MPP27_GPIO,
347 + MPP28_GPIO,
348 + MPP29_GPIO, /* Eject button */
349 + MPP30_GPIO,
350 + MPP31_GPIO,
351 + MPP32_GPIO,
352 + MPP33_GPIO,
353 + MPP34_GPIO,
354 + MPP35_GPIO, /* FR6192 has only 36 GPIOs */
355 + 0
356 + };
357 + kirkwood_mpp_conf(kwmpp_config, NULL);
358 +
359 + return 0;
360 +}
361 +
362 +int board_init(void)
363 +{
364 + /* Boot parameters address */
365 + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
366 +
367 + kw_gpio_set_valid(20, 1);
368 + kw_gpio_set_valid(21, 1);
369 + kw_gpio_set_valid(22, 1);
370 + kw_gpio_set_valid(24, 1);
371 +
372 + return 0;
373 +}
374 +
375 +#ifdef CONFIG_RESET_PHY_R
376 +/* Configure and initialize PHY */
377 +void reset_phy(void)
378 +{
379 + u16 reg;
380 + u16 devadr;
381 + char *name = "egiga0";
382 +
383 + if (miiphy_set_current_dev(name))
384 + return;
385 +
386 + /* command to read PHY dev address */
387 + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
388 + printf("Err..(%s) could not read PHY dev address\n", __func__);
389 + return;
390 + }
391 +
392 + /*
393 + * Enable RGMII delay on Tx and Rx for CPU port
394 + * Ref: sec 4.7.2 of chip datasheet
395 + */
396 + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
397 + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
398 + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
399 + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
400 + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
401 +
402 + /* reset the phy */
403 + miiphy_reset(name, devadr);
404 +
405 + debug("88E1116 Initialized on %s\n", name);
406 +}
407 +#endif /* CONFIG_RESET_PHY_R */
408 +
409 +#ifdef CONFIG_KIRKWOOD_MMC
410 +int board_mmc_init(bd_t *bis)
411 +{
412 + kw_mmc_initialize(bis);
413 + return 0;
414 +}
415 +#endif /* CONFIG_KIRKWOOD_MMC */
416 +
417 +
418 +#define GREEN_LED (1 << 22)
419 +#define RED_LED (1 << 24)
420 +#define BOTH_LEDS (GREEN_LED | RED_LED)
421 +#define NEITHER_LED 0
422 +
423 +static void set_leds(u32 leds, u32 blinking)
424 +{
425 + struct kwgpio_registers *r;
426 + u32 oe;
427 + u32 bl;
428 +
429 + r = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
430 + oe = readl(&r->oe) | BOTH_LEDS;
431 + writel(oe & ~leds, &r->oe); /* active low */
432 + bl = readl(&r->blink_en) & ~BOTH_LEDS;
433 + writel(bl | blinking, &r->blink_en);
434 +}
435 +
436 +void show_boot_progress(int val)
437 +{
438 + switch (val) {
439 + case BOOTSTAGE_ID_RUN_OS: /* booting Linux */
440 + set_leds(BOTH_LEDS, NEITHER_LED);
441 + break;
442 + case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */
443 + set_leds(GREEN_LED, GREEN_LED);
444 + break;
445 + default:
446 + if (val < 0) /* error */
447 + set_leds(RED_LED, RED_LED);
448 + break;
449 + }
450 +}
451 +
452 +#if defined(CONFIG_KIRKWOOD_GPIO)
453 +/* Return GPIO button status */
454 +/*
455 +un-pressed:
456 + gpio-29 (Eject Button ) in hi (act lo) - IRQ edge (clear )
457 +pressed
458 + gpio-29 (Eject Button ) in lo (act hi) - IRQ edge (clear )
459 +*/
460 +
461 +static int
462 +do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
463 +{
464 + if (strcmp(argv[1], "eject") == 0) {
465 + kw_gpio_set_valid(BTN_EJECT, GPIO_INPUT_OK);
466 + kw_gpio_direction_input(BTN_EJECT);
467 + return kw_gpio_get_value(BTN_EJECT);
468 + }
469 + else
470 + return -1;
471 +}
472 +
473 +
474 +U_BOOT_CMD(button, 2, 0, do_read_button,
475 + "Return GPIO button status 0=off 1=on",
476 + "- button eject: test buttons states\n"
477 +);
478 +
479 +#endif
480 --- /dev/null
481 +++ b/board/cloudengines/pogoplugv4/pogoplugv4.h
482 @@ -0,0 +1,50 @@
483 +/*
484 + * Copyright (C) 2016
485 + * bodhi <mibodhi@gmail.com>
486 + *
487 + * Copyright (C) 2012
488 + * David Purdy <david.c.purdy@gmail.com>
489 + *
490 + * Based on Kirkwood support:
491 + * (C) Copyright 2009
492 + * Marvell Semiconductor <www.marvell.com>
493 + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
494 + *
495 + * See file CREDITS for list of people who contributed to this
496 + * project.
497 + *
498 + * This program is free software; you can redistribute it and/or
499 + * modify it under the terms of the GNU General Public License as
500 + * published by the Free Software Foundation; either version 2 of
501 + * the License, or (at your option) any later version.
502 + *
503 + * This program is distributed in the hope that it will be useful,
504 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
505 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
506 + * GNU General Public License for more details.
507 + *
508 + * You should have received a copy of the GNU General Public License
509 + * along with this program; If not, see <http://www.gnu.org/licenses/>.
510 + */
511 +
512 +#ifndef __POGOPLUGV4_H
513 +#define __POGOPLUGV4_H
514 +
515 +/* GPIO configuration */
516 +#define POGOPLUGV4_OE_LOW (~(0))
517 +#define POGOPLUGV4_OE_HIGH (~(0))
518 +#define POGOPLUGV4_OE_VAL_LOW (1 << 29)
519 +#define POGOPLUGV4_OE_VAL_HIGH 0
520 +
521 +/* PHY related */
522 +#define MV88E1116_LED_FCTRL_REG 10
523 +#define MV88E1116_CPRSP_CR3_REG 21
524 +#define MV88E1116_MAC_CTRL_REG 21
525 +#define MV88E1116_PGADR_REG 22
526 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
527 +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
528 +
529 +/* button */
530 +#define BTN_EJECT 29
531 +
532 +#endif /* __POGOPLUGV4_H */
533 --- /dev/null
534 +++ b/configs/pogoplugv4_defconfig
535 @@ -0,0 +1,43 @@
536 +CONFIG_ARM=y
537 +CONFIG_KIRKWOOD=y
538 +CONFIG_SYS_TEXT_BASE=0x600000
539 +CONFIG_TARGET_POGOPLUGV4=y
540 +CONFIG_SYS_PROMPT="pogoplugv4> "
541 +CONFIG_IDENT_STRING="\nPogoplug V4"
542 +CONFIG_NR_DRAM_BANKS=2
543 +CONFIG_BOOTDELAY=3
544 +# CONFIG_CMD_IMLS is not set
545 +# CONFIG_CMD_FLASH is not set
546 +CONFIG_MVGBE=y
547 +CONFIG_MII=y
548 +CONFIG_SYS_NS16550=y
549 +CONFIG_CMD_FDT=y
550 +CONFIG_OF_LIBFDT=y
551 +CONFIG_OF_BOOTZ=y
552 +CONFIG_CMD_SETEXPR=y
553 +CONFIG_CMD_DHCP=y
554 +CONFIG_CMD_MII=y
555 +CONFIG_CMD_PING=y
556 +CONFIG_CMD_DNS=y
557 +CONFIG_CMD_SNTP=y
558 +CONFIG_CMD_USB=y
559 +CONFIG_CMD_DATE=y
560 +CONFIG_CMD_EXT2=y
561 +CONFIG_CMD_EXT4=y
562 +CONFIG_CMD_FAT=y
563 +CONFIG_CMD_JFFS2=y
564 +CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x1c0000(uboot),0x40000(uboot_env),0x7e00000(ubi)"
565 +CONFIG_CMD_MTDPARTS=y
566 +CONFIG_CMD_ENV=y
567 +CONFIG_CMD_NAND=y
568 +CONFIG_CMD_MMC=y
569 +CONFIG_CMD_GPIO=y
570 +CONFIG_EFI_PARTITION=y
571 +CONFIG_ENV_IS_IN_NAND=y
572 +CONFIG_CMD_UBI=y
573 +CONFIG_USB=y
574 +CONFIG_USB_EHCI_HCD=y
575 +CONFIG_USB_STORAGE=y
576 +CONFIG_LZMA=y
577 +CONFIG_LZO=y
578 +CONFIG_SYS_LONGHELP=y
579 --- a/drivers/gpio/kw_gpio.c
580 +++ b/drivers/gpio/kw_gpio.c
581 @@ -147,3 +147,36 @@ void kw_gpio_set_blink(unsigned pin, int
582 /* Set blinking. */
583 __set_blinking(pin, blink);
584 }
585 +
586 +
587 +/*
588 + * Hooks to GENERIC_GPIO primitives
589 + */
590 +
591 +int gpio_direction_input(unsigned pin)
592 +{
593 + return kw_gpio_direction_input(pin);
594 +}
595 +
596 +int gpio_direction_output(unsigned pin, int value)
597 +{
598 + return kw_gpio_direction_output(pin, value);
599 +}
600 +
601 +void gpio_set_value(unsigned pin, int value) {
602 + kw_gpio_set_value(pin, value);
603 +}
604 +
605 +int gpio_get_value(unsigned pin) {
606 + return kw_gpio_get_value(pin);
607 +}
608 +
609 +int gpio_request(unsigned gpio, const char *label)
610 +{
611 + return 0;
612 +}
613 +
614 +int gpio_free(unsigned gpio)
615 +{
616 + return 0;
617 +}
618 --- a/drivers/mmc/Makefile
619 +++ b/drivers/mmc/Makefile
620 @@ -61,6 +61,7 @@ obj-$(CONFIG_MMC_SDHCI_TANGIER) += tang
621 obj-$(CONFIG_MMC_SDHCI_TEGRA) += tegra_mmc.o
622 obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o
623 obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o
624 +obj-$(CONFIG_KIRKWOOD_MMC) += kirkwood_mmc.o
625
626 obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
627 obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o
628 --- /dev/null
629 +++ b/drivers/mmc/kirkwood_mmc.c
630 @@ -0,0 +1,482 @@
631 +/*
632 + * (C) Copyright 2014 bodhi <mibodhi@gmail.com>
633 + *
634 + * Based on
635 + *
636 + * (C) Copyright 2014 <ebbes.ebbes@gmail.com>
637 + *
638 + * Based on
639 + *
640 + * Driver for Marvell SDIO/MMC controller
641 + *
642 + * (C) Copyright 2012
643 + * Marvell Semiconductor <www.marvell.com>
644 + * Written-by: Gérald Kerma <uboot at doukki.net>
645 + * See file CREDITS for list of people who contributed to this
646 + * project.
647 + *
648 + * This program is free software; you can redistribute it and/or
649 + * modify it under the terms of the GNU General Public License as
650 + * published by the Free Software Foundation; either version 2 of
651 + * the License, or (at your option) any later version.
652 + *
653 + * This program is distributed in the hope that it will be useful,
654 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
655 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
656 + * GNU General Public License for more details.
657 + *
658 + * You should have received a copy of the GNU General Public License
659 + * along with this program; if not, write to the Free Software
660 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
661 + * MA 02111-1307 USA
662 + */
663 +
664 +#include <common.h>
665 +#include <malloc.h>
666 +#include <part.h>
667 +#include <mmc.h>
668 +#include <asm/io.h>
669 +#include <asm/arch/cpu.h>
670 +#include <asm/arch/soc.h>
671 +
672 +#include <kirkwood_mmc.h>
673 +
674 +#define DRIVER_NAME "kwsdio"
675 +
676 +static int kw_mmc_setup_data(struct mmc_data *data)
677 +{
678 + u32 ctrl_reg;
679 +
680 +#ifdef DEBUG
681 + printf("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME,
682 + (data->flags & MMC_DATA_READ) ? "read" : "write",
683 + data->blocks, data->blocksize);
684 +#endif
685 +
686 + /* default to maximum timeout */
687 + ctrl_reg = kwsd_read(SDIO_HOST_CTRL);
688 + ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
689 + kwsd_write(SDIO_HOST_CTRL, ctrl_reg);
690 +
691 + if (data->flags & MMC_DATA_READ) {
692 + kwsd_write(SDIO_SYS_ADDR_LOW,(u32)data->dest & 0xffff);
693 + kwsd_write(SDIO_SYS_ADDR_HI,(u32)data->dest >> 16);
694 + } else {
695 + kwsd_write(SDIO_SYS_ADDR_LOW,(u32)data->src & 0xffff);
696 + kwsd_write(SDIO_SYS_ADDR_HI,(u32)data->src >> 16);
697 + }
698 +
699 + kwsd_write(SDIO_BLK_COUNT, data->blocks);
700 + kwsd_write(SDIO_BLK_SIZE, data->blocksize);
701 +
702 + return 0;
703 +}
704 +
705 +static int kw_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
706 +{
707 + int timeout = 10;
708 + int err;
709 + ushort waittype = 0;
710 + ushort resptype = 0;
711 + ushort xfertype = 0;
712 + ushort resp_indx = 0;
713 +
714 +#ifdef CONFIG_MMC_DEBUG
715 + printf("cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n", cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
716 +#endif
717 +
718 + udelay(10000);
719 +
720 +#ifdef CONFIG_MMC_DEBUG
721 + printf("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME, cmd->cmdidx, kwsd_read(SDIO_HW_STATE));
722 +#endif
723 +
724 + /* Checking if card is busy */
725 + while ((kwsd_read(SDIO_HW_STATE) & CARD_BUSY)) {
726 + if (timeout == 0) {
727 + printf("%s: card busy!\n", DRIVER_NAME);
728 + return -1;
729 + }
730 + timeout--;
731 + udelay(1000);
732 + }
733 +
734 + /* Set up for a data transfer if we have one */
735 + if (data) {
736 + if ((err = kw_mmc_setup_data(data)))
737 + return err;
738 + }
739 +
740 + resptype = SDIO_CMD_INDEX(cmd->cmdidx);
741 +
742 + /* Analyzing resptype/xfertype/waittype for the command */
743 + if (cmd->resp_type & MMC_RSP_BUSY)
744 + resptype |= SDIO_CMD_RSP_48BUSY;
745 + else if (cmd->resp_type & MMC_RSP_136)
746 + resptype |= SDIO_CMD_RSP_136;
747 + else if (cmd->resp_type & MMC_RSP_PRESENT)
748 + resptype |= SDIO_CMD_RSP_48;
749 + else
750 + resptype |= SDIO_CMD_RSP_NONE;
751 +
752 + if (cmd->resp_type & MMC_RSP_CRC)
753 + resptype |= SDIO_CMD_CHECK_CMDCRC;
754 +
755 + if (cmd->resp_type & MMC_RSP_OPCODE)
756 + resptype |= SDIO_CMD_INDX_CHECK;
757 +
758 + if (cmd->resp_type & MMC_RSP_PRESENT) {
759 + resptype |= SDIO_UNEXPECTED_RESP;
760 + waittype |= SDIO_NOR_UNEXP_RSP;
761 + }
762 +
763 + if (data) {
764 + resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
765 + xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
766 + if (data->flags & MMC_DATA_READ) {
767 + xfertype |= SDIO_XFER_MODE_TO_HOST;
768 + waittype = SDIO_NOR_DMA_INI;
769 + } else
770 + waittype |= SDIO_NOR_XFER_DONE;
771 + } else
772 + waittype |= SDIO_NOR_CMD_DONE;
773 +
774 + /* Setting cmd arguments */
775 + kwsd_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
776 + kwsd_write(SDIO_ARG_HI, cmd->cmdarg >> 16);
777 +
778 + /* Setting Xfer mode */
779 + kwsd_write(SDIO_XFER_MODE, xfertype);
780 +
781 + kwsd_write(SDIO_NOR_INTR_STATUS, ~SDIO_NOR_CARD_INT);
782 + kwsd_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
783 +
784 + /* Sending command */
785 + kwsd_write(SDIO_CMD, resptype);
786 +/*
787 + kwsd_write(SDIO_CMD, KW_MMC_MAKE_CMD(cmd->cmdidx, resptype));
788 +*/
789 +
790 + kwsd_write(SDIO_NOR_INTR_EN, SDIO_POLL_MASK);
791 + kwsd_write(SDIO_ERR_INTR_EN, SDIO_POLL_MASK);
792 +
793 + /* Waiting for completion */
794 + timeout = 1000000;
795 +
796 + while (!((kwsd_read(SDIO_NOR_INTR_STATUS)) & waittype)) {
797 + if (kwsd_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
798 +#ifdef DEBUG
799 + printf("%s: kw_mmc_send_cmd: error! cmdidx : %d, err reg: %04x\n", DRIVER_NAME, cmd->cmdidx,
800 +wsd_read(SDIO_ERR_INTR_STATUS));
801 +#endif
802 + if (kwsd_read(SDIO_ERR_INTR_STATUS) & (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) {
803 + return -ETIMEDOUT;
804 + }
805 + return -ECOMM;
806 + }
807 +
808 + timeout--;
809 + udelay(1);
810 + if (timeout <= 0) {
811 + printf("%s: command timed out\n", DRIVER_NAME);
812 + return -ETIMEDOUT;
813 + }
814 + }
815 +
816 + /* Handling response */
817 + if (cmd->resp_type & MMC_RSP_136) {
818 + uint response[8];
819 + for (resp_indx = 0; resp_indx < 8; resp_indx++)
820 + response[resp_indx] = kwsd_read(SDIO_RSP(resp_indx));
821 +
822 + cmd->response[0] = ((response[0] & 0x03ff) << 22) |
823 + ((response[1] & 0xffff) << 6) |
824 + ((response[2] & 0xfc00) >> 10);
825 + cmd->response[1] = ((response[2] & 0x03ff) << 22) |
826 + ((response[3] & 0xffff) << 6) |
827 + ((response[4] & 0xfc00) >> 10);
828 + cmd->response[2] = ((response[4] & 0x03ff) << 22) |
829 + ((response[5] & 0xffff) << 6) |
830 + ((response[6] & 0xfc00) >> 10);
831 + cmd->response[3] = ((response[6] & 0x03ff) << 22) |
832 + ((response[7] & 0x3fff) << 8);
833 + } else if (cmd->resp_type & MMC_RSP_PRESENT) {
834 + uint response[3];
835 + for (resp_indx = 0; resp_indx < 3; resp_indx++)
836 + response[resp_indx] = kwsd_read(SDIO_RSP(resp_indx));
837 +
838 + cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) |
839 + ((response[1] & 0xffff) << (14 - 8)) |
840 + ((response[0] & 0x03ff) << (30 - 8));
841 + cmd->response[1] = ((response[0] & 0xfc00) >> 10);
842 + cmd->response[2] = 0;
843 + cmd->response[3] = 0;
844 + }
845 +
846 +#ifdef CONFIG_MMC_DEBUG
847 + printf("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type);
848 + printf("[0x%x] ", cmd->response[0]);
849 + printf("[0x%x] ", cmd->response[1]);
850 + printf("[0x%x] ", cmd->response[2]);
851 + printf("[0x%x] ", cmd->response[3]);
852 + printf("\n");
853 +#endif
854 +
855 + return 0;
856 +}
857 +
858 +#if 0
859 +/* Disable these three functions as they are not used anyway */
860 +
861 +static void kwsd_power_up(void)
862 +{
863 +#ifdef DEBUG
864 + printf("%s: power up\n", DRIVER_NAME);
865 +#endif
866 + /* disable interrupts */
867 + kwsd_write(SDIO_NOR_INTR_EN, 0);
868 + kwsd_write(SDIO_ERR_INTR_EN, 0);
869 +
870 + /* SW reset */
871 + kwsd_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
872 +
873 + kwsd_write(SDIO_XFER_MODE, 0);
874 +
875 + /* enable status */
876 + kwsd_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
877 + kwsd_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
878 +
879 + /* enable interrupts status */
880 + kwsd_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
881 + kwsd_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
882 +}
883 +
884 +static void kwsd_power_down(void)
885 +{
886 +#ifdef DEBUG
887 + printf("%s: power down\n", DRIVER_NAME);
888 +#endif
889 + /* disable interrupts */
890 + kwsd_write(SDIO_NOR_INTR_EN, 0);
891 + kwsd_write(SDIO_ERR_INTR_EN, 0);
892 +
893 + /* SW reset */
894 + kwsd_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
895 +
896 + kwsd_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
897 +
898 + /* disable status */
899 + kwsd_write(SDIO_NOR_STATUS_EN, 0);
900 + kwsd_write(SDIO_ERR_STATUS_EN, 0);
901 +
902 + /* enable interrupts status */
903 + kwsd_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
904 + kwsd_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
905 +}
906 +
907 +static u32 kw_mmc_get_base_clock(void)
908 +{
909 + /* Original version did a check for board device id and revision id
910 + * and assigned one of these clocks:
911 + * KW_MMC_BASE_FAST_CLK_100 (revid == 0 && devid != MV88F6282_DEV_ID)
912 + * KW_MMC_BASE_FAST_CLK_200 (revid != 0 || devid == MV88F6282_DEV_ID)
913 + * However, this check was disabled and
914 + * KW_MMC_BASE_FAST_CLOCK
915 + * was returned in every case.
916 + * Therefore, all of the dead logic was removed. */
917 + return KW_MMC_BASE_FAST_CLOCK;
918 +}
919 +#endif /* #if 0 */
920 +
921 +static inline u32 kw_mmc_get_base_clock(void)
922 +{
923 + /* get MMC base clock. If any logic other than just returning
924 + * a fixed value is ever used, remove inline modifier. */
925 +
926 + /* Possible values:
927 + * - KW_MMC_BASE_FAST_CLOCK (166 MHz)
928 + * - KW_MMC_BASE_FAST_CLK_100 (100 MHz)
929 + * - KW_MMC_BASE_FAST_CLK_200 (200 MHz)
930 + *
931 + * Tests have shown that 200 MHz is more reliable than
932 + * 166 MHz, so this value is used. */
933 + return KW_MMC_BASE_FAST_CLK_200;
934 +}
935 +
936 +static void kw_mmc_set_clk(unsigned int clock)
937 +{
938 + unsigned int m;
939 +
940 + if (clock == 0) {
941 +#ifdef DEBUG
942 + printf("%s: clock off\n", DRIVER_NAME);
943 +#endif
944 + kwsd_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
945 + kwsd_write(SDIO_CLK_DIV, KW_MMC_BASE_DIV_MAX);
946 + } else {
947 + m = kw_mmc_get_base_clock() / (2 * clock) - 1;
948 + if (m > KW_MMC_BASE_DIV_MAX)
949 + m = KW_MMC_BASE_DIV_MAX;
950 +#ifdef DEBUG
951 + printf("%s: kw_mmc_set_clk: base = %d dividor = 0x%x clock=%d\n", DRIVER_NAME,
952 +w_mmc_get_base_clock(), m, clock);
953 +#endif
954 + kwsd_write(SDIO_CLK_DIV, m & KW_MMC_BASE_DIV_MAX);
955 + }
956 + udelay(10000);
957 +}
958 +
959 +static void kw_mmc_set_bus(unsigned int bus)
960 +{
961 + u32 ctrl_reg = 0;
962 +
963 + ctrl_reg = kwsd_read(SDIO_HOST_CTRL);
964 + ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
965 +
966 + switch (bus) {
967 + case 4:
968 + ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
969 + break;
970 + case 1:
971 + default:
972 + ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;
973 + }
974 + /* default transfer mode */
975 + ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN;
976 + ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;
977 +
978 + /* default to maximum timeout */
979 + ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
980 +
981 + ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN;
982 +
983 + ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;
984 +
985 + /*
986 + * The HI_SPEED_EN bit is causing trouble with many (but not all)
987 + * high speed SD, SDHC and SDIO cards. Not enabling that bit
988 + * makes all cards work. So let's just ignore that bit for now
989 + * and revisit this issue if problems for not enabling this bit
990 + * are ever reported.
991 + */
992 +#if 0
993 + if (ios->timing == MMC_TIMING_MMC_HS ||
994 + ios->timing == MMC_TIMING_SD_HS)
995 + ctrl_reg |= SDIO_HOST_CTRL_HI_SPEED_EN;
996 +#endif
997 +
998 +#ifdef DEBUG
999 + printf("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg,
1000 + (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
1001 + "push-pull" : "open-drain",
1002 + (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
1003 + "4bit-width" : "1bit-width",
1004 + (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
1005 + "high-speed" : "");
1006 +#endif
1007 +
1008 + kwsd_write(SDIO_HOST_CTRL, ctrl_reg);
1009 + udelay(10000);
1010 +}
1011 +
1012 +static void kw_mmc_set_ios(struct mmc *mmc)
1013 +{
1014 +#ifdef DEBUG
1015 + printf("%s: bus[%d] clock[%d]\n", DRIVER_NAME, mmc->bus_width, mmc->clock);
1016 +#endif
1017 + kw_mmc_set_bus(mmc->bus_width);
1018 + kw_mmc_set_clk(mmc->clock);
1019 +}
1020 +
1021 +static int kw_mmc_init(struct mmc *mmc)
1022 +{
1023 +#ifdef DEBUG
1024 + printf("%s: kw_mmc_init\n", DRIVER_NAME);
1025 +#endif
1026 +
1027 + /*
1028 + * Setting host parameters
1029 + * Initial Host Ctrl : Timeout : max , Normal Speed mode, 4-bit data mode
1030 + * Big Endian, SD memory Card, Push_pull CMD Line
1031 + */
1032 + kwsd_write(SDIO_HOST_CTRL,
1033 + SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) |
1034 + SDIO_HOST_CTRL_DATA_WIDTH_4_BITS |
1035 + SDIO_HOST_CTRL_BIG_ENDIAN |
1036 + SDIO_HOST_CTRL_PUSH_PULL_EN |
1037 + SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);
1038 +
1039 + kwsd_write(SDIO_CLK_CTRL, 0);
1040 +
1041 + /* enable status */
1042 + kwsd_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
1043 + kwsd_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
1044 +
1045 + /* disable interrupts */
1046 + kwsd_write(SDIO_NOR_INTR_EN, 0);
1047 + kwsd_write(SDIO_ERR_INTR_EN, 0);
1048 +
1049 + /* SW reset */
1050 + kwsd_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
1051 +
1052 + udelay(10000);
1053 + return 0;
1054 +}
1055 +
1056 +int kw_mmc_initialize(bd_t *bis)
1057 +{
1058 + struct mmc *mmc = NULL;
1059 + struct mmc_config *cfg = NULL;
1060 + struct mmc_ops *ops = NULL;
1061 + char *name = NULL;
1062 +
1063 +#ifdef DEBUG
1064 + printf("%s: %s base_clock = %d\n", DRIVER_NAME, kirkwood_id(), kw_mmc_get_base_clock());
1065 +#endif
1066 + mmc = malloc(sizeof(struct mmc));
1067 + if (!mmc)
1068 + return -1;
1069 + memset(mmc, 0, sizeof(*mmc));
1070 +
1071 + cfg = malloc(sizeof(*cfg));
1072 + if (cfg == NULL)
1073 + return -1;
1074 + memset(cfg, 0, sizeof(*cfg));
1075 + mmc->cfg = cfg; /* provided configuration */
1076 +
1077 + ops = malloc(sizeof(*ops));
1078 + if (ops == NULL)
1079 + return -1;
1080 + memset(ops, 0, sizeof(*ops));
1081 + cfg->ops = ops;
1082 +
1083 + name = malloc(sizeof(DRIVER_NAME)+1);
1084 + if (name == NULL)
1085 + return -1;
1086 + cfg->name = name;
1087 +
1088 + sprintf(cfg->name, DRIVER_NAME);
1089 +
1090 + ops->send_cmd = kw_mmc_send_cmd;
1091 + ops->set_ios = kw_mmc_set_ios;
1092 + ops->init = kw_mmc_init;
1093 +
1094 + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1095 + cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS;
1096 +
1097 + cfg->f_min = kw_mmc_get_base_clock()/KW_MMC_BASE_DIV_MAX;
1098 + cfg->f_max = KW_MMC_CLOCKRATE_MAX;
1099 + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1100 +
1101 + mmc = mmc_create (cfg, NULL);
1102 +
1103 + if (mmc == NULL) {
1104 + free(name);
1105 + free(ops);
1106 + free(cfg);
1107 + printf("\nFailed to Initialize MMC\n");
1108 + return -1;
1109 + }
1110 +
1111 + return 0;
1112 +}
1113 --- a/include/configs/mv-common.h
1114 +++ b/include/configs/mv-common.h
1115 @@ -77,4 +77,10 @@
1116 #define CONFIG_SYS_MAX_NAND_DEVICE 1
1117 #endif
1118
1119 +/*
1120 + * Kirkwood MMC
1121 + */
1122 +#if defined(CONFIG_KIRKWOOD) && defined(CONFIG_CMD_MMC)
1123 +#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
1124 +#endif /* defined(CONFIG_KIRKWOOD) && defined(CONFIG_CMD_MMC) */
1125 #endif /* _MV_COMMON_H */
1126 --- /dev/null
1127 +++ b/include/configs/pogoplugv4.h
1128 @@ -0,0 +1,127 @@
1129 +/*
1130 + * Copyright (C) 2014-2016 bodhi <mibodhi@gmail.com>
1131 + * Based on
1132 + *
1133 + * Copyright (C) 2012
1134 + * David Purdy <david.c.purdy@gmail.com>
1135 + *
1136 + * Based on Kirkwood support:
1137 + * (C) Copyright 2009
1138 + * Marvell Semiconductor <www.marvell.com>
1139 + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
1140 + *
1141 + * See file CREDITS for list of people who contributed to this
1142 + * project.
1143 + *
1144 + * This program is free software; you can redistribute it and/or
1145 + * modify it under the terms of the GNU General Public License as
1146 + * published by the Free Software Foundation; either version 2 of
1147 + * the License, or (at your option) any later version.
1148 + *
1149 + * This program is distributed in the hope that it will be useful,
1150 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1151 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1152 + * GNU General Public License for more details.
1153 + *
1154 + * You should have received a copy of the GNU General Public License
1155 + * along with this program; If not, see <http://www.gnu.org/licenses/>.
1156 + */
1157 +
1158 +#ifndef _CONFIG_POGOPLUGV4_H
1159 +#define _CONFIG_POGOPLUGV4_H
1160 +
1161 +/*
1162 + * Machine type definition and ID
1163 + */
1164 +#define MACH_TYPE_POGOPLUGV4 3960
1165 +#define CONFIG_MACH_TYPE MACH_TYPE_POGOPLUGV4
1166 +
1167 +/*
1168 + * High Level Configuration Options (easy to change)
1169 + */
1170 +#define CONFIG_FEROCEON_88FR131 /* #define CPU Core subversion */
1171 +#define CONFIG_KW88F6192 /* SOC Name */
1172 +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
1173 +
1174 +#define CONFIG_FEATURE_COMMAND_EDITING
1175 +#define CONFIG_SYS_64BIT_LBA
1176 +
1177 +/*
1178 + * Commands configuration
1179 + */
1180 +
1181 +#define CONFIG_KIRKWOOD_GPIO
1182 +#define CONFIG_PREBOOT
1183 +
1184 +/*
1185 + * mv-common.h should be defined after CMD configs since it used them
1186 + * to enable certain macros
1187 + */
1188 +#include "mv-common.h"
1189 +
1190 +/*
1191 + * Environment variables configurations
1192 + */
1193 +#ifdef CONFIG_CMD_NAND
1194 +
1195 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
1196 +
1197 +
1198 +#endif
1199 +
1200 +#define CONFIG_ENV_SIZE 0x20000 /* 128k */
1201 +#define CONFIG_ENV_ADDR 0x1c0000
1202 +#define CONFIG_ENV_OFFSET 0x1c0000 /* env starts here */
1203 +
1204 +/*
1205 + * Default environment variables
1206 + */
1207 +#define CONFIG_BOOTCOMMAND \
1208 + "usb reset ; " \
1209 + "fatload usb 0:1 0x2000000 initramfs.bin ; "\
1210 + "bootm 0x2000000 ; " \
1211 + "ubi part ubi; " \
1212 + "ubi read 0x800000 kernel; " \
1213 + "bootm 0x800000"
1214 +
1215 +#define CONFIG_EXTRA_ENV_SETTINGS \
1216 + "console=console=ttyS0,115200\0" \
1217 + "mtdids=nand0=orion_nand\0" \
1218 + "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
1219 + "bootargs_root=\0"
1220 +
1221 +/*
1222 + * Ethernet Driver configuration
1223 + */
1224 +#ifdef CONFIG_CMD_NET
1225 +#define CONFIG_NETCONSOLE
1226 +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
1227 +#define CONFIG_PHY_BASE_ADR 0
1228 +#endif /* CONFIG_CMD_NET */
1229 +
1230 +/*
1231 + * File system
1232 + */
1233 +#define CONFIG_JFFS2_NAND
1234 +#define CONFIG_JFFS2_LZO
1235 +
1236 +/*
1237 + * SATA
1238 + */
1239 +#ifdef CONFIG_MVSATA_IDE
1240 +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
1241 +#endif
1242 +
1243 +/*
1244 + * Date Time
1245 + */
1246 +#ifdef CONFIG_CMD_DATE
1247 +#define CONFIG_RTC_MV
1248 +#endif /* CONFIG_CMD_DATE */
1249 +
1250 +/*
1251 + * Kirkwood GPIO
1252 + */
1253 +#define CONFIG_KIRKWOOD_GPIO
1254 +
1255 +#endif /* _CONFIG_POGOPLUGV4_H */
1256 --- /dev/null
1257 +++ b/include/kirkwood_mmc.h
1258 @@ -0,0 +1,268 @@
1259 +/*
1260 + * (C) Copyright 2014 <ebbes.ebbes@gmail.com>
1261 + *
1262 + * Based on
1263 + *
1264 + * (C) Copyright 2012
1265 + * Marvell Semiconductor <www.marvell.com>
1266 + * Written-by: Gérald Kerma <uboot at doukki.net>
1267 + * See file CREDITS for list of people who contributed to this
1268 + * project.
1269 + *
1270 + * This program is free software; you can redistribute it and/or
1271 + * modify it under the terms of the GNU General Public License as
1272 + * published by the Free Software Foundation; either version 2 of
1273 + * the License, or (at your option) any later version.
1274 + *
1275 + * This program is distributed in the hope that it will be useful,
1276 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1277 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1278 + * GNU General Public License for more details.
1279 + *
1280 + * You should have received a copy of the GNU General Public License
1281 + * along with this program; if not, write to the Free Software
1282 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1283 + * MA 02111-1307 USA
1284 + */
1285 +
1286 +#ifndef __KIRKWOOD_MMC_H__
1287 +#define __KIRKWOOD_MMC_H__
1288 +
1289 +/*
1290 + * Clock rates
1291 + */
1292 +
1293 +#define KW_MMC_CLOCKRATE_MAX 50000000
1294 +#define KW_MMC_BASE_DIV_MAX 0x7ff
1295 +#define KW_MMC_BASE_FAST_CLOCK CONFIG_SYS_TCLK
1296 +#define KW_MMC_BASE_FAST_CLK_100 100000000
1297 +#define KW_MMC_BASE_FAST_CLK_200 200000000
1298 +
1299 +/*
1300 + * Macros
1301 + */
1302 +#define kwsd_write(offs, val) writel(val, CONFIG_SYS_MMC_BASE + (offs))
1303 +#define kwsd_read(offs) readl(CONFIG_SYS_MMC_BASE + (offs))
1304 +
1305 +#define KW_MMC_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
1306 +
1307 +/* SDIO register */
1308 +#define SDIO_SYS_ADDR_LOW 0x000
1309 +#define SDIO_SYS_ADDR_HI 0x004
1310 +#define SDIO_BLK_SIZE 0x008
1311 +#define SDIO_BLK_COUNT 0x00c
1312 +#define SDIO_ARG_LOW 0x010
1313 +#define SDIO_ARG_HI 0x014
1314 +#define SDIO_XFER_MODE 0x018
1315 +#define SDIO_CMD 0x01c
1316 +#define SDIO_RSP(i) (0x020 + ((i)<<2))
1317 +#define SDIO_RSP0 0x020
1318 +#define SDIO_RSP1 0x024
1319 +#define SDIO_RSP2 0x028
1320 +#define SDIO_RSP3 0x02c
1321 +#define SDIO_RSP4 0x030
1322 +#define SDIO_RSP5 0x034
1323 +#define SDIO_RSP6 0x038
1324 +#define SDIO_RSP7 0x03c
1325 +#define SDIO_BUF_DATA_PORT 0x040
1326 +#define SDIO_RSVED 0x044
1327 +#define SDIO_HW_STATE 0x048
1328 +#define SDIO_PRESENT_STATE0 0x048
1329 +#define SDIO_PRESENT_STATE1 0x04c
1330 +#define SDIO_HOST_CTRL 0x050
1331 +#define SDIO_BLK_GAP_CTRL 0x054
1332 +#define SDIO_CLK_CTRL 0x058
1333 +#define SDIO_SW_RESET 0x05c
1334 +#define SDIO_NOR_INTR_STATUS 0x060
1335 +#define SDIO_ERR_INTR_STATUS 0x064
1336 +#define SDIO_NOR_STATUS_EN 0x068
1337 +#define SDIO_ERR_STATUS_EN 0x06c
1338 +#define SDIO_NOR_INTR_EN 0x070
1339 +#define SDIO_ERR_INTR_EN 0x074
1340 +#define SDIO_AUTOCMD12_ERR_STATUS 0x078
1341 +#define SDIO_CURR_BYTE_LEFT 0x07c
1342 +#define SDIO_CURR_BLK_LEFT 0x080
1343 +#define SDIO_AUTOCMD12_ARG_LOW 0x084
1344 +#define SDIO_AUTOCMD12_ARG_HI 0x088
1345 +#define SDIO_AUTOCMD12_INDEX 0x08c
1346 +#define SDIO_AUTO_RSP(i) (0x090 + ((i)<<2))
1347 +#define SDIO_AUTO_RSP0 0x090
1348 +#define SDIO_AUTO_RSP1 0x094
1349 +#define SDIO_AUTO_RSP2 0x098
1350 +#define SDIO_CLK_DIV 0x128
1351 +
1352 +#define WINDOW_CTRL(i) (0x108 + ((i) << 3))
1353 +#define WINDOW_BASE(i) (0x10c + ((i) << 3))
1354 +
1355 +/* SDIO_PRESENT_STATE */
1356 +#define CARD_BUSY (1 << 1)
1357 +#define CMD_INHIBIT (1 << 0)
1358 +#define CMD_TXACTIVE (1 << 8)
1359 +#define CMD_RXACTIVE (1 << 9)
1360 +#define CMD_AUTOCMD12ACTIVE (1 << 14)
1361 +#define CMD_BUS_BUSY (CMD_AUTOCMD12ACTIVE | \
1362 + CMD_RXACTIVE | \
1363 + CMD_TXACTIVE | \
1364 + CMD_INHIBIT | \
1365 + CARD_BUSY)
1366 +
1367 +/*
1368 + * SDIO_CMD
1369 + */
1370 +
1371 +#define SDIO_CMD_RSP_NONE (0 << 0)
1372 +#define SDIO_CMD_RSP_136 (1 << 0)
1373 +#define SDIO_CMD_RSP_48 (2 << 0)
1374 +#define SDIO_CMD_RSP_48BUSY (3 << 0)
1375 +
1376 +#define SDIO_CMD_CHECK_DATACRC16 (1 << 2)
1377 +#define SDIO_CMD_CHECK_CMDCRC (1 << 3)
1378 +#define SDIO_CMD_INDX_CHECK (1 << 4)
1379 +#define SDIO_CMD_DATA_PRESENT (1 << 5)
1380 +#define SDIO_UNEXPECTED_RESP (1 << 7)
1381 +
1382 +#define SDIO_CMD_INDEX(x) ((x) << 8)
1383 +
1384 +/*
1385 + * SDIO_XFER_MODE
1386 + */
1387 +
1388 +#define SDIO_XFER_MODE_STOP_CLK (1 << 5)
1389 +#define SDIO_XFER_MODE_HW_WR_DATA_EN (1 << 1)
1390 +#define SDIO_XFER_MODE_AUTO_CMD12 (1 << 2)
1391 +#define SDIO_XFER_MODE_INT_CHK_EN (1 << 3)
1392 +#define SDIO_XFER_MODE_TO_HOST (1 << 4)
1393 +#define SDIO_XFER_MODE_DMA (0 << 6)
1394 +
1395 +/*
1396 + * SDIO_HOST_CTRL
1397 + */
1398 +
1399 +#define SDIO_HOST_CTRL_PUSH_PULL_EN (1 << 0)
1400 +
1401 +#define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY (0 << 1)
1402 +#define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY (1 << 1)
1403 +#define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO (2 << 1)
1404 +#define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC (3 << 1)
1405 +#define SDIO_HOST_CTRL_CARD_TYPE_MASK (3 << 1)
1406 +
1407 +#define SDIO_HOST_CTRL_BIG_ENDIAN (1 << 3)
1408 +#define SDIO_HOST_CTRL_LSB_FIRST (1 << 4)
1409 +#define SDIO_HOST_CTRL_DATA_WIDTH_1_BIT (0 << 9)
1410 +#define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS (1 << 9)
1411 +#define SDIO_HOST_CTRL_HI_SPEED_EN (1 << 10)
1412 +
1413 +#define SDIO_HOST_CTRL_TMOUT_MAX 0xf
1414 +#define SDIO_HOST_CTRL_TMOUT_MASK (0xf << 11)
1415 +#define SDIO_HOST_CTRL_TMOUT(x) ((x) << 11)
1416 +#define SDIO_HOST_CTRL_TMOUT_EN (1 << 15)
1417 +
1418 +/*
1419 + * SDIO_SW_RESET
1420 + */
1421 +
1422 +#define SDIO_SW_RESET_NOW (1 << 8)
1423 +
1424 +/*
1425 + * Normal interrupt status bits
1426 + */
1427 +
1428 +#define SDIO_NOR_ERROR (1 << 15)
1429 +#define SDIO_NOR_UNEXP_RSP (1 << 14)
1430 +#define SDIO_NOR_AUTOCMD12_DONE (1 << 13)
1431 +#define SDIO_NOR_SUSPEND_ON (1 << 12)
1432 +#define SDIO_NOR_LMB_FF_8W_AVAIL (1 << 11)
1433 +#define SDIO_NOR_LMB_FF_8W_FILLED (1 << 10)
1434 +#define SDIO_NOR_READ_WAIT_ON (1 << 9)
1435 +#define SDIO_NOR_CARD_INT (1 << 8)
1436 +#define SDIO_NOR_READ_READY (1 << 5)
1437 +#define SDIO_NOR_WRITE_READY (1 << 4)
1438 +#define SDIO_NOR_DMA_INI (1 << 3)
1439 +#define SDIO_NOR_BLK_GAP_EVT (1 << 2)
1440 +#define SDIO_NOR_XFER_DONE (1 << 1)
1441 +#define SDIO_NOR_CMD_DONE (1 << 0)
1442 +
1443 +/*
1444 + * Error status bits
1445 + */
1446 +
1447 +#define SDIO_ERR_CRC_STATUS (1 << 14)
1448 +#define SDIO_ERR_CRC_STARTBIT (1 << 13)
1449 +#define SDIO_ERR_CRC_ENDBIT (1 << 12)
1450 +#define SDIO_ERR_RESP_TBIT (1 << 11)
1451 +#define SDIO_ERR_XFER_SIZE (1 << 10)
1452 +#define SDIO_ERR_CMD_STARTBIT (1 << 9)
1453 +#define SDIO_ERR_AUTOCMD12 (1 << 8)
1454 +#define SDIO_ERR_DATA_ENDBIT (1 << 6)
1455 +#define SDIO_ERR_DATA_CRC (1 << 5)
1456 +#define SDIO_ERR_DATA_TIMEOUT (1 << 4)
1457 +#define SDIO_ERR_CMD_INDEX (1 << 3)
1458 +#define SDIO_ERR_CMD_ENDBIT (1 << 2)
1459 +#define SDIO_ERR_CMD_CRC (1 << 1)
1460 +#define SDIO_ERR_CMD_TIMEOUT (1 << 0)
1461 +#define SDIO_POLL_MASK 0xffff /* enable all for polling */
1462 +
1463 +#define MMC_BLOCK_SIZE 512
1464 +
1465 +/*
1466 + * CMD12 error status bits
1467 + */
1468 +
1469 +#define SDIO_AUTOCMD12_ERR_NOTEXE (1 << 0)
1470 +#define SDIO_AUTOCMD12_ERR_TIMEOUT (1 << 1)
1471 +#define SDIO_AUTOCMD12_ERR_CRC (1 << 2)
1472 +#define SDIO_AUTOCMD12_ERR_ENDBIT (1 << 3)
1473 +#define SDIO_AUTOCMD12_ERR_INDEX (1 << 4)
1474 +#define SDIO_AUTOCMD12_ERR_RESP_T_BIT (1 << 5)
1475 +#define SDIO_AUTOCMD12_ERR_RESP_STARTBIT (1 << 6)
1476 +
1477 +#define MMC_RSP_PRESENT (1 << 0)
1478 +#define MMC_RSP_136 (1 << 1) /* 136 bit response */
1479 +#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
1480 +#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
1481 +#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
1482 +
1483 +#define MMC_BUSMODE_OPENDRAIN 1
1484 +#define MMC_BUSMODE_PUSHPULL 2
1485 +
1486 +#define MMC_BUS_WIDTH_1 0
1487 +#define MMC_BUS_WIDTH_4 2
1488 +#define MMC_BUS_WIDTH_8 3
1489 +
1490 +#define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */
1491 +#define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */
1492 +#define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */
1493 +#define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */
1494 +#define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */
1495 +#define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */
1496 +#define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */
1497 +
1498 +#define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */
1499 +#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */
1500 +#define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */
1501 +#define MMC_CAP_1_8V_DDR (1 << 11) /* can support */
1502 + /* DDR mode at 1.8V */
1503 +#define MMC_CAP_1_2V_DDR (1 << 12) /* can support */
1504 + /* DDR mode at 1.2V */
1505 +#define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */
1506 +#define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */
1507 +#define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */
1508 +#define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */
1509 +#define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */
1510 +#define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */
1511 +#define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */
1512 +#define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */
1513 +#define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */
1514 +#define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */
1515 +#define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */
1516 +#define MMC_CAP_HW_RESET (1 << 31) /* Hardware reset */
1517 +
1518 +/*
1519 + * Functions prototypes
1520 + *
1521 + * Original patch had static function declarations in this header file.
1522 + * Those should rather not be declared in the header as they only cause compiler warnings.
1523 + */
1524 +int kw_mmc_initialize(bd_t *bis);
1525 +
1526 +#endif /* __KIRKWOOD_MMC_H__ */
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