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kobs-ng: add new package
[openwrt/staging/wigyori.git] / package / boot / uboot-lantiq / patches / 0025-MIPS-add-board-support-for-AVM-FritzBox-3370.patch
1 From 51f04c00e831b49587f9f766ff1af67d2122feb2 Mon Sep 17 00:00:00 2001
2 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 Date: Fri, 30 Nov 2012 18:09:47 +0100
4 Subject: MIPS: add board support for AVM FritzBox 3370
5
6 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
7
8 --- /dev/null
9 +++ b/board/avm/fb3370/Makefile
10 @@ -0,0 +1,29 @@
11 +#
12 +# This file is released under the terms of GPL v2 and any later version.
13 +# See the file COPYING in the root directory of the source tree for details.
14 +#
15 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
16 +# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
17 +#
18 +
19 +include $(TOPDIR)/config.mk
20 +
21 +LIB = $(obj)lib$(BOARD).o
22 +
23 +COBJS = $(BOARD).o
24 +
25 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
26 +OBJS := $(addprefix $(obj),$(COBJS))
27 +SOBJS := $(addprefix $(obj),$(SOBJS))
28 +
29 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
30 + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
31 +
32 +#########################################################################
33 +
34 +# defines $(obj).depend target
35 +include $(SRCTREE)/rules.mk
36 +
37 +sinclude $(obj).depend
38 +
39 +#########################################################################
40 --- /dev/null
41 +++ b/board/avm/fb3370/config.mk
42 @@ -0,0 +1,8 @@
43 +#
44 +# This file is released under the terms of GPL v2 and any later version.
45 +# See the file COPYING in the root directory of the source tree for details.
46 +#
47 +# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
48 +#
49 +
50 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
51 --- /dev/null
52 +++ b/board/avm/fb3370/ddr_settings.h
53 @@ -0,0 +1,70 @@
54 +/*
55 + * This file is released under the terms of GPL v2 and any later version.
56 + * See the file COPYING in the root directory of the source tree for details.
57 + *
58 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
59 + * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
60 + */
61 +
62 +#define MC_CCR00_VALUE 0x101
63 +#define MC_CCR01_VALUE 0x1000100
64 +#define MC_CCR02_VALUE 0x1010000
65 +#define MC_CCR03_VALUE 0x101
66 +#define MC_CCR04_VALUE 0x1000000
67 +#define MC_CCR05_VALUE 0x1000101
68 +#define MC_CCR06_VALUE 0x1000100
69 +#define MC_CCR07_VALUE 0x1010000
70 +#define MC_CCR08_VALUE 0x1000101
71 +#define MC_CCR09_VALUE 0x0
72 +#define MC_CCR10_VALUE 0x2000100
73 +#define MC_CCR11_VALUE 0x2000300
74 +#define MC_CCR12_VALUE 0x30000
75 +#define MC_CCR13_VALUE 0x202
76 +#define MC_CCR14_VALUE 0x7080A0F
77 +#define MC_CCR15_VALUE 0x2040F
78 +#define MC_CCR16_VALUE 0x40000
79 +#define MC_CCR17_VALUE 0x70102
80 +#define MC_CCR18_VALUE 0x4020002
81 +#define MC_CCR19_VALUE 0x30302
82 +#define MC_CCR20_VALUE 0x8000700
83 +#define MC_CCR21_VALUE 0x40F020A
84 +#define MC_CCR22_VALUE 0x0
85 +#define MC_CCR23_VALUE 0xC020000
86 +#define MC_CCR24_VALUE 0x4401B04
87 +#define MC_CCR25_VALUE 0x0
88 +#define MC_CCR26_VALUE 0x0
89 +#define MC_CCR27_VALUE 0x6420000
90 +#define MC_CCR28_VALUE 0x0
91 +#define MC_CCR29_VALUE 0x0
92 +#define MC_CCR30_VALUE 0x798
93 +#define MC_CCR31_VALUE 0x0
94 +#define MC_CCR32_VALUE 0x0
95 +#define MC_CCR33_VALUE 0x650000
96 +#define MC_CCR34_VALUE 0x200C8
97 +#define MC_CCR35_VALUE 0x1D445D
98 +#define MC_CCR36_VALUE 0xC8
99 +#define MC_CCR37_VALUE 0xC351
100 +#define MC_CCR38_VALUE 0x0
101 +#define MC_CCR39_VALUE 0x141F04
102 +#define MC_CCR40_VALUE 0x142704
103 +#define MC_CCR41_VALUE 0x141b42
104 +#define MC_CCR42_VALUE 0x141b42
105 +#define MC_CCR43_VALUE 0x566504
106 +#define MC_CCR44_VALUE 0x566504
107 +#define MC_CCR45_VALUE 0x565F17
108 +#define MC_CCR46_VALUE 0x565F17
109 +#define MC_CCR47_VALUE 0x0
110 +#define MC_CCR48_VALUE 0x0
111 +#define MC_CCR49_VALUE 0x0
112 +#define MC_CCR50_VALUE 0x0
113 +#define MC_CCR51_VALUE 0x0
114 +#define MC_CCR52_VALUE 0x133
115 +#define MC_CCR53_VALUE 0xF3014B27
116 +#define MC_CCR54_VALUE 0xF3014B27
117 +#define MC_CCR55_VALUE 0xF3014B27
118 +#define MC_CCR56_VALUE 0xF3014B27
119 +#define MC_CCR57_VALUE 0x7800301
120 +#define MC_CCR58_VALUE 0x7800301
121 +#define MC_CCR59_VALUE 0x7800301
122 +#define MC_CCR60_VALUE 0x7800301
123 +#define MC_CCR61_VALUE 0x4
124 --- /dev/null
125 +++ b/board/avm/fb3370/fb3370.c
126 @@ -0,0 +1,139 @@
127 +/*
128 + * This file is released under the terms of GPL v2 and any later version.
129 + * See the file COPYING in the root directory of the source tree for details.
130 + *
131 + * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
132 + */
133 +
134 +#include <common.h>
135 +#include <spi.h>
136 +#include <asm/gpio.h>
137 +#include <asm/lantiq/eth.h>
138 +#include <asm/lantiq/chipid.h>
139 +#include <asm/lantiq/cpu.h>
140 +#include <asm/arch/gphy.h>
141 +
142 +#if defined(CONFIG_SPL_BUILD)
143 +#define do_gpio_init 1
144 +#define do_pll_init 1
145 +#define do_dcdc_init 0
146 +#elif defined(CONFIG_SYS_BOOT_RAM)
147 +#define do_gpio_init 1
148 +#define do_pll_init 0
149 +#define do_dcdc_init 1
150 +#elif defined(CONFIG_SYS_BOOT_NOR)
151 +#define do_gpio_init 1
152 +#define do_pll_init 1
153 +#define do_dcdc_init 1
154 +#else
155 +#define do_gpio_init 0
156 +#define do_pll_init 0
157 +#define do_dcdc_init 1
158 +#endif
159 +
160 +static void gpio_init(void)
161 +{
162 + /* SPI CS 0.4 to serial flash */
163 + gpio_direction_output(10, 1);
164 +
165 + /* EBU.FL_CS1 as output for NAND CE */
166 + gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
167 + /* EBU.FL_A23 as output for NAND CLE */
168 + gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
169 + /* EBU.FL_A24 as output for NAND ALE */
170 + gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
171 + /* GPIO 3.0 as input for NAND Ready Busy */
172 + gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
173 + /* GPIO 3.1 as output for NAND Read */
174 + gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
175 +}
176 +
177 +int board_early_init_f(void)
178 +{
179 + if (do_gpio_init)
180 + gpio_init();
181 +
182 + if (do_pll_init)
183 + ltq_pll_init();
184 +
185 + if (do_dcdc_init)
186 + ltq_dcdc_init(0x7F);
187 +
188 + return 0;
189 +}
190 +
191 +int checkboard(void)
192 +{
193 + puts("Board: " CONFIG_BOARD_NAME "\n");
194 + ltq_chip_print_info();
195 +
196 + return 0;
197 +}
198 +
199 +static const struct ltq_eth_port_config eth_port_config[] = {
200 + /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */
201 + { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
202 + /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */
203 + { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
204 + /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */
205 + { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
206 + /* GMAC3: unused */
207 + { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
208 + /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */
209 + { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
210 + /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
211 + { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
212 +};
213 +
214 +static const struct ltq_eth_board_config eth_board_config = {
215 + .ports = eth_port_config,
216 + .num_ports = ARRAY_SIZE(eth_port_config),
217 +};
218 +
219 +int board_eth_init(bd_t * bis)
220 +{
221 + const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
222 + const ulong fw_addr = 0x80FF0000;
223 +
224 + ltq_gphy_phy11g_a1x_load(fw_addr);
225 +
226 + ltq_cgu_gphy_clk_src(clk);
227 +
228 + ltq_rcu_gphy_boot(0, fw_addr);
229 + ltq_rcu_gphy_boot(1, fw_addr);
230 +
231 + return ltq_eth_initialize(&eth_board_config);
232 +}
233 +
234 +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
235 +{
236 + if (bus)
237 + return 0;
238 +
239 + if (cs == 4)
240 + return 1;
241 +
242 + return 0;
243 +}
244 +
245 +void spi_cs_activate(struct spi_slave *slave)
246 +{
247 + switch (slave->cs) {
248 + case 4:
249 + gpio_set_value(10, 0);
250 + break;
251 + default:
252 + break;
253 + }
254 +}
255 +
256 +void spi_cs_deactivate(struct spi_slave *slave)
257 +{
258 + switch (slave->cs) {
259 + case 4:
260 + gpio_set_value(10, 1);
261 + break;
262 + default:
263 + break;
264 + }
265 +}
266 --- a/boards.cfg
267 +++ b/boards.cfg
268 @@ -451,6 +451,9 @@ incaip mips
269 incaip_100MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=100000000
270 incaip_133MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=133000000
271 incaip_150MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=150000000
272 +fb3370_ram mips mips32 fb3370 avm vrx200 fb3370:SYS_BOOT_RAM
273 +fb3370_eva mips mips32 fb3370 avm vrx200 fb3370:SYS_BOOT_EVA
274 +fb3370_sfspl mips mips32 fb3370 avm vrx200 fb3370:SYS_BOOT_SFSPL
275 easy80920_nor mips mips32 easy80920 lantiq vrx200 easy80920:SYS_BOOT_NOR
276 easy80920_norspl mips mips32 easy80920 lantiq vrx200 easy80920:SYS_BOOT_NORSPL
277 easy80920_ram mips mips32 easy80920 lantiq vrx200 easy80920:SYS_BOOT_RAM
278 --- /dev/null
279 +++ b/include/configs/fb3370.h
280 @@ -0,0 +1,75 @@
281 +/*
282 + * This file is released under the terms of GPL v2 and any later version.
283 + * See the file COPYING in the root directory of the source tree for details.
284 + *
285 + * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
286 + */
287 +
288 +#ifndef __CONFIG_H
289 +#define __CONFIG_H
290 +
291 +#define CONFIG_MACH_TYPE "FB3370"
292 +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
293 +#define CONFIG_BOARD_NAME "AVM FritzBox 3370"
294 +
295 +/* Configure SoC */
296 +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
297 +
298 +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
299 +
300 +#define CONFIG_LTQ_SUPPORT_SPI_FLASH
301 +#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29LV620 serial flash */
302 +
303 +#define CONFIG_LTQ_SUPPORT_NAND_FLASH
304 +
305 +#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */
306 +#define CONFIG_SPL_SPI_BUS 0
307 +#define CONFIG_SPL_SPI_CS 4
308 +#define CONFIG_SPL_SPI_MAX_HZ 25000000
309 +#define CONFIG_SPL_SPI_MODE 0
310 +
311 +#define CONFIG_LTQ_SPL_COMP_LZO
312 +#define CONFIG_LTQ_SPL_CONSOLE
313 +
314 +#define CONFIG_SYS_DRAM_PROBE
315 +
316 +/* Environment */
317 +#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS
318 +#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS
319 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ
320 +#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE
321 +
322 +#if defined(CONFIG_SYS_BOOT_SFSPL)
323 +#define CONFIG_ENV_IS_IN_SPI_FLASH
324 +#define CONFIG_ENV_OVERWRITE
325 +#define CONFIG_ENV_OFFSET (192 * 1024)
326 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
327 +#else
328 +#define CONFIG_ENV_IS_NOWHERE
329 +#endif
330 +
331 +#define CONFIG_ENV_SIZE (8 * 1024)
332 +
333 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
334 +
335 +/* Console */
336 +#define CONFIG_LTQ_ADVANCED_CONSOLE
337 +#define CONFIG_BAUDRATE 115200
338 +#define CONFIG_CONSOLE_ASC 1
339 +#define CONFIG_CONSOLE_DEV "ttyLTQ1"
340 +
341 +/* Commands */
342 +#define CONFIG_CMD_PING
343 +
344 +/* Pull in default board configs for Lantiq XWAY VRX200 */
345 +#include <asm/lantiq/config.h>
346 +#include <asm/arch/config.h>
347 +
348 +#define CONFIG_ENV_UPDATE_UBOOT_SF \
349 + "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0"
350 +
351 +#define CONFIG_EXTRA_ENV_SETTINGS \
352 + CONFIG_ENV_LANTIQ_DEFAULTS \
353 + CONFIG_ENV_UPDATE_UBOOT_SF
354 +
355 +#endif /* __CONFIG_H */
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