package/boot/uboot-lantiq/patches/0028-MIPS-add-board-support-for-Arcadyan-ARV4519.patch

   1 From 4a738c02a7190756e01ba58c93c4b07bc6d6c2aa Mon Sep 17 00:00:00 2001
   2 From: Luka Perkov <luka@openwrt.org>
   3 Date: Wed, 29 Aug 2012 22:08:42 +0200
   4 Subject: MIPS: add board support for Arcadyan ARV4519
   5
   6 Signed-off-by: Luka Perkov <luka@openwrt.org>
   7 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
   8
   9 --- /dev/null
  10 +++ b/board/arcadyan/arv4519pw/Makefile
  11 @@ -0,0 +1,29 @@
  12 +#
  13 +# This file is released under the terms of GPL v2 and any later version.
  14 +# See the file COPYING in the root directory of the source tree for details.
  15 +#
  16 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
  17 +# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
  18 +#
  19 +
  20 +include $(TOPDIR)/config.mk
  21 +
  22 +LIB    = $(obj)lib$(BOARD).o
  23 +
  24 +COBJS  = $(BOARD).o
  25 +
  26 +SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  27 +OBJS   := $(addprefix $(obj),$(COBJS))
  28 +SOBJS  := $(addprefix $(obj),$(SOBJS))
  29 +
  30 +$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
  31 +       $(call cmd_link_o_target, $(OBJS) $(SOBJS))
  32 +
  33 +#########################################################################
  34 +
  35 +# defines $(obj).depend target
  36 +include $(SRCTREE)/rules.mk
  37 +
  38 +sinclude $(obj).depend
  39 +
  40 +#########################################################################
  41 --- /dev/null
  42 +++ b/board/arcadyan/arv4519pw/arv4519pw.c
  43 @@ -0,0 +1,52 @@
  44 +/*
  45 + * This file is released under the terms of GPL v2 and any later version.
  46 + * See the file COPYING in the root directory of the source tree for details.
  47 + *
  48 + * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
  49 + */
  50 +
  51 +#include <common.h>
  52 +#include <switch.h>
  53 +#include <asm/gpio.h>
  54 +#include <asm/lantiq/eth.h>
  55 +#include <asm/lantiq/reset.h>
  56 +#include <asm/lantiq/chipid.h>
  57 +
  58 +int board_early_init_f(void)
  59 +{
  60 +       return 0;
  61 +}
  62 +
  63 +int checkboard(void)
  64 +{
  65 +       puts("Board: " CONFIG_BOARD_NAME "\n");
  66 +       ltq_chip_print_info();
  67 +
  68 +       return 0;
  69 +}
  70 +
  71 +static const struct ltq_eth_port_config eth_port_config[] = {
  72 +       /* MAC0: Atheros ar8216 switch */
  73 +       { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_NONE },
  74 +};
  75 +
  76 +static const struct ltq_eth_board_config eth_board_config = {
  77 +       .ports = eth_port_config,
  78 +       .num_ports = ARRAY_SIZE(eth_port_config),
  79 +};
  80 +
  81 +int board_eth_init(bd_t *bis)
  82 +{
  83 +       return ltq_eth_initialize(&eth_board_config);
  84 +}
  85 +
  86 +static struct switch_device ar8216_dev = {
  87 +       .name = "ar8216",
  88 +       .cpu_port = 0,
  89 +       .port_mask = 0xF,
  90 +};
  91 +
  92 +int board_switch_init(void)
  93 +{
  94 +       return switch_device_register(&ar8216_dev);
  95 +}
  96 --- /dev/null
  97 +++ b/board/arcadyan/arv4519pw/config.mk
  98 @@ -0,0 +1,8 @@
  99 +#
 100 +# This file is released under the terms of GPL v2 and any later version.
 101 +# See the file COPYING in the root directory of the source tree for details.
 102 +#
 103 +# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
 104 +#
 105 +
 106 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
 107 --- /dev/null
 108 +++ b/board/arcadyan/arv4519pw/ddr_settings.h
 109 @@ -0,0 +1,56 @@
 110 +/*
 111 + * This file is released under the terms of GPL v2 and any later version.
 112 + * See the file COPYING in the root directory of the source tree for details.
 113 + *
 114 + * generated with lantiq_ram_extract_magic.awk
 115 + *
 116 + * Copyright (C) 2011 Luka Perkov <luka@openwrt.org>
 117 + */
 118 +
 119 +#define MC_DC00_VALUE  0x1B1B
 120 +#define MC_DC01_VALUE  0x0
 121 +#define MC_DC02_VALUE  0x0
 122 +#define MC_DC03_VALUE  0x0
 123 +#define MC_DC04_VALUE  0x0
 124 +#define MC_DC05_VALUE  0x200
 125 +#define MC_DC06_VALUE  0x605
 126 +#define MC_DC07_VALUE  0x303
 127 +#define MC_DC08_VALUE  0x102
 128 +#define MC_DC09_VALUE  0x70A
 129 +#define MC_DC10_VALUE  0x203
 130 +#define MC_DC11_VALUE  0xC02
 131 +#define MC_DC12_VALUE  0x1C8
 132 +#define MC_DC13_VALUE  0x1
 133 +#define MC_DC14_VALUE  0x0
 134 +#define MC_DC15_VALUE  0x131
 135 +#define MC_DC16_VALUE  0xC800
 136 +#define MC_DC17_VALUE  0xD
 137 +#define MC_DC18_VALUE  0x301
 138 +#define MC_DC19_VALUE  0x200
 139 +#define MC_DC20_VALUE  0xA04
 140 +#define MC_DC21_VALUE  0x1700
 141 +#define MC_DC22_VALUE  0x1717
 142 +#define MC_DC23_VALUE  0x0
 143 +#define MC_DC24_VALUE  0x5A
 144 +#define MC_DC25_VALUE  0x0
 145 +#define MC_DC26_VALUE  0x0
 146 +#define MC_DC27_VALUE  0x0
 147 +#define MC_DC28_VALUE  0x510
 148 +#define MC_DC29_VALUE  0x4E20
 149 +#define MC_DC30_VALUE  0x8235
 150 +#define MC_DC31_VALUE  0x0
 151 +#define MC_DC32_VALUE  0x0
 152 +#define MC_DC33_VALUE  0x0
 153 +#define MC_DC34_VALUE  0x0
 154 +#define MC_DC35_VALUE  0x0
 155 +#define MC_DC36_VALUE  0x0
 156 +#define MC_DC37_VALUE  0x0
 157 +#define MC_DC38_VALUE  0x0
 158 +#define MC_DC39_VALUE  0x0
 159 +#define MC_DC40_VALUE  0x0
 160 +#define MC_DC41_VALUE  0x0
 161 +#define MC_DC42_VALUE  0x0
 162 +#define MC_DC43_VALUE  0x0
 163 +#define MC_DC44_VALUE  0x0
 164 +#define MC_DC45_VALUE  0x500
 165 +#define MC_DC46_VALUE  0x0
 166 --- a/boards.cfg
 167 +++ b/boards.cfg
 168 @@ -438,6 +438,8 @@ vct_premium                  mips
 169  vct_premium_onenand          mips        mips32      vct                 micronas       -           vct:VCT_PREMIUM,VCT_ONENAND
 170  vct_premium_onenand_small    mips        mips32      vct                 micronas       -           vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE
 171  vct_premium_small            mips        mips32      vct                 micronas       -           vct:VCT_PREMIUM,VCT_SMALL_IMAGE
 172 +arv4519pw_ram                mips        mips32      arv4519pw           arcadyan       danube      arv4519pw:SYS_BOOT_RAM
 173 +arv4519pw_nor                mips        mips32      arv4519pw           arcadyan       danube      arv4519pw:SYS_BOOT_NOR
 174  arv7518pw_ram                mips        mips32      arv7518pw           arcadyan       danube      arv7518pw:SYS_BOOT_RAM
 175  arv7518pw_nor                mips        mips32      arv7518pw           arcadyan       danube      arv7518pw:SYS_BOOT_NOR
 176  dbau1000                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1000
 177 --- /dev/null
 178 +++ b/include/configs/arv4519pw.h
 179 @@ -0,0 +1,69 @@
 180 +/*
 181 + * This file is released under the terms of GPL v2 and any later version.
 182 + * See the file COPYING in the root directory of the source tree for details.
 183 + *
 184 + * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
 185 + */
 186 +
 187 +#ifndef __CONFIG_H
 188 +#define __CONFIG_H
 189 +
 190 +#define CONFIG_MACH_TYPE       "ARV4519PW"
 191 +#define CONFIG_IDENT_STRING    " "CONFIG_MACH_TYPE
 192 +#define CONFIG_BOARD_NAME      "Arcadyan ARV4519PW"
 193 +
 194 +/* Configure SoC */
 195 +#define CONFIG_LTQ_SUPPORT_UART                /* Enable ASC and UART */
 196 +#define CONFIG_LTQ_SUPPORT_ETHERNET    /* Enable ethernet */
 197 +#define CONFIG_LTQ_SUPPORT_NOR_FLASH   /* Have a parallel NOR flash */
 198 +
 199 +/* Switch devices */
 200 +#define CONFIG_SWITCH_MULTI
 201 +#define CONFIG_SWITCH_AR8216
 202 +
 203 +/* Environment */
 204 +#if defined(CONFIG_SYS_BOOT_NOR)
 205 +#define CONFIG_ENV_IS_IN_FLASH
 206 +#define CONFIG_ENV_OVERWRITE
 207 +#define CONFIG_ENV_OFFSET              (192 * 1024)
 208 +#define CONFIG_ENV_SIZE                        (64 * 1024)
 209 +#define CONFIG_ENV_SECT_SIZE           (64 * 1024)
 210 +#else
 211 +#define CONFIG_ENV_IS_NOWHERE
 212 +#define CONFIG_ENV_SIZE                        (2 * 1024)
 213 +#endif
 214 +
 215 +#define CONFIG_LOADADDR                        CONFIG_SYS_LOAD_ADDR
 216 +
 217 +/* Console */
 218 +#define CONFIG_LTQ_ADVANCED_CONSOLE
 219 +#define CONFIG_BAUDRATE                        115200
 220 +#define CONFIG_CONSOLE_ASC             1
 221 +#define CONFIG_CONSOLE_DEV             "ttyLTQ1"
 222 +
 223 +/* Commands */
 224 +#define CONFIG_CMD_PING
 225 +
 226 +/* Pull in default board configs for Lantiq XWAY Danube */
 227 +#include <asm/lantiq/config.h>
 228 +#include <asm/arch/config.h>
 229 +
 230 +/* Compression */
 231 +#define CONFIG_LZMA
 232 +
 233 +/* Auto boot */
 234 +#define CONFIG_BOOTDELAY               2
 235 +
 236 +/* Environment configuration */
 237 +#define CONFIG_BOOTCOMMAND                     \
 238 +       "run addeth; bootm ${kernel_addr}"
 239 +
 240 +#define CONFIG_ENV_UPDATE_UBOOT_NOR            \
 241 +       "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
 242 +
 243 +#define CONFIG_EXTRA_ENV_SETTINGS              \
 244 +       CONFIG_ENV_LANTIQ_DEFAULTS              \
 245 +       CONFIG_ENV_UPDATE_UBOOT_NOR             \
 246 +       "kernel_addr=0xB0040000\0"
 247 +
 248 +#endif /* __CONFIG_H */