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uboot-lantiq: update to v2013.10
[openwrt/staging/wigyori.git] / package / boot / uboot-lantiq / patches / 0036-MIPS-add-board-support-for-Arcadyan-Easybox-904.patch
1 From 60856fa8f9866f292df740ea98752a70738eb59a Mon Sep 17 00:00:00 2001
2 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 Date: Fri, 9 Aug 2013 18:11:07 +0200
4 Subject: MIPS: add board support for Arcadyan Easybox 904
5
6 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
7
8 diff --git a/board/arcadyan/easybox904/Makefile b/board/arcadyan/easybox904/Makefile
9 new file mode 100644
10 index 0000000..0380dea
11 --- /dev/null
12 +++ b/board/arcadyan/easybox904/Makefile
13 @@ -0,0 +1,27 @@
14 +#
15 +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
16 +#
17 +# SPDX-License-Identifier: GPL-2.0+
18 +#
19 +
20 +include $(TOPDIR)/config.mk
21 +
22 +LIB = $(obj)lib$(BOARD).o
23 +
24 +COBJS = $(BOARD).o
25 +
26 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
27 +OBJS := $(addprefix $(obj),$(COBJS))
28 +SOBJS := $(addprefix $(obj),$(SOBJS))
29 +
30 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
31 + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
32 +
33 +#########################################################################
34 +
35 +# defines $(obj).depend target
36 +include $(SRCTREE)/rules.mk
37 +
38 +sinclude $(obj).depend
39 +
40 +#########################################################################
41 diff --git a/board/arcadyan/easybox904/config.mk b/board/arcadyan/easybox904/config.mk
42 new file mode 100644
43 index 0000000..9d8953b
44 --- /dev/null
45 +++ b/board/arcadyan/easybox904/config.mk
46 @@ -0,0 +1,7 @@
47 +#
48 +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
49 +#
50 +# SPDX-License-Identifier: GPL-2.0+
51 +#
52 +
53 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
54 diff --git a/board/arcadyan/easybox904/ddr_settings.h b/board/arcadyan/easybox904/ddr_settings.h
55 new file mode 100644
56 index 0000000..24541bc
57 --- /dev/null
58 +++ b/board/arcadyan/easybox904/ddr_settings.h
59 @@ -0,0 +1,68 @@
60 +/*
61 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
62 + *
63 + * SPDX-License-Identifier: GPL-2.0+
64 + */
65 +
66 +#define MC_CCR00_VALUE 0x101
67 +#define MC_CCR01_VALUE 0x1000100
68 +#define MC_CCR02_VALUE 0x1010000
69 +#define MC_CCR03_VALUE 0x101
70 +#define MC_CCR04_VALUE 0x1000000
71 +#define MC_CCR05_VALUE 0x1000101
72 +#define MC_CCR06_VALUE 0x1000100
73 +#define MC_CCR07_VALUE 0x1010000
74 +#define MC_CCR08_VALUE 0x1000101
75 +#define MC_CCR09_VALUE 0x1000000
76 +#define MC_CCR10_VALUE 0x2000100
77 +#define MC_CCR11_VALUE 0x2000300
78 +#define MC_CCR12_VALUE 0x30000
79 +#define MC_CCR13_VALUE 0x202
80 +#define MC_CCR14_VALUE 0x7080A0F
81 +#define MC_CCR15_VALUE 0x2040F
82 +#define MC_CCR16_VALUE 0x40000
83 +#define MC_CCR17_VALUE 0x70102
84 +#define MC_CCR18_VALUE 0x4020002
85 +#define MC_CCR19_VALUE 0x30302
86 +#define MC_CCR20_VALUE 0x8000700
87 +#define MC_CCR21_VALUE 0x40F020A
88 +#define MC_CCR22_VALUE 0x0
89 +#define MC_CCR23_VALUE 0xC020000
90 +#define MC_CCR24_VALUE 0x4401503
91 +#define MC_CCR25_VALUE 0x0
92 +#define MC_CCR26_VALUE 0x0
93 +#define MC_CCR27_VALUE 0x6420000
94 +#define MC_CCR28_VALUE 0x0
95 +#define MC_CCR29_VALUE 0x0
96 +#define MC_CCR30_VALUE 0x798
97 +#define MC_CCR31_VALUE 0x0
98 +#define MC_CCR32_VALUE 0x0
99 +#define MC_CCR33_VALUE 0x650000
100 +#define MC_CCR34_VALUE 0x200C8
101 +#define MC_CCR35_VALUE 0x1536B0
102 +#define MC_CCR36_VALUE 0xC8
103 +#define MC_CCR37_VALUE 0xC351
104 +#define MC_CCR38_VALUE 0x0
105 +#define MC_CCR39_VALUE 0x142404
106 +#define MC_CCR40_VALUE 0x142604
107 +#define MC_CCR41_VALUE 0x141B42
108 +#define MC_CCR42_VALUE 0x141B42
109 +#define MC_CCR43_VALUE 0x566504
110 +#define MC_CCR44_VALUE 0x566504
111 +#define MC_CCR45_VALUE 0x565F17
112 +#define MC_CCR46_VALUE 0x565F17
113 +#define MC_CCR47_VALUE 0x0
114 +#define MC_CCR48_VALUE 0x0
115 +#define MC_CCR49_VALUE 0x0
116 +#define MC_CCR50_VALUE 0x0
117 +#define MC_CCR51_VALUE 0x0
118 +#define MC_CCR52_VALUE 0x133
119 +#define MC_CCR53_VALUE 0xF3014B27
120 +#define MC_CCR54_VALUE 0xF3014B27
121 +#define MC_CCR55_VALUE 0xF3014B27
122 +#define MC_CCR56_VALUE 0xF3014B27
123 +#define MC_CCR57_VALUE 0x7C00301
124 +#define MC_CCR58_VALUE 0x7C00301
125 +#define MC_CCR59_VALUE 0x7C00301
126 +#define MC_CCR60_VALUE 0x7C00301
127 +#define MC_CCR61_VALUE 0x4
128 diff --git a/board/arcadyan/easybox904/easybox904.c b/board/arcadyan/easybox904/easybox904.c
129 new file mode 100644
130 index 0000000..4dbe044
131 --- /dev/null
132 +++ b/board/arcadyan/easybox904/easybox904.c
133 @@ -0,0 +1,98 @@
134 +/*
135 + * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
136 + *
137 + * SPDX-License-Identifier: GPL-2.0+
138 + */
139 +
140 +#include <common.h>
141 +#include <spi.h>
142 +#include <asm/gpio.h>
143 +#include <asm/lantiq/eth.h>
144 +#include <asm/lantiq/chipid.h>
145 +#include <asm/lantiq/cpu.h>
146 +#include <asm/arch/gphy.h>
147 +
148 +#if defined(CONFIG_SPL_BUILD)
149 +#define do_gpio_init 1
150 +#define do_pll_init 1
151 +#define do_dcdc_init 0
152 +#elif defined(CONFIG_SYS_BOOT_RAM)
153 +#define do_gpio_init 1
154 +#define do_pll_init 0
155 +#define do_dcdc_init 1
156 +#else
157 +#define do_gpio_init 0
158 +#define do_pll_init 0
159 +#define do_dcdc_init 1
160 +#endif
161 +
162 +static inline void gpio_init(void)
163 +{
164 + /* EBU.FL_CS1 as output for NAND CE */
165 + gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
166 + /* EBU.FL_A23 as output for NAND CLE */
167 + gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
168 + /* EBU.FL_A24 as output for NAND ALE */
169 + gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
170 + /* GPIO 3.0 as input for NAND Ready Busy */
171 + gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
172 + /* GPIO 3.1 as output for NAND Read */
173 + gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
174 +}
175 +
176 +int board_early_init_f(void)
177 +{
178 + if (do_gpio_init)
179 + gpio_init();
180 +
181 + if (do_pll_init)
182 + ltq_pll_init();
183 +
184 + if (do_dcdc_init)
185 + ltq_dcdc_init(0x7F);
186 +
187 + return 0;
188 +}
189 +
190 +int checkboard(void)
191 +{
192 + puts("Board: " CONFIG_BOARD_NAME "\n");
193 + ltq_chip_print_info();
194 +
195 + return 0;
196 +}
197 +
198 +static const struct ltq_eth_port_config eth_port_config[] = {
199 + /* GMAC0: ??? */
200 + { 0, 0x0, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE },
201 + /* GMAC1: ??? */
202 + { 1, 0x1, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE },
203 + /* GMAC2: ??? */
204 + { 2, 0x11, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE },
205 + /* GMAC3: unused */
206 + { 3, 0x0, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE },
207 + /* GMAC4: internal GPHY1 with 10/100/1000 firmware for WANoE port */
208 + { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
209 + /* GMAC5: ??? */
210 + { 5, 0x5, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE },
211 +};
212 +
213 +static const struct ltq_eth_board_config eth_board_config = {
214 + .ports = eth_port_config,
215 + .num_ports = ARRAY_SIZE(eth_port_config),
216 +};
217 +
218 +int board_eth_init(bd_t * bis)
219 +{
220 + const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
221 + const ulong fw_ge_addr = 0x80FE0000;
222 +
223 + ltq_gphy_phy11g_a2x_load(fw_ge_addr);
224 +
225 + ltq_cgu_gphy_clk_src(clk);
226 +
227 + ltq_rcu_gphy_boot(0, fw_ge_addr);
228 + ltq_rcu_gphy_boot(1, fw_ge_addr);
229 +
230 + return ltq_eth_initialize(&eth_board_config);
231 +}
232 diff --git a/boards.cfg b/boards.cfg
233 index 0cbf756..f10be39 100644
234 --- a/boards.cfg
235 +++ b/boards.cfg
236 @@ -529,6 +529,7 @@ Active mips mips32 incaip - incaip
237 Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
238 Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
239 Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
240 +Active mips mips32 vrx200 arcadyan easybox904 easybox904_ram easybox904:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
241 Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
242 Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
243 Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
244 diff --git a/include/configs/easybox904.h b/include/configs/easybox904.h
245 new file mode 100644
246 index 0000000..c892d77
247 --- /dev/null
248 +++ b/include/configs/easybox904.h
249 @@ -0,0 +1,45 @@
250 +/*
251 + * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
252 + *
253 + * SPDX-License-Identifier: GPL-2.0+
254 + */
255 +
256 +#ifndef __CONFIG_H
257 +#define __CONFIG_H
258 +
259 +#define CONFIG_MACH_TYPE "EASYBOX904"
260 +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
261 +#define CONFIG_BOARD_NAME "Arcadyan EasyBox 904"
262 +
263 +/* Configure SoC */
264 +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
265 +
266 +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
267 +
268 +#define CONFIG_LTQ_SUPPORT_NAND_FLASH
269 +
270 +#define CONFIG_SYS_DRAM_PROBE
271 +
272 +/* Environment */
273 +#define CONFIG_ENV_IS_NOWHERE
274 +
275 +#define CONFIG_ENV_SIZE (8 * 1024)
276 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
277 +
278 +/* Console */
279 +#define CONFIG_LTQ_ADVANCED_CONSOLE
280 +#define CONFIG_BAUDRATE 115200
281 +#define CONFIG_CONSOLE_ASC 1
282 +#define CONFIG_CONSOLE_DEV "ttyLTQ1"
283 +
284 +/* Pull in default board configs for Lantiq XWAY VRX200 */
285 +#include <asm/lantiq/config.h>
286 +#include <asm/arch/config.h>
287 +
288 +/* Pull in default OpenWrt configs for Lantiq SoC */
289 +#include "openwrt-lantiq-common.h"
290 +
291 +#define CONFIG_EXTRA_ENV_SETTINGS \
292 + CONFIG_ENV_LANTIQ_DEFAULTS
293 +
294 +#endif /* __CONFIG_H */
295 --
296 1.8.3.2
297
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