package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vr9.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_ptm_vr9.c
   4 ** PROJECT      : UEIP
   5 ** MODULES      : PTM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : PTM driver common source file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 *******************************************************************************/
  23
  24
  25
  26 /*
  27  * ####################################
  28  *              Head File
  29  * ####################################
  30  */
  31
  32 /*
  33  *  Common Head File
  34  */
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/version.h>
  38 #include <linux/types.h>
  39 #include <linux/errno.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/init.h>
  42 #include <linux/ioctl.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/reset.h>
  45 #include <asm/delay.h>
  46
  47 /*
  48  *  Chip Specific Head File
  49  */
  50 #include "ifxmips_ptm_vdsl.h"
  51 #include "ifxmips_ptm_fw_vr9.h"
  52
  53 #include <lantiq_soc.h>
  54
  55 static inline void init_pmu(void);
  56 static inline void uninit_pmu(void);
  57 static inline void reset_ppe(struct platform_device *pdev);
  58 static inline void init_pdma(void);
  59 static inline void init_mailbox(void);
  60 static inline void init_atm_tc(void);
  61 static inline void clear_share_buffer(void);
  62
  63 #define IFX_PMU_MODULE_PPE_SLL01  BIT(19)
  64 #define IFX_PMU_MODULE_PPE_TC     BIT(21)
  65 #define IFX_PMU_MODULE_PPE_EMA    BIT(22)
  66 #define IFX_PMU_MODULE_PPE_QSB    BIT(18)
  67 #define IFX_PMU_MODULE_AHBS       BIT(13)
  68 #define IFX_PMU_MODULE_DSL_DFE    BIT(9)
  69
  70
  71 static inline void init_pmu(void)
  72 {
  73         ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
  74                 IFX_PMU_MODULE_PPE_TC |
  75                 IFX_PMU_MODULE_PPE_EMA |
  76                 IFX_PMU_MODULE_AHBS |
  77                 IFX_PMU_MODULE_DSL_DFE);
  78
  79 }
  80
  81 static inline void uninit_pmu(void)
  82 {
  83 }
  84
  85 static inline void reset_ppe(struct platform_device *pdev)
  86 {
  87 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
  88         struct device *dev = &pdev->dev;
  89         struct reset_control *dsp;
  90         struct reset_control *dfe;
  91         struct reset_control *tc;
  92
  93         dsp = devm_reset_control_get(dev, "dsp");
  94         if (IS_ERR(dsp)) {
  95                 if (PTR_ERR(dsp) != -EPROBE_DEFER)
  96                         dev_err(dev, "Failed to lookup dsp reset\n");
  97 //              return PTR_ERR(dsp);
  98         }
  99
 100         dfe = devm_reset_control_get(dev, "dfe");
 101         if (IS_ERR(dfe)) {
 102                 if (PTR_ERR(dfe) != -EPROBE_DEFER)
 103                         dev_err(dev, "Failed to lookup dfe reset\n");
 104 //              return PTR_ERR(dfe);
 105         }
 106
 107         tc = devm_reset_control_get(dev, "tc");
 108         if (IS_ERR(tc)) {
 109                 if (PTR_ERR(tc) != -EPROBE_DEFER)
 110                         dev_err(dev, "Failed to lookup tc reset\n");
 111 //              return PTR_ERR(tc);
 112         }
 113
 114         reset_control_assert(dsp);
 115         udelay(1000);
 116         reset_control_assert(dfe);
 117         udelay(1000);
 118         reset_control_assert(tc);
 119         udelay(1000);
 120         *PP32_SRST &= ~0x000303CF;
 121         udelay(1000);
 122         *PP32_SRST |= 0x000303CF;
 123         udelay(1000);
 124 #endif
 125 }
 126
 127 static inline void init_pdma(void)
 128 {
 129     IFX_REG_W32(0x00000001, PDMA_CFG);
 130     IFX_REG_W32(0x00082C00, PDMA_RX_CTX_CFG);
 131     IFX_REG_W32(0x00081B00, PDMA_TX_CTX_CFG);
 132     IFX_REG_W32(0x02040604, PDMA_RX_MAX_LEN_REG);
 133     IFX_REG_W32(0x000F003F, PDMA_RX_DELAY_CFG);
 134
 135     IFX_REG_W32(0x00000011, SAR_MODE_CFG);
 136     IFX_REG_W32(0x00082A00, SAR_RX_CTX_CFG);
 137     IFX_REG_W32(0x00082E00, SAR_TX_CTX_CFG);
 138     IFX_REG_W32(0x00001021, SAR_POLY_CFG_SET0);
 139     IFX_REG_W32(0x1EDC6F41, SAR_POLY_CFG_SET1);
 140     IFX_REG_W32(0x04C11DB7, SAR_POLY_CFG_SET2);
 141     IFX_REG_W32(0x00000F3E, SAR_CRC_SIZE_CFG);
 142
 143     IFX_REG_W32(0x01001900, SAR_PDMA_RX_CMDBUF_CFG);
 144     IFX_REG_W32(0x01001A00, SAR_PDMA_TX_CMDBUF_CFG);
 145 }
 146
 147 static inline void init_mailbox(void)
 148 {
 149     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
 150     IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
 151     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
 152     IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
 153 }
 154
 155 static inline void init_atm_tc(void)
 156 {
 157     IFX_REG_W32(0x00010040, SFSM_CFG0);
 158     IFX_REG_W32(0x00010040, SFSM_CFG1);
 159     IFX_REG_W32(0x00020000, SFSM_PGCNT0);
 160     IFX_REG_W32(0x00020000, SFSM_PGCNT1);
 161     IFX_REG_W32(0x00000000, DREG_AT_IDLE0);
 162     IFX_REG_W32(0x00000000, DREG_AT_IDLE1);
 163     IFX_REG_W32(0x00000000, DREG_AR_IDLE0);
 164     IFX_REG_W32(0x00000000, DREG_AR_IDLE1);
 165     IFX_REG_W32(0x0000080C, DREG_B0_LADR);
 166     IFX_REG_W32(0x0000080C, DREG_B1_LADR);
 167
 168     IFX_REG_W32(0x000001F0, DREG_AR_CFG0);
 169     IFX_REG_W32(0x000001F0, DREG_AR_CFG1);
 170     IFX_REG_W32(0x000001E0, DREG_AT_CFG0);
 171     IFX_REG_W32(0x000001E0, DREG_AT_CFG1);
 172
 173     /*  clear sync state    */
 174     //IFX_REG_W32(0, SFSM_STATE0);
 175     //IFX_REG_W32(0, SFSM_STATE1);
 176
 177     IFX_REG_W32_MASK(0, 1 << 14, SFSM_CFG0);    //  enable SFSM storing
 178     IFX_REG_W32_MASK(0, 1 << 14, SFSM_CFG1);
 179
 180     IFX_REG_W32_MASK(0, 1 << 15, SFSM_CFG0);    //  HW keep the IDLE cells in RTHA buffer
 181     IFX_REG_W32_MASK(0, 1 << 15, SFSM_CFG1);
 182
 183     IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0);
 184     IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1);
 185     IFX_REG_W32(0x00030028, FFSM_CFG0);         //  Force_idle
 186     IFX_REG_W32(0x00030028, FFSM_CFG1);
 187 }
 188
 189 static inline void clear_share_buffer(void)
 190 {
 191     volatile u32 *p;
 192     unsigned int i;
 193
 194     p = SB_RAM0_ADDR(0);
 195     for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
 196         IFX_REG_W32(0, p++);
 197
 198     p = SB_RAM6_ADDR(0);
 199     for ( i = 0; i < SB_RAM6_DWLEN; i++ )
 200         IFX_REG_W32(0, p++);
 201 }
 202
 203 /*
 204  *  Description:
 205  *    Download PPE firmware binary code.
 206  *  Input:
 207  *    pp32      --- int, which pp32 core
 208  *    src       --- u32 *, binary code buffer
 209  *    dword_len --- unsigned int, binary code length in DWORD (32-bit)
 210  *  Output:
 211  *    int       --- 0:    Success
 212  *                  else:           Error Code
 213  */
 214 static inline int pp32_download_code(int pp32, u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
 215 {
 216     unsigned int clr, set;
 217     volatile u32 *dest;
 218
 219     if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
 220         || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
 221         return -1;
 222
 223     clr = pp32 ? 0xF0 : 0x0F;
 224     if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
 225         set = pp32 ? (3 << 6): (2 << 2);
 226     else
 227         set = 0x00;
 228     IFX_REG_W32_MASK(clr, set, CDM_CFG);
 229
 230     /*  copy code   */
 231     dest = CDM_CODE_MEMORY(pp32, 0);
 232     while ( code_dword_len-- > 0 )
 233         IFX_REG_W32(*code_src++, dest++);
 234
 235     /*  copy data   */
 236     dest = CDM_DATA_MEMORY(pp32, 0);
 237     while ( data_dword_len-- > 0 )
 238         IFX_REG_W32(*data_src++, dest++);
 239
 240     return 0;
 241 }
 242
 243
 244
 245 /*
 246  * ####################################
 247  *           Global Function
 248  * ####################################
 249  */
 250
 251 extern void ifx_ptm_get_fw_ver(unsigned int *major, unsigned int *minor)
 252 {
 253     ASSERT(major != NULL, "pointer is NULL");
 254     ASSERT(minor != NULL, "pointer is NULL");
 255
 256     *major = FW_VER_ID->major;
 257     *minor = FW_VER_ID->minor;
 258 }
 259
 260 void ifx_ptm_init_chip(struct platform_device *pdev)
 261 {
 262     init_pmu();
 263
 264     reset_ppe(pdev);
 265
 266     init_pdma();
 267
 268     init_mailbox();
 269
 270     init_atm_tc();
 271
 272     clear_share_buffer();
 273 }
 274
 275 void ifx_ptm_uninit_chip(void)
 276 {
 277     uninit_pmu();
 278 }
 279
 280 /*
 281  *  Description:
 282  *    Initialize and start up PP32.
 283  *  Input:
 284  *    none
 285  *  Output:
 286  *    int  --- 0: Success
 287  *             else:        Error Code
 288  */
 289 int ifx_pp32_start(int pp32)
 290 {
 291     unsigned int mask = 1 << (pp32 << 4);
 292     int ret;
 293
 294     /*  download firmware   */
 295     ret = pp32_download_code(pp32, firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
 296     if ( ret != 0 )
 297         return ret;
 298
 299     /*  run PP32    */
 300     IFX_REG_W32_MASK(mask, 0, PP32_FREEZE);
 301
 302     /*  idle for a while to let PP32 init itself    */
 303     udelay(10);
 304
 305     return 0;
 306 }
 307
 308 /*
 309  *  Description:
 310  *    Halt PP32.
 311  *  Input:
 312  *    none
 313  *  Output:
 314  *    none
 315  */
 316 void ifx_pp32_stop(int pp32)
 317 {
 318     unsigned int mask = 1 << (pp32 << 4);
 319
 320     /*  halt PP32   */
 321     IFX_REG_W32_MASK(0, mask, PP32_FREEZE);
 322 }