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ath9k: add back missing fixes from the last version
[openwrt/staging/wigyori.git] / package / kernel / mac80211 / patches / 300-pending_work.patch
1 commit fdf9a4517b60d847b9bc0a30249efd96559fa450
2 Author: Felix Fietkau <nbd@openwrt.org>
3 Date: Tue Sep 9 09:48:30 2014 +0200
4
5 ath9k_hw: fix PLL clock initialization for newer SoC
6
7 On AR934x and newer SoC devices, the layout of the AR_RTC_PLL_CONTROL
8 register changed. This currently breaks at least 5/10 MHz operation.
9 AR933x uses the old layout.
10
11 It might also have been causing other stability issues because of the
12 different location of the PLL_BYPASS bit which needs to be set during
13 PLL clock initialization.
14
15 This patch also removes more instances of hardcoded register values in
16 favor of properly computed ones with the PLL_BYPASS bit added.
17
18 Reported-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
19 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
20
21 commit b6d1f51cd8bdc9d952147a960fbf1f261d8e4188
22 Author: Felix Fietkau <nbd@openwrt.org>
23 Date: Mon Sep 8 18:35:08 2014 +0200
24
25 ath9k_hw: reduce ANI spur immunity setting on HT40 extension channel
26
27 The cycpwr_thr1 value needs to be lower on the extension channel than on
28 the control channel, similar to how the register settings are programmed
29 in the initvals.
30
31 Also drop the unnecessary check for HT40 - this register can always be
32 written. This patch has been reported to improve HT40 stability and
33 throughput in some environments.
34
35 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
36
37 commit 5ad2dfbaa19aa45d29184d30c8c5dae0e110074a
38 Author: Felix Fietkau <nbd@openwrt.org>
39 Date: Mon Sep 8 18:31:26 2014 +0200
40
41 Revert "ath9k_hw: reduce ANI firstep range for older chips"
42
43 This reverts commit 09efc56345be4146ab9fc87a55c837ed5d6ea1ab
44
45 I've received reports that this change is decreasing throughput in some
46 rare conditions on an AR9280 based device
47
48 Cc: stable@vger.kernel.org
49 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
50
51 commit 4c82fc569cf2f29e6c66d98ef4a1b0f3b6a98e9d
52 Author: Felix Fietkau <nbd@openwrt.org>
53 Date: Sat Sep 27 22:39:27 2014 +0200
54
55 ath9k_hw: disable hardware ad-hoc flag on ar934x rev 3
56
57 On AR934x rev 3, settin the ad-hoc flag completely messes up hardware
58 state - beacons get stuck, almost no packets make it out, hardware is
59 constantly reset.
60
61 When leaving out that flag and setting up the hw like in AP mode, TSF
62 timers won't be automatically synced, but at least the rest works.
63
64 AR934x rev 2 and older are not affected by this bug
65
66 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
67
68 commit ecfb4b3fff006372ac5c40871f9bb182fd00444f
69 Author: Felix Fietkau <nbd@openwrt.org>
70 Date: Sat Sep 27 22:15:43 2014 +0200
71
72 ath9k: use ah->get_mac_revision for all SoC devices if available
73
74 It is needed for AR934x as well
75
76 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
77
78 commit c11113bc25df22898fb995d3205bdc4f27c98073
79 Author: Felix Fietkau <nbd@openwrt.org>
80 Date: Sat Sep 27 18:04:58 2014 +0200
81
82 ath5k: add missing include for debug code
83
84 Needed for calling vmalloc()/vfree()
85
86 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
87
88 commit 83f76a9f9a42773c7eef90bb86b4b2c16b0b3755
89 Author: Felix Fietkau <nbd@openwrt.org>
90 Date: Sat Sep 27 15:58:51 2014 +0200
91
92 ath5k: fix AHB kconfig dependency
93
94 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
95
96 commit ddd67f2a5cfd73fad4b78190025402d419b9f0a9
97 Author: Felix Fietkau <nbd@openwrt.org>
98 Date: Sat Sep 27 15:57:09 2014 +0200
99
100 Revert "ath5k: Remove AHB bus support"
101
102 This reverts commit 093ec3c5337434f40d77c1af06c139da3e5ba6dc.
103
104 --- a/drivers/net/wireless/ath/ath5k/Kconfig
105 +++ b/drivers/net/wireless/ath/ath5k/Kconfig
106 @@ -2,12 +2,14 @@ config ATH5K
107 tristate "Atheros 5xxx wireless cards support"
108 depends on m
109 depends on PCI && MAC80211
110 + depends on (PCI || ATHEROS_AR231X) && MAC80211
111 select ATH_COMMON
112 select MAC80211_LEDS
113 select BACKPORT_LEDS_CLASS
114 select BACKPORT_NEW_LEDS
115 select BACKPORT_AVERAGE
116 - select ATH5K_PCI
117 + select ATH5K_AHB if ATHEROS_AR231X
118 + select ATH5K_PCI if !ATHEROS_AR231X
119 ---help---
120 This module adds support for wireless adapters based on
121 Atheros 5xxx chipset.
122 @@ -52,9 +54,16 @@ config ATH5K_TRACER
123
124 If unsure, say N.
125
126 +config ATH5K_AHB
127 + bool "Atheros 5xxx AHB bus support"
128 + depends on ATHEROS_AR231X
129 + ---help---
130 + This adds support for WiSoC type chipsets of the 5xxx Atheros
131 + family.
132 +
133 config ATH5K_PCI
134 bool "Atheros 5xxx PCI bus support"
135 - depends on PCI
136 + depends on !ATHEROS_AR231X
137 ---help---
138 This adds support for PCI type chipsets of the 5xxx Atheros
139 family.
140 --- /dev/null
141 +++ b/drivers/net/wireless/ath/ath5k/ahb.c
142 @@ -0,0 +1,234 @@
143 +/*
144 + * Copyright (c) 2008-2009 Atheros Communications Inc.
145 + * Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org>
146 + * Copyright (c) 2009 Imre Kaloz <kaloz@openwrt.org>
147 + *
148 + * Permission to use, copy, modify, and/or distribute this software for any
149 + * purpose with or without fee is hereby granted, provided that the above
150 + * copyright notice and this permission notice appear in all copies.
151 + *
152 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
153 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
154 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
155 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
156 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
157 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
158 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
159 + */
160 +
161 +#include <linux/nl80211.h>
162 +#include <linux/platform_device.h>
163 +#include <linux/etherdevice.h>
164 +#include <linux/export.h>
165 +#include <ar231x_platform.h>
166 +#include "ath5k.h"
167 +#include "debug.h"
168 +#include "base.h"
169 +#include "reg.h"
170 +
171 +/* return bus cachesize in 4B word units */
172 +static void ath5k_ahb_read_cachesize(struct ath_common *common, int *csz)
173 +{
174 + *csz = L1_CACHE_BYTES >> 2;
175 +}
176 +
177 +static bool
178 +ath5k_ahb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
179 +{
180 + struct ath5k_hw *ah = common->priv;
181 + struct platform_device *pdev = to_platform_device(ah->dev);
182 + struct ar231x_board_config *bcfg = dev_get_platdata(&pdev->dev);
183 + u16 *eeprom, *eeprom_end;
184 +
185 + eeprom = (u16 *) bcfg->radio;
186 + eeprom_end = ((void *) bcfg->config) + BOARD_CONFIG_BUFSZ;
187 +
188 + eeprom += off;
189 + if (eeprom > eeprom_end)
190 + return false;
191 +
192 + *data = *eeprom;
193 + return true;
194 +}
195 +
196 +int ath5k_hw_read_srev(struct ath5k_hw *ah)
197 +{
198 + struct platform_device *pdev = to_platform_device(ah->dev);
199 + struct ar231x_board_config *bcfg = dev_get_platdata(&pdev->dev);
200 + ah->ah_mac_srev = bcfg->devid;
201 + return 0;
202 +}
203 +
204 +static int ath5k_ahb_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
205 +{
206 + struct platform_device *pdev = to_platform_device(ah->dev);
207 + struct ar231x_board_config *bcfg = dev_get_platdata(&pdev->dev);
208 + u8 *cfg_mac;
209 +
210 + if (to_platform_device(ah->dev)->id == 0)
211 + cfg_mac = bcfg->config->wlan0_mac;
212 + else
213 + cfg_mac = bcfg->config->wlan1_mac;
214 +
215 + memcpy(mac, cfg_mac, ETH_ALEN);
216 + return 0;
217 +}
218 +
219 +static const struct ath_bus_ops ath_ahb_bus_ops = {
220 + .ath_bus_type = ATH_AHB,
221 + .read_cachesize = ath5k_ahb_read_cachesize,
222 + .eeprom_read = ath5k_ahb_eeprom_read,
223 + .eeprom_read_mac = ath5k_ahb_eeprom_read_mac,
224 +};
225 +
226 +/*Initialization*/
227 +static int ath_ahb_probe(struct platform_device *pdev)
228 +{
229 + struct ar231x_board_config *bcfg = dev_get_platdata(&pdev->dev);
230 + struct ath5k_hw *ah;
231 + struct ieee80211_hw *hw;
232 + struct resource *res;
233 + void __iomem *mem;
234 + int irq;
235 + int ret = 0;
236 + u32 reg;
237 +
238 + if (!dev_get_platdata(&pdev->dev)) {
239 + dev_err(&pdev->dev, "no platform data specified\n");
240 + ret = -EINVAL;
241 + goto err_out;
242 + }
243 +
244 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
245 + if (res == NULL) {
246 + dev_err(&pdev->dev, "no memory resource found\n");
247 + ret = -ENXIO;
248 + goto err_out;
249 + }
250 +
251 + mem = ioremap_nocache(res->start, resource_size(res));
252 + if (mem == NULL) {
253 + dev_err(&pdev->dev, "ioremap failed\n");
254 + ret = -ENOMEM;
255 + goto err_out;
256 + }
257 +
258 + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
259 + if (res == NULL) {
260 + dev_err(&pdev->dev, "no IRQ resource found\n");
261 + ret = -ENXIO;
262 + goto err_iounmap;
263 + }
264 +
265 + irq = res->start;
266 +
267 + hw = ieee80211_alloc_hw(sizeof(struct ath5k_hw), &ath5k_hw_ops);
268 + if (hw == NULL) {
269 + dev_err(&pdev->dev, "no memory for ieee80211_hw\n");
270 + ret = -ENOMEM;
271 + goto err_iounmap;
272 + }
273 +
274 + ah = hw->priv;
275 + ah->hw = hw;
276 + ah->dev = &pdev->dev;
277 + ah->iobase = mem;
278 + ah->irq = irq;
279 + ah->devid = bcfg->devid;
280 +
281 + if (bcfg->devid >= AR5K_SREV_AR2315_R6) {
282 + /* Enable WMAC AHB arbitration */
283 + reg = ioread32((void __iomem *) AR5K_AR2315_AHB_ARB_CTL);
284 + reg |= AR5K_AR2315_AHB_ARB_CTL_WLAN;
285 + iowrite32(reg, (void __iomem *) AR5K_AR2315_AHB_ARB_CTL);
286 +
287 + /* Enable global WMAC swapping */
288 + reg = ioread32((void __iomem *) AR5K_AR2315_BYTESWAP);
289 + reg |= AR5K_AR2315_BYTESWAP_WMAC;
290 + iowrite32(reg, (void __iomem *) AR5K_AR2315_BYTESWAP);
291 + } else {
292 + /* Enable WMAC DMA access (assuming 5312 or 231x*/
293 + /* TODO: check other platforms */
294 + reg = ioread32((void __iomem *) AR5K_AR5312_ENABLE);
295 + if (to_platform_device(ah->dev)->id == 0)
296 + reg |= AR5K_AR5312_ENABLE_WLAN0;
297 + else
298 + reg |= AR5K_AR5312_ENABLE_WLAN1;
299 + iowrite32(reg, (void __iomem *) AR5K_AR5312_ENABLE);
300 +
301 + /*
302 + * On a dual-band AR5312, the multiband radio is only
303 + * used as pass-through. Disable 2 GHz support in the
304 + * driver for it
305 + */
306 + if (to_platform_device(ah->dev)->id == 0 &&
307 + (bcfg->config->flags & (BD_WLAN0 | BD_WLAN1)) ==
308 + (BD_WLAN1 | BD_WLAN0))
309 + ah->ah_capabilities.cap_needs_2GHz_ovr = true;
310 + else
311 + ah->ah_capabilities.cap_needs_2GHz_ovr = false;
312 + }
313 +
314 + ret = ath5k_init_ah(ah, &ath_ahb_bus_ops);
315 + if (ret != 0) {
316 + dev_err(&pdev->dev, "failed to attach device, err=%d\n", ret);
317 + ret = -ENODEV;
318 + goto err_free_hw;
319 + }
320 +
321 + platform_set_drvdata(pdev, hw);
322 +
323 + return 0;
324 +
325 + err_free_hw:
326 + ieee80211_free_hw(hw);
327 + err_iounmap:
328 + iounmap(mem);
329 + err_out:
330 + return ret;
331 +}
332 +
333 +static int ath_ahb_remove(struct platform_device *pdev)
334 +{
335 + struct ar231x_board_config *bcfg = dev_get_platdata(&pdev->dev);
336 + struct ieee80211_hw *hw = platform_get_drvdata(pdev);
337 + struct ath5k_hw *ah;
338 + u32 reg;
339 +
340 + if (!hw)
341 + return 0;
342 +
343 + ah = hw->priv;
344 +
345 + if (bcfg->devid >= AR5K_SREV_AR2315_R6) {
346 + /* Disable WMAC AHB arbitration */
347 + reg = ioread32((void __iomem *) AR5K_AR2315_AHB_ARB_CTL);
348 + reg &= ~AR5K_AR2315_AHB_ARB_CTL_WLAN;
349 + iowrite32(reg, (void __iomem *) AR5K_AR2315_AHB_ARB_CTL);
350 + } else {
351 + /*Stop DMA access */
352 + reg = ioread32((void __iomem *) AR5K_AR5312_ENABLE);
353 + if (to_platform_device(ah->dev)->id == 0)
354 + reg &= ~AR5K_AR5312_ENABLE_WLAN0;
355 + else
356 + reg &= ~AR5K_AR5312_ENABLE_WLAN1;
357 + iowrite32(reg, (void __iomem *) AR5K_AR5312_ENABLE);
358 + }
359 +
360 + ath5k_deinit_ah(ah);
361 + iounmap(ah->iobase);
362 + ieee80211_free_hw(hw);
363 +
364 + return 0;
365 +}
366 +
367 +static struct platform_driver ath_ahb_driver = {
368 + .probe = ath_ahb_probe,
369 + .remove = ath_ahb_remove,
370 + .driver = {
371 + .name = "ar231x-wmac",
372 + .owner = THIS_MODULE,
373 + },
374 +};
375 +
376 +module_platform_driver(ath_ahb_driver);
377 --- a/drivers/net/wireless/ath/ath5k/ath5k.h
378 +++ b/drivers/net/wireless/ath/ath5k/ath5k.h
379 @@ -1647,6 +1647,32 @@ static inline struct ath_regulatory *ath
380 return &(ath5k_hw_common(ah)->regulatory);
381 }
382
383 +#ifdef CONFIG_ATHEROS_AR231X
384 +#define AR5K_AR2315_PCI_BASE ((void __iomem *)0xb0100000)
385 +
386 +static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg)
387 +{
388 + /* On AR2315 and AR2317 the PCI clock domain registers
389 + * are outside of the WMAC register space */
390 + if (unlikely((reg >= 0x4000) && (reg < 0x5000) &&
391 + (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6)))
392 + return AR5K_AR2315_PCI_BASE + reg;
393 +
394 + return ah->iobase + reg;
395 +}
396 +
397 +static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
398 +{
399 + return ioread32(ath5k_ahb_reg(ah, reg));
400 +}
401 +
402 +static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
403 +{
404 + iowrite32(val, ath5k_ahb_reg(ah, reg));
405 +}
406 +
407 +#else
408 +
409 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
410 {
411 return ioread32(ah->iobase + reg);
412 @@ -1657,6 +1683,8 @@ static inline void ath5k_hw_reg_write(st
413 iowrite32(val, ah->iobase + reg);
414 }
415
416 +#endif
417 +
418 static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah)
419 {
420 return ath5k_hw_common(ah)->bus_ops->ath_bus_type;
421 --- a/drivers/net/wireless/ath/ath5k/base.c
422 +++ b/drivers/net/wireless/ath/ath5k/base.c
423 @@ -99,6 +99,15 @@ static int ath5k_reset(struct ath5k_hw *
424
425 /* Known SREVs */
426 static const struct ath5k_srev_name srev_names[] = {
427 +#ifdef CONFIG_ATHEROS_AR231X
428 + { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
429 + { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
430 + { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
431 + { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
432 + { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
433 + { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
434 + { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
435 +#else
436 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
437 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
438 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
439 @@ -117,6 +126,7 @@ static const struct ath5k_srev_name srev
440 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
441 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
442 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
443 +#endif
444 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
445 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
446 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
447 @@ -132,6 +142,10 @@ static const struct ath5k_srev_name srev
448 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
449 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
450 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
451 +#ifdef CONFIG_ATHEROS_AR231X
452 + { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
453 + { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
454 +#endif
455 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
456 };
457
458 --- a/drivers/net/wireless/ath/ath5k/led.c
459 +++ b/drivers/net/wireless/ath/ath5k/led.c
460 @@ -163,14 +163,20 @@ int ath5k_init_leds(struct ath5k_hw *ah)
461 {
462 int ret = 0;
463 struct ieee80211_hw *hw = ah->hw;
464 +#ifndef CONFIG_ATHEROS_AR231X
465 struct pci_dev *pdev = ah->pdev;
466 +#endif
467 char name[ATH5K_LED_MAX_NAME_LEN + 1];
468 const struct pci_device_id *match;
469
470 if (!ah->pdev)
471 return 0;
472
473 +#ifdef CONFIG_ATHEROS_AR231X
474 + match = NULL;
475 +#else
476 match = pci_match_id(&ath5k_led_devices[0], pdev);
477 +#endif
478 if (match) {
479 __set_bit(ATH_STAT_LEDSOFT, ah->status);
480 ah->led_pin = ATH_PIN(match->driver_data);
481 --- a/drivers/net/wireless/ath/ath5k/debug.c
482 +++ b/drivers/net/wireless/ath/ath5k/debug.c
483 @@ -65,6 +65,7 @@
484
485 #include <linux/seq_file.h>
486 #include <linux/list.h>
487 +#include <linux/vmalloc.h>
488 #include "debug.h"
489 #include "ath5k.h"
490 #include "reg.h"
491 --- a/drivers/net/wireless/ath/ath9k/hw.c
492 +++ b/drivers/net/wireless/ath/ath9k/hw.c
493 @@ -222,31 +222,28 @@ static void ath9k_hw_read_revisions(stru
494 {
495 u32 val;
496
497 + if (ah->get_mac_revision)
498 + ah->hw_version.macRev = ah->get_mac_revision();
499 +
500 switch (ah->hw_version.devid) {
501 case AR5416_AR9100_DEVID:
502 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
503 break;
504 case AR9300_DEVID_AR9330:
505 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
506 - if (ah->get_mac_revision) {
507 - ah->hw_version.macRev = ah->get_mac_revision();
508 - } else {
509 + if (!ah->get_mac_revision) {
510 val = REG_READ(ah, AR_SREV);
511 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
512 }
513 return;
514 case AR9300_DEVID_AR9340:
515 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
516 - val = REG_READ(ah, AR_SREV);
517 - ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
518 return;
519 case AR9300_DEVID_QCA955X:
520 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
521 return;
522 case AR9300_DEVID_AR953X:
523 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
524 - if (ah->get_mac_revision)
525 - ah->hw_version.macRev = ah->get_mac_revision();
526 return;
527 }
528
529 @@ -704,6 +701,8 @@ static void ath9k_hw_init_pll(struct ath
530 {
531 u32 pll;
532
533 + pll = ath9k_hw_compute_pll_control(ah, chan);
534 +
535 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
536 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
537 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
538 @@ -754,7 +753,8 @@ static void ath9k_hw_init_pll(struct ath
539 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
540 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
541
542 - REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
543 + REG_WRITE(ah, AR_RTC_PLL_CONTROL,
544 + pll | AR_RTC_9300_PLL_BYPASS);
545 udelay(1000);
546
547 /* program refdiv, nint, frac to RTC register */
548 @@ -770,7 +770,8 @@ static void ath9k_hw_init_pll(struct ath
549 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
550 u32 regval, pll2_divint, pll2_divfrac, refdiv;
551
552 - REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
553 + REG_WRITE(ah, AR_RTC_PLL_CONTROL,
554 + pll | AR_RTC_9300_SOC_PLL_BYPASS);
555 udelay(1000);
556
557 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
558 @@ -843,7 +844,6 @@ static void ath9k_hw_init_pll(struct ath
559 udelay(1000);
560 }
561
562 - pll = ath9k_hw_compute_pll_control(ah, chan);
563 if (AR_SREV_9565(ah))
564 pll |= 0x40000;
565 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
566 @@ -1192,9 +1192,12 @@ static void ath9k_hw_set_operating_mode(
567
568 switch (opmode) {
569 case NL80211_IFTYPE_ADHOC:
570 - set |= AR_STA_ID1_ADHOC;
571 - REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
572 - break;
573 + if (!AR_SREV_9340_13(ah)) {
574 + set |= AR_STA_ID1_ADHOC;
575 + REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
576 + break;
577 + }
578 + /* fall through */
579 case NL80211_IFTYPE_MESH_POINT:
580 case NL80211_IFTYPE_AP:
581 set |= AR_STA_ID1_STA_AP;
582 --- a/drivers/net/wireless/ath/ath9k/reg.h
583 +++ b/drivers/net/wireless/ath/ath9k/reg.h
584 @@ -903,6 +903,10 @@
585 #define AR_SREV_9340(_ah) \
586 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9340))
587
588 +#define AR_SREV_9340_13(_ah) \
589 + (AR_SREV_9340((_ah)) && \
590 + ((_ah)->hw_version.macRev == AR_SREV_REVISION_9340_13))
591 +
592 #define AR_SREV_9340_13_OR_LATER(_ah) \
593 (AR_SREV_9340((_ah)) && \
594 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9340_13))
595 @@ -1240,12 +1244,23 @@ enum {
596 #define AR_CH0_DPLL3_PHASE_SHIFT_S 23
597 #define AR_PHY_CCA_NOM_VAL_2GHZ -118
598
599 +#define AR_RTC_9300_SOC_PLL_DIV_INT 0x0000003f
600 +#define AR_RTC_9300_SOC_PLL_DIV_INT_S 0
601 +#define AR_RTC_9300_SOC_PLL_DIV_FRAC 0x000fffc0
602 +#define AR_RTC_9300_SOC_PLL_DIV_FRAC_S 6
603 +#define AR_RTC_9300_SOC_PLL_REFDIV 0x01f00000
604 +#define AR_RTC_9300_SOC_PLL_REFDIV_S 20
605 +#define AR_RTC_9300_SOC_PLL_CLKSEL 0x06000000
606 +#define AR_RTC_9300_SOC_PLL_CLKSEL_S 25
607 +#define AR_RTC_9300_SOC_PLL_BYPASS 0x08000000
608 +
609 #define AR_RTC_9300_PLL_DIV 0x000003ff
610 #define AR_RTC_9300_PLL_DIV_S 0
611 #define AR_RTC_9300_PLL_REFDIV 0x00003C00
612 #define AR_RTC_9300_PLL_REFDIV_S 10
613 #define AR_RTC_9300_PLL_CLKSEL 0x0000C000
614 #define AR_RTC_9300_PLL_CLKSEL_S 14
615 +#define AR_RTC_9300_PLL_BYPASS 0x00010000
616
617 #define AR_RTC_9160_PLL_DIV 0x000003ff
618 #define AR_RTC_9160_PLL_DIV_S 0
619 --- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
620 +++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
621 @@ -1004,9 +1004,11 @@ static bool ar5008_hw_ani_control_new(st
622 case ATH9K_ANI_FIRSTEP_LEVEL:{
623 u32 level = param;
624
625 - value = level;
626 + value = level * 2;
627 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
628 AR_PHY_FIND_SIG_FIRSTEP, value);
629 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
630 + AR_PHY_FIND_SIG_FIRSTEP_LOW, value);
631
632 if (level != aniState->firstepLevel) {
633 ath_dbg(common, ANI,
634 @@ -1040,9 +1042,8 @@ static bool ar5008_hw_ani_control_new(st
635 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
636 AR_PHY_TIMING5_CYCPWR_THR1, value);
637
638 - if (IS_CHAN_HT40(ah->curchan))
639 - REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
640 - AR_PHY_EXT_TIMING5_CYCPWR_THR1, value);
641 + REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
642 + AR_PHY_EXT_TIMING5_CYCPWR_THR1, value - 1);
643
644 if (level != aniState->spurImmunityLevel) {
645 ath_dbg(common, ANI,
646 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
647 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
648 @@ -517,6 +517,23 @@ static void ar9003_hw_spur_mitigate(stru
649 ar9003_hw_spur_mitigate_ofdm(ah, chan);
650 }
651
652 +static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah,
653 + struct ath9k_channel *chan)
654 +{
655 + u32 pll;
656 +
657 + pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV);
658 +
659 + if (chan && IS_CHAN_HALF_RATE(chan))
660 + pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL);
661 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
662 + pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL);
663 +
664 + pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT);
665 +
666 + return pll;
667 +}
668 +
669 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
670 struct ath9k_channel *chan)
671 {
672 @@ -1781,7 +1798,12 @@ void ar9003_hw_attach_phy_ops(struct ath
673
674 priv_ops->rf_set_freq = ar9003_hw_set_channel;
675 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
676 - priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
677 +
678 + if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah))
679 + priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc;
680 + else
681 + priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
682 +
683 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
684 priv_ops->init_bb = ar9003_hw_init_bb;
685 priv_ops->process_ini = ar9003_hw_process_ini;
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