target/linux/amazon-2.6/files/include/asm-mips/amazon/amazon_mei.h

   1 #ifndef         _AMAZON_MEI_H
   2 #define         _AMAZON_MEI_H
   3 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
   4
   5 #include "amazon_mei_app.h"
   6
   7 #define AMAZON_MEI_DEBUG_ON
   8 #define AMAZON_MEI_CMV_EXTRA
   9
  10 #define AMAZON_MEI_MAJOR        106
  11
  12 /*
  13 **      Define where in ME Processor's memory map the Stratify chip lives
  14 */
  15 #define MEI_SPACE_ACCESS        0xB0100C00
  16
  17 #define MAXSWAPSIZE             8 * 1024        //8k *(32bits)
  18 //#define AMAZON_ADSL_IMAGESIZE  16*1024        // 16k * (32bits)
  19
  20
  21 //      Mailboxes
  22 #define MSG_LENGTH              16      // x16 bits
  23 #define YES_REPLY               1
  24 #define NO_REPLY                0
  25
  26 #define CMV_TIMEOUT             100     //jiffies
  27 #define MIB_INTERVAL            10000   //msec
  28
  29 /***  Bit definitions ***/
  30
  31 #define FALSE   0
  32 #define TRUE    1
  33 #define BIT0    1<<0
  34 #define BIT1    1<<1
  35 #define BIT2    1<<2
  36 #define BIT3    1<<3
  37 #define BIT4    1<<4
  38 #define BIT5    1<<5
  39 #define BIT6    1<<6
  40 #define BIT7    1<<7
  41 #define BIT8    1<<8
  42 #define BIT9    1<<9
  43 #define BIT10   1<<10
  44 #define BIT11   1<<11
  45 #define BIT12   1<<12
  46 #define BIT13   1<<13
  47 #define BIT14   1<<14
  48 #define BIT15   1<<15
  49 #define BIT16   1<<16
  50 #define BIT17   1<<17
  51 #define BIT18   1<<18
  52 #define BIT19   1<<19
  53 #define BIT20   1<<20
  54 #define BIT21   1<<21
  55 #define BIT22   1<<22
  56 #define BIT23   1<<23
  57 #define BIT24   1<<24
  58 #define BIT25   1<<25
  59 #define BIT26   1<<26
  60 #define BIT27   1<<27
  61 #define BIT28   1<<28
  62 #define BIT29   1<<29
  63 #define BIT30   1<<30
  64 #define BIT31   1<<31
  65
  66
  67 /***    Register address offsets, relative to MEI_SPACE_ADDRESS ***/
  68 #define MEI_DATA_XFR                            (0x0000 + MEI_SPACE_ACCESS)
  69 #define MEI_VERSION                             (0x0200 + MEI_SPACE_ACCESS)
  70 #define ARC_GP_STAT                             (0x0204 + MEI_SPACE_ACCESS)
  71 #define MEI_XFR_ADDR                            (0x020C + MEI_SPACE_ACCESS)
  72 #define MEI_TO_ARC_INT                          (0x021C + MEI_SPACE_ACCESS)
  73 #define ARC_TO_MEI_INT                          (0x0220 + MEI_SPACE_ACCESS)
  74 #define ARC_TO_MEI_INT_MASK                     (0x0224 + MEI_SPACE_ACCESS)
  75 #define MEI_DEBUG_WAD                           (0x0228 + MEI_SPACE_ACCESS)
  76 #define MEI_DEBUG_RAD                           (0x022C + MEI_SPACE_ACCESS)
  77 #define MEI_DEBUG_DATA                          (0x0230 + MEI_SPACE_ACCESS)
  78 #define MEI_DEBUG_DEC                           (0x0234 + MEI_SPACE_ACCESS)
  79 #define MEI_CONTROL                             (0x0238 + MEI_SPACE_ACCESS)
  80 #define AT_CELLRDY_BC0                          (0x023C + MEI_SPACE_ACCESS)
  81 #define AT_CELLRDY_BC1                          (0x0240 + MEI_SPACE_ACCESS)
  82 #define AR_CELLRDY_BC0                          (0x0244 + MEI_SPACE_ACCESS)
  83 #define AR_CELLRDY_BC1                          (0x0248 + MEI_SPACE_ACCESS)
  84 #define AAI_ACCESS                              (0x024C + MEI_SPACE_ACCESS)
  85 #define AAITXCB0                                (0x0300 + MEI_SPACE_ACCESS)
  86 #define AAITXCB1                                (0x0304 + MEI_SPACE_ACCESS)
  87 #define AAIRXCB0                                (0x0308 + MEI_SPACE_ACCESS)
  88 #define AAIRXCB1                                (0x030C + MEI_SPACE_ACCESS)
  89
  90
  91 //      MEI_TO_ARC_INTERRUPT Register definitions
  92 #define MEI_TO_ARC_INT1                 BIT3
  93 #define MEI_TO_ARC_INT0                 BIT2
  94 #define MEI_TO_ARC_CS_DONE              BIT1
  95 #define MEI_TO_ARC_MSGAV                BIT0
  96
  97 //      ARC_TO_MEI_INTERRUPT Register definitions
  98 #define ARC_TO_MEI_INT1                 BIT8
  99 #define ARC_TO_MEI_INT0                 BIT7
 100 #define ARC_TO_MEI_CS_REQ               BIT6
 101 #define ARC_TO_MEI_DBG_DONE             BIT5
 102 #define ARC_TO_MEI_MSGACK               BIT4
 103 #define ARC_TO_MEI_NO_ACCESS            BIT3
 104 #define ARC_TO_MEI_CHECK_AAITX          BIT2
 105 #define ARC_TO_MEI_CHECK_AAIRX          BIT1
 106 #define ARC_TO_MEI_MSGAV                BIT0
 107
 108 //      ARC_TO_MEI_INTERRUPT_MASK Register definitions
 109 #define GP_INT1_EN                      BIT8
 110 #define GP_INT0_EN                      BIT7
 111 #define CS_REQ_EN                       BIT6
 112 #define DBG_DONE_EN                     BIT5
 113 #define MSGACK_EN                       BIT4
 114 #define NO_ACC_EN                       BIT3
 115 #define AAITX_EN                        BIT2
 116 #define AAIRX_EN                        BIT1
 117 #define MSGAV_EN                        BIT0
 118
 119 //      MEI_CONTROL Register definitions
 120 #define INT_LEVEL                       BIT2
 121 #define SOFT_RESET                      BIT1
 122 #define HOST_MSTR                       BIT0
 123
 124 //      MEI_DEBUG_DECODE Register definitions
 125 #define MEI_DEBUG_DEC_MASK              (0x3)
 126 #define MEI_DEBUG_DEC_AUX_MASK          (0x0)
 127 #define MEI_DEBUG_DEC_DMP1_MASK         (0x1)
 128 #define MEI_DEBUG_DEC_DMP2_MASK         (0x2)
 129 #define MEI_DEBUG_DEC_CORE_MASK         (0x3)
 130
 131
 132 //      ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
 133 //      page swap requests.
 134 #define MEI_TO_ARC_MAILBOX              (0x15FC0)
 135 #define MEI_TO_ARC_MAILBOXR             (0x15FEC)
 136 #define ARC_TO_MEI_MAILBOX              (0x15F90)
 137 #define ARC_MEI_MAILBOXR                (0x15FBC)
 138
 139 // Codeswap request messages are indicated by setting BIT31
 140 #define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK      (0x80000000)
 141
 142 /*
 143 **      Swap page header
 144 */
 145 //      Page must be loaded at boot time if size field has BIT31 set
 146 #define BOOT_FLAG       (BIT31)
 147 #define BOOT_FLAG_MASK  ~BOOT_FLAG
 148
 149 //      Swap page header describes size in 32-bit words, load location, and image offset
 150 //      for program and/or data segments
 151 typedef struct _arc_swp_page_hdr
 152 {
 153         u32             p_offset;       //      Offset bytes of progseg from beginning of image
 154         u32             p_dest;         //      Destination addr of progseg on processor
 155         u32             p_size;         //      Size in 32-bitwords of program segment
 156         u32             d_offset;       //      Offset bytes of dataseg from beginning of image
 157         u32             d_dest;         //      Destination addr of dataseg on processor
 158         u32             d_size;         //      Size in 32-bitwords of data segment
 159 }ARC_SWP_PAGE_HDR;
 160
 161
 162 /*
 163 **      Swap image header
 164 */
 165 #define GET_PROG        0       //      Flag used for program mem segment
 166 #define GET_DATA        1       //      Flag used for data mem segment
 167
 168 //      Image header contains size of image, checksum for image, and count of
 169 //      page headers. Following that are 'count' page headers followed by
 170 //      the code and/or data segments to be loaded
 171 typedef struct _arc_img_hdr
 172 {
 173         u32                     size;           //      Size of binary image in bytes
 174         u32                     checksum;       //      Checksum for image
 175         u32                     count;          //      Count of swp pages in image
 176         ARC_SWP_PAGE_HDR        page[1];        //      Should be "count" pages - '1' to make compiler happy
 177 }ARC_IMG_HDR;
 178
 179
 180
 181 /*
 182 **      Native size for the Stratiphy interface is 32-bits. All reads and writes
 183 **      MUST be aligned on 32-bit boundaries. Trickery must be invoked to read word and/or
 184 **      byte data. Read routines are provided. Write routines are probably a bad idea, as the
 185 **      Arc has unrestrained, unseen access to the same memory, so a read-modify-write cycle
 186 **      could very well have unintended results.
 187 */
 188 MEI_ERROR meiCMV(u16 *, int);                         // first arg is CMV to ARC, second to indicate whether need reply
 189
 190 void meiLongwordWrite(u32 ul_address, u32 ul_data);
 191 void meiLongwordRead(u32 ul_address, u32 *pul_data);
 192
 193
 194 MEI_ERROR meiDMAWrite(u32 destaddr, u32 *databuff, u32 databuffsize);
 195 MEI_ERROR meiDebugWrite(u32 destaddr, u32 *databuff, u32 databuffsize);
 196
 197 MEI_ERROR meiDMARead(u32 srcaddr, u32 *databuff, u32 databuffsize);
 198 MEI_ERROR meiDebugRead(u32 srcaddr, u32 *databuff, u32 databuffsize);
 199
 200 void meiPollForDbgDone(void);
 201
 202 void meiMailboxInterruptsDisable(void);
 203 void meiMailboxInterruptsEnable(void);
 204
 205 MEI_ERROR meiMailboxWrite(u16 *msgsrcbuffer, u16 msgsize);
 206 MEI_ERROR meiMailboxRead(u16 *msgdestbuffer, u16 msgsize);
 207
 208 int meiGetPage( u32 Page, u32 data, u32 MaxSize, u32 *Buffer, u32 *Dest);
 209
 210 MEI_ERROR meiHaltArc(void);
 211 MEI_ERROR meiRunArc(void);
 212
 213 MEI_ERROR meiDownloadBootCode(void);
 214
 215 MEI_ERROR meiForceRebootAdslModem(void);
 216
 217 void makeCMV(u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data);
 218
 219 #endif
 220