target/linux/apm821xx/patches-4.19/010-dmaengine-dw-dmac-implement-dma-prot.patch

   1 From 7b0c03ecc42fb223baf015877fee9d517c2c8af1 Mon Sep 17 00:00:00 2001
   2 From: Christian Lamparter <chunkeey@gmail.com>
   3 Date: Sat, 17 Nov 2018 17:17:21 +0100
   4 Subject: dmaengine: dw-dmac: implement dma protection control setting
   5
   6 This patch adds a new device-tree property that allows to
   7 specify the dma protection control bits for the all of the
   8 DMA controller's channel uniformly.
   9
  10 Setting the "correct" bits can have a huge impact on the
  11 PPC460EX and APM82181 that use this DMA engine in combination
  12 with a DesignWare' SATA-II core (sata_dwc_460ex driver).
  13
  14 In the OpenWrt Forum, the user takimata reported that:
  15 |It seems your patch unleashed the full power of the SATA port.
  16 |Where I was previously hitting a really hard limit at around
  17 |82 MB/s for reading and 27 MB/s for writing, I am now getting this:
  18 |
  19 |root@OpenWrt:/mnt# time dd if=/dev/zero of=tempfile bs=1M count=1024
  20 |1024+0 records in
  21 |1024+0 records out
  22 |real    0m 13.65s
  23 |user    0m 0.01s
  24 |sys     0m 11.89s
  25 |
  26 |root@OpenWrt:/mnt# time dd if=tempfile of=/dev/null bs=1M count=1024
  27 |1024+0 records in
  28 |1024+0 records out
  29 |real    0m 8.41s
  30 |user    0m 0.01s
  31 |sys     0m 4.70s
  32 |
  33 |This means: 121 MB/s reading and 75 MB/s writing!
  34 |
  35 |The drive is a WD Green WD10EARX taken from an older MBL Single.
  36 |I repeated the test a few times with even larger files to rule out
  37 |any caching, I'm still seeing the same great performance. OpenWrt is
  38 |now completely on par with the original MBL firmware's performance.
  39
  40 Another user And.short reported:
  41 |I can report that your fix worked! Boots up fine with two
  42 |drives even with more partitions, and no more reboot on
  43 |concurrent disk access!
  44
  45 A closer look into the sata_dwc_460ex code revealed that
  46 the driver did initally set the correct protection control
  47 bits. However, this feature was lost when the sata_dwc_460ex
  48 driver was converted to the generic DMA driver framework.
  49
  50 BugLink: https://forum.openwrt.org/t/wd-mybook-live-duo-two-disks/16195/55
  51 BugLink: https://forum.openwrt.org/t/wd-mybook-live-duo-two-disks/16195/50
  52 Fixes: 8b3444852a2b ("sata_dwc_460ex: move to generic DMA driver")
  53 Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
  54 Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
  55 Signed-off-by: Vinod Koul <vkoul@kernel.org>
  56 ---
  57
  58 --- a/drivers/dma/dw/core.c
  59 +++ b/drivers/dma/dw/core.c
  60 @@ -160,12 +160,14 @@ static void dwc_initialize_chan_idma32(s
  61
  62  static void dwc_initialize_chan_dw(struct dw_dma_chan *dwc)
  63  {
  64 +       struct dw_dma *dw = to_dw_dma(dwc->chan.device);
  65         u32 cfghi = DWC_CFGH_FIFO_MODE;
  66         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
  67         bool hs_polarity = dwc->dws.hs_polarity;
  68
  69         cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id);
  70         cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id);
  71 +       cfghi |= DWC_CFGH_PROTCTL(dw->pdata->protctl);
  72
  73         /* Set polarity of handshake interface */
  74         cfglo |= hs_polarity ? DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0;
  75 --- a/drivers/dma/dw/platform.c
  76 +++ b/drivers/dma/dw/platform.c
  77 @@ -162,6 +162,12 @@ dw_dma_parse_dt(struct platform_device *
  78                         pdata->multi_block[tmp] = 1;
  79         }
  80
  81 +       if (!of_property_read_u32(np, "snps,dma-protection-control", &tmp)) {
  82 +               if (tmp > CHAN_PROTCTL_MASK)
  83 +                       return NULL;
  84 +               pdata->protctl = tmp;
  85 +       }
  86 +
  87         return pdata;
  88  }
  89  #else
  90 --- a/drivers/dma/dw/regs.h
  91 +++ b/drivers/dma/dw/regs.h
  92 @@ -200,6 +200,10 @@ enum dw_dma_msize {
  93  #define DWC_CFGH_FCMODE                (1 << 0)
  94  #define DWC_CFGH_FIFO_MODE     (1 << 1)
  95  #define DWC_CFGH_PROTCTL(x)    ((x) << 2)
  96 +#define DWC_CFGH_PROTCTL_DATA  (0 << 2)        /* data access - always set */
  97 +#define DWC_CFGH_PROTCTL_PRIV  (1 << 2)        /* privileged -> AHB HPROT[1] */
  98 +#define DWC_CFGH_PROTCTL_BUFFER        (2 << 2)        /* bufferable -> AHB HPROT[2] */
  99 +#define DWC_CFGH_PROTCTL_CACHE (4 << 2)        /* cacheable  -> AHB HPROT[3] */
 100  #define DWC_CFGH_DS_UPD_EN     (1 << 5)
 101  #define DWC_CFGH_SS_UPD_EN     (1 << 6)
 102  #define DWC_CFGH_SRC_PER(x)    ((x) << 7)
 103 --- a/include/linux/platform_data/dma-dw.h
 104 +++ b/include/linux/platform_data/dma-dw.h
 105 @@ -49,6 +49,7 @@ struct dw_dma_slave {
 106   * @data_width: Maximum data width supported by hardware per AHB master
 107   *             (in bytes, power of 2)
 108   * @multi_block: Multi block transfers supported by hardware per channel.
 109 + * @protctl: Protection control signals setting per channel.
 110   */
 111  struct dw_dma_platform_data {
 112         unsigned int    nr_channels;
 113 @@ -65,6 +66,11 @@ struct dw_dma_platform_data {
 114         unsigned char   nr_masters;
 115         unsigned char   data_width[DW_DMA_MAX_NR_MASTERS];
 116         unsigned char   multi_block[DW_DMA_MAX_NR_CHANNELS];
 117 +#define CHAN_PROTCTL_PRIVILEGED                BIT(0)
 118 +#define CHAN_PROTCTL_BUFFERABLE                BIT(1)
 119 +#define CHAN_PROTCTL_CACHEABLE         BIT(2)
 120 +#define CHAN_PROTCTL_MASK              GENMASK(2, 0)
 121 +       unsigned char   protctl;
 122  };
 123
 124  #endif /* _PLATFORM_DATA_DMA_DW_H */
 125 --- /dev/null
 126 +++ b/include/dt-bindings/dma/dw-dmac.h
 127 @@ -0,0 +1,14 @@
 128 +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
 129 +
 130 +#ifndef __DT_BINDINGS_DMA_DW_DMAC_H__
 131 +#define __DT_BINDINGS_DMA_DW_DMAC_H__
 132 +
 133 +/*
 134 + * Protection Control bits provide protection against illegal transactions.
 135 + * The protection bits[0:2] are one-to-one mapped to AHB HPROT[3:1] signals.
 136 + */
 137 +#define DW_DMAC_HPROT1_PRIVILEGED_MODE (1 << 0)        /* Privileged Mode */
 138 +#define DW_DMAC_HPROT2_BUFFERABLE      (1 << 1)        /* DMA is bufferable */
 139 +#define DW_DMAC_HPROT3_CACHEABLE       (1 << 2)        /* DMA is cacheable */
 140 +
 141 +#endif /* __DT_BINDINGS_DMA_DW_DMAC_H__ */