2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
24 #include <asm/mach-ath79/ath79.h>
25 #include <asm/mach-ath79/ar71xx_regs.h>
26 #include <asm/mach-ath79/irq.h>
31 unsigned char ath79_mac_base
[ETH_ALEN
] __initdata
;
33 static struct resource ath79_mdio0_resources
[] = {
36 .flags
= IORESOURCE_MEM
,
37 .start
= AR71XX_GE0_BASE
,
38 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
42 static struct ag71xx_mdio_platform_data ath79_mdio0_data
;
44 struct platform_device ath79_mdio0_device
= {
45 .name
= "ag71xx-mdio",
47 .resource
= ath79_mdio0_resources
,
48 .num_resources
= ARRAY_SIZE(ath79_mdio0_resources
),
50 .platform_data
= &ath79_mdio0_data
,
54 static struct resource ath79_mdio1_resources
[] = {
57 .flags
= IORESOURCE_MEM
,
58 .start
= AR71XX_GE1_BASE
,
59 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
63 static struct ag71xx_mdio_platform_data ath79_mdio1_data
;
65 struct platform_device ath79_mdio1_device
= {
66 .name
= "ag71xx-mdio",
68 .resource
= ath79_mdio1_resources
,
69 .num_resources
= ARRAY_SIZE(ath79_mdio1_resources
),
71 .platform_data
= &ath79_mdio1_data
,
75 static void ath79_set_pll(u32 cfg_reg
, u32 pll_reg
, u32 pll_val
, u32 shift
)
80 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
82 t
= __raw_readl(base
+ cfg_reg
);
85 __raw_writel(t
, base
+ cfg_reg
);
88 __raw_writel(pll_val
, base
+ pll_reg
);
91 __raw_writel(t
, base
+ cfg_reg
);
95 __raw_writel(t
, base
+ cfg_reg
);
98 printk(KERN_DEBUG
"ar71xx: pll_reg %#x: %#x\n",
99 (unsigned int)(base
+ pll_reg
), __raw_readl(base
+ pll_reg
));
104 static void __init
ath79_mii_ctrl_set_if(unsigned int reg
,
110 base
= ioremap(AR71XX_MII_BASE
, AR71XX_MII_SIZE
);
112 t
= __raw_readl(base
+ reg
);
113 t
&= ~(AR71XX_MII_CTRL_IF_MASK
);
114 t
|= (mii_if
& AR71XX_MII_CTRL_IF_MASK
);
115 __raw_writel(t
, base
+ reg
);
120 static void ath79_mii_ctrl_set_speed(unsigned int reg
, unsigned int speed
)
123 unsigned int mii_speed
;
128 mii_speed
= AR71XX_MII_CTRL_SPEED_10
;
131 mii_speed
= AR71XX_MII_CTRL_SPEED_100
;
134 mii_speed
= AR71XX_MII_CTRL_SPEED_1000
;
140 base
= ioremap(AR71XX_MII_BASE
, AR71XX_MII_SIZE
);
142 t
= __raw_readl(base
+ reg
);
143 t
&= ~(AR71XX_MII_CTRL_SPEED_MASK
<< AR71XX_MII_CTRL_SPEED_SHIFT
);
144 t
|= mii_speed
<< AR71XX_MII_CTRL_SPEED_SHIFT
;
145 __raw_writel(t
, base
+ reg
);
150 static unsigned long ar934x_get_mdio_ref_clock(void)
156 base
= ioremap(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
159 t
= __raw_readl(base
+ AR934X_PLL_SWITCH_CLOCK_CONTROL_REG
);
160 if (t
& AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL
) {
161 ret
= 100 * 1000 * 1000;
165 clk
= clk_get(NULL
, "ref");
167 ret
= clk_get_rate(clk
);
175 void __init
ath79_register_mdio(unsigned int id
, u32 phy_mask
)
177 struct platform_device
*mdio_dev
;
178 struct ag71xx_mdio_platform_data
*mdio_data
;
181 if (ath79_soc
== ATH79_SOC_AR9341
||
182 ath79_soc
== ATH79_SOC_AR9342
||
183 ath79_soc
== ATH79_SOC_AR9344
||
184 ath79_soc
== ATH79_SOC_QCA9558
)
190 printk(KERN_ERR
"ar71xx: invalid MDIO id %u\n", id
);
195 case ATH79_SOC_AR7241
:
196 case ATH79_SOC_AR9330
:
197 case ATH79_SOC_AR9331
:
198 mdio_dev
= &ath79_mdio1_device
;
199 mdio_data
= &ath79_mdio1_data
;
202 case ATH79_SOC_AR9341
:
203 case ATH79_SOC_AR9342
:
204 case ATH79_SOC_AR9344
:
205 case ATH79_SOC_QCA9558
:
207 mdio_dev
= &ath79_mdio0_device
;
208 mdio_data
= &ath79_mdio0_data
;
210 mdio_dev
= &ath79_mdio1_device
;
211 mdio_data
= &ath79_mdio1_data
;
215 case ATH79_SOC_AR7242
:
216 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
,
217 AR7242_PLL_REG_ETH0_INT_CLOCK
, 0x62000000,
218 AR71XX_ETH0_PLL_SHIFT
);
221 mdio_dev
= &ath79_mdio0_device
;
222 mdio_data
= &ath79_mdio0_data
;
226 mdio_data
->phy_mask
= phy_mask
;
229 case ATH79_SOC_AR7240
:
230 mdio_data
->is_ar7240
= 1;
232 case ATH79_SOC_AR7241
:
233 mdio_data
->builtin_switch
= 1;
236 case ATH79_SOC_AR9330
:
237 mdio_data
->is_ar9330
= 1;
239 case ATH79_SOC_AR9331
:
240 mdio_data
->builtin_switch
= 1;
243 case ATH79_SOC_AR9341
:
244 case ATH79_SOC_AR9342
:
245 case ATH79_SOC_AR9344
:
247 mdio_data
->builtin_switch
= 1;
248 mdio_data
->ref_clock
= ar934x_get_mdio_ref_clock();
249 mdio_data
->mdio_clock
= 6250000;
251 mdio_data
->is_ar934x
= 1;
253 case ATH79_SOC_QCA9558
:
255 mdio_data
->builtin_switch
= 1;
256 mdio_data
->is_ar934x
= 1;
263 platform_device_register(mdio_dev
);
266 struct ath79_eth_pll_data ath79_eth0_pll_data
;
267 struct ath79_eth_pll_data ath79_eth1_pll_data
;
269 static u32
ath79_get_eth_pll(unsigned int mac
, int speed
)
271 struct ath79_eth_pll_data
*pll_data
;
276 pll_data
= &ath79_eth0_pll_data
;
279 pll_data
= &ath79_eth1_pll_data
;
287 pll_val
= pll_data
->pll_10
;
290 pll_val
= pll_data
->pll_100
;
293 pll_val
= pll_data
->pll_1000
;
302 static void ath79_set_speed_ge0(int speed
)
304 u32 val
= ath79_get_eth_pll(0, speed
);
306 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH0_INT_CLOCK
,
307 val
, AR71XX_ETH0_PLL_SHIFT
);
308 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL
, speed
);
311 static void ath79_set_speed_ge1(int speed
)
313 u32 val
= ath79_get_eth_pll(1, speed
);
315 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH1_INT_CLOCK
,
316 val
, AR71XX_ETH1_PLL_SHIFT
);
317 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL
, speed
);
320 static void ar7242_set_speed_ge0(int speed
)
322 u32 val
= ath79_get_eth_pll(0, speed
);
325 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
326 __raw_writel(val
, base
+ AR7242_PLL_REG_ETH0_INT_CLOCK
);
330 static void ar91xx_set_speed_ge0(int speed
)
332 u32 val
= ath79_get_eth_pll(0, speed
);
334 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG
, AR913X_PLL_REG_ETH0_INT_CLOCK
,
335 val
, AR913X_ETH0_PLL_SHIFT
);
336 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL
, speed
);
339 static void ar91xx_set_speed_ge1(int speed
)
341 u32 val
= ath79_get_eth_pll(1, speed
);
343 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG
, AR913X_PLL_REG_ETH1_INT_CLOCK
,
344 val
, AR913X_ETH1_PLL_SHIFT
);
345 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL
, speed
);
348 static void ar934x_set_speed_ge0(int speed
)
351 u32 val
= ath79_get_eth_pll(0, speed
);
353 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
354 __raw_writel(val
, base
+ AR934X_PLL_ETH_XMII_CONTROL_REG
);
358 static void qca955x_set_speed_xmii(int speed
)
361 u32 val
= ath79_get_eth_pll(0, speed
);
363 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
364 __raw_writel(val
, base
+ QCA955X_PLL_ETH_XMII_CONTROL_REG
);
368 static void qca955x_set_speed_sgmii(int speed
)
371 u32 val
= ath79_get_eth_pll(1, speed
);
373 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
374 __raw_writel(val
, base
+ QCA955X_PLL_ETH_SGMII_CONTROL_REG
);
378 static void ath79_set_speed_dummy(int speed
)
382 static void ath79_ddr_no_flush(void)
386 static void ath79_ddr_flush_ge0(void)
388 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0
);
391 static void ath79_ddr_flush_ge1(void)
393 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1
);
396 static void ar724x_ddr_flush_ge0(void)
398 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0
);
401 static void ar724x_ddr_flush_ge1(void)
403 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1
);
406 static void ar91xx_ddr_flush_ge0(void)
408 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0
);
411 static void ar91xx_ddr_flush_ge1(void)
413 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1
);
416 static void ar933x_ddr_flush_ge0(void)
418 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0
);
421 static void ar933x_ddr_flush_ge1(void)
423 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1
);
426 static struct resource ath79_eth0_resources
[] = {
429 .flags
= IORESOURCE_MEM
,
430 .start
= AR71XX_GE0_BASE
,
431 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
434 .flags
= IORESOURCE_IRQ
,
435 .start
= ATH79_CPU_IRQ_GE0
,
436 .end
= ATH79_CPU_IRQ_GE0
,
440 struct ag71xx_platform_data ath79_eth0_data
= {
441 .reset_bit
= AR71XX_RESET_GE0_MAC
,
444 struct platform_device ath79_eth0_device
= {
447 .resource
= ath79_eth0_resources
,
448 .num_resources
= ARRAY_SIZE(ath79_eth0_resources
),
450 .platform_data
= &ath79_eth0_data
,
454 static struct resource ath79_eth1_resources
[] = {
457 .flags
= IORESOURCE_MEM
,
458 .start
= AR71XX_GE1_BASE
,
459 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
462 .flags
= IORESOURCE_IRQ
,
463 .start
= ATH79_CPU_IRQ_GE1
,
464 .end
= ATH79_CPU_IRQ_GE1
,
468 struct ag71xx_platform_data ath79_eth1_data
= {
469 .reset_bit
= AR71XX_RESET_GE1_MAC
,
472 struct platform_device ath79_eth1_device
= {
475 .resource
= ath79_eth1_resources
,
476 .num_resources
= ARRAY_SIZE(ath79_eth1_resources
),
478 .platform_data
= &ath79_eth1_data
,
482 struct ag71xx_switch_platform_data ath79_switch_data
;
484 #define AR71XX_PLL_VAL_1000 0x00110000
485 #define AR71XX_PLL_VAL_100 0x00001099
486 #define AR71XX_PLL_VAL_10 0x00991099
488 #define AR724X_PLL_VAL_1000 0x00110000
489 #define AR724X_PLL_VAL_100 0x00001099
490 #define AR724X_PLL_VAL_10 0x00991099
492 #define AR7242_PLL_VAL_1000 0x16000000
493 #define AR7242_PLL_VAL_100 0x00000101
494 #define AR7242_PLL_VAL_10 0x00001616
496 #define AR913X_PLL_VAL_1000 0x1a000000
497 #define AR913X_PLL_VAL_100 0x13000a44
498 #define AR913X_PLL_VAL_10 0x00441099
500 #define AR933X_PLL_VAL_1000 0x00110000
501 #define AR933X_PLL_VAL_100 0x00001099
502 #define AR933X_PLL_VAL_10 0x00991099
504 #define AR934X_PLL_VAL_1000 0x16000000
505 #define AR934X_PLL_VAL_100 0x00000101
506 #define AR934X_PLL_VAL_10 0x00001616
508 static void __init
ath79_init_eth_pll_data(unsigned int id
)
510 struct ath79_eth_pll_data
*pll_data
;
511 u32 pll_10
, pll_100
, pll_1000
;
515 pll_data
= &ath79_eth0_pll_data
;
518 pll_data
= &ath79_eth1_pll_data
;
525 case ATH79_SOC_AR7130
:
526 case ATH79_SOC_AR7141
:
527 case ATH79_SOC_AR7161
:
528 pll_10
= AR71XX_PLL_VAL_10
;
529 pll_100
= AR71XX_PLL_VAL_100
;
530 pll_1000
= AR71XX_PLL_VAL_1000
;
533 case ATH79_SOC_AR7240
:
534 case ATH79_SOC_AR7241
:
535 pll_10
= AR724X_PLL_VAL_10
;
536 pll_100
= AR724X_PLL_VAL_100
;
537 pll_1000
= AR724X_PLL_VAL_1000
;
540 case ATH79_SOC_AR7242
:
541 pll_10
= AR7242_PLL_VAL_10
;
542 pll_100
= AR7242_PLL_VAL_100
;
543 pll_1000
= AR7242_PLL_VAL_1000
;
546 case ATH79_SOC_AR9130
:
547 case ATH79_SOC_AR9132
:
548 pll_10
= AR913X_PLL_VAL_10
;
549 pll_100
= AR913X_PLL_VAL_100
;
550 pll_1000
= AR913X_PLL_VAL_1000
;
553 case ATH79_SOC_AR9330
:
554 case ATH79_SOC_AR9331
:
555 pll_10
= AR933X_PLL_VAL_10
;
556 pll_100
= AR933X_PLL_VAL_100
;
557 pll_1000
= AR933X_PLL_VAL_1000
;
560 case ATH79_SOC_AR9341
:
561 case ATH79_SOC_AR9342
:
562 case ATH79_SOC_AR9344
:
563 case ATH79_SOC_QCA9558
:
564 pll_10
= AR934X_PLL_VAL_10
;
565 pll_100
= AR934X_PLL_VAL_100
;
566 pll_1000
= AR934X_PLL_VAL_1000
;
573 if (!pll_data
->pll_10
)
574 pll_data
->pll_10
= pll_10
;
576 if (!pll_data
->pll_100
)
577 pll_data
->pll_100
= pll_100
;
579 if (!pll_data
->pll_1000
)
580 pll_data
->pll_1000
= pll_1000
;
583 static int __init
ath79_setup_phy_if_mode(unsigned int id
,
584 struct ag71xx_platform_data
*pdata
)
591 case ATH79_SOC_AR7130
:
592 case ATH79_SOC_AR7141
:
593 case ATH79_SOC_AR7161
:
594 case ATH79_SOC_AR9130
:
595 case ATH79_SOC_AR9132
:
596 switch (pdata
->phy_if_mode
) {
597 case PHY_INTERFACE_MODE_MII
:
598 mii_if
= AR71XX_MII0_CTRL_IF_MII
;
600 case PHY_INTERFACE_MODE_GMII
:
601 mii_if
= AR71XX_MII0_CTRL_IF_GMII
;
603 case PHY_INTERFACE_MODE_RGMII
:
604 mii_if
= AR71XX_MII0_CTRL_IF_RGMII
;
606 case PHY_INTERFACE_MODE_RMII
:
607 mii_if
= AR71XX_MII0_CTRL_IF_RMII
;
612 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL
, mii_if
);
615 case ATH79_SOC_AR7240
:
616 case ATH79_SOC_AR7241
:
617 case ATH79_SOC_AR9330
:
618 case ATH79_SOC_AR9331
:
619 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_MII
;
622 case ATH79_SOC_AR7242
:
625 case ATH79_SOC_AR9341
:
626 case ATH79_SOC_AR9342
:
627 case ATH79_SOC_AR9344
:
628 switch (pdata
->phy_if_mode
) {
629 case PHY_INTERFACE_MODE_MII
:
630 case PHY_INTERFACE_MODE_GMII
:
631 case PHY_INTERFACE_MODE_RGMII
:
632 case PHY_INTERFACE_MODE_RMII
:
639 case ATH79_SOC_QCA9558
:
640 switch (pdata
->phy_if_mode
) {
641 case PHY_INTERFACE_MODE_MII
:
642 case PHY_INTERFACE_MODE_RGMII
:
643 case PHY_INTERFACE_MODE_SGMII
:
656 case ATH79_SOC_AR7130
:
657 case ATH79_SOC_AR7141
:
658 case ATH79_SOC_AR7161
:
659 case ATH79_SOC_AR9130
:
660 case ATH79_SOC_AR9132
:
661 switch (pdata
->phy_if_mode
) {
662 case PHY_INTERFACE_MODE_RMII
:
663 mii_if
= AR71XX_MII1_CTRL_IF_RMII
;
665 case PHY_INTERFACE_MODE_RGMII
:
666 mii_if
= AR71XX_MII1_CTRL_IF_RGMII
;
671 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL
, mii_if
);
674 case ATH79_SOC_AR7240
:
675 case ATH79_SOC_AR7241
:
676 case ATH79_SOC_AR9330
:
677 case ATH79_SOC_AR9331
:
678 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_GMII
;
681 case ATH79_SOC_AR7242
:
684 case ATH79_SOC_AR9341
:
685 case ATH79_SOC_AR9342
:
686 case ATH79_SOC_AR9344
:
687 switch (pdata
->phy_if_mode
) {
688 case PHY_INTERFACE_MODE_MII
:
689 case PHY_INTERFACE_MODE_GMII
:
696 case ATH79_SOC_QCA9558
:
697 switch (pdata
->phy_if_mode
) {
698 case PHY_INTERFACE_MODE_MII
:
699 case PHY_INTERFACE_MODE_RGMII
:
700 case PHY_INTERFACE_MODE_SGMII
:
716 void __init
ath79_setup_ar933x_phy4_switch(bool mac
, bool mdio
)
721 base
= ioremap(AR933X_GMAC_BASE
, AR933X_GMAC_SIZE
);
723 t
= __raw_readl(base
+ AR933X_GMAC_REG_ETH_CFG
);
724 t
&= ~(AR933X_ETH_CFG_SW_PHY_SWAP
| AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
);
726 t
|= AR933X_ETH_CFG_SW_PHY_SWAP
;
728 t
|= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
;
729 __raw_writel(t
, base
+ AR933X_GMAC_REG_ETH_CFG
);
734 void __init
ath79_setup_ar934x_eth_cfg(u32 mask
)
739 base
= ioremap(AR934X_GMAC_BASE
, AR934X_GMAC_SIZE
);
741 t
= __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
743 t
&= ~(AR934X_ETH_CFG_RGMII_GMAC0
|
744 AR934X_ETH_CFG_MII_GMAC0
|
745 AR934X_ETH_CFG_GMII_GMAC0
|
746 AR934X_ETH_CFG_SW_ONLY_MODE
|
747 AR934X_ETH_CFG_SW_PHY_SWAP
);
751 __raw_writel(t
, base
+ AR934X_GMAC_REG_ETH_CFG
);
753 __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
758 static int ath79_eth_instance __initdata
;
759 void __init
ath79_register_eth(unsigned int id
)
761 struct platform_device
*pdev
;
762 struct ag71xx_platform_data
*pdata
;
766 printk(KERN_ERR
"ar71xx: invalid ethernet id %d\n", id
);
770 ath79_init_eth_pll_data(id
);
773 pdev
= &ath79_eth0_device
;
775 pdev
= &ath79_eth1_device
;
777 pdata
= pdev
->dev
.platform_data
;
779 err
= ath79_setup_phy_if_mode(id
, pdata
);
782 "ar71xx: invalid PHY interface mode for GE%u\n", id
);
787 case ATH79_SOC_AR7130
:
789 pdata
->ddr_flush
= ath79_ddr_flush_ge0
;
790 pdata
->set_speed
= ath79_set_speed_ge0
;
792 pdata
->ddr_flush
= ath79_ddr_flush_ge1
;
793 pdata
->set_speed
= ath79_set_speed_ge1
;
797 case ATH79_SOC_AR7141
:
798 case ATH79_SOC_AR7161
:
800 pdata
->ddr_flush
= ath79_ddr_flush_ge0
;
801 pdata
->set_speed
= ath79_set_speed_ge0
;
803 pdata
->ddr_flush
= ath79_ddr_flush_ge1
;
804 pdata
->set_speed
= ath79_set_speed_ge1
;
809 case ATH79_SOC_AR7242
:
811 pdata
->reset_bit
|= AR724X_RESET_GE0_MDIO
|
812 AR71XX_RESET_GE0_PHY
;
813 pdata
->ddr_flush
= ar724x_ddr_flush_ge0
;
814 pdata
->set_speed
= ar7242_set_speed_ge0
;
816 pdata
->reset_bit
|= AR724X_RESET_GE1_MDIO
|
817 AR71XX_RESET_GE1_PHY
;
818 pdata
->ddr_flush
= ar724x_ddr_flush_ge1
;
819 pdata
->set_speed
= ath79_set_speed_dummy
;
822 pdata
->is_ar724x
= 1;
824 if (!pdata
->fifo_cfg1
)
825 pdata
->fifo_cfg1
= 0x0010ffff;
826 if (!pdata
->fifo_cfg2
)
827 pdata
->fifo_cfg2
= 0x015500aa;
828 if (!pdata
->fifo_cfg3
)
829 pdata
->fifo_cfg3
= 0x01f00140;
832 case ATH79_SOC_AR7241
:
834 pdata
->reset_bit
|= AR724X_RESET_GE0_MDIO
;
836 pdata
->reset_bit
|= AR724X_RESET_GE1_MDIO
;
838 case ATH79_SOC_AR7240
:
840 pdata
->reset_bit
|= AR71XX_RESET_GE0_PHY
;
841 pdata
->ddr_flush
= ar724x_ddr_flush_ge0
;
842 pdata
->set_speed
= ath79_set_speed_dummy
;
844 pdata
->phy_mask
= BIT(4);
846 pdata
->reset_bit
|= AR71XX_RESET_GE1_PHY
;
847 pdata
->ddr_flush
= ar724x_ddr_flush_ge1
;
848 pdata
->set_speed
= ath79_set_speed_dummy
;
850 pdata
->speed
= SPEED_1000
;
851 pdata
->duplex
= DUPLEX_FULL
;
852 pdata
->switch_data
= &ath79_switch_data
;
854 ath79_switch_data
.phy_poll_mask
|= BIT(4);
857 pdata
->is_ar724x
= 1;
858 if (ath79_soc
== ATH79_SOC_AR7240
)
859 pdata
->is_ar7240
= 1;
861 if (!pdata
->fifo_cfg1
)
862 pdata
->fifo_cfg1
= 0x0010ffff;
863 if (!pdata
->fifo_cfg2
)
864 pdata
->fifo_cfg2
= 0x015500aa;
865 if (!pdata
->fifo_cfg3
)
866 pdata
->fifo_cfg3
= 0x01f00140;
869 case ATH79_SOC_AR9130
:
871 pdata
->ddr_flush
= ar91xx_ddr_flush_ge0
;
872 pdata
->set_speed
= ar91xx_set_speed_ge0
;
874 pdata
->ddr_flush
= ar91xx_ddr_flush_ge1
;
875 pdata
->set_speed
= ar91xx_set_speed_ge1
;
877 pdata
->is_ar91xx
= 1;
880 case ATH79_SOC_AR9132
:
882 pdata
->ddr_flush
= ar91xx_ddr_flush_ge0
;
883 pdata
->set_speed
= ar91xx_set_speed_ge0
;
885 pdata
->ddr_flush
= ar91xx_ddr_flush_ge1
;
886 pdata
->set_speed
= ar91xx_set_speed_ge1
;
888 pdata
->is_ar91xx
= 1;
892 case ATH79_SOC_AR9330
:
893 case ATH79_SOC_AR9331
:
895 pdata
->reset_bit
= AR933X_RESET_GE0_MAC
|
896 AR933X_RESET_GE0_MDIO
;
897 pdata
->ddr_flush
= ar933x_ddr_flush_ge0
;
898 pdata
->set_speed
= ath79_set_speed_dummy
;
900 pdata
->phy_mask
= BIT(4);
902 pdata
->reset_bit
= AR933X_RESET_GE1_MAC
|
903 AR933X_RESET_GE1_MDIO
;
904 pdata
->ddr_flush
= ar933x_ddr_flush_ge1
;
905 pdata
->set_speed
= ath79_set_speed_dummy
;
907 pdata
->speed
= SPEED_1000
;
908 pdata
->duplex
= DUPLEX_FULL
;
909 pdata
->switch_data
= &ath79_switch_data
;
911 ath79_switch_data
.phy_poll_mask
|= BIT(4);
915 pdata
->is_ar724x
= 1;
917 if (!pdata
->fifo_cfg1
)
918 pdata
->fifo_cfg1
= 0x0010ffff;
919 if (!pdata
->fifo_cfg2
)
920 pdata
->fifo_cfg2
= 0x015500aa;
921 if (!pdata
->fifo_cfg3
)
922 pdata
->fifo_cfg3
= 0x01f00140;
925 case ATH79_SOC_AR9341
:
926 case ATH79_SOC_AR9342
:
927 case ATH79_SOC_AR9344
:
929 pdata
->reset_bit
= AR934X_RESET_GE0_MAC
|
930 AR934X_RESET_GE0_MDIO
;
931 pdata
->set_speed
= ar934x_set_speed_ge0
;
933 pdata
->reset_bit
= AR934X_RESET_GE1_MAC
|
934 AR934X_RESET_GE1_MDIO
;
935 pdata
->set_speed
= ath79_set_speed_dummy
;
937 pdata
->switch_data
= &ath79_switch_data
;
939 /* reset the built-in switch */
940 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH
);
941 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH
);
944 pdata
->ddr_flush
= ath79_ddr_no_flush
;
946 pdata
->is_ar724x
= 1;
948 if (!pdata
->fifo_cfg1
)
949 pdata
->fifo_cfg1
= 0x0010ffff;
950 if (!pdata
->fifo_cfg2
)
951 pdata
->fifo_cfg2
= 0x015500aa;
952 if (!pdata
->fifo_cfg3
)
953 pdata
->fifo_cfg3
= 0x01f00140;
956 case ATH79_SOC_QCA9558
:
958 pdata
->reset_bit
= QCA955X_RESET_GE0_MAC
|
959 QCA955X_RESET_GE0_MDIO
;
960 pdata
->set_speed
= qca955x_set_speed_xmii
;
962 pdata
->reset_bit
= QCA955X_RESET_GE1_MAC
|
963 QCA955X_RESET_GE1_MDIO
;
964 pdata
->set_speed
= qca955x_set_speed_sgmii
;
967 pdata
->ddr_flush
= ath79_ddr_no_flush
;
969 pdata
->is_ar724x
= 1;
971 if (!pdata
->fifo_cfg1
)
972 pdata
->fifo_cfg1
= 0x0010ffff;
973 if (!pdata
->fifo_cfg2
)
974 pdata
->fifo_cfg2
= 0x015500aa;
975 if (!pdata
->fifo_cfg3
)
976 pdata
->fifo_cfg3
= 0x01f00140;
983 switch (pdata
->phy_if_mode
) {
984 case PHY_INTERFACE_MODE_GMII
:
985 case PHY_INTERFACE_MODE_RGMII
:
986 case PHY_INTERFACE_MODE_SGMII
:
987 if (!pdata
->has_gbit
) {
988 printk(KERN_ERR
"ar71xx: no gbit available on eth%d\n",
997 if (!is_valid_ether_addr(pdata
->mac_addr
)) {
998 random_ether_addr(pdata
->mac_addr
);
1000 "ar71xx: using random MAC address for eth%d\n",
1001 ath79_eth_instance
);
1004 if (pdata
->mii_bus_dev
== NULL
) {
1005 switch (ath79_soc
) {
1006 case ATH79_SOC_AR9341
:
1007 case ATH79_SOC_AR9342
:
1008 case ATH79_SOC_AR9344
:
1010 pdata
->mii_bus_dev
= &ath79_mdio0_device
.dev
;
1012 pdata
->mii_bus_dev
= &ath79_mdio1_device
.dev
;
1015 case ATH79_SOC_AR7241
:
1016 case ATH79_SOC_AR9330
:
1017 case ATH79_SOC_AR9331
:
1018 pdata
->mii_bus_dev
= &ath79_mdio1_device
.dev
;
1021 case ATH79_SOC_QCA9558
:
1022 /* don't assign any MDIO device by default */
1026 pdata
->mii_bus_dev
= &ath79_mdio0_device
.dev
;
1031 /* Reset the device */
1032 ath79_device_reset_set(pdata
->reset_bit
);
1035 ath79_device_reset_clear(pdata
->reset_bit
);
1038 platform_device_register(pdev
);
1039 ath79_eth_instance
++;
1042 void __init
ath79_set_mac_base(unsigned char *mac
)
1044 memcpy(ath79_mac_base
, mac
, ETH_ALEN
);
1047 void __init
ath79_parse_mac_addr(char *mac_str
)
1052 t
= sscanf(mac_str
, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1053 &tmp
[0], &tmp
[1], &tmp
[2], &tmp
[3], &tmp
[4], &tmp
[5]);
1056 t
= sscanf(mac_str
, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1057 &tmp
[0], &tmp
[1], &tmp
[2], &tmp
[3], &tmp
[4], &tmp
[5]);
1060 ath79_set_mac_base(tmp
);
1062 printk(KERN_DEBUG
"ar71xx: failed to parse mac address "
1063 "\"%s\"\n", mac_str
);
1066 static int __init
ath79_ethaddr_setup(char *str
)
1068 ath79_parse_mac_addr(str
);
1071 __setup("ethaddr=", ath79_ethaddr_setup
);
1073 static int __init
ath79_kmac_setup(char *str
)
1075 ath79_parse_mac_addr(str
);
1078 __setup("kmac=", ath79_kmac_setup
);
1080 void __init
ath79_init_mac(unsigned char *dst
, const unsigned char *src
,
1088 if (!src
|| !is_valid_ether_addr(src
)) {
1089 memset(dst
, '\0', ETH_ALEN
);
1093 t
= (((u32
) src
[3]) << 16) + (((u32
) src
[4]) << 8) + ((u32
) src
[5]);
1099 dst
[3] = (t
>> 16) & 0xff;
1100 dst
[4] = (t
>> 8) & 0xff;
1104 void __init
ath79_init_local_mac(unsigned char *dst
, const unsigned char *src
)
1111 if (!src
|| !is_valid_ether_addr(src
)) {
1112 memset(dst
, '\0', ETH_ALEN
);
1116 for (i
= 0; i
< ETH_ALEN
; i
++)