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ar71xx: rbspi: mark rb911L user led as active low
[openwrt/staging/wigyori.git] / target / linux / ar71xx / files / arch / mips / ath79 / mach-rbspi.c
1 /*
2 * MikroTik SPI-NOR RouterBOARDs support
3 *
4 * - MikroTik RouterBOARD mAP 2nD
5 * - MikroTik RouterBOARD mAP L-2nD
6 * - MikroTik RouterBOARD 911-2Hn (911 Lite2)
7 * - MikroTik RouterBOARD 911-5Hn (911 Lite5)
8 * - MikroTik RouterBOARD 931-2nD (hAP mini)
9 * - MikroTik RouterBOARD 941L-2nD
10 * - MikroTik RouterBOARD 951Ui-2nD
11 * - MikroTik RouterBOARD 952Ui-5ac2nD
12 * - MikroTik RouterBOARD 962UiGS-5HacT2HnT
13 * - MikroTik RouterBOARD 750UP r2
14 * - MikroTik RouterBOARD 750P-PBr2
15 * - MikroTik RouterBOARD 750 r2
16 * - MikroTik RouterBOARD LHG 5nD
17 * - MikroTik RouterBOARD wAP2nD
18 * - MikroTik RouterBOARD wAP G-5HacT2HnDwAP (wAP AC)
19 * - MikroTik RouterBOARD wAP R-2nD
20 *
21 * Preliminary support for the following hardware
22 * - MikroTik RouterBOARD cAP2nD
23 * Furthermore, the cAP lite (cAPL2nD) appears to feature the exact same
24 * hardware as the mAP L-2nD. It is unknown if they share the same board
25 * identifier.
26 *
27 * Copyright (C) 2017-2018 Thibaut VARENE <varenet@parisc-linux.org>
28 * Copyright (C) 2016 David Hutchison <dhutchison@bluemesh.net>
29 * Copyright (C) 2017 Ryan Mounce <ryan@mounce.com.au>
30 *
31 * This program is free software; you can redistribute it and/or modify it
32 * under the terms of the GNU General Public License version 2 as published
33 * by the Free Software Foundation.
34 */
35
36 #include <linux/pci.h>
37 #include <linux/platform_device.h>
38 #include <linux/phy.h>
39 #include <linux/routerboot.h>
40 #include <linux/gpio.h>
41
42 #include <linux/spi/spi.h>
43 #include <linux/spi/74x164.h>
44
45 #include <linux/mtd/mtd.h>
46 #include <linux/mtd/partitions.h>
47
48 #include <linux/ar8216_platform.h>
49 #include <linux/platform_data/phy-at803x.h>
50 #include <linux/platform_data/mdio-gpio.h>
51
52 #include <asm/prom.h>
53 #include <asm/mach-ath79/ar71xx_regs.h>
54 #include <asm/mach-ath79/ath79.h>
55
56 #include "common.h"
57 #include "dev-eth.h"
58 #include "dev-spi.h"
59 #include "dev-gpio-buttons.h"
60 #include "dev-leds-gpio.h"
61 #include "dev-m25p80.h"
62 #include "dev-usb.h"
63 #include "dev-wmac.h"
64 #include "machtypes.h"
65 #include "pci.h"
66 #include "routerboot.h"
67
68 #define RBSPI_KEYS_POLL_INTERVAL 20 /* msecs */
69 #define RBSPI_KEYS_DEBOUNCE_INTERVAL (3 * RBSPI_KEYS_POLL_INTERVAL)
70
71 #define RBSPI_HAS_USB BIT(0)
72 #define RBSPI_HAS_WLAN0 BIT(1)
73 #define RBSPI_HAS_WLAN1 BIT(2)
74 #define RBSPI_HAS_WAN4 BIT(3) /* has WAN port on PHY4 */
75 #define RBSPI_HAS_SSR BIT(4) /* has an SSR on SPI bus 0 */
76 #define RBSPI_HAS_POE BIT(5)
77 #define RBSPI_HAS_MDIO1 BIT(6)
78 #define RBSPI_HAS_PCI BIT(7)
79
80 #define RB_ROUTERBOOT_OFFSET 0x0000
81 #define RB_BIOS_SIZE 0x1000
82 #define RB_SOFT_CFG_SIZE 0x1000
83
84 /* Flash partitions indexes */
85 enum {
86 RBSPI_PART_RBOOT,
87 RBSPI_PART_HCONF,
88 RBSPI_PART_BIOS,
89 RBSPI_PART_RBOOT2,
90 RBSPI_PART_SCONF,
91 RBSPI_PART_FIRMW,
92 RBSPI_PARTS
93 };
94
95 static struct mtd_partition rbspi_spi_partitions[RBSPI_PARTS];
96
97 /*
98 * Setup the SPI flash partition table based on initial parsing.
99 * The kernel can be at any aligned position and have any size.
100 */
101 static void __init rbspi_init_partitions(const struct rb_info *info)
102 {
103 struct mtd_partition *parts = rbspi_spi_partitions;
104 memset(parts, 0x0, sizeof(*parts));
105
106 parts[RBSPI_PART_RBOOT].name = "routerboot";
107 parts[RBSPI_PART_RBOOT].offset = RB_ROUTERBOOT_OFFSET;
108 parts[RBSPI_PART_RBOOT].size = info->hard_cfg_offs;
109 parts[RBSPI_PART_RBOOT].mask_flags = MTD_WRITEABLE;
110
111 parts[RBSPI_PART_HCONF].name = "hard_config";
112 parts[RBSPI_PART_HCONF].offset = info->hard_cfg_offs;
113 parts[RBSPI_PART_HCONF].size = info->hard_cfg_size;
114 parts[RBSPI_PART_HCONF].mask_flags = MTD_WRITEABLE;
115
116 parts[RBSPI_PART_BIOS].name = "bios";
117 parts[RBSPI_PART_BIOS].offset = info->hard_cfg_offs
118 + info->hard_cfg_size;
119 parts[RBSPI_PART_BIOS].size = RB_BIOS_SIZE;
120 parts[RBSPI_PART_BIOS].mask_flags = MTD_WRITEABLE;
121
122 parts[RBSPI_PART_RBOOT2].name = "routerboot2";
123 parts[RBSPI_PART_RBOOT2].offset = parts[RBSPI_PART_BIOS].offset
124 + RB_BIOS_SIZE;
125 parts[RBSPI_PART_RBOOT2].size = info->soft_cfg_offs
126 - parts[RBSPI_PART_RBOOT2].offset;
127 parts[RBSPI_PART_RBOOT2].mask_flags = MTD_WRITEABLE;
128
129 parts[RBSPI_PART_SCONF].name = "soft_config";
130 parts[RBSPI_PART_SCONF].offset = info->soft_cfg_offs;
131 parts[RBSPI_PART_SCONF].size = RB_SOFT_CFG_SIZE;
132
133 parts[RBSPI_PART_FIRMW].name = "firmware";
134 parts[RBSPI_PART_FIRMW].offset = parts[RBSPI_PART_SCONF].offset
135 + parts[RBSPI_PART_SCONF].size;
136 parts[RBSPI_PART_FIRMW].size = MTDPART_SIZ_FULL;
137 }
138
139 static struct flash_platform_data rbspi_spi_flash_data = {
140 .parts = rbspi_spi_partitions,
141 .nr_parts = ARRAY_SIZE(rbspi_spi_partitions),
142 };
143
144 /*
145 * Several boards only have a single reset button, use a common
146 * structure for that.
147 */
148 static struct gpio_keys_button rbspi_gpio_keys_reset[] __initdata = {
149 {
150 .desc = "Reset button",
151 .type = EV_KEY,
152 .code = KEY_RESTART,
153 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
154 .gpio = -ENOENT, /* filled dynamically */
155 .active_low = 1,
156 },
157 };
158
159 /* RB mAP L-2nD gpios */
160 #define RBMAPL_GPIO_LED_POWER 17
161 #define RBMAPL_GPIO_LED_USER 14
162 #define RBMAPL_GPIO_LED_ETH 4
163 #define RBMAPL_GPIO_LED_WLAN 11
164 #define RBMAPL_GPIO_BTN_RESET 16
165
166 static struct gpio_led rbmapl_leds[] __initdata = {
167 {
168 .name = "rb:green:power",
169 .gpio = RBMAPL_GPIO_LED_POWER,
170 .active_low = 0,
171 .default_state = LEDS_GPIO_DEFSTATE_ON,
172 }, {
173 .name = "rb:green:user",
174 .gpio = RBMAPL_GPIO_LED_USER,
175 .active_low = 0,
176 }, {
177 .name = "rb:green:eth",
178 .gpio = RBMAPL_GPIO_LED_ETH,
179 .active_low = 0,
180 }, {
181 .name = "rb:green:wlan",
182 .gpio = RBMAPL_GPIO_LED_WLAN,
183 .active_low = 0,
184 },
185 };
186
187 /* RB 941L-2nD gpios */
188 #define RBHAPL_GPIO_LED_USER 14
189 #define RBHAPL_GPIO_BTN_RESET 16
190
191 static struct gpio_led rbhapl_leds[] __initdata = {
192 {
193 .name = "rb:green:user",
194 .gpio = RBHAPL_GPIO_LED_USER,
195 .active_low = 1,
196 },
197 };
198
199 /* common RB SSRs */
200 #define RBSPI_SSR_GPIO_BASE 40
201 #define RBSPI_SSR_GPIO(bit) (RBSPI_SSR_GPIO_BASE + (bit))
202
203 /* RB 951Ui-2nD gpios */
204 #define RB952_SSR_BIT_LED_LAN1 0
205 #define RB952_SSR_BIT_LED_LAN2 1
206 #define RB952_SSR_BIT_LED_LAN3 2
207 #define RB952_SSR_BIT_LED_LAN4 3
208 #define RB952_SSR_BIT_LED_LAN5 4
209 #define RB952_SSR_BIT_USB_POWER 5
210 #define RB952_SSR_BIT_LED_WLAN 6
211 #define RB952_GPIO_SSR_CS 11
212 #define RB952_GPIO_LED_USER 4
213 #define RB952_GPIO_POE_POWER 14
214 #define RB952_GPIO_POE_STATUS 12
215 #define RB952_GPIO_BTN_RESET 16
216 #define RB952_GPIO_USB_PWROFF RBSPI_SSR_GPIO(RB952_SSR_BIT_USB_POWER)
217 #define RB952_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN1)
218 #define RB952_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN2)
219 #define RB952_GPIO_LED_LAN3 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN3)
220 #define RB952_GPIO_LED_LAN4 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN4)
221 #define RB952_GPIO_LED_LAN5 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN5)
222 #define RB952_GPIO_LED_WLAN RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_WLAN)
223
224 static struct gpio_led rb952_leds[] __initdata = {
225 {
226 .name = "rb:green:user",
227 .gpio = RB952_GPIO_LED_USER,
228 .active_low = 0,
229 }, {
230 .name = "rb:blue:wlan",
231 .gpio = RB952_GPIO_LED_WLAN,
232 .active_low = 1,
233 }, {
234 .name = "rb:green:port1",
235 .gpio = RB952_GPIO_LED_LAN1,
236 .active_low = 1,
237 }, {
238 .name = "rb:green:port2",
239 .gpio = RB952_GPIO_LED_LAN2,
240 .active_low = 1,
241 }, {
242 .name = "rb:green:port3",
243 .gpio = RB952_GPIO_LED_LAN3,
244 .active_low = 1,
245 }, {
246 .name = "rb:green:port4",
247 .gpio = RB952_GPIO_LED_LAN4,
248 .active_low = 1,
249 }, {
250 .name = "rb:green:port5",
251 .gpio = RB952_GPIO_LED_LAN5,
252 .active_low = 1,
253 },
254 };
255
256
257 /* RB 962UiGS-5HacT2HnT gpios */
258 #define RB962_WIFI_LED_1 1
259 #define RB962_WIFI_LED_2 2
260 #define RB962_GPIO_POE_STATUS 2
261 #define RB962_GPIO_POE_POWER 3
262 #define RB962_GPIO_LED_USER 12
263 #define RB962_GPIO_USB_PWROFF 13
264 #define RB962_GPIO_BTN_RESET 20
265
266 static struct gpio_led rb962_leds_gpio[] __initdata = {
267 {
268 .name = "rb:green:user",
269 .gpio = RB962_GPIO_LED_USER,
270 .active_low = 1,
271 },
272 };
273
274 static const struct ar8327_led_info rb962_leds_ar8327[] = {
275 AR8327_LED_INFO(PHY0_0, HW, "rb:green:port1"),
276 AR8327_LED_INFO(PHY1_0, HW, "rb:green:port2"),
277 AR8327_LED_INFO(PHY2_0, HW, "rb:green:port3"),
278 AR8327_LED_INFO(PHY3_0, HW, "rb:green:port4"),
279 AR8327_LED_INFO(PHY4_0, HW, "rb:green:port5"),
280 };
281
282 static struct ar8327_pad_cfg rb962_ar8327_pad0_cfg = {
283 .mode = AR8327_PAD_MAC_RGMII,
284 .txclk_delay_en = true,
285 .rxclk_delay_en = true,
286 .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
287 .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
288 .mac06_exchange_dis = true,
289 };
290
291 static struct ar8327_pad_cfg rb962_ar8327_pad6_cfg = {
292 /* Use SGMII interface for GMAC6 of the AR8337 switch */
293 .mode = AR8327_PAD_MAC_SGMII,
294 .rxclk_delay_en = true,
295 .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0,
296 };
297
298 static struct ar8327_led_cfg rb962_ar8327_led_cfg = {
299 .led_ctrl0 = 0xc737c737,
300 .led_ctrl1 = 0x00000000,
301 .led_ctrl2 = 0x00000000,
302 .led_ctrl3 = 0x0030c300,
303 .open_drain = false,
304 };
305
306 static struct ar8327_platform_data rb962_ar8327_data = {
307 .pad0_cfg = &rb962_ar8327_pad0_cfg,
308 .pad6_cfg = &rb962_ar8327_pad6_cfg,
309 .port0_cfg = {
310 .force_link = 1,
311 .speed = AR8327_PORT_SPEED_1000,
312 .duplex = 1,
313 .txpause = 1,
314 .rxpause = 1,
315 },
316 .port6_cfg = {
317 .force_link = 1,
318 .speed = AR8327_PORT_SPEED_1000,
319 .duplex = 1,
320 .txpause = 1,
321 .rxpause = 1,
322 },
323 .led_cfg = &rb962_ar8327_led_cfg,
324 .num_leds = ARRAY_SIZE(rb962_leds_ar8327),
325 .leds = rb962_leds_ar8327,
326 };
327
328 static struct mdio_board_info rb962_mdio0_info[] = {
329 {
330 .bus_id = "ag71xx-mdio.0",
331 .phy_addr = 0,
332 .platform_data = &rb962_ar8327_data,
333 },
334 };
335
336 /* RB wAP-2nD gpios */
337 #define RBWAP_GPIO_LED_USER 14
338 #define RBWAP_GPIO_LED_WLAN 11
339 #define RBWAP_GPIO_BTN_RESET 16
340
341 static struct gpio_led rbwap_leds[] __initdata = {
342 {
343 .name = "rb:green:user",
344 .gpio = RBWAP_GPIO_LED_USER,
345 .active_low = 1,
346 }, {
347 .name = "rb:green:wlan",
348 .gpio = RBWAP_GPIO_LED_WLAN,
349 .active_low = 1,
350 },
351 };
352
353 /* RB cAP-2nD gpios */
354 #define RBCAP_GPIO_LED_1 14
355 #define RBCAP_GPIO_LED_2 12
356 #define RBCAP_GPIO_LED_3 11
357 #define RBCAP_GPIO_LED_4 4
358 #define RBCAP_GPIO_LED_ALL 13
359
360 static struct gpio_led rbcap_leds[] __initdata = {
361 {
362 .name = "rb:green:rssi1",
363 .gpio = RBCAP_GPIO_LED_1,
364 .active_low = 1,
365 }, {
366 .name = "rb:green:rssi2",
367 .gpio = RBCAP_GPIO_LED_2,
368 .active_low = 1,
369 }, {
370 .name = "rb:green:rssi3",
371 .gpio = RBCAP_GPIO_LED_3,
372 .active_low = 1,
373 }, {
374 .name = "rb:green:rssi4",
375 .gpio = RBCAP_GPIO_LED_4,
376 .active_low = 1,
377 },
378 };
379
380 /* RB mAP-2nD gpios */
381 #define RBMAP_SSR_BIT_LED_LAN1 0
382 #define RBMAP_SSR_BIT_LED_LAN2 1
383 #define RBMAP_SSR_BIT_LED_POEO 2
384 #define RBMAP_SSR_BIT_LED_USER 3
385 #define RBMAP_SSR_BIT_LED_WLAN 4
386 #define RBMAP_SSR_BIT_USB_POWER 5
387 #define RBMAP_SSR_BIT_LED_APCAP 6
388 #define RBMAP_GPIO_BTN_RESET 16
389 #define RBMAP_GPIO_SSR_CS 11
390 #define RBMAP_GPIO_LED_POWER 4
391 #define RBMAP_GPIO_POE_POWER 14
392 #define RBMAP_GPIO_POE_STATUS 12
393 #define RBMAP_GPIO_USB_PWROFF RBSPI_SSR_GPIO(RBMAP_SSR_BIT_USB_POWER)
394 #define RBMAP_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN1)
395 #define RBMAP_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN2)
396 #define RBMAP_GPIO_LED_POEO RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_POEO)
397 #define RBMAP_GPIO_LED_USER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_USER)
398 #define RBMAP_GPIO_LED_WLAN RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_WLAN)
399 #define RBMAP_GPIO_LED_APCAP RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_APCAP)
400
401 static struct gpio_led rbmap_leds[] __initdata = {
402 {
403 .name = "rb:green:power",
404 .gpio = RBMAP_GPIO_LED_POWER,
405 .active_low = 1,
406 .default_state = LEDS_GPIO_DEFSTATE_ON,
407 }, {
408 .name = "rb:green:eth1",
409 .gpio = RBMAP_GPIO_LED_LAN1,
410 .active_low = 1,
411 }, {
412 .name = "rb:green:eth2",
413 .gpio = RBMAP_GPIO_LED_LAN2,
414 .active_low = 1,
415 }, {
416 .name = "rb:red:poe_out",
417 .gpio = RBMAP_GPIO_LED_POEO,
418 .active_low = 1,
419 }, {
420 .name = "rb:green:user",
421 .gpio = RBMAP_GPIO_LED_USER,
422 .active_low = 1,
423 }, {
424 .name = "rb:green:wlan",
425 .gpio = RBMAP_GPIO_LED_WLAN,
426 .active_low = 1,
427 }, {
428 .name = "rb:green:ap_cap",
429 .gpio = RBMAP_GPIO_LED_APCAP,
430 .active_low = 1,
431 },
432 };
433
434 /* RB LHG 5nD gpios */
435 #define RBLHG_GPIO_LED_0 13
436 #define RBLHG_GPIO_LED_1 12
437 #define RBLHG_GPIO_LED_2 4
438 #define RBLHG_GPIO_LED_3 21
439 #define RBLHG_GPIO_LED_4 18
440 #define RBLHG_GPIO_LED_ETH 14
441 #define RBLHG_GPIO_LED_POWER 11
442 #define RBLHG_GPIO_LED_USER 20
443 #define RBLHG_GPIO_BTN_RESET 15
444
445 static struct gpio_led rblhg_leds[] __initdata = {
446 {
447 .name = "rb:green:rssi0",
448 .gpio = RBLHG_GPIO_LED_0,
449 .active_low = 1,
450 }, {
451 .name = "rb:green:rssi1",
452 .gpio = RBLHG_GPIO_LED_1,
453 .active_low = 1,
454 }, {
455 .name = "rb:green:rssi2",
456 .gpio = RBLHG_GPIO_LED_2,
457 .active_low = 1,
458 }, {
459 .name = "rb:green:rssi3",
460 .gpio = RBLHG_GPIO_LED_3,
461 .active_low = 1,
462 }, {
463 .name = "rb:green:rssi4",
464 .gpio = RBLHG_GPIO_LED_4,
465 .active_low = 1,
466 }, {
467 .name = "rb:green:eth",
468 .gpio = RBLHG_GPIO_LED_ETH,
469 .active_low = 1,
470 }, {
471 .name = "rb:green:user",
472 .gpio = RBLHG_GPIO_LED_USER,
473 .active_low = 1,
474 }, {
475 .name = "rb:blue:power",
476 .gpio = RBLHG_GPIO_LED_POWER,
477 .active_low = 0,
478 .default_state = LEDS_GPIO_DEFSTATE_ON,
479 },
480 };
481
482 /* RB w APG-5HacT2HnD (wAP AC) gpios*/
483 #define RBWAPGSC_WIFI_LED_1 1
484 #define RBWAPGSC_WIFI_LED_2 8
485 #define RBWAPGSC_WIFI_LED_3 9
486 #define RBWAPGSC_GPIO_LED_POWER 16
487 #define RBWAPGSC_GPIO_BTN_RESET 1
488 #define RBWAPGSC_GPIO_MDIO_MDC 12
489 #define RBWAPGSC_GPIO_MDIO_DATA 11
490 #define RBWAPGSC_MDIO_PHYADDR 0
491
492 static struct gpio_led rbwapgsc_leds[] __initdata = {
493 {
494 .name = "rb:green:power",
495 .gpio = RBWAPGSC_GPIO_LED_POWER,
496 .active_low = 1,
497 .default_state = LEDS_GPIO_DEFSTATE_ON,
498 },
499 };
500
501 static struct mdio_gpio_platform_data rbwapgsc_mdio_data = {
502 .mdc = RBWAPGSC_GPIO_MDIO_MDC,
503 .mdio = RBWAPGSC_GPIO_MDIO_DATA,
504 .phy_mask = ~BIT(RBWAPGSC_MDIO_PHYADDR),
505 };
506
507 static struct platform_device rbwapgsc_phy_device = {
508 .name = "mdio-gpio",
509 .id = 1,
510 .dev = {
511 .platform_data = &rbwapgsc_mdio_data
512 },
513 };
514
515 /* RB911L GPIOs */
516 #define RB911L_GPIO_BTN_RESET 15
517 #define RB911L_GPIO_LED_1 13
518 #define RB911L_GPIO_LED_2 12
519 #define RB911L_GPIO_LED_3 4
520 #define RB911L_GPIO_LED_4 21
521 #define RB911L_GPIO_LED_5 18
522 #define RB911L_GPIO_LED_ETH 20
523 #define RB911L_GPIO_LED_POWER 11
524 #define RB911L_GPIO_LED_USER 3
525 #define RB911L_GPIO_PIN_HOLE 14 /* for reference, active low */
526
527 static struct gpio_led rb911l_leds[] __initdata = {
528 {
529 .name = "rb:green:eth",
530 .gpio = RB911L_GPIO_LED_ETH,
531 .active_low = 1,
532 }, {
533 .name = "rb:green:led1",
534 .gpio = RB911L_GPIO_LED_1,
535 .active_low = 1,
536 }, {
537 .name = "rb:green:led2",
538 .gpio = RB911L_GPIO_LED_2,
539 .active_low = 1,
540 }, {
541 .name = "rb:green:led3",
542 .gpio = RB911L_GPIO_LED_3,
543 .active_low = 1,
544 }, {
545 .name = "rb:green:led4",
546 .gpio = RB911L_GPIO_LED_4,
547 .active_low = 1,
548 }, {
549 .name = "rb:green:led5",
550 .gpio = RB911L_GPIO_LED_5,
551 .active_low = 1,
552 }, {
553 .name = "rb:green:power",
554 .gpio = RB911L_GPIO_LED_POWER,
555 .default_state = LEDS_GPIO_DEFSTATE_ON,
556 .active_low = 1,
557 .open_drain = 1,
558 }, {
559 .name = "rb:green:user",
560 .gpio = RB911L_GPIO_LED_USER,
561 .active_low = 1,
562 .open_drain = 1,
563 },
564 };
565
566 /* RB 931-2nD gpios */
567 #define RB931_GPIO_BTN_RESET 0
568 #define RB931_GPIO_BTN_MODE 9
569 #define RB931_GPIO_LED_USER 1
570
571 static struct gpio_keys_button rb931_gpio_keys[] __initdata = {
572 {
573 .desc = "Reset button",
574 .type = EV_KEY,
575 .code = KEY_RESTART,
576 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
577 .gpio = RB931_GPIO_BTN_RESET,
578 .active_low = 1,
579 }, {
580 .desc = "Mode button",
581 .type = EV_KEY,
582 .code = BTN_0,
583 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
584 .gpio = RB931_GPIO_BTN_MODE,
585 .active_low = 1,
586 }
587 };
588
589 static struct gpio_led rb931_leds[] __initdata = {
590 {
591 .name = "rb:green:user",
592 .gpio = RB931_GPIO_LED_USER,
593 .active_low = 1,
594 },
595 };
596
597 static struct gen_74x164_chip_platform_data rbspi_ssr_data = {
598 .base = RBSPI_SSR_GPIO_BASE,
599 .num_registers = 1,
600 };
601
602 /* the spi-ath79 driver can only natively handle CS0. Other CS are bit-banged */
603 static int rbspi_spi_cs_gpios[] = {
604 -ENOENT, /* CS0 is always -ENOENT: natively handled */
605 -ENOENT, /* CS1 can be updated by the code as necessary */
606 };
607
608 static struct ath79_spi_platform_data rbspi_ath79_spi_data = {
609 .bus_num = 0,
610 .cs_gpios = rbspi_spi_cs_gpios,
611 };
612
613 /*
614 * Global spi_board_info: devices that don't have an SSR only have the SPI NOR
615 * flash on bus0 CS0, while devices that have an SSR add it on the same bus CS1
616 */
617 static struct spi_board_info rbspi_spi_info[] = {
618 {
619 .bus_num = 0,
620 .chip_select = 0,
621 .max_speed_hz = 25000000,
622 .modalias = "m25p80",
623 .platform_data = &rbspi_spi_flash_data,
624 }, {
625 .bus_num = 0,
626 .chip_select = 1,
627 .max_speed_hz = 25000000,
628 .modalias = "74x164",
629 .platform_data = &rbspi_ssr_data,
630 }
631 };
632
633 void __init rbspi_wlan_init(u16 id, int wmac_offset)
634 {
635 char *art_buf;
636 u8 wlan_mac[ETH_ALEN];
637
638 art_buf = rb_get_ext_wlan_data(id);
639 if (!art_buf)
640 return;
641
642 ath79_init_mac(wlan_mac, ath79_mac_base, wmac_offset);
643 ath79_register_wmac(art_buf + 0x1000, wlan_mac);
644
645 kfree(art_buf);
646 }
647
648 #define RBSPI_MACH_BUFLEN 64
649 /*
650 * Common platform init routine for all SPI NOR devices.
651 */
652 static __init const struct rb_info *rbspi_platform_setup(void)
653 {
654 const struct rb_info *info;
655 char buf[RBSPI_MACH_BUFLEN] = "MikroTik ";
656 char *str;
657 int len = RBSPI_MACH_BUFLEN - strlen(buf) - 1;
658
659 info = rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE)), 0x20000);
660 if (!info)
661 return NULL;
662
663 if (info->board_name) {
664 str = "RouterBOARD ";
665 if (strncmp(info->board_name, str, strlen(str))) {
666 strncat(buf, str, len);
667 len -= strlen(str);
668 }
669 strncat(buf, info->board_name, len);
670 }
671 else
672 strncat(buf, "UNKNOWN", len);
673
674 mips_set_machine_name(buf);
675
676 /* fix partitions based on flash parsing */
677 rbspi_init_partitions(info);
678
679 return info;
680 }
681
682 /*
683 * Common peripherals init routine for all SPI NOR devices.
684 * Sets SPI and USB.
685 */
686 static void __init rbspi_peripherals_setup(u32 flags)
687 {
688 unsigned spi_n;
689
690 if (flags & RBSPI_HAS_SSR)
691 spi_n = ARRAY_SIZE(rbspi_spi_info);
692 else
693 spi_n = 1; /* only one device on bus0 */
694
695 rbspi_ath79_spi_data.num_chipselect = spi_n;
696 rbspi_ath79_spi_data.cs_gpios = rbspi_spi_cs_gpios;
697 ath79_register_spi(&rbspi_ath79_spi_data, rbspi_spi_info, spi_n);
698
699 if (flags & RBSPI_HAS_USB)
700 ath79_register_usb();
701
702 if (flags & RBSPI_HAS_PCI)
703 ath79_register_pci();
704 }
705
706 /*
707 * Common network init routine for all SPI NOR devices.
708 * Sets LAN/WAN/WLAN.
709 */
710 static void __init rbspi_network_setup(u32 flags, int gmac1_offset,
711 int wmac0_offset, int wmac1_offset)
712 {
713 /* for QCA953x that will init mdio1_device/data */
714 ath79_register_mdio(0, 0x0);
715 if (flags & RBSPI_HAS_MDIO1)
716 ath79_register_mdio(1, 0x0);
717
718 if (flags & RBSPI_HAS_WAN4) {
719 ath79_setup_ar934x_eth_cfg(0);
720
721 /* set switch to oper mode 1, PHY4 connected to CPU */
722 ath79_switch_data.phy4_mii_en = 1;
723 ath79_switch_data.phy_poll_mask |= BIT(4);
724
725 /* init GMAC0 connected to PHY4 at 100M */
726 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
727 ath79_eth0_data.phy_mask = BIT(4);
728 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
729 ath79_register_eth(0);
730 } else {
731 /* set the SoC to SW_ONLY_MODE, which connects all PHYs
732 * to the internal switch.
733 * We hijack ath79_setup_ar934x_eth_cfg() to set the switch in
734 * the QCA953x, this works because this configuration bit is
735 * the same as the AR934x. There's no equivalent function for
736 * QCA953x for now. */
737 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
738 }
739
740 /* init GMAC1 */
741 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, gmac1_offset);
742 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
743 ath79_register_eth(1);
744
745 if (flags & RBSPI_HAS_WLAN0)
746 rbspi_wlan_init(0, wmac0_offset);
747
748 if (flags & RBSPI_HAS_WLAN1)
749 rbspi_wlan_init(1, wmac1_offset);
750 }
751
752 static __init void rbspi_register_reset_button(int gpio)
753 {
754 rbspi_gpio_keys_reset[0].gpio = gpio;
755 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
756 ARRAY_SIZE(rbspi_gpio_keys_reset),
757 rbspi_gpio_keys_reset);
758 }
759
760 /*
761 * Init the mAP lite hardware (QCA953x).
762 * The mAP L-2nD (mAP lite) has a single ethernet port, connected to PHY0.
763 * Trying to use GMAC0 in direct mode was unsucessful, so we're
764 * using SW_ONLY_MODE, which connects PHY0 to MAC1 on the internal
765 * switch, which is connected to GMAC1 on the SoC. GMAC0 is unused.
766 */
767 static void __init rbmapl_setup(void)
768 {
769 u32 flags = RBSPI_HAS_WLAN0;
770
771 if (!rbspi_platform_setup())
772 return;
773
774 rbspi_peripherals_setup(flags);
775
776 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
777 rbspi_network_setup(flags, 0, 1, 0);
778
779 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmapl_leds), rbmapl_leds);
780
781 /* mAP lite has a single reset button as gpio 16 */
782 rbspi_register_reset_button(RBMAPL_GPIO_BTN_RESET);
783
784 /* clear internal multiplexing */
785 ath79_gpio_output_select(RBMAPL_GPIO_LED_ETH, AR934X_GPIO_OUT_GPIO);
786 ath79_gpio_output_select(RBMAPL_GPIO_LED_POWER, AR934X_GPIO_OUT_GPIO);
787 }
788
789 /*
790 * Init the hAP lite hardware (QCA953x).
791 * The 941-2nD (hAP lite) has 4 ethernet ports, with port 2-4
792 * being assigned to LAN on the casing, and port 1 being assigned
793 * to "internet" (WAN) on the casing. Port 1 is connected to PHY3.
794 * Since WAN is neither PHY0 nor PHY4, we cannot use GMAC0 with this device.
795 */
796 static void __init rbhapl_setup(void)
797 {
798 u32 flags = RBSPI_HAS_WLAN0;
799
800 if (!rbspi_platform_setup())
801 return;
802
803 rbspi_peripherals_setup(flags);
804
805 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 4 */
806 rbspi_network_setup(flags, 0, 4, 0);
807
808 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbhapl_leds), rbhapl_leds);
809
810 /* hAP lite has a single reset button as gpio 16 */
811 rbspi_register_reset_button(RBHAPL_GPIO_BTN_RESET);
812 }
813
814 /*
815 * The hAP, hAP ac lite, hEX lite and hEX PoE lite share the same platform
816 */
817 static void __init rbspi_952_750r2_setup(u32 flags)
818 {
819 if (flags & RBSPI_HAS_SSR)
820 rbspi_spi_cs_gpios[1] = RB952_GPIO_SSR_CS;
821
822 rbspi_peripherals_setup(flags);
823
824 /*
825 * GMAC1 is HW MAC + 1, WLAN0 MAC IS HW MAC + 5 (hAP),
826 * WLAN1 MAC IS HW MAC + 6 (hAP ac lite)
827 */
828 rbspi_network_setup(flags, 1, 5, 6);
829
830 if (flags & RBSPI_HAS_USB)
831 gpio_request_one(RB952_GPIO_USB_PWROFF, GPIOF_ACTIVE_LOW |
832 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
833 "USB power off");
834
835 if (flags & RBSPI_HAS_POE)
836 gpio_request_one(RB952_GPIO_POE_POWER,
837 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
838 "POE power");
839
840 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb952_leds), rb952_leds);
841
842 /* These devices have a single reset button as gpio 16 */
843 rbspi_register_reset_button(RB952_GPIO_BTN_RESET);
844 }
845
846 /*
847 * Init the hAP (ac lite) hardware (QCA953x).
848 * The 951Ui-2nD (hAP) has 5 ethernet ports, with ports 2-5 being assigned
849 * to LAN on the casing, and port 1 being assigned to "internet" (WAN).
850 * Port 1 is connected to PHY4 (the ports are labelled in reverse physical
851 * number), so the SoC can be set to connect GMAC0 to PHY4 and GMAC1 to the
852 * internal switch for the LAN ports.
853 * The device also has USB, PoE output and an SSR used for LED multiplexing.
854 * The 952Ui-5ac2nD (hAP ac lite) is nearly identical to the hAP, it adds a
855 * QCA9887 5GHz radio via PCI and moves 2.4GHz from WLAN0 to WLAN1.
856 */
857 static void __init rb952_setup(void)
858 {
859 u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_USB |
860 RBSPI_HAS_SSR | RBSPI_HAS_POE;
861
862 if (!rbspi_platform_setup())
863 return;
864
865 /* differentiate the hAP from the hAP ac lite */
866 if (strstr(mips_get_machine_name(), "952Ui-5ac2nD"))
867 flags |= RBSPI_HAS_WLAN1 | RBSPI_HAS_PCI;
868 else
869 flags |= RBSPI_HAS_WLAN0;
870
871 rbspi_952_750r2_setup(flags);
872 }
873
874 /*
875 * Init the hEX (PoE) lite hardware (QCA953x).
876 * The 750UP r2 (hEX PoE lite) is nearly identical to the hAP, only without
877 * WLAN. The 750 r2 (hEX lite) is nearly identical to the 750UP r2, only
878 * without USB and POE. The 750P Pbr2 (Powerbox) is nearly identical to hEX PoE
879 * lite, only without USB. It shares the same bootloader board identifier.
880 */
881 static void __init rb750upr2_setup(void)
882 {
883 u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_SSR;
884
885 if (!rbspi_platform_setup())
886 return;
887
888 /* differentiate the hEX lite from the hEX PoE lite */
889 if (strstr(mips_get_machine_name(), "750UP r2"))
890 flags |= RBSPI_HAS_USB | RBSPI_HAS_POE;
891
892 /* differentiate the Powerbox from the hEX lite */
893 else if (strstr(mips_get_machine_name(), "750P r2"))
894 flags |= RBSPI_HAS_POE;
895
896 rbspi_952_750r2_setup(flags);
897 }
898
899 /*
900 * Init the hAP ac / 962UiGS-5HacT2HnT hardware (QCA9558).
901 * The hAP ac has 5 ethernet ports provided by an AR8337 switch. Port 1 is
902 * assigned to WAN, ports 2-5 are assigned to LAN. Port 0 is connected to the
903 * SoC, ports 1-5 of the switch are connected to physical ports 1-5 in order.
904 * The SFP cage is not assigned by default on RouterOS. Extra work is required
905 * to support this interface as it is directly connected to the SoC (eth1).
906 * Wireless is provided by a 2.4GHz radio on the SoC (WLAN1) and a 5GHz radio
907 * attached via PCI (QCA9880). Red and green WLAN LEDs are populated however
908 * they are not attached to GPIOs, extra work is required to support these.
909 * PoE and USB output power control is supported.
910 */
911 static void __init rb962_setup(void)
912 {
913 u32 flags = RBSPI_HAS_USB | RBSPI_HAS_POE | RBSPI_HAS_PCI;
914
915 if (!rbspi_platform_setup())
916 return;
917
918 rbspi_peripherals_setup(flags);
919
920 /* Do not call rbspi_network_setup as we have a discrete switch chip */
921 ath79_eth0_pll_data.pll_1000 = 0xae000000;
922 ath79_eth0_pll_data.pll_100 = 0xa0000101;
923 ath79_eth0_pll_data.pll_10 = 0xa0001313;
924
925 ath79_register_mdio(0, 0x0);
926 mdiobus_register_board_info(rb962_mdio0_info,
927 ARRAY_SIZE(rb962_mdio0_info));
928
929 ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
930
931 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
932 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
933 ath79_eth0_data.phy_mask = BIT(0);
934 ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
935 ath79_register_eth(0);
936
937 /* WLAN1 MAC is HW MAC + 7 */
938 rbspi_wlan_init(1, 7);
939
940 if (flags & RBSPI_HAS_USB)
941 gpio_request_one(RB962_GPIO_USB_PWROFF, GPIOF_ACTIVE_LOW |
942 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
943 "USB power off");
944
945 /* PoE output GPIO is inverted, set GPIOF_ACTIVE_LOW for consistency */
946 if (flags & RBSPI_HAS_POE)
947 gpio_request_one(RB962_GPIO_POE_POWER,
948 GPIOF_OUT_INIT_HIGH | GPIOF_ACTIVE_LOW |
949 GPIOF_EXPORT_DIR_FIXED,
950 "POE power");
951
952 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb962_leds_gpio),
953 rb962_leds_gpio);
954
955 /* This device has a single reset button as gpio 20 */
956 rbspi_register_reset_button(RB962_GPIO_BTN_RESET);
957 }
958
959 /*
960 * Init the LHG hardware (AR9344).
961 * The LHG 5nD has a single ethernet port connected to PHY0.
962 * Wireless is provided via 5GHz WLAN1.
963 */
964 static void __init rblhg_setup(void)
965 {
966 u32 flags = RBSPI_HAS_WLAN1 | RBSPI_HAS_MDIO1;
967
968 if (!rbspi_platform_setup())
969 return;
970
971 rbspi_peripherals_setup(flags);
972
973 /* GMAC1 is HW MAC, WLAN1 MAC is HW MAC + 1 */
974 rbspi_network_setup(flags, 0, 0, 1);
975
976 ath79_register_leds_gpio(-1, ARRAY_SIZE(rblhg_leds), rblhg_leds);
977
978 rbspi_register_reset_button(RBLHG_GPIO_BTN_RESET);
979 }
980
981 /*
982 * Init the wAP hardware.
983 * The wAP 2nD has a single ethernet port.
984 */
985 static void __init rbwap_setup(void)
986 {
987 u32 flags = RBSPI_HAS_WLAN0;
988
989 if (!rbspi_platform_setup())
990 return;
991
992 rbspi_peripherals_setup(flags);
993
994 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
995 rbspi_network_setup(flags, 0, 1, 0);
996
997 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwap_leds), rbwap_leds);
998
999 /* wAP has a single reset button as GPIO 16 */
1000 rbspi_register_reset_button(RBWAP_GPIO_BTN_RESET);
1001 }
1002
1003 /*
1004 * Init the cAP hardware (EXPERIMENTAL).
1005 * The cAP 2nD has a single ethernet port, and a global LED switch.
1006 */
1007 static void __init rbcap_setup(void)
1008 {
1009 u32 flags = RBSPI_HAS_WLAN0;
1010
1011 if (!rbspi_platform_setup())
1012 return;
1013
1014 rbspi_peripherals_setup(flags);
1015
1016 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
1017 rbspi_network_setup(flags, 0, 1, 0);
1018
1019 gpio_request_one(RBCAP_GPIO_LED_ALL,
1020 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
1021 "LEDs enable");
1022
1023 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbcap_leds), rbcap_leds);
1024 }
1025
1026 /*
1027 * Init the mAP hardware.
1028 * The mAP 2nD has two ethernet ports, PoE output, SSR for LED
1029 * multiplexing and USB port.
1030 */
1031 static void __init rbmap_setup(void)
1032 {
1033 u32 flags = RBSPI_HAS_USB | RBSPI_HAS_WLAN0 |
1034 RBSPI_HAS_SSR | RBSPI_HAS_POE;
1035
1036 if (!rbspi_platform_setup())
1037 return;
1038
1039 rbspi_spi_cs_gpios[1] = RBMAP_GPIO_SSR_CS;
1040 rbspi_peripherals_setup(flags);
1041
1042 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 2 */
1043 rbspi_network_setup(flags, 0, 2, 0);
1044
1045 if (flags & RBSPI_HAS_POE)
1046 gpio_request_one(RBMAP_GPIO_POE_POWER,
1047 GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
1048 "POE power");
1049
1050 if (flags & RBSPI_HAS_USB)
1051 gpio_request_one(RBMAP_GPIO_USB_PWROFF,
1052 GPIOF_OUT_INIT_HIGH | GPIOF_ACTIVE_LOW |
1053 GPIOF_EXPORT_DIR_FIXED,
1054 "USB power off");
1055
1056 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmap_leds), rbmap_leds);
1057
1058 /* mAP 2nD has a single reset button as gpio 16 */
1059 rbspi_register_reset_button(RBMAP_GPIO_BTN_RESET);
1060 }
1061
1062 /*
1063 * Init the wAPGSC (RB wAPG-5HacT2HnD // wAP AC) hardware.
1064 * The wAPGSC has one Ethernet port via AR8033 with PoE input, dual radio (SoC
1065 * 2.4 GHz and external QCA9880) and a ZT2046Q temperature and voltage sensor
1066 * (currently not supported).
1067 */
1068 static void __init rbwapgsc_setup(void)
1069 {
1070 u32 flags = RBSPI_HAS_PCI;
1071
1072 if (!rbspi_platform_setup())
1073 return;
1074
1075 rbspi_peripherals_setup(flags);
1076
1077 platform_device_register(&rbwapgsc_phy_device);
1078
1079 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
1080 ath79_eth1_data.mii_bus_dev = &rbwapgsc_phy_device.dev;
1081 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
1082 ath79_eth1_data.phy_mask = BIT(RBWAPGSC_MDIO_PHYADDR);
1083 ath79_eth1_pll_data.pll_1000 = 0x03000101;
1084 ath79_eth1_pll_data.pll_100 = 0x80000101;
1085 ath79_eth1_pll_data.pll_10 = 0x80001313;
1086 ath79_eth1_data.speed = SPEED_1000;
1087 ath79_eth1_data.duplex = DUPLEX_FULL;
1088 ath79_register_eth(1);
1089
1090 rbspi_wlan_init(1, 2);
1091
1092 rbspi_register_reset_button(RBWAPGSC_GPIO_BTN_RESET);
1093
1094 ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE|
1095 QCA955X_GPIO_REG_OUT_FUNC4|
1096 QCA955X_GPIO_REG_OUT_FUNC3);
1097
1098 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwapgsc_leds),
1099 rbwapgsc_leds);
1100 }
1101
1102 /*
1103 * Setup the 911L hardware (AR9344).
1104 */
1105 static void __init rb911l_setup(void)
1106 {
1107 const struct rb_info *info;
1108
1109 info = rbspi_platform_setup();
1110 if (!info)
1111 return;
1112
1113 if (!rb_has_hw_option(info, RB_HW_OPT_NO_NAND)) {
1114 /*
1115 * Old hardware revisions might be equipped with a NAND flash
1116 * chip instead of the 16MiB SPI NOR device. Those boards are
1117 * not supported at the moment, so throw a warning and skip
1118 * the peripheral setup to avoid messing up the data in the
1119 * flash chip.
1120 */
1121 WARN(1, "The NAND flash on this board is not supported.\n");
1122 } else {
1123 rbspi_peripherals_setup(0);
1124 }
1125
1126 ath79_register_mdio(1, 0x0);
1127
1128 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
1129
1130 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
1131 ath79_eth1_data.speed = SPEED_1000;
1132 ath79_eth1_data.duplex = DUPLEX_FULL;
1133
1134 ath79_register_eth(1);
1135
1136 rbspi_wlan_init(0, 1);
1137
1138 rbspi_register_reset_button(RB911L_GPIO_BTN_RESET);
1139
1140 /* Make the eth LED controllable by software. */
1141 ath79_gpio_output_select(RB911L_GPIO_LED_ETH, AR934X_GPIO_OUT_GPIO);
1142
1143 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb911l_leds), rb911l_leds);
1144 }
1145
1146 /*
1147 * Init the hAP mini hardware (QCA953x).
1148 * The 931-2nD (hAP mini) has 3 ethernet ports, with port 2-3
1149 * being assigned to LAN on the casing, and port 1 being assigned
1150 * to "internet" (WAN) on the casing. Port 1 is connected to PHY2.
1151 * Since WAN is neither PHY0 nor PHY4, we cannot use GMAC0 with this device.
1152 */
1153 static void __init rb931_setup(void)
1154 {
1155 u32 flags = RBSPI_HAS_WLAN0;
1156
1157 if (!rbspi_platform_setup())
1158 return;
1159
1160 rbspi_peripherals_setup(flags);
1161
1162 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 3 */
1163 rbspi_network_setup(flags, 0, 3, 0);
1164
1165 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb931_leds), rb931_leds);
1166
1167 /* hAP mini has two buttons */
1168 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
1169 ARRAY_SIZE(rb931_gpio_keys),
1170 rb931_gpio_keys);
1171 }
1172
1173 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAPL, "map-hb", rbmapl_setup);
1174 MIPS_MACHINE_NONAME(ATH79_MACH_RB_941, "H951L", rbhapl_setup);
1175 MIPS_MACHINE_NONAME(ATH79_MACH_RB_911L, "911L", rb911l_setup);
1176 MIPS_MACHINE_NONAME(ATH79_MACH_RB_952, "952-hb", rb952_setup);
1177 MIPS_MACHINE_NONAME(ATH79_MACH_RB_962, "962", rb962_setup);
1178 MIPS_MACHINE_NONAME(ATH79_MACH_RB_750UPR2, "750-hb", rb750upr2_setup);
1179 MIPS_MACHINE_NONAME(ATH79_MACH_RB_LHG5, "lhg", rblhg_setup);
1180 MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAP, "wap-hb", rbwap_setup);
1181 MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAPR, "wap-lte", rbwap_setup);
1182 MIPS_MACHINE_NONAME(ATH79_MACH_RB_CAP, "cap-hb", rbcap_setup);
1183 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAP, "map2-hb", rbmap_setup);
1184 MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAPAC, "wapg-sc", rbwapgsc_setup);
1185 MIPS_MACHINE_NONAME(ATH79_MACH_RB_931, "931", rb931_setup);
Staging tree of Zoltan Herpai