target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c

   1 /*
   2  *  Atheros AR71xx PCI host controller driver
   3  *
   4  *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/resource.h>
  15 #include <linux/types.h>
  16 #include <linux/delay.h>
  17 #include <linux/bitops.h>
  18 #include <linux/pci.h>
  19 #include <linux/pci_regs.h>
  20
  21 #include <asm/mach-ar71xx/ar71xx.h>
  22 #include <asm/mach-ar71xx/pci.h>
  23
  24 #undef DEBUG
  25 #ifdef DEBUG
  26 #define DBG(fmt, args...)       printk(KERN_DEBUG fmt, ## args)
  27 #else
  28 #define DBG(fmt, args...)
  29 #endif
  30
  31 #define AR71XX_PCI_DELAY        100 /* msecs */
  32
  33 #if 0
  34 #define PCI_IDSEL_BASE  PCI_IDSEL_ADL_START
  35 #else
  36 #define PCI_IDSEL_BASE  0
  37 #endif
  38
  39 static unsigned ar71xx_pci_nr_irqs;
  40 static struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata;
  41 static void __iomem *ar71xx_pcicfg_base;
  42
  43 static DEFINE_SPINLOCK(ar71xx_pci_lock);
  44
  45 static inline void ar71xx_pci_delay(void)
  46 {
  47         mdelay(AR71XX_PCI_DELAY);
  48 }
  49
  50 static inline u32 ar71xx_pcicfg_rr(unsigned int reg)
  51 {
  52         return __raw_readl(ar71xx_pcicfg_base + reg);
  53 }
  54
  55 static inline void ar71xx_pcicfg_wr(unsigned int reg, u32 val)
  56 {
  57         __raw_writel(val, ar71xx_pcicfg_base + reg);
  58 }
  59
  60 /* Byte lane enable bits */
  61 static u8 ble_table[4][4] = {
  62         {0x0, 0xf, 0xf, 0xf},
  63         {0xe, 0xd, 0xb, 0x7},
  64         {0xc, 0xf, 0x3, 0xf},
  65         {0xf, 0xf, 0xf, 0xf},
  66 };
  67
  68 static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
  69 {
  70         u32 t;
  71
  72         t = ble_table[size & 3][where & 3];
  73         BUG_ON(t == 0xf);
  74         t <<= (local) ? 20 : 4;
  75         return t;
  76 }
  77
  78 static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
  79                                         int where)
  80 {
  81         u32 ret;
  82
  83         if (!bus->number) {
  84                 /* type 0 */
  85                 ret = (1 << (PCI_IDSEL_BASE + PCI_SLOT(devfn)))
  86                     | (PCI_FUNC(devfn) << 8) | (where & ~3);
  87         } else {
  88                 /* type 1 */
  89                 ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11)
  90                     | (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
  91         }
  92
  93         return ret;
  94 }
  95
  96 static int __ar71xx_pci_be_handler(int is_fixup)
  97 {
  98         u32 pci_err;
  99         u32 ahb_err;
 100
 101         pci_err = ar71xx_pcicfg_rr(PCI_REG_PCI_ERR) & 3;
 102         if (pci_err) {
 103                 if (!is_fixup)
 104                         printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n",
 105                                 pci_err,
 106                                 ar71xx_pcicfg_rr(PCI_REG_PCI_ERR_ADDR));
 107
 108                 ar71xx_pcicfg_wr(PCI_REG_PCI_ERR, pci_err);
 109         }
 110
 111         ahb_err = ar71xx_pcicfg_rr(PCI_REG_AHB_ERR) & 1;
 112         if (ahb_err) {
 113                 if (!is_fixup)
 114                         printk(KERN_ALERT "AHB error at AHB address 0x%x\n",
 115                                 ar71xx_pcicfg_rr(PCI_REG_AHB_ERR_ADDR));
 116
 117                 ar71xx_pcicfg_wr(PCI_REG_AHB_ERR, ahb_err);
 118         }
 119
 120         return ((ahb_err | pci_err) ? 1 : 0);
 121 }
 122
 123 static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
 124                         unsigned int devfn, int where, int size, u32 cmd)
 125 {
 126         u32 addr;
 127
 128         addr = ar71xx_pci_bus_addr(bus, devfn, where);
 129
 130         DBG("PCI: set cfgaddr: %02x:%02x.%01x/%02x:%01d, addr=%08x\n",
 131                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 132                 where, size, addr);
 133
 134         ar71xx_pcicfg_wr(PCI_REG_CFG_AD, addr);
 135         ar71xx_pcicfg_wr(PCI_REG_CFG_CBE,
 136                         cmd | ar71xx_pci_get_ble(where, size, 0));
 137
 138         return __ar71xx_pci_be_handler(1);
 139 }
 140
 141 static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 142                                   int where, int size, u32 *value)
 143 {
 144         static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
 145         unsigned long flags;
 146         u32 data;
 147         int ret;
 148
 149         ret = PCIBIOS_SUCCESSFUL;
 150
 151         DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number,
 152                         PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
 153
 154         spin_lock_irqsave(&ar71xx_pci_lock, flags);
 155
 156         if (bus->number == 0 && devfn == 0) {
 157                 u32 t;
 158
 159                 t = PCI_CRP_CMD_READ | (where & ~3);
 160
 161                 ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t);
 162                 data = ar71xx_pcicfg_rr(PCI_REG_CRP_RDDATA);
 163
 164                 DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data);
 165
 166         } else {
 167                 int err;
 168
 169                 err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
 170                                                 PCI_CFG_CMD_READ);
 171
 172                 if (err == 0) {
 173                         data = ar71xx_pcicfg_rr(PCI_REG_CFG_RDDATA);
 174                 } else {
 175                         ret = PCIBIOS_DEVICE_NOT_FOUND;
 176                         data = ~0;
 177                 }
 178         }
 179
 180         spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
 181
 182         DBG("PCI: read config: data=%08x raw=%08x\n",
 183                 (data >> (8 * (where & 3))) & mask[size & 7], data);
 184
 185         *value = (data >> (8 * (where & 3))) & mask[size & 7];
 186
 187         return ret;
 188 }
 189
 190 static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 191                                    int where, int size, u32 value)
 192 {
 193         unsigned long flags;
 194         int ret;
 195
 196         DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d value=%08x\n",
 197                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 198                 where, size, value);
 199
 200         value = value << (8 * (where & 3));
 201         ret = PCIBIOS_SUCCESSFUL;
 202
 203         spin_lock_irqsave(&ar71xx_pci_lock, flags);
 204         if (bus->number == 0 && devfn == 0) {
 205                 u32 t;
 206
 207                 t = PCI_CRP_CMD_WRITE | (where & ~3);
 208                 t |= ar71xx_pci_get_ble(where, size, 1);
 209
 210                 DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value);
 211
 212                 ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t);
 213                 ar71xx_pcicfg_wr(PCI_REG_CRP_WRDATA, value);
 214         } else {
 215                 int err;
 216
 217                 err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
 218                                                 PCI_CFG_CMD_WRITE);
 219
 220                 if (err == 0)
 221                         ar71xx_pcicfg_wr(PCI_REG_CFG_WRDATA, value);
 222                 else
 223                         ret = PCIBIOS_DEVICE_NOT_FOUND;
 224         }
 225         spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
 226
 227         return ret;
 228 }
 229
 230 static void ar71xx_pci_fixup(struct pci_dev *dev)
 231 {
 232         u32 t;
 233
 234         if (dev->bus->number != 0 || dev->devfn != 0)
 235                 return;
 236
 237         DBG("PCI: fixup host controller %s (%04x:%04x)\n", pci_name(dev),
 238                 dev->vendor, dev->device);
 239
 240         /* setup COMMAND register */
 241         t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
 242           | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
 243
 244         pci_write_config_word(dev, PCI_COMMAND, t);
 245 }
 246
 247 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup);
 248
 249 int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
 250 {
 251         int irq = -1;
 252         int i;
 253
 254         slot -= PCI_IDSEL_ADL_START - PCI_IDSEL_BASE;
 255
 256         for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
 257                 struct ar71xx_pci_irq *entry;
 258
 259                 entry = &ar71xx_pci_irq_map[i];
 260                 if (entry->slot == slot && entry->pin == pin) {
 261                         irq = entry->irq;
 262                         break;
 263                 }
 264         }
 265
 266         if (irq < 0) {
 267                 printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
 268                                 pin, pci_name((struct pci_dev *)dev));
 269         } else {
 270                 printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
 271                                 irq, pin, pci_name((struct pci_dev *)dev));
 272         }
 273
 274         return irq;
 275 }
 276
 277 int pcibios_plat_dev_init(struct pci_dev *dev)
 278 {
 279         return 0;
 280 }
 281
 282 static struct pci_ops ar71xx_pci_ops = {
 283         .read   = ar71xx_pci_read_config,
 284         .write  = ar71xx_pci_write_config,
 285 };
 286
 287 static struct resource ar71xx_pci_io_resource = {
 288         .name           = "PCI IO space",
 289         .start          = 0,
 290         .end            = 0,
 291         .flags          = IORESOURCE_IO,
 292 };
 293
 294 static struct resource ar71xx_pci_mem_resource = {
 295         .name           = "PCI memory space",
 296         .start          = AR71XX_PCI_MEM_BASE,
 297         .end            = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
 298         .flags          = IORESOURCE_MEM
 299 };
 300
 301 static struct pci_controller ar71xx_pci_controller = {
 302         .pci_ops        = &ar71xx_pci_ops,
 303         .mem_resource   = &ar71xx_pci_mem_resource,
 304         .io_resource    = &ar71xx_pci_io_resource,
 305 };
 306
 307 static int __init __ar71xx_pci_bios_init(unsigned nr_irqs,
 308                                          struct ar71xx_pci_irq *map)
 309 {
 310         ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
 311         ar71xx_pci_delay();
 312
 313         ar71xx_device_start(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
 314         ar71xx_pci_delay();
 315
 316         ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
 317                                                 AR71XX_PCI_CFG_SIZE);
 318
 319         ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
 320         ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
 321         ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
 322         ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
 323         ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
 324         ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
 325         ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
 326         ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
 327
 328         ar71xx_pci_delay();
 329
 330         /* clear bus errors */
 331         (void)__ar71xx_pci_be_handler(1);
 332
 333         ar71xx_pci_nr_irqs = nr_irqs;
 334         ar71xx_pci_irq_map = map;
 335         ar71xx_pci_be_handler = __ar71xx_pci_be_handler;
 336
 337         register_pci_controller(&ar71xx_pci_controller);
 338
 339         return 0;
 340 }
 341
 342 static int __init __ar71xx_pci_init(void)
 343 {
 344         ar71xx_pci_bios_init = __ar71xx_pci_bios_init;
 345         return 0;
 346 }
 347 pure_initcall(__ar71xx_pci_init);