target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c

   1 /*
   2  *  Atheros AR724x PCI host controller driver
   3  *
   4  *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  Parts of this file are based on Atheros' 2.6.15 BSP
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License version 2 as published
  10  *  by the Free Software Foundation.
  11  */
  12
  13 #include <linux/resource.h>
  14 #include <linux/types.h>
  15 #include <linux/delay.h>
  16 #include <linux/bitops.h>
  17 #include <linux/pci.h>
  18 #include <linux/pci_regs.h>
  19
  20 #include <asm/mach-ar71xx/ar71xx.h>
  21 #include <asm/mach-ar71xx/pci.h>
  22
  23 #undef DEBUG
  24 #ifdef DEBUG
  25 #define DBG(fmt, args...)       printk(KERN_INFO fmt, ## args)
  26 #else
  27 #define DBG(fmt, args...)
  28 #endif
  29
  30 static void __iomem *ar724x_pci_localcfg_base;
  31 static void __iomem *ar724x_pci_devcfg_base;
  32 static int ar724x_pci_fixup_enable;
  33
  34 static DEFINE_SPINLOCK(ar724x_pci_lock);
  35
  36 static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value)
  37 {
  38         unsigned long flags;
  39         u32 data;
  40
  41         spin_lock_irqsave(&ar724x_pci_lock, flags);
  42         data = __raw_readl(base + (where & ~3));
  43
  44         switch (size) {
  45         case 1:
  46                 if (where & 1)
  47                         data >>= 8;
  48                 if (where & 2)
  49                         data >>= 16;
  50                 data &= 0xFF;
  51                 break;
  52         case 2:
  53                 if (where & 2)
  54                         data >>= 16;
  55                 data &= 0xFFFF;
  56                 break;
  57         }
  58
  59         *value = data;
  60         spin_unlock_irqrestore(&ar724x_pci_lock, flags);
  61 }
  62
  63 static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value)
  64 {
  65         unsigned long flags;
  66         u32 data;
  67         int s;
  68
  69         spin_lock_irqsave(&ar724x_pci_lock, flags);
  70         data = __raw_readl(base + (where & ~3));
  71
  72         switch (size) {
  73         case 1:
  74                 s = ((where & 3) << 3);
  75                 data &= ~(0xFF << s);
  76                 data |= ((value & 0xFF) << s);
  77                 break;
  78         case 2:
  79                 s = ((where & 2) << 3);
  80                 data &= ~(0xFFFF << s);
  81                 data |= ((value & 0xFFFF) << s);
  82                 break;
  83         case 4:
  84                 data = value;
  85                 break;
  86         }
  87
  88         __raw_writel(data, base + (where & ~3));
  89         /* flush write */
  90         (void)__raw_readl(base + (where & ~3));
  91         spin_unlock_irqrestore(&ar724x_pci_lock, flags);
  92 }
  93
  94 static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn,
  95                                   int where, int size, u32 *value)
  96 {
  97
  98         if (bus->number != 0 || devfn != 0)
  99                 return PCIBIOS_DEVICE_NOT_FOUND;
 100
 101         ar724x_pci_read(ar724x_pci_devcfg_base, where, size, value);
 102
 103         DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
 104                         bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 105                         where, size, *value);
 106
 107         /*
 108          * WAR for BAR issue - We are unable to access the PCI device space
 109          * if we set the BAR with proper base address
 110          */
 111         if ((where == 0x10) && (size == 4))
 112                 ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0xffff);
 113
 114         return PCIBIOS_SUCCESSFUL;
 115 }
 116
 117 static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 118                                    int where, int size, u32 value)
 119 {
 120         if (bus->number != 0 || devfn != 0)
 121                 return PCIBIOS_DEVICE_NOT_FOUND;
 122
 123         DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
 124                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 125                 where, size, value);
 126
 127         ar724x_pci_write(ar724x_pci_devcfg_base, where, size, value);
 128
 129         return PCIBIOS_SUCCESSFUL;
 130 }
 131
 132 static void ar724x_pci_fixup(struct pci_dev *dev)
 133 {
 134         u16 cmd;
 135
 136         if (!ar724x_pci_fixup_enable)
 137                 return;
 138
 139         if (dev->bus->number != 0 || dev->devfn != 0)
 140                 return;
 141
 142         /* setup COMMAND register */
 143         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 144         cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 145                PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
 146                PCI_COMMAND_FAST_BACK;
 147
 148         pci_write_config_word(dev, PCI_COMMAND, cmd);
 149 }
 150 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar724x_pci_fixup);
 151
 152 int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
 153                                   uint8_t pin)
 154 {
 155         int irq = -1;
 156         int i;
 157
 158         for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
 159                 struct ar71xx_pci_irq *entry;
 160                 entry = &ar71xx_pci_irq_map[i];
 161
 162                 if (entry->slot == slot && entry->pin == pin) {
 163                         irq = entry->irq;
 164                         break;
 165                 }
 166         }
 167
 168         if (irq < 0)
 169                 printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
 170                                 pin, pci_name((struct pci_dev *)dev));
 171         else
 172                 printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
 173                                 irq, pin, pci_name((struct pci_dev *)dev));
 174
 175         return irq;
 176 }
 177
 178 static struct pci_ops ar724x_pci_ops = {
 179         .read   = ar724x_pci_read_config,
 180         .write  = ar724x_pci_write_config,
 181 };
 182
 183 static struct resource ar724x_pci_io_resource = {
 184         .name           = "PCI IO space",
 185         .start          = 0,
 186         .end            = 0,
 187         .flags          = IORESOURCE_IO,
 188 };
 189
 190 static struct resource ar724x_pci_mem_resource = {
 191         .name           = "PCI memory space",
 192         .start          = AR71XX_PCI_MEM_BASE,
 193         .end            = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
 194         .flags          = IORESOURCE_MEM
 195 };
 196
 197 static struct pci_controller ar724x_pci_controller = {
 198         .pci_ops        = &ar724x_pci_ops,
 199         .mem_resource   = &ar724x_pci_mem_resource,
 200         .io_resource    = &ar724x_pci_io_resource,
 201 };
 202
 203 static void __init ar724x_pci_reset(void)
 204 {
 205         ar71xx_device_stop(AR724X_RESET_PCIE);
 206         ar71xx_device_stop(AR724X_RESET_PCIE_PHY);
 207         ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL);
 208         udelay(100);
 209
 210         ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL);
 211         udelay(100);
 212         ar71xx_device_start(AR724X_RESET_PCIE_PHY);
 213         ar71xx_device_start(AR724X_RESET_PCIE);
 214 }
 215
 216 static int __init ar724x_pci_setup(void)
 217 {
 218         u32 t;
 219
 220         /* setup COMMAND register */
 221         t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
 222             PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
 223
 224         ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t);
 225         ar724x_pci_write(ar724x_pci_localcfg_base, 0x20, 4, 0x1ff01000);
 226         ar724x_pci_write(ar724x_pci_localcfg_base, 0x24, 4, 0x1ff01000);
 227
 228         t = ar724x_pci_rr(AR724X_PCI_REG_RESET);
 229         if (t != 0x7) {
 230                 udelay(100000);
 231                 ar724x_pci_wr_nf(AR724X_PCI_REG_RESET, 0);
 232                 udelay(100);
 233                 ar724x_pci_wr_nf(AR724X_PCI_REG_RESET, 4);
 234                 udelay(100000);
 235         }
 236
 237         ar724x_pci_wr(AR724X_PCI_REG_APP, AR724X_PCI_APP_LTSSM_ENABLE);
 238         udelay(1000);
 239
 240         t = ar724x_pci_rr(AR724X_PCI_REG_APP);
 241         if ((t & AR724X_PCI_APP_LTSSM_ENABLE) == 0x0) {
 242                 printk(KERN_WARNING "PCI: no PCIe module found\n");
 243                 return -ENODEV;
 244         }
 245
 246         return 0;
 247 }
 248
 249 int __init ar724x_pcibios_init(void)
 250 {
 251         int ret;
 252
 253         ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE,
 254                                                    AR724X_PCI_CRP_SIZE);
 255
 256         ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE,
 257                                                  AR724X_PCI_CFG_SIZE);
 258
 259         ar724x_pci_reset();
 260         ret = ar724x_pci_setup();
 261         if (ret)
 262                 return ret;
 263
 264         ar724x_pci_fixup_enable = 1;
 265         register_pci_controller(&ar724x_pci_controller);
 266
 267         return 0;
 268 }