ath79: move dts-v1 statement to ath79.dtsi
[openwrt/staging/wigyori.git] / target / linux / ath79 / dts / qca9558_dlink_dap-2695-a1.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qca955x.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "dlink,dap-2695-a1", "qca,qca9558";
10 model = "D-link DAP-2695-A1";
11
12 aliases {
13 led-boot = &led_power_red;
14 led-failsafe = &led_power_red;
15 led-running = &led_power_green;
16 led-upgrade = &led_power_red;
17 };
18
19 leds {
20 compatible = "gpio-leds";
21
22 led_power_green: power_green {
23 label = "d-link:green:power";
24 gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
25 default-state = "on";
26 };
27
28 led_power_red: power_red {
29 label = "d-link:red:power";
30 gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
31 };
32
33 wifi2g {
34 label = "d-link:green:wifi2g";
35 gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
36 linux,default-trigger = "phy1tpt";
37 };
38 };
39
40 keys {
41 compatible = "gpio-keys";
42
43 reset {
44 label = "reset";
45 linux,code = <KEY_RESTART>;
46 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
47 };
48 };
49 };
50
51 &spi {
52 status = "okay";
53 num-cs = <1>;
54
55 flash@0 {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 compatible = "mx25l12805d";
59 reg = <0>;
60 spi-max-frequency = <25000000>;
61
62 partitions {
63 compatible = "fixed-partitions";
64 #address-cells = <1>;
65 #size-cells = <1>;
66
67 partition@0 {
68 label = "u-boot";
69 reg = <0x000000 0x040000>;
70 read-only;
71 };
72
73 partition@40000 {
74 label = "bdcfg";
75 reg = <0x040000 0x010000>;
76 read-only;
77 };
78
79 partition@50000 {
80 label = "rgdb";
81 reg = <0x050000 0x010000>;
82 read-only;
83 };
84
85 partition@60000 {
86 label = "langpack";
87 reg = <0x060000 0x010000>;
88 read-only;
89 };
90
91 partition@70000 {
92 compatible = "wrg";
93 label = "firmware";
94 reg = <0x070000 0xf00000>;
95 };
96
97 partition@f70000 {
98 label = "captival";
99 reg = <0xf70000 0x070000>;
100 read-only;
101 };
102
103 partition@fe0000 {
104 label = "certificate";
105 reg = <0xfe0000 0x010000>;
106 read-only;
107 };
108
109 art: partition@ff0000 {
110 label = "art";
111 reg = <0xff0000 0x010000>;
112 read-only;
113 };
114 };
115 };
116 };
117
118 &mdio0 {
119 status = "okay";
120
121 phy0: ethernet-phy@0 {
122 reg = <0>;
123
124 qca,ar8327-initvals = <
125 0x04 0x07600000 /* PORT0_PAD_CTRL */
126 0x0c 0x00080080 /* PORT6_PAD_CTRL */
127 0x7c 0x0000007e /* PORT0_STATUS */
128 0x94 0x0000007e /* PORT6_STATUS */
129 >;
130 };
131 };
132
133 &eth0 {
134 status = "okay";
135
136 phy-handle = <&phy0>;
137 phy-mode = "rgmii";
138 pll-data = <0x56000000 0x00000101 0x00001616>;
139
140 fixed-link {
141 speed = <1000>;
142 full-duplex;
143 };
144 };
145
146 &eth1 {
147 status = "okay";
148
149 phy-mask = <0>;
150 phy-mode = "sgmii";
151 pll-data = <0x03000101 0x00000101 0x00001616>;
152
153 fixed-link {
154 speed = <1000>;
155 full-duplex;
156 };
157 };
158
159 &pcie0 {
160 status = "okay";
161 };
162
163 &uart {
164 status = "okay";
165 };
166
167 &wmac {
168 status = "okay";
169
170 qca,no-eeprom;
171 };