ath79: add QCA956x GMAC config
[openwrt/staging/wigyori.git] / target / linux / ath79 / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_gmac.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published
6 * by the Free Software Foundation.
7 */
8
9 #include <linux/sizes.h>
10 #include <linux/of_address.h>
11 #include "ag71xx.h"
12
13 static void ag71xx_of_set(struct device_node *np, const char *prop,
14 u32 *reg, u32 shift, u32 mask)
15 {
16 u32 val;
17
18 if (of_property_read_u32(np, prop, &val))
19 return;
20
21 *reg &= ~(mask << shift);
22 *reg |= ((val & mask) << shift);
23 }
24
25 static void ag71xx_of_bit(struct device_node *np, const char *prop,
26 u32 *reg, u32 mask)
27 {
28 u32 val;
29
30 if (of_property_read_u32(np, prop, &val))
31 return;
32
33 if (val)
34 *reg |= mask;
35 else
36 *reg &= ~mask;
37 }
38
39 static void ag71xx_setup_gmac_933x(struct device_node *np, void __iomem *base)
40 {
41 u32 val = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
42
43 ag71xx_of_bit(np, "switch-phy-swap", &val, AR933X_ETH_CFG_SW_PHY_SWAP);
44 ag71xx_of_bit(np, "switch-phy-addr-swap", &val,
45 AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
46
47 __raw_writel(val, base + AR933X_GMAC_REG_ETH_CFG);
48 }
49
50 static void ag71xx_setup_gmac_934x(struct device_node *np, void __iomem *base)
51 {
52 u32 val = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
53
54 ag71xx_of_bit(np, "rgmii-gmac0", &val, AR934X_ETH_CFG_RGMII_GMAC0);
55 ag71xx_of_bit(np, "mii-gmac0", &val, AR934X_ETH_CFG_MII_GMAC0);
56 ag71xx_of_bit(np, "gmii-gmac0", &val, AR934X_ETH_CFG_GMII_GMAC0);
57 ag71xx_of_bit(np, "switch-phy-swap", &val, AR934X_ETH_CFG_SW_PHY_SWAP);
58 ag71xx_of_bit(np, "switch-only-mode", &val,
59 AR934X_ETH_CFG_SW_ONLY_MODE);
60
61 __raw_writel(val, base + AR934X_GMAC_REG_ETH_CFG);
62 }
63
64 static void ag71xx_setup_gmac_955x(struct device_node *np, void __iomem *base)
65 {
66 u32 val = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
67
68 ag71xx_of_bit(np, "rgmii-enabled", &val, QCA955X_ETH_CFG_RGMII_EN);
69 ag71xx_of_bit(np, "ge0-sgmii", &val, QCA955X_ETH_CFG_GE0_SGMII);
70 ag71xx_of_set(np, "txen-delay", &val, QCA955X_ETH_CFG_TXE_DELAY_SHIFT, 0x3);
71 ag71xx_of_set(np, "txd-delay", &val, QCA955X_ETH_CFG_TXD_DELAY_SHIFT, 0x3);
72 ag71xx_of_set(np, "rxdv-delay", &val, QCA955X_ETH_CFG_RDV_DELAY_SHIFT, 0x3);
73 ag71xx_of_set(np, "rxd-delay", &val, QCA955X_ETH_CFG_RXD_DELAY_SHIFT, 0x3);
74
75 __raw_writel(val, base + QCA955X_GMAC_REG_ETH_CFG);
76 }
77
78 static void ag71xx_setup_gmac_956x(struct device_node *np, void __iomem *base)
79 {
80 u32 val = __raw_readl(base + QCA956X_GMAC_REG_ETH_CFG);
81
82 ag71xx_of_bit(np, "switch-phy-swap", &val, QCA956X_ETH_CFG_SW_PHY_SWAP);
83 ag71xx_of_bit(np, "switch-phy-addr-swap", &val,
84 QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP);
85
86 __raw_writel(val, base + QCA956X_GMAC_REG_ETH_CFG);
87 }
88
89 int ag71xx_setup_gmac(struct device_node *np)
90 {
91 struct device_node *np_dev;
92 void __iomem *base;
93 int err = 0;
94
95 np = of_get_child_by_name(np, "gmac-config");
96 if (!np)
97 return 0;
98
99 np_dev = of_parse_phandle(np, "device", 0);
100 if (!np_dev)
101 goto out;
102
103 base = of_iomap(np_dev, 0);
104 if (!base) {
105 pr_err("%pOF: can't map GMAC registers\n", np_dev);
106 err = -ENOMEM;
107 goto err_iomap;
108 }
109
110 if (of_device_is_compatible(np_dev, "qca,ar9330-gmac"))
111 ag71xx_setup_gmac_933x(np, base);
112 else if (of_device_is_compatible(np_dev, "qca,ar9340-gmac"))
113 ag71xx_setup_gmac_934x(np, base);
114 else if (of_device_is_compatible(np_dev, "qca,qca9550-gmac"))
115 ag71xx_setup_gmac_955x(np, base);
116 else if (of_device_is_compatible(np_dev, "qca,qca9560-gmac"))
117 ag71xx_setup_gmac_956x(np, base);
118
119 iounmap(base);
120
121 err_iomap:
122 of_node_put(np_dev);
123 out:
124 of_node_put(np);
125 return err;
126 }