1 From e93fe20529aeb8738b87533f66c46e2c21524530 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Tue, 6 Mar 2018 10:06:10 +0100
4 Subject: [PATCH 09/33] MIPS: ath79: add lots of missing registers
6 This patch adds many new registers for various QCA MIPS SoCs. The patch is
7 an aggragate of many contributions made to OpenWrt.
9 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
10 Signed-off-by: Henryk Heisig <hyniu@o2.pl>
11 Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
12 Signed-off-by: Weijie Gao <hackpascal@gmail.com>
13 Signed-off-by: Felix Fietkau <nbd@nbd.name>
14 Signed-off-by: Julien Dusser <julien.dusser@free.fr>
15 Signed-off-by: John Crispin <john@phrozen.org>
17 arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 771 ++++++++++++++++++++++++-
18 1 file changed, 770 insertions(+), 1 deletion(-)
20 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
21 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
23 #include <linux/bitops.h>
25 #define AR71XX_APB_BASE 0x18000000
26 +#define AR71XX_GE0_BASE 0x19000000
27 +#define AR71XX_GE0_SIZE 0x10000
28 +#define AR71XX_GE1_BASE 0x1a000000
29 +#define AR71XX_GE1_SIZE 0x10000
30 #define AR71XX_EHCI_BASE 0x1b000000
31 #define AR71XX_EHCI_SIZE 0x1000
32 #define AR71XX_OHCI_BASE 0x1c000000
34 #define AR71XX_PLL_SIZE 0x100
35 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
36 #define AR71XX_RESET_SIZE 0x100
37 +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
38 +#define AR71XX_MII_SIZE 0x100
40 #define AR71XX_PCI_MEM_BASE 0x10000000
41 #define AR71XX_PCI_MEM_SIZE 0x07000000
44 #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
45 #define AR933X_UART_SIZE 0x14
46 +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
47 +#define AR933X_GMAC_SIZE 0x04
48 #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
49 #define AR933X_WMAC_SIZE 0x20000
50 #define AR933X_EHCI_BASE 0x1b000000
51 #define AR933X_EHCI_SIZE 0x1000
53 +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
54 +#define AR934X_GMAC_SIZE 0x14
55 #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
56 #define AR934X_WMAC_SIZE 0x20000
57 #define AR934X_EHCI_BASE 0x1b000000
58 #define AR934X_EHCI_SIZE 0x200
59 +#define AR934X_NFC_BASE 0x1b000200
60 +#define AR934X_NFC_SIZE 0xb8
61 #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
62 #define AR934X_SRIF_SIZE 0x1000
64 +#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
65 +#define QCA953X_GMAC_SIZE 0x14
66 +#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
67 +#define QCA953X_WMAC_SIZE 0x20000
68 +#define QCA953X_EHCI_BASE 0x1b000000
69 +#define QCA953X_EHCI_SIZE 0x200
70 +#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
71 +#define QCA953X_SRIF_SIZE 0x1000
73 +#define QCA953X_PCI_CFG_BASE0 0x14000000
74 +#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
75 +#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
76 +#define QCA953X_PCI_MEM_BASE0 0x10000000
77 +#define QCA953X_PCI_MEM_SIZE 0x02000000
79 #define QCA955X_PCI_MEM_BASE0 0x10000000
80 #define QCA955X_PCI_MEM_BASE1 0x12000000
81 #define QCA955X_PCI_MEM_SIZE 0x02000000
83 #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
84 #define QCA955X_PCI_CTRL_SIZE 0x100
86 +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
87 +#define QCA955X_GMAC_SIZE 0x40
88 #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
89 #define QCA955X_WMAC_SIZE 0x20000
90 #define QCA955X_EHCI0_BASE 0x1b000000
91 #define QCA955X_EHCI1_BASE 0x1b400000
92 #define QCA955X_EHCI_SIZE 0x1000
93 +#define QCA955X_NFC_BASE 0x1b800200
94 +#define QCA955X_NFC_SIZE 0xb8
96 +#define QCA956X_PCI_MEM_BASE1 0x12000000
97 +#define QCA956X_PCI_MEM_SIZE 0x02000000
98 +#define QCA956X_PCI_CFG_BASE1 0x16000000
99 +#define QCA956X_PCI_CFG_SIZE 0x1000
100 +#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
101 +#define QCA956X_PCI_CRP_SIZE 0x1000
102 +#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
103 +#define QCA956X_PCI_CTRL_SIZE 0x100
105 +#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
106 +#define QCA956X_WMAC_SIZE 0x20000
107 +#define QCA956X_EHCI0_BASE 0x1b000000
108 +#define QCA956X_EHCI1_BASE 0x1b400000
109 +#define QCA956X_EHCI_SIZE 0x200
110 +#define QCA956X_GMAC_SGMII_BASE (AR71XX_APB_BASE + 0x00070000)
111 +#define QCA956X_GMAC_SGMII_SIZE 0x64
112 +#define QCA956X_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
113 +#define QCA956X_PLL_SIZE 0x50
114 +#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
115 +#define QCA956X_GMAC_SIZE 0x64
120 +#define QCA956X_MAC_CFG_BASE 0xb9000000
121 +#define QCA956X_MAC_CFG_SIZE 0x64
123 +#define QCA956X_MAC_CFG1_REG 0x00
124 +#define QCA956X_MAC_CFG1_SOFT_RST BIT(31)
125 +#define QCA956X_MAC_CFG1_RX_RST BIT(19)
126 +#define QCA956X_MAC_CFG1_TX_RST BIT(18)
127 +#define QCA956X_MAC_CFG1_LOOPBACK BIT(8)
128 +#define QCA956X_MAC_CFG1_RX_EN BIT(2)
129 +#define QCA956X_MAC_CFG1_TX_EN BIT(0)
131 +#define QCA956X_MAC_CFG2_REG 0x04
132 +#define QCA956X_MAC_CFG2_IF_1000 BIT(9)
133 +#define QCA956X_MAC_CFG2_IF_10_100 BIT(8)
134 +#define QCA956X_MAC_CFG2_HUGE_FRAME_EN BIT(5)
135 +#define QCA956X_MAC_CFG2_LEN_CHECK BIT(4)
136 +#define QCA956X_MAC_CFG2_PAD_CRC_EN BIT(2)
137 +#define QCA956X_MAC_CFG2_FDX BIT(0)
139 +#define QCA956X_MAC_MII_MGMT_CFG_REG 0x20
140 +#define QCA956X_MGMT_CFG_CLK_DIV_20 0x07
142 +#define QCA956X_MAC_FIFO_CFG0_REG 0x48
143 +#define QCA956X_MAC_FIFO_CFG1_REG 0x4c
144 +#define QCA956X_MAC_FIFO_CFG2_REG 0x50
145 +#define QCA956X_MAC_FIFO_CFG3_REG 0x54
146 +#define QCA956X_MAC_FIFO_CFG4_REG 0x58
147 +#define QCA956X_MAC_FIFO_CFG5_REG 0x5c
149 +#define QCA956X_DAM_RESET_OFFSET 0xb90001bc
150 +#define QCA956X_DAM_RESET_SIZE 0x4
151 +#define QCA956X_INLINE_CHKSUM_ENG BIT(27)
156 #define AR934X_DDR_REG_FLUSH_PCIE 0xa8
157 #define AR934X_DDR_REG_FLUSH_WMAC 0xac
159 +#define QCA953X_DDR_REG_FLUSH_GE0 0x9c
160 +#define QCA953X_DDR_REG_FLUSH_GE1 0xa0
161 +#define QCA953X_DDR_REG_FLUSH_USB 0xa4
162 +#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
163 +#define QCA953X_DDR_REG_FLUSH_WMAC 0xac
169 #define AR71XX_AHB_DIV_SHIFT 20
170 #define AR71XX_AHB_DIV_MASK 0x7
172 +#define AR71XX_ETH0_PLL_SHIFT 17
173 +#define AR71XX_ETH1_PLL_SHIFT 19
175 #define AR724X_PLL_REG_CPU_CONFIG 0x00
176 #define AR724X_PLL_REG_PCIE_CONFIG 0x10
178 +#define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS BIT(16)
179 +#define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET BIT(25)
181 #define AR724X_PLL_FB_SHIFT 0
182 #define AR724X_PLL_FB_MASK 0x3ff
183 #define AR724X_PLL_REF_DIV_SHIFT 10
185 #define AR724X_DDR_DIV_SHIFT 22
186 #define AR724X_DDR_DIV_MASK 0x3
188 +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
190 #define AR913X_PLL_REG_CPU_CONFIG 0x00
191 #define AR913X_PLL_REG_ETH_CONFIG 0x04
192 #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
194 #define AR913X_AHB_DIV_SHIFT 19
195 #define AR913X_AHB_DIV_MASK 0x1
197 +#define AR913X_ETH0_PLL_SHIFT 20
198 +#define AR913X_ETH1_PLL_SHIFT 22
200 #define AR933X_PLL_CPU_CONFIG_REG 0x00
201 #define AR933X_PLL_CLOCK_CTRL_REG 0x08
204 #define AR934X_PLL_CPU_CONFIG_REG 0x00
205 #define AR934X_PLL_DDR_CONFIG_REG 0x04
206 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
207 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
208 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
210 #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
211 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
213 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
214 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
216 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
218 +#define QCA953X_PLL_CPU_CONFIG_REG 0x00
219 +#define QCA953X_PLL_DDR_CONFIG_REG 0x04
220 +#define QCA953X_PLL_CLK_CTRL_REG 0x08
221 +#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
222 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
223 +#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48
225 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
226 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
227 +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
228 +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
229 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
230 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
231 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
232 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
234 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
235 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
236 +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
237 +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
238 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
239 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
240 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
241 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
243 +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
244 +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
245 +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
246 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
247 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
248 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
249 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
250 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
251 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
252 +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
253 +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
254 +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
256 #define QCA955X_PLL_CPU_CONFIG_REG 0x00
257 #define QCA955X_PLL_DDR_CONFIG_REG 0x04
258 #define QCA955X_PLL_CLK_CTRL_REG 0x08
259 +#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
260 +#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
261 +#define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c
263 #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
264 #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
266 #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
267 #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
269 +#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2)
270 +#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1)
271 +#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0)
273 +#define QCA956X_PLL_CPU_CONFIG_REG 0x00
274 +#define QCA956X_PLL_CPU_CONFIG1_REG 0x04
275 +#define QCA956X_PLL_DDR_CONFIG_REG 0x08
276 +#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
277 +#define QCA956X_PLL_CLK_CTRL_REG 0x10
278 +#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG 0x28
279 +#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30
280 +#define QCA956X_PLL_ETH_SGMII_SERDES_REG 0x4c
282 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
283 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
284 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
285 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
287 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
288 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
289 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
290 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff
291 +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
292 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
294 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
295 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
296 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
297 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
299 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
300 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
301 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
302 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff
303 +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
304 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
306 +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
307 +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
308 +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
309 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
310 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
311 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
312 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
313 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
314 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
315 +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20)
316 +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
317 +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
319 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB BIT(5)
320 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1 BIT(6)
321 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL BIT(7)
322 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SHIFT 8
323 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0xf
324 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EN_PLL_TOP BIT(12)
325 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2 BIT(13)
326 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1 BIT(14)
327 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2 BIT(15)
328 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE BIT(16)
329 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EEE_ENABLE BIT(17)
330 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL BIT(18)
331 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCHCLK_SEL BIT(19)
333 +#define QCA956X_PLL_ETH_XMII_TX_INVERT BIT(1)
334 +#define QCA956X_PLL_ETH_XMII_GIGE BIT(25)
335 +#define QCA956X_PLL_ETH_XMII_RX_DELAY_SHIFT 28
336 +#define QCA956X_PLL_ETH_XMII_RX_DELAY_MASK 0x3
337 +#define QCA956X_PLL_ETH_XMII_TX_DELAY_SHIFT 26
338 +#define QCA956X_PLL_ETH_XMII_TX_DELAY_MASK 3
340 +#define QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2)
341 +#define QCA956X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1)
342 +#define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0)
347 @@ -317,10 +542,19 @@
348 #define AR934X_RESET_REG_BOOTSTRAP 0xb0
349 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
351 +#define QCA953X_RESET_REG_RESET_MODULE 0x1c
352 +#define QCA953X_RESET_REG_BOOTSTRAP 0xb0
353 +#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
355 #define QCA955X_RESET_REG_RESET_MODULE 0x1c
356 #define QCA955X_RESET_REG_BOOTSTRAP 0xb0
357 #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
359 +#define QCA956X_RESET_REG_RESET_MODULE 0x1c
360 +#define QCA956X_RESET_REG_BOOTSTRAP 0xb0
361 +#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac
363 +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
364 #define MISC_INT_ETHSW BIT(12)
365 #define MISC_INT_TIMER4 BIT(10)
366 #define MISC_INT_TIMER3 BIT(9)
367 @@ -370,16 +604,123 @@
368 #define AR913X_RESET_USB_HOST BIT(5)
369 #define AR913X_RESET_USB_PHY BIT(4)
371 +#define AR933X_RESET_GE1_MDIO BIT(23)
372 +#define AR933X_RESET_GE0_MDIO BIT(22)
373 +#define AR933X_RESET_GE1_MAC BIT(13)
374 #define AR933X_RESET_WMAC BIT(11)
375 +#define AR933X_RESET_GE0_MAC BIT(9)
376 #define AR933X_RESET_USB_HOST BIT(5)
377 #define AR933X_RESET_USB_PHY BIT(4)
378 #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
380 +#define AR934X_RESET_HOST BIT(31)
381 +#define AR934X_RESET_SLIC BIT(30)
382 +#define AR934X_RESET_HDMA BIT(29)
383 +#define AR934X_RESET_EXTERNAL BIT(28)
384 +#define AR934X_RESET_RTC BIT(27)
385 +#define AR934X_RESET_PCIE_EP_INT BIT(26)
386 +#define AR934X_RESET_CHKSUM_ACC BIT(25)
387 +#define AR934X_RESET_FULL_CHIP BIT(24)
388 +#define AR934X_RESET_GE1_MDIO BIT(23)
389 +#define AR934X_RESET_GE0_MDIO BIT(22)
390 +#define AR934X_RESET_CPU_NMI BIT(21)
391 +#define AR934X_RESET_CPU_COLD BIT(20)
392 +#define AR934X_RESET_HOST_RESET_INT BIT(19)
393 +#define AR934X_RESET_PCIE_EP BIT(18)
394 +#define AR934X_RESET_UART1 BIT(17)
395 +#define AR934X_RESET_DDR BIT(16)
396 +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
397 +#define AR934X_RESET_NANDF BIT(14)
398 +#define AR934X_RESET_GE1_MAC BIT(13)
399 +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
400 #define AR934X_RESET_USB_PHY_ANALOG BIT(11)
401 +#define AR934X_RESET_HOST_DMA_INT BIT(10)
402 +#define AR934X_RESET_GE0_MAC BIT(9)
403 +#define AR934X_RESET_ETH_SWITCH BIT(8)
404 +#define AR934X_RESET_PCIE_PHY BIT(7)
405 +#define AR934X_RESET_PCIE BIT(6)
406 #define AR934X_RESET_USB_HOST BIT(5)
407 #define AR934X_RESET_USB_PHY BIT(4)
408 #define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
409 +#define AR934X_RESET_LUT BIT(2)
410 +#define AR934X_RESET_MBOX BIT(1)
411 +#define AR934X_RESET_I2S BIT(0)
413 +#define QCA953X_RESET_USB_EXT_PWR BIT(29)
414 +#define QCA953X_RESET_EXTERNAL BIT(28)
415 +#define QCA953X_RESET_RTC BIT(27)
416 +#define QCA953X_RESET_FULL_CHIP BIT(24)
417 +#define QCA953X_RESET_GE1_MDIO BIT(23)
418 +#define QCA953X_RESET_GE0_MDIO BIT(22)
419 +#define QCA953X_RESET_CPU_NMI BIT(21)
420 +#define QCA953X_RESET_CPU_COLD BIT(20)
421 +#define QCA953X_RESET_DDR BIT(16)
422 +#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
423 +#define QCA953X_RESET_GE1_MAC BIT(13)
424 +#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
425 +#define QCA953X_RESET_USB_PHY_ANALOG BIT(11)
426 +#define QCA953X_RESET_GE0_MAC BIT(9)
427 +#define QCA953X_RESET_ETH_SWITCH BIT(8)
428 +#define QCA953X_RESET_PCIE_PHY BIT(7)
429 +#define QCA953X_RESET_PCIE BIT(6)
430 +#define QCA953X_RESET_USB_HOST BIT(5)
431 +#define QCA953X_RESET_USB_PHY BIT(4)
432 +#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
434 +#define QCA955X_RESET_HOST BIT(31)
435 +#define QCA955X_RESET_SLIC BIT(30)
436 +#define QCA955X_RESET_HDMA BIT(29)
437 +#define QCA955X_RESET_EXTERNAL BIT(28)
438 +#define QCA955X_RESET_RTC BIT(27)
439 +#define QCA955X_RESET_PCIE_EP_INT BIT(26)
440 +#define QCA955X_RESET_CHKSUM_ACC BIT(25)
441 +#define QCA955X_RESET_FULL_CHIP BIT(24)
442 +#define QCA955X_RESET_GE1_MDIO BIT(23)
443 +#define QCA955X_RESET_GE0_MDIO BIT(22)
444 +#define QCA955X_RESET_CPU_NMI BIT(21)
445 +#define QCA955X_RESET_CPU_COLD BIT(20)
446 +#define QCA955X_RESET_HOST_RESET_INT BIT(19)
447 +#define QCA955X_RESET_PCIE_EP BIT(18)
448 +#define QCA955X_RESET_UART1 BIT(17)
449 +#define QCA955X_RESET_DDR BIT(16)
450 +#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
451 +#define QCA955X_RESET_NANDF BIT(14)
452 +#define QCA955X_RESET_GE1_MAC BIT(13)
453 +#define QCA955X_RESET_SGMII_ANALOG BIT(12)
454 +#define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
455 +#define QCA955X_RESET_HOST_DMA_INT BIT(10)
456 +#define QCA955X_RESET_GE0_MAC BIT(9)
457 +#define QCA955X_RESET_SGMII BIT(8)
458 +#define QCA955X_RESET_PCIE_PHY BIT(7)
459 +#define QCA955X_RESET_PCIE BIT(6)
460 +#define QCA955X_RESET_USB_HOST BIT(5)
461 +#define QCA955X_RESET_USB_PHY BIT(4)
462 +#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
463 +#define QCA955X_RESET_LUT BIT(2)
464 +#define QCA955X_RESET_MBOX BIT(1)
465 +#define QCA955X_RESET_I2S BIT(0)
467 +#define QCA956X_RESET_EXTERNAL BIT(28)
468 +#define QCA956X_RESET_FULL_CHIP BIT(24)
469 +#define QCA956X_RESET_GE1_MDIO BIT(23)
470 +#define QCA956X_RESET_GE0_MDIO BIT(22)
471 +#define QCA956X_RESET_CPU_NMI BIT(21)
472 +#define QCA956X_RESET_CPU_COLD BIT(20)
473 +#define QCA956X_RESET_DMA BIT(19)
474 +#define QCA956X_RESET_DDR BIT(16)
475 +#define QCA956X_RESET_GE1_MAC BIT(13)
476 +#define QCA956X_RESET_SGMII_ANALOG BIT(12)
477 +#define QCA956X_RESET_USB_PHY_ANALOG BIT(11)
478 +#define QCA956X_RESET_GE0_MAC BIT(9)
479 +#define QCA956X_RESET_SGMII BIT(8)
480 +#define QCA956X_RESET_USB_HOST BIT(5)
481 +#define QCA956X_RESET_USB_PHY BIT(4)
482 +#define QCA956X_RESET_USBSUS_OVERRIDE BIT(3)
483 +#define QCA956X_RESET_SWITCH_ANALOG BIT(2)
484 +#define QCA956X_RESET_SWITCH BIT(0)
486 +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
487 +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
488 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
490 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
492 #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
493 #define AR934X_BOOTSTRAP_DDR1 BIT(0)
495 +#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
496 +#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
497 +#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
498 +#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
499 +#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
500 +#define QCA953X_BOOTSTRAP_DDR1 BIT(0)
502 #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
504 +#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)
506 #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
507 #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
508 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
510 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
511 AR934X_PCIE_WMAC_INT_PCIE_RC3)
513 +#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
514 +#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1)
515 +#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
516 +#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
517 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4)
518 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
519 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
520 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
521 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
522 +#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
523 + (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
524 + QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
526 +#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
527 + (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
528 + QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
529 + QCA953X_PCIE_WMAC_INT_PCIE_RC3)
531 #define QCA955X_EXT_INT_WMAC_MISC BIT(0)
532 #define QCA955X_EXT_INT_WMAC_TX BIT(1)
533 #define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
535 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
536 QCA955X_EXT_INT_PCIE_RC2_INT3)
538 +#define QCA956X_EXT_INT_WMAC_MISC BIT(0)
539 +#define QCA956X_EXT_INT_WMAC_TX BIT(1)
540 +#define QCA956X_EXT_INT_WMAC_RXLP BIT(2)
541 +#define QCA956X_EXT_INT_WMAC_RXHP BIT(3)
542 +#define QCA956X_EXT_INT_PCIE_RC1 BIT(4)
543 +#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5)
544 +#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6)
545 +#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7)
546 +#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8)
547 +#define QCA956X_EXT_INT_PCIE_RC2 BIT(12)
548 +#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13)
549 +#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14)
550 +#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15)
551 +#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16)
552 +#define QCA956X_EXT_INT_USB1 BIT(24)
553 +#define QCA956X_EXT_INT_USB2 BIT(28)
555 +#define QCA956X_EXT_INT_WMAC_ALL \
556 + (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
557 + QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
559 +#define QCA956X_EXT_INT_PCIE_RC1_ALL \
560 + (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
561 + QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
562 + QCA956X_EXT_INT_PCIE_RC1_INT3)
564 +#define QCA956X_EXT_INT_PCIE_RC2_ALL \
565 + (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
566 + QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
567 + QCA956X_EXT_INT_PCIE_RC2_INT3)
569 #define REV_ID_MAJOR_MASK 0xfff0
570 #define REV_ID_MAJOR_AR71XX 0x00a0
571 #define REV_ID_MAJOR_AR913X 0x00b0
573 #define REV_ID_MAJOR_AR9341 0x0120
574 #define REV_ID_MAJOR_AR9342 0x1120
575 #define REV_ID_MAJOR_AR9344 0x2120
576 +#define REV_ID_MAJOR_QCA9533 0x0140
577 +#define REV_ID_MAJOR_QCA9533_V2 0x0160
578 #define REV_ID_MAJOR_QCA9556 0x0130
579 #define REV_ID_MAJOR_QCA9558 0x1130
580 +#define REV_ID_MAJOR_TP9343 0x0150
581 +#define REV_ID_MAJOR_QCA956X 0x1150
583 #define AR71XX_REV_ID_MINOR_MASK 0x3
584 #define AR71XX_REV_ID_MINOR_AR7130 0x0
587 #define AR934X_REV_ID_REVISION_MASK 0xf
589 +#define QCA953X_REV_ID_REVISION_MASK 0xf
591 #define QCA955X_REV_ID_REVISION_MASK 0xf
593 +#define QCA956X_REV_ID_REVISION_MASK 0xf
598 @@ -521,15 +928,63 @@
599 #define AR71XX_GPIO_REG_INT_ENABLE 0x24
600 #define AR71XX_GPIO_REG_FUNC 0x28
602 +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
603 +#define AR934X_GPIO_REG_OUT_FUNC1 0x30
604 +#define AR934X_GPIO_REG_OUT_FUNC2 0x34
605 +#define AR934X_GPIO_REG_OUT_FUNC3 0x38
606 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
607 +#define AR934X_GPIO_REG_OUT_FUNC5 0x40
608 #define AR934X_GPIO_REG_FUNC 0x6c
610 +#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c
611 +#define QCA953X_GPIO_REG_OUT_FUNC1 0x30
612 +#define QCA953X_GPIO_REG_OUT_FUNC2 0x34
613 +#define QCA953X_GPIO_REG_OUT_FUNC3 0x38
614 +#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c
615 +#define QCA953X_GPIO_REG_IN_ENABLE0 0x44
616 +#define QCA953X_GPIO_REG_FUNC 0x6c
618 +#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10
619 +#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11
620 +#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9
621 +#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8
622 +#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12
623 +#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41
624 +#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42
625 +#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43
626 +#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
627 +#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
629 +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
630 +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
631 +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
632 +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
633 +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
634 +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
635 +#define QCA955X_GPIO_REG_FUNC 0x6c
637 +#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
638 +#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
639 +#define QCA956X_GPIO_REG_OUT_FUNC2 0x34
640 +#define QCA956X_GPIO_REG_OUT_FUNC3 0x38
641 +#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c
642 +#define QCA956X_GPIO_REG_OUT_FUNC5 0x40
643 +#define QCA956X_GPIO_REG_IN_ENABLE0 0x44
644 +#define QCA956X_GPIO_REG_IN_ENABLE3 0x50
645 +#define QCA956X_GPIO_REG_FUNC 0x6c
647 +#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32
648 +#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33
650 #define AR71XX_GPIO_COUNT 16
651 #define AR7240_GPIO_COUNT 18
652 #define AR7241_GPIO_COUNT 20
653 #define AR913X_GPIO_COUNT 22
654 #define AR933X_GPIO_COUNT 30
655 #define AR934X_GPIO_COUNT 23
656 +#define QCA953X_GPIO_COUNT 18
657 #define QCA955X_GPIO_COUNT 24
658 +#define QCA956X_GPIO_COUNT 23
662 @@ -552,4 +1007,318 @@
663 #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
664 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
666 +#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0
667 +#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4
668 +#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8
670 +#define QCA953X_SRIF_DDR_DPLL1_REG 0x240
671 +#define QCA953X_SRIF_DDR_DPLL2_REG 0x244
672 +#define QCA953X_SRIF_DDR_DPLL3_REG 0x248
674 +#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27
675 +#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
676 +#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
677 +#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff
678 +#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
680 +#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
681 +#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13
682 +#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
684 +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
685 +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
686 +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
687 +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
688 +#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
689 +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
690 +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
692 +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
693 +#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
694 +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
695 +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
696 +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
697 +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
698 +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
699 +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
700 +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
701 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
702 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
703 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
704 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
705 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
706 +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
707 +#define AR724X_GPIO_FUNC_UART_EN BIT(1)
708 +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
710 +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
711 +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
712 +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
713 +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
714 +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
715 +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
716 +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
717 +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
718 +#define AR913X_GPIO_FUNC_UART_EN BIT(8)
719 +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
721 +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
722 +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
723 +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
724 +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
725 +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
726 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
727 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
728 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
729 +#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
730 +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
731 +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
732 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
733 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
734 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
735 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
736 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
737 +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
738 +#define AR933X_GPIO_FUNC_UART_EN BIT(1)
739 +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
741 +#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
742 +#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
743 +#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
744 +#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
745 +#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
746 +#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
747 +#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
748 +#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2)
749 +#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1)
751 +#define AR934X_GPIO_OUT_GPIO 0
752 +#define AR934X_GPIO_OUT_SPI_CS1 7
753 +#define AR934X_GPIO_OUT_LED_LINK0 41
754 +#define AR934X_GPIO_OUT_LED_LINK1 42
755 +#define AR934X_GPIO_OUT_LED_LINK2 43
756 +#define AR934X_GPIO_OUT_LED_LINK3 44
757 +#define AR934X_GPIO_OUT_LED_LINK4 45
758 +#define AR934X_GPIO_OUT_EXT_LNA0 46
759 +#define AR934X_GPIO_OUT_EXT_LNA1 47
761 +#define QCA955X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
762 +#define QCA955X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
763 +#define QCA955X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
764 +#define QCA955X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
765 +#define QCA955X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
766 +#define QCA955X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
767 +#define QCA955X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
768 +#define QCA955X_GPIO_FUNC_JTAG_DISABLE BIT(1)
770 +#define QCA955X_GPIO_OUT_GPIO 0
771 +#define QCA955X_MII_EXT_MDI 1
772 +#define QCA955X_SLIC_DATA_OUT 3
773 +#define QCA955X_SLIC_PCM_FS 4
774 +#define QCA955X_SLIC_PCM_CLK 5
775 +#define QCA955X_SPI_CLK 8
776 +#define QCA955X_SPI_CS_0 9
777 +#define QCA955X_SPI_CS_1 10
778 +#define QCA955X_SPI_CS_2 11
779 +#define QCA955X_SPI_MISO 12
780 +#define QCA955X_I2S_CLK 13
781 +#define QCA955X_I2S_WS 14
782 +#define QCA955X_I2S_SD 15
783 +#define QCA955X_I2S_MCK 16
784 +#define QCA955X_SPDIF_OUT 17
785 +#define QCA955X_UART1_TD 18
786 +#define QCA955X_UART1_RTS 19
787 +#define QCA955X_UART1_RD 20
788 +#define QCA955X_UART1_CTS 21
789 +#define QCA955X_UART0_SOUT 22
790 +#define QCA955X_SPDIF2_OUT 23
791 +#define QCA955X_LED_SGMII_SPEED0 24
792 +#define QCA955X_LED_SGMII_SPEED1 25
793 +#define QCA955X_LED_SGMII_DUPLEX 26
794 +#define QCA955X_LED_SGMII_LINK_UP 27
795 +#define QCA955X_SGMII_SPEED0_INVERT 28
796 +#define QCA955X_SGMII_SPEED1_INVERT 29
797 +#define QCA955X_SGMII_DUPLEX_INVERT 30
798 +#define QCA955X_SGMII_LINK_UP_INVERT 31
799 +#define QCA955X_GE1_MII_MDO 32
800 +#define QCA955X_GE1_MII_MDC 33
801 +#define QCA955X_SWCOM2 38
802 +#define QCA955X_SWCOM3 39
803 +#define QCA955X_MAC2_GPIO 40
804 +#define QCA955X_MAC3_GPIO 41
805 +#define QCA955X_ATT_LED 42
806 +#define QCA955X_PWR_LED 43
807 +#define QCA955X_TX_FRAME 44
808 +#define QCA955X_RX_CLEAR_EXTERNAL 45
809 +#define QCA955X_LED_NETWORK_EN 46
810 +#define QCA955X_LED_POWER_EN 47
811 +#define QCA955X_WMAC_GLUE_WOW 68
812 +#define QCA955X_RX_CLEAR_EXTENSION 70
813 +#define QCA955X_CP_NAND_CS1 73
814 +#define QCA955X_USB_SUSPEND 74
815 +#define QCA955X_ETH_TX_ERR 75
816 +#define QCA955X_DDR_DQ_OE 76
817 +#define QCA955X_CLKREQ_N_EP 77
818 +#define QCA955X_CLKREQ_N_RC 78
819 +#define QCA955X_CLK_OBS0 79
820 +#define QCA955X_CLK_OBS1 80
821 +#define QCA955X_CLK_OBS2 81
822 +#define QCA955X_CLK_OBS3 82
823 +#define QCA955X_CLK_OBS4 83
824 +#define QCA955X_CLK_OBS5 84
829 +#define AR71XX_MII_REG_MII0_CTRL 0x00
830 +#define AR71XX_MII_REG_MII1_CTRL 0x04
832 +#define AR71XX_MII_CTRL_IF_MASK 3
833 +#define AR71XX_MII_CTRL_SPEED_SHIFT 4
834 +#define AR71XX_MII_CTRL_SPEED_MASK 3
835 +#define AR71XX_MII_CTRL_SPEED_10 0
836 +#define AR71XX_MII_CTRL_SPEED_100 1
837 +#define AR71XX_MII_CTRL_SPEED_1000 2
839 +#define AR71XX_MII0_CTRL_IF_GMII 0
840 +#define AR71XX_MII0_CTRL_IF_MII 1
841 +#define AR71XX_MII0_CTRL_IF_RGMII 2
842 +#define AR71XX_MII0_CTRL_IF_RMII 3
844 +#define AR71XX_MII1_CTRL_IF_RGMII 0
845 +#define AR71XX_MII1_CTRL_IF_RMII 1
848 + * AR933X GMAC interface
850 +#define AR933X_GMAC_REG_ETH_CFG 0x00
852 +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
853 +#define AR933X_ETH_CFG_MII_GE0 BIT(1)
854 +#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
855 +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
856 +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
857 +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
858 +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
859 +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
860 +#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
861 +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
862 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
865 + * AR934X GMAC Interface
867 +#define AR934X_GMAC_REG_ETH_CFG 0x00
869 +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
870 +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
871 +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
872 +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
873 +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
874 +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
875 +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
876 +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
877 +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
878 +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
879 +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
880 +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
881 +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
882 +#define AR934X_ETH_CFG_RXD_DELAY BIT(14)
883 +#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3
884 +#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14
885 +#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
886 +#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
887 +#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
890 + * QCA953X GMAC Interface
892 +#define QCA953X_GMAC_REG_ETH_CFG 0x00
894 +#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6)
895 +#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7)
896 +#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9)
897 +#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
900 + * QCA955X GMAC Interface
903 +#define QCA955X_GMAC_REG_ETH_CFG 0x00
904 +#define QCA955X_GMAC_REG_SGMII_SERDES 0x18
906 +#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
907 +#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
908 +#define QCA955X_ETH_CFG_GMII_GE0 BIT(2)
909 +#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3)
910 +#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4)
911 +#define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5)
912 +#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
913 +#define QCA955X_ETH_CFG_RMII_GE0 BIT(10)
914 +#define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11)
915 +#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12)
916 +#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3
917 +#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14
918 +#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
919 +#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3
920 +#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16
921 +#define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3
922 +#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18
923 +#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
924 +#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
926 +#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
927 +#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
928 +#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
930 + * QCA956X GMAC Interface
933 +#define QCA956X_GMAC_REG_ETH_CFG 0x00
934 +#define QCA956X_GMAC_REG_SGMII_RESET 0x14
935 +#define QCA956X_GMAC_REG_SGMII_SERDES 0x18
936 +#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c
937 +#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34
938 +#define QCA956X_GMAC_REG_SGMII_DEBUG 0x58
940 +#define QCA956X_ETH_CFG_RGMII_EN BIT(0)
941 +#define QCA956X_ETH_CFG_GE0_SGMII BIT(6)
942 +#define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7)
943 +#define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8)
944 +#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9)
945 +#define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10)
946 +#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
947 +#define QCA956X_ETH_CFG_RXD_DELAY_MASK 0x3
948 +#define QCA956X_ETH_CFG_RXD_DELAY_SHIFT 14
949 +#define QCA956X_ETH_CFG_RDV_DELAY_MASK 0x3
950 +#define QCA956X_ETH_CFG_RDV_DELAY_SHIFT 16
952 +#define QCA956X_SGMII_RESET_RX_CLK_N_RESET 0x0
953 +#define QCA956X_SGMII_RESET_RX_CLK_N BIT(0)
954 +#define QCA956X_SGMII_RESET_TX_CLK_N BIT(1)
955 +#define QCA956X_SGMII_RESET_RX_125M_N BIT(2)
956 +#define QCA956X_SGMII_RESET_TX_125M_N BIT(3)
957 +#define QCA956X_SGMII_RESET_HW_RX_125M_N BIT(4)
959 +#define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3
960 +#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT 1
961 +#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7
962 +#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4
963 +#define QCA956X_SGMII_SERDES_PLL_BW BIT(8)
964 +#define QCA956X_SGMII_SERDES_VCO_FAST BIT(9)
965 +#define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10)
966 +#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
967 +#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16)
968 +#define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17)
969 +#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
970 +#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
971 +#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT 27
972 +#define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf
974 +#define QCA956X_MR_AN_CONTROL_AN_ENABLE BIT(12)
975 +#define QCA956X_MR_AN_CONTROL_PHY_RESET BIT(15)
977 +#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0
978 +#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7
980 #endif /* __ASM_MACH_AR71XX_REGS_H */
projects / openwrt / staging / wigyori.git / blob