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b224c3585b41f421a8b116a6cf6902a62a8bff06
[openwrt/staging/wigyori.git] / target / linux / atheros / patches-3.18 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -96,6 +96,19 @@ config AR7
4 Support for the Texas Instruments AR7 System-on-a-Chip
5 family: TNETD7100, 7200 and 7300.
6
7 +config ATH25
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config ATH79
21 bool "Atheros AR71XX/AR724X/AR913X based boards"
22 select ARCH_REQUIRE_GPIOLIB
23 @@ -834,6 +847,7 @@ config MIPS_PARAVIRT
24
25 endchoice
26
27 +source "arch/mips/ath25/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -2,6 +2,7 @@
34
35 platforms += alchemy
36 platforms += ar7
37 +platforms += ath25
38 platforms += ath79
39 platforms += bcm47xx
40 platforms += bcm63xx
41 --- /dev/null
42 +++ b/arch/mips/ath25/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATH25) += ath25/
48 +cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
49 +load-$(CONFIG_ATH25) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ath25/Kconfig
52 @@ -0,0 +1,9 @@
53 +config SOC_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATH25
56 + default y
57 +
58 +config SOC_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATH25
61 + default y
62 --- /dev/null
63 +++ b/arch/mips/ath25/Makefile
64 @@ -0,0 +1,13 @@
65 +#
66 +# This file is subject to the terms and conditions of the GNU General Public
67 +# License. See the file "COPYING" in the main directory of this archive
68 +# for more details.
69 +#
70 +# Copyright (C) 2006 FON Technology, SL.
71 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
72 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
73 +#
74 +
75 +obj-y += board.o prom.o devices.o
76 +obj-$(CONFIG_SOC_AR5312) += ar5312.o
77 +obj-$(CONFIG_SOC_AR2315) += ar2315.o
78 --- /dev/null
79 +++ b/arch/mips/ath25/board.c
80 @@ -0,0 +1,229 @@
81 +/*
82 + * This file is subject to the terms and conditions of the GNU General Public
83 + * License. See the file "COPYING" in the main directory of this archive
84 + * for more details.
85 + *
86 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
87 + * Copyright (C) 2006 FON Technology, SL.
88 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
89 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
90 + */
91 +
92 +#include <generated/autoconf.h>
93 +#include <linux/init.h>
94 +#include <linux/module.h>
95 +#include <linux/types.h>
96 +#include <linux/string.h>
97 +#include <linux/platform_device.h>
98 +#include <linux/kernel.h>
99 +#include <linux/random.h>
100 +#include <linux/etherdevice.h>
101 +#include <linux/irq.h>
102 +#include <linux/io.h>
103 +#include <asm/irq_cpu.h>
104 +#include <asm/reboot.h>
105 +#include <asm/bootinfo.h>
106 +#include <asm/time.h>
107 +
108 +#include <ath25_platform.h>
109 +#include "devices.h"
110 +#include "ar5312.h"
111 +#include "ar2315.h"
112 +
113 +void (*ar231x_irq_dispatch)(void);
114 +
115 +static inline bool check_radio_magic(u8 *addr)
116 +{
117 + addr += 0x7a; /* offset for flash magic */
118 + return (addr[0] == 0x5a) && (addr[1] == 0xa5);
119 +}
120 +
121 +static inline bool check_notempty(u8 *addr)
122 +{
123 + return *(u32 *)addr != 0xffffffff;
124 +}
125 +
126 +static inline bool check_board_data(u8 *flash_limit, u8 *addr, bool broken)
127 +{
128 + /* config magic found */
129 + if (*((u32 *)addr) == AR231X_BD_MAGIC)
130 + return true;
131 +
132 + if (!broken)
133 + return false;
134 +
135 + if (check_radio_magic(addr + 0xf8))
136 + ar231x_board.radio = addr + 0xf8;
137 + if ((addr < flash_limit + 0x10000) &&
138 + check_radio_magic(addr + 0x10000))
139 + ar231x_board.radio = addr + 0x10000;
140 +
141 + if (ar231x_board.radio) {
142 + /* broken board data detected, use radio data to find the
143 + * offset, user will fix this */
144 + return true;
145 + }
146 +
147 + return false;
148 +}
149 +
150 +static u8 * __init find_board_config(u8 *flash_limit, bool broken)
151 +{
152 + u8 *addr;
153 + u8 *begin = flash_limit - 0x1000;
154 + u8 *end = flash_limit - 0x30000;
155 +
156 + for (addr = begin; addr >= end; addr -= 0x1000)
157 + if (check_board_data(flash_limit, addr, broken))
158 + return addr;
159 +
160 + return NULL;
161 +}
162 +
163 +static u8 * __init find_radio_config(u8 *flash_limit, u8 *bcfg)
164 +{
165 + u8 *rcfg, *begin, *end;
166 +
167 + /*
168 + * Now find the start of Radio Configuration data, using heuristics:
169 + * Search forward from Board Configuration data by 0x1000 bytes
170 + * at a time until we find non-0xffffffff.
171 + */
172 + begin = bcfg + 0x1000;
173 + end = flash_limit;
174 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
175 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
176 + return rcfg;
177 +
178 + /* AR2316 relocates radio config to new location */
179 + begin = bcfg + 0xf8;
180 + end = flash_limit - 0x1000 + 0xf8;
181 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
182 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
183 + return rcfg;
184 +
185 + pr_warn("WARNING: Could not find Radio Configuration data\n");
186 +
187 + return NULL;
188 +}
189 +
190 +int __init ar231x_find_config(u8 *flash_limit)
191 +{
192 + struct ar231x_boarddata *config;
193 + unsigned int rcfg_size;
194 + int broken_boarddata = 0;
195 + u8 *bcfg, *rcfg;
196 + u8 *board_data;
197 + u8 *radio_data;
198 + u8 *mac_addr;
199 + u32 offset;
200 +
201 + ar231x_board.config = NULL;
202 + ar231x_board.radio = NULL;
203 + /* Copy the board and radio data to RAM, because accessing the mapped
204 + * memory of the flash directly after booting is not safe */
205 +
206 + /* Try to find valid board and radio data */
207 + bcfg = find_board_config(flash_limit, false);
208 +
209 + /* If that fails, try to at least find valid radio data */
210 + if (!bcfg) {
211 + bcfg = find_board_config(flash_limit, true);
212 + broken_boarddata = 1;
213 + }
214 +
215 + if (!bcfg) {
216 + pr_warn("WARNING: No board configuration data found!\n");
217 + return -ENODEV;
218 + }
219 +
220 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
221 + ar231x_board.config = (struct ar231x_boarddata *)board_data;
222 + memcpy(board_data, bcfg, 0x100);
223 + if (broken_boarddata) {
224 + pr_warn("WARNING: broken board data detected\n");
225 + config = ar231x_board.config;
226 + if (is_zero_ether_addr(config->enet0_mac)) {
227 + pr_info("Fixing up empty mac addresses\n");
228 + config->reset_config_gpio = 0xffff;
229 + config->sys_led_gpio = 0xffff;
230 + random_ether_addr(config->wlan0_mac);
231 + config->wlan0_mac[0] &= ~0x06;
232 + random_ether_addr(config->enet0_mac);
233 + random_ether_addr(config->enet1_mac);
234 + }
235 + }
236 +
237 + /* Radio config starts 0x100 bytes after board config, regardless
238 + * of what the physical layout on the flash chip looks like */
239 +
240 + if (ar231x_board.radio)
241 + rcfg = (u8 *)ar231x_board.radio;
242 + else
243 + rcfg = find_radio_config(flash_limit, bcfg);
244 +
245 + if (!rcfg)
246 + return -ENODEV;
247 +
248 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
249 + ar231x_board.radio = radio_data;
250 + offset = radio_data - board_data;
251 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
252 + offset);
253 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
254 + memcpy(radio_data, rcfg, rcfg_size);
255 +
256 + mac_addr = &radio_data[0x1d * 2];
257 + if (is_broadcast_ether_addr(mac_addr)) {
258 + pr_info("Radio MAC is blank; using board-data\n");
259 + ether_addr_copy(mac_addr, ar231x_board.config->wlan0_mac);
260 + }
261 +
262 + return 0;
263 +}
264 +
265 +static void ar231x_halt(void)
266 +{
267 + local_irq_disable();
268 + while (1)
269 + ;
270 +}
271 +
272 +void __init plat_mem_setup(void)
273 +{
274 + _machine_halt = ar231x_halt;
275 + pm_power_off = ar231x_halt;
276 +
277 + ar5312_plat_setup();
278 + ar2315_plat_setup();
279 +
280 + /* Disable data watchpoints */
281 + write_c0_watchlo0(0);
282 +}
283 +
284 +asmlinkage void plat_irq_dispatch(void)
285 +{
286 + ar231x_irq_dispatch();
287 +}
288 +
289 +void __init plat_time_init(void)
290 +{
291 + ar5312_time_init();
292 + ar2315_time_init();
293 +}
294 +
295 +unsigned int __cpuinit get_c0_compare_int(void)
296 +{
297 + return CP0_LEGACY_COMPARE_IRQ;
298 +}
299 +
300 +void __init arch_init_irq(void)
301 +{
302 + clear_c0_status(ST0_IM);
303 + mips_cpu_irq_init();
304 +
305 + /* Initialize interrupt controllers */
306 + ar5312_irq_init();
307 + ar2315_irq_init();
308 +}
309 +
310 --- /dev/null
311 +++ b/arch/mips/ath25/prom.c
312 @@ -0,0 +1,37 @@
313 +/*
314 + * This file is subject to the terms and conditions of the GNU General Public
315 + * License. See the file "COPYING" in the main directory of this archive
316 + * for more details.
317 + *
318 + * Copyright MontaVista Software Inc
319 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
320 + * Copyright (C) 2006 FON Technology, SL.
321 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
322 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
323 + */
324 +
325 +/*
326 + * Prom setup file for ar231x
327 + */
328 +
329 +#include <linux/init.h>
330 +#include <generated/autoconf.h>
331 +#include <linux/kernel.h>
332 +#include <linux/string.h>
333 +#include <linux/mm.h>
334 +#include <linux/bootmem.h>
335 +
336 +#include <asm/bootinfo.h>
337 +#include <asm/addrspace.h>
338 +#include "ar5312.h"
339 +#include "ar2315.h"
340 +
341 +void __init prom_init(void)
342 +{
343 + ar5312_prom_init();
344 + ar2315_prom_init();
345 +}
346 +
347 +void __init prom_free_prom_memory(void)
348 +{
349 +}
350 --- /dev/null
351 +++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
352 @@ -0,0 +1,84 @@
353 +#ifndef __ASM_MACH_ATH25_PLATFORM_H
354 +#define __ASM_MACH_ATH25_PLATFORM_H
355 +
356 +#include <linux/etherdevice.h>
357 +
358 +/*
359 + * This is board-specific data that is stored in a "fixed" location in flash.
360 + * It is shared across operating systems, so it should not be changed lightly.
361 + * The main reason we need it is in order to extract the ethernet MAC
362 + * address(es).
363 + */
364 +struct ar231x_boarddata {
365 + u32 magic; /* board data is valid */
366 +#define AR231X_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
367 + u16 cksum; /* checksum (starting with BD_REV 2) */
368 + u16 rev; /* revision of this struct */
369 +#define BD_REV 4
370 + char board_name[64]; /* Name of board */
371 + u16 major; /* Board major number */
372 + u16 minor; /* Board minor number */
373 + u32 flags; /* Board configuration */
374 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
375 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
376 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
377 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
378 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
379 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
380 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
381 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
382 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
383 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
384 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
385 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
386 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
387 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
388 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
389 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
390 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
391 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
392 + u16 reset_config_gpio; /* Reset factory GPIO pin */
393 + u16 sys_led_gpio; /* System LED GPIO pin */
394 +
395 + u32 cpu_freq; /* CPU core frequency in Hz */
396 + u32 sys_freq; /* System frequency in Hz */
397 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
398 +
399 + u8 wlan0_mac[ETH_ALEN];
400 + u8 enet0_mac[ETH_ALEN];
401 + u8 enet1_mac[ETH_ALEN];
402 +
403 + u16 pci_id; /* Pseudo PCIID for common code */
404 + u16 mem_cap; /* cap bank1 in MB */
405 +
406 + /* version 3 */
407 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
408 +};
409 +
410 +#define BOARD_CONFIG_BUFSZ 0x1000
411 +
412 +/*
413 + * Platform device information for the Wireless MAC
414 + */
415 +struct ar231x_board_config {
416 + u16 devid;
417 +
418 + /* board config data */
419 + struct ar231x_boarddata *config;
420 +
421 + /* radio calibration data */
422 + const char *radio;
423 +};
424 +
425 +/*
426 + * Platform device information for the Ethernet MAC
427 + */
428 +struct ar231x_eth {
429 + void (*reset_set)(u32);
430 + void (*reset_clear)(u32);
431 + u32 reset_mac;
432 + u32 reset_phy;
433 + char *macaddr;
434 +};
435 +
436 +#endif /* __ASM_MACH_ATH25_PLATFORM_H */
437 --- /dev/null
438 +++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
439 @@ -0,0 +1,64 @@
440 +/*
441 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
442 + *
443 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
444 + *
445 + * This file was derived from: include/asm-mips/cpu-features.h
446 + * Copyright (C) 2003, 2004 Ralf Baechle
447 + * Copyright (C) 2004 Maciej W. Rozycki
448 + *
449 + * This program is free software; you can redistribute it and/or modify it
450 + * under the terms of the GNU General Public License version 2 as published
451 + * by the Free Software Foundation.
452 + *
453 + */
454 +#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
455 +#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
456 +
457 +/*
458 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
459 + */
460 +#define cpu_has_tlb 1
461 +#define cpu_has_4kex 1
462 +#define cpu_has_3k_cache 0
463 +#define cpu_has_4k_cache 1
464 +#define cpu_has_tx39_cache 0
465 +#define cpu_has_sb1_cache 0
466 +#define cpu_has_fpu 0
467 +#define cpu_has_32fpr 0
468 +#define cpu_has_counter 1
469 +#define cpu_has_ejtag 1
470 +
471 +#if !defined(CONFIG_SOC_AR5312)
472 +# define cpu_has_llsc 1
473 +#else
474 +/*
475 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
476 + * ll/sc instructions.
477 + */
478 +# define cpu_has_llsc 0
479 +#endif
480 +
481 +#define cpu_has_mips16 0
482 +#define cpu_has_mdmx 0
483 +#define cpu_has_mips3d 0
484 +#define cpu_has_smartmips 0
485 +
486 +#define cpu_has_mips32r1 1
487 +
488 +#if !defined(CONFIG_SOC_AR5312)
489 +# define cpu_has_mips32r2 1
490 +#endif
491 +
492 +#define cpu_has_mips64r1 0
493 +#define cpu_has_mips64r2 0
494 +
495 +#define cpu_has_dsp 0
496 +#define cpu_has_mipsmt 0
497 +
498 +#define cpu_has_64bits 0
499 +#define cpu_has_64bit_zero_reg 0
500 +#define cpu_has_64bit_gp_regs 0
501 +#define cpu_has_64bit_addresses 0
502 +
503 +#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
504 --- /dev/null
505 +++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
506 @@ -0,0 +1,76 @@
507 +/*
508 + * This file is subject to the terms and conditions of the GNU General Public
509 + * License. See the file "COPYING" in the main directory of this archive
510 + * for more details.
511 + *
512 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
513 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
514 + *
515 + */
516 +#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
517 +#define __ASM_MACH_ATH25_DMA_COHERENCE_H
518 +
519 +#include <linux/device.h>
520 +#include <ar2315_regs.h>
521 +
522 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
523 +{
524 +#ifdef CONFIG_PCI
525 + extern struct bus_type pci_bus_type;
526 +
527 + if (dev && dev->bus == &pci_bus_type)
528 + return AR2315_PCI_HOST_SDRAM_BASEADDR;
529 +#endif
530 + return 0;
531 +}
532 +
533 +static inline dma_addr_t
534 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
535 +{
536 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
537 +}
538 +
539 +static inline dma_addr_t
540 +plat_map_dma_mem_page(struct device *dev, struct page *page)
541 +{
542 + return page_to_phys(page) + ar231x_dev_offset(dev);
543 +}
544 +
545 +static inline unsigned long
546 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
547 +{
548 + return dma_addr - ar231x_dev_offset(dev);
549 +}
550 +
551 +static inline void
552 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
553 + enum dma_data_direction direction)
554 +{
555 +}
556 +
557 +static inline int plat_dma_supported(struct device *dev, u64 mask)
558 +{
559 + return 1;
560 +}
561 +
562 +static inline void plat_extra_sync_for_device(struct device *dev)
563 +{
564 +}
565 +
566 +static inline int plat_dma_mapping_error(struct device *dev,
567 + dma_addr_t dma_addr)
568 +{
569 + return 0;
570 +}
571 +
572 +static inline int plat_device_is_coherent(struct device *dev)
573 +{
574 +#ifdef CONFIG_DMA_COHERENT
575 + return 1;
576 +#endif
577 +#ifdef CONFIG_DMA_NONCOHERENT
578 + return 0;
579 +#endif
580 +}
581 +
582 +#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
583 --- /dev/null
584 +++ b/arch/mips/include/asm/mach-ath25/gpio.h
585 @@ -0,0 +1,16 @@
586 +#ifndef __ASM_MACH_ATH25_GPIO_H
587 +#define __ASM_MACH_ATH25_GPIO_H
588 +
589 +#include <asm-generic/gpio.h>
590 +
591 +#define gpio_get_value __gpio_get_value
592 +#define gpio_set_value __gpio_set_value
593 +#define gpio_cansleep __gpio_cansleep
594 +#define gpio_to_irq __gpio_to_irq
595 +
596 +static inline int irq_to_gpio(unsigned irq)
597 +{
598 + return -EINVAL;
599 +}
600 +
601 +#endif /* __ASM_MACH_ATH25_GPIO_H */
602 --- /dev/null
603 +++ b/arch/mips/include/asm/mach-ath25/war.h
604 @@ -0,0 +1,25 @@
605 +/*
606 + * This file is subject to the terms and conditions of the GNU General Public
607 + * License. See the file "COPYING" in the main directory of this archive
608 + * for more details.
609 + *
610 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
611 + */
612 +#ifndef __ASM_MACH_ATH25_WAR_H
613 +#define __ASM_MACH_ATH25_WAR_H
614 +
615 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
616 +#define R4600_V1_HIT_CACHEOP_WAR 0
617 +#define R4600_V2_HIT_CACHEOP_WAR 0
618 +#define R5432_CP0_INTERRUPT_WAR 0
619 +#define BCM1250_M3_WAR 0
620 +#define SIBYTE_1956_WAR 0
621 +#define MIPS4K_ICACHE_REFILL_WAR 0
622 +#define MIPS_CACHE_SYNC_WAR 0
623 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
624 +#define RM9000_CDEX_SMP_WAR 0
625 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
626 +#define R10000_LLSC_WAR 0
627 +#define MIPS34K_MISSED_ITLB_WAR 0
628 +
629 +#endif /* __ASM_MACH_ATH25_WAR_H */
630 --- /dev/null
631 +++ b/arch/mips/include/asm/mach-ath25/ar2315_regs.h
632 @@ -0,0 +1,608 @@
633 +/*
634 + * Register definitions for AR2315+
635 + *
636 + * This file is subject to the terms and conditions of the GNU General Public
637 + * License. See the file "COPYING" in the main directory of this archive
638 + * for more details.
639 + *
640 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
641 + * Copyright (C) 2006 FON Technology, SL.
642 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
643 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
644 + */
645 +
646 +#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
647 +#define __ASM_MACH_ATH25_AR2315_REGS_H
648 +
649 +/*
650 + * IRQs
651 + */
652 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
653 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
654 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
655 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
656 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
657 +
658 +/*
659 + * Miscellaneous interrupts, which share IP2.
660 + */
661 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+0)
662 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+1)
663 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+2)
664 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+3)
665 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+4)
666 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+5)
667 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+6)
668 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
669 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+8)
670 +#define AR2315_MISC_IRQ_COUNT 9
671 +
672 +/*
673 + * PCI interrupts, which share IP5
674 + * Keep ordered according to AR2315_PCI_INT_XXX bits
675 + */
676 +#define AR2315_PCI_IRQ_BASE 0x50
677 +#define AR2315_PCI_IRQ_EXT (AR2315_PCI_IRQ_BASE+0)
678 +#define AR2315_PCI_IRQ_ABORT (AR2315_PCI_IRQ_BASE+1)
679 +#define AR2315_PCI_IRQ_COUNT 2
680 +#define AR2315_PCI_IRQ_SHIFT 25 /* in AR2315_PCI_INT_STATUS */
681 +
682 +/*
683 + * Address map
684 + */
685 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
686 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
687 +#define AR2315_PCI 0x10100000 /* PCI MMR */
688 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
689 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
690 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
691 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
692 +#define AR2315_UART0 0x11100000 /* UART MMR */
693 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
694 +#define AR2315_PCIEXT 0x80000000 /* pci external */
695 +#define AR2315_PCIEXT_SZ 0x40000000
696 +
697 +/* MII registers offset inside Ethernet MMR region */
698 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
699 +
700 +/*
701 + * Cold reset register
702 + */
703 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
704 +
705 +#define AR2315_RESET_COLD_AHB 0x00000001
706 +#define AR2315_RESET_COLD_APB 0x00000002
707 +#define AR2315_RESET_COLD_CPU 0x00000004
708 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
709 +#define AR2315_RESET_SYSTEM \
710 + (RESET_COLD_CPU |\
711 + RESET_COLD_APB |\
712 + RESET_COLD_AHB) /* full system */
713 +#define AR2317_RESET_SYSTEM 0x00000010
714 +
715 +/*
716 + * Reset register
717 + */
718 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
719 +
720 +/* warm reset WLAN0 MAC */
721 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
722 +/* warm reset WLAN0 BaseBand */
723 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
724 +/* warm reset MPEG-TS */
725 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
726 +/* warm reset PCI ahb/dma */
727 +#define AR2315_RESET_PCIDMA 0x00000008
728 +/* warm reset memory controller */
729 +#define AR2315_RESET_MEMCTL 0x00000010
730 +/* warm reset local bus */
731 +#define AR2315_RESET_LOCAL 0x00000020
732 +/* warm reset I2C bus */
733 +#define AR2315_RESET_I2C_RSVD 0x00000040
734 +/* warm reset SPI interface */
735 +#define AR2315_RESET_SPI 0x00000080
736 +/* warm reset UART0 */
737 +#define AR2315_RESET_UART0 0x00000100
738 +/* warm reset IR interface */
739 +#define AR2315_RESET_IR_RSVD 0x00000200
740 +/* cold reset ENET0 phy */
741 +#define AR2315_RESET_EPHY0 0x00000400
742 +/* cold reset ENET0 mac */
743 +#define AR2315_RESET_ENET0 0x00000800
744 +
745 +/*
746 + * AHB master arbitration control
747 + */
748 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
749 +
750 +/* CPU, default */
751 +#define AR2315_ARB_CPU 0x00000001
752 +/* WLAN */
753 +#define AR2315_ARB_WLAN 0x00000002
754 +/* MPEG-TS */
755 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
756 +/* LOCAL */
757 +#define AR2315_ARB_LOCAL 0x00000008
758 +/* PCI */
759 +#define AR2315_ARB_PCI 0x00000010
760 +/* Ethernet */
761 +#define AR2315_ARB_ETHERNET 0x00000020
762 +/* retry policy, debug only */
763 +#define AR2315_ARB_RETRY 0x00000100
764 +
765 +/*
766 + * Config Register
767 + */
768 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
769 +
770 +/* EC - AHB bridge endianess */
771 +#define AR2315_CONFIG_AHB 0x00000001
772 +/* WLAN byteswap */
773 +#define AR2315_CONFIG_WLAN 0x00000002
774 +/* MPEG-TS byteswap */
775 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
776 +/* PCI byteswap */
777 +#define AR2315_CONFIG_PCI 0x00000008
778 +/* Memory controller endianess */
779 +#define AR2315_CONFIG_MEMCTL 0x00000010
780 +/* Local bus byteswap */
781 +#define AR2315_CONFIG_LOCAL 0x00000020
782 +/* Ethernet byteswap */
783 +#define AR2315_CONFIG_ETHERNET 0x00000040
784 +
785 +/* CPU write buffer merge */
786 +#define AR2315_CONFIG_MERGE 0x00000200
787 +/* CPU big endian */
788 +#define AR2315_CONFIG_CPU 0x00000400
789 +#define AR2315_CONFIG_PCIAHB 0x00000800
790 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
791 +/* SPI byteswap */
792 +#define AR2315_CONFIG_SPI 0x00008000
793 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
794 +#define AR2315_CONFIG_CPU_PCI 0x00020000
795 +#define AR2315_CONFIG_CPU_MMR 0x00040000
796 +#define AR2315_CONFIG_BIG 0x00000400
797 +
798 +/*
799 + * NMI control
800 + */
801 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
802 +
803 +#define AR2315_NMI_EN 1
804 +
805 +/*
806 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
807 + */
808 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
809 +
810 +#define AR2315_REV_MAJ 0x00f0
811 +#define AR2315_REV_MAJ_S 4
812 +#define AR2315_REV_MIN 0x000f
813 +#define AR2315_REV_MIN_S 0
814 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
815 +
816 +/*
817 + * Interface Enable
818 + */
819 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
820 +
821 +#define AR2315_IF_MASK 0x00000007
822 +#define AR2315_IF_DISABLED 0
823 +#define AR2315_IF_PCI 1
824 +#define AR2315_IF_TS_LOCAL 2
825 +/* only for emulation with separate pins */
826 +#define AR2315_IF_ALL 3
827 +#define AR2315_IF_LOCAL_HOST 0x00000008
828 +#define AR2315_IF_PCI_HOST 0x00000010
829 +#define AR2315_IF_PCI_INTR 0x00000020
830 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
831 +#define AR2315_IF_PCI_CLK_INPUT 0
832 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
833 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
834 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
835 +#define AR2315_IF_PCI_CLK_SHIFT 16
836 +
837 +/*
838 + * APB Interrupt control
839 + */
840 +
841 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
842 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
843 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
844 +
845 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
846 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
847 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
848 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
849 +#define AR2315_ISR_APB 0x0010 /* APB error */
850 +#define AR2315_ISR_TIMER 0x0020 /* timer */
851 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
852 +#define AR2315_ISR_WD 0x0080 /* watchdog */
853 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
854 +
855 +#define AR2315_GISR_MISC 0x0001
856 +#define AR2315_GISR_WLAN0 0x0002
857 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
858 +#define AR2315_GISR_LOCALPCI 0x0008
859 +#define AR2315_GISR_WMACPOLL 0x0010
860 +#define AR2315_GISR_TIMER 0x0020
861 +#define AR2315_GISR_ETHERNET 0x0040
862 +
863 +/*
864 + * Interrupt routing from IO to the processor IP bits
865 + * Define our inter mask and level
866 + */
867 +#define AR2315_INTR_MISCIO SR_IBIT3
868 +#define AR2315_INTR_WLAN0 SR_IBIT4
869 +#define AR2315_INTR_ENET0 SR_IBIT5
870 +#define AR2315_INTR_LOCALPCI SR_IBIT6
871 +#define AR2315_INTR_WMACPOLL SR_IBIT7
872 +#define AR2315_INTR_COMPARE SR_IBIT8
873 +
874 +/*
875 + * Timers
876 + */
877 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
878 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
879 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
880 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
881 +
882 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
883 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
884 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
885 +
886 +/*
887 + * CPU Performance Counters
888 + */
889 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
890 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
891 +
892 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
893 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
894 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
895 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
896 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
897 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
898 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
899 +
900 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
901 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
902 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
903 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
904 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
905 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
906 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
907 +
908 +/*
909 + * AHB Error Reporting.
910 + */
911 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
912 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
913 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
914 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
915 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
916 +
917 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
918 + /* write 1 to clear all bits in ERR0 */
919 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
920 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
921 +
922 +#define AR2315_PROCERR_HMAST 0x0000000f
923 +#define AR2315_PROCERR_HMAST_DFLT 0
924 +#define AR2315_PROCERR_HMAST_WMAC 1
925 +#define AR2315_PROCERR_HMAST_ENET 2
926 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
927 +#define AR2315_PROCERR_HMAST_LOCAL 4
928 +#define AR2315_PROCERR_HMAST_CPU 5
929 +#define AR2315_PROCERR_HMAST_PCITGT 6
930 +
931 +#define AR2315_PROCERR_HMAST_S 0
932 +#define AR2315_PROCERR_HWRITE 0x00000010
933 +#define AR2315_PROCERR_HSIZE 0x00000060
934 +#define AR2315_PROCERR_HSIZE_S 5
935 +#define AR2315_PROCERR_HTRANS 0x00000180
936 +#define AR2315_PROCERR_HTRANS_S 7
937 +#define AR2315_PROCERR_HBURST 0x00000e00
938 +#define AR2315_PROCERR_HBURST_S 9
939 +
940 +/*
941 + * Clock Control
942 + */
943 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
944 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
945 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
946 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
947 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
948 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
949 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
950 +
951 +/* PLLc Control fields */
952 +#define PLLC_REF_DIV_M 0x00000003
953 +#define PLLC_REF_DIV_S 0
954 +#define PLLC_FDBACK_DIV_M 0x0000007C
955 +#define PLLC_FDBACK_DIV_S 2
956 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
957 +#define PLLC_ADD_FDBACK_DIV_S 7
958 +#define PLLC_CLKC_DIV_M 0x0001c000
959 +#define PLLC_CLKC_DIV_S 14
960 +#define PLLC_CLKM_DIV_M 0x00700000
961 +#define PLLC_CLKM_DIV_S 20
962 +
963 +/* CPU CLK Control fields */
964 +#define CPUCLK_CLK_SEL_M 0x00000003
965 +#define CPUCLK_CLK_SEL_S 0
966 +#define CPUCLK_CLK_DIV_M 0x0000000c
967 +#define CPUCLK_CLK_DIV_S 2
968 +
969 +/* AMBA CLK Control fields */
970 +#define AMBACLK_CLK_SEL_M 0x00000003
971 +#define AMBACLK_CLK_SEL_S 0
972 +#define AMBACLK_CLK_DIV_M 0x0000000c
973 +#define AMBACLK_CLK_DIV_S 2
974 +
975 +/* GPIO MMR base address */
976 +#define AR2315_GPIO (AR2315_DSLBASE + 0x0088)
977 +
978 +#define AR2315_RESET_GPIO 5
979 +
980 +/*
981 + * PCI Clock Control
982 + */
983 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
984 +
985 +#define AR2315_PCICLK_INPUT_M 0x3
986 +#define AR2315_PCICLK_INPUT_S 0
987 +
988 +#define AR2315_PCICLK_PLLC_CLKM 0
989 +#define AR2315_PCICLK_PLLC_CLKM1 1
990 +#define AR2315_PCICLK_PLLC_CLKC 2
991 +#define AR2315_PCICLK_REF_CLK 3
992 +
993 +#define AR2315_PCICLK_DIV_M 0xc
994 +#define AR2315_PCICLK_DIV_S 2
995 +
996 +#define AR2315_PCICLK_IN_FREQ 0
997 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
998 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
999 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1000 +
1001 +/*
1002 + * Observation Control Register
1003 + */
1004 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1005 +#define OCR_GPIO0_IRIN 0x0040
1006 +#define OCR_GPIO1_IROUT 0x0080
1007 +#define OCR_GPIO3_RXCLR 0x0200
1008 +
1009 +/*
1010 + * General Clock Control
1011 + */
1012 +
1013 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1014 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1015 +#define MISCCLK_PROCREFCLK 0x00000002
1016 +
1017 +/*
1018 + * SDRAM Controller
1019 + * - No read or write buffers are included.
1020 + */
1021 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1022 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1023 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1024 +
1025 +#define SDRAM_DATA_WIDTH_M 0x00006000
1026 +#define SDRAM_DATA_WIDTH_S 13
1027 +
1028 +#define SDRAM_COL_WIDTH_M 0x00001E00
1029 +#define SDRAM_COL_WIDTH_S 9
1030 +
1031 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1032 +#define SDRAM_ROW_WIDTH_S 5
1033 +
1034 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1035 +#define SDRAM_BANKADDR_BITS_S 3
1036 +
1037 +/*
1038 + * PCI Bus Interface Registers
1039 + */
1040 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1041 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1042 +
1043 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1044 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1045 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1046 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1047 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1048 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1049 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1050 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1051 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1052 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1053 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1054 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1055 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1056 + * disable */
1057 +
1058 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1059 +
1060 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1061 +
1062 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1063 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1064 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1065 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1066 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1067 +
1068 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1069 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1070 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1071 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1072 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1073 +
1074 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1075 +
1076 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1077 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1078 +
1079 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1080 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1081 +
1082 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1083 +
1084 +#define AR2315_PCI_ISR (AR2315_PCI + 0x0500) /* write one to clr */
1085 +#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
1086 +#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
1087 +#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
1088 +#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
1089 +#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
1090 +#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
1091 +#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
1092 +#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
1093 +#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1094 +#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
1095 +#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
1096 +#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
1097 +
1098 +#define AR2315_PCI_IMR (AR2315_PCI + 0x0504) /* mask _PCI_ISR bits */
1099 +
1100 +#define AR2315_PCI_IER (AR2315_PCI + 0x0508) /* global PCI int en */
1101 +#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
1102 +#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
1103 +
1104 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1105 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1106 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1107 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1108 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1109 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1110 +
1111 +/*
1112 + * Local Bus Interface Registers
1113 + */
1114 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1115 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1116 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1117 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1118 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1119 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1120 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1121 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1122 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1123 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1124 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1125 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1126 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1127 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1128 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1129 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1130 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1131 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1132 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1133 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1134 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1135 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1136 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1137 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1138 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1139 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1140 +
1141 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1142 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1143 +
1144 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1145 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1146 +
1147 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1148 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1149 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1150 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1151 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1152 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1153 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1154 +#define AR2315_LBM_TIMEOUT_SHFT 7
1155 +#define AR2315_LBM_PORTMUX 0x07000000
1156 +
1157 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1158 +
1159 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1160 +#define AR2315_LB_TXEN_0 0x01
1161 +#define AR2315_LB_TXEN_1 0x02
1162 +#define AR2315_LB_TXEN_2 0x04
1163 +#define AR2315_LB_TXEN_3 0x08
1164 +
1165 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1166 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1167 +
1168 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1169 +#define AR2315_LB_RXEN 0x01
1170 +
1171 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1172 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1173 +
1174 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1175 +#define AR2315_INT_TX_DESC 0x0001
1176 +#define AR2315_INT_TX_OK 0x0002
1177 +#define AR2315_INT_TX_ERR 0x0004
1178 +#define AR2315_INT_TX_EOF 0x0008
1179 +#define AR2315_INT_RX_DESC 0x0010
1180 +#define AR2315_INT_RX_OK 0x0020
1181 +#define AR2315_INT_RX_ERR 0x0040
1182 +#define AR2315_INT_RX_EOF 0x0080
1183 +#define AR2315_INT_TX_TRUNC 0x0100
1184 +#define AR2315_INT_TX_STARVE 0x0200
1185 +#define AR2315_INT_LB_TIMEOUT 0x0400
1186 +#define AR2315_INT_LB_ERR 0x0800
1187 +#define AR2315_INT_MBOX_WR 0x1000
1188 +#define AR2315_INT_MBOX_RD 0x2000
1189 +
1190 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1191 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1192 +
1193 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1194 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1195 +
1196 +/*
1197 + * IR Interface Registers
1198 + */
1199 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1200 +
1201 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1202 +
1203 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1204 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1205 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1206 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1207 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1208 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1209 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1210 +
1211 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1212 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1213 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1214 +
1215 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1216 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1217 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1218 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1219 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1220 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1221 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1222 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1223 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1224 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1225 +
1226 +/*
1227 + * We need some arbitrary non-zero value to be programmed to the BAR1 register
1228 + * of PCI host controller to enable DMA. The same value should be used as the
1229 + * offset to calculate the physical address of DMA buffer for PCI devices.
1230 + */
1231 +#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
1232 +
1233 +/* ??? access BAR */
1234 +#define AR2315_PCI_HOST_MBAR0 0x10000000
1235 +/* RAM access BAR */
1236 +#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
1237 +/* ??? access BAR */
1238 +#define AR2315_PCI_HOST_MBAR2 0x30000000
1239 +
1240 +#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
1241 --- /dev/null
1242 +++ b/arch/mips/include/asm/mach-ath25/ar5312_regs.h
1243 @@ -0,0 +1,235 @@
1244 +/*
1245 + * This file is subject to the terms and conditions of the GNU General Public
1246 + * License. See the file "COPYING" in the main directory of this archive
1247 + * for more details.
1248 + *
1249 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1250 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1251 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1252 + */
1253 +
1254 +#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
1255 +#define __ASM_MACH_ATH25_AR5312_REGS_H
1256 +
1257 +#include <asm/addrspace.h>
1258 +
1259 +/*
1260 + * IRQs
1261 + */
1262 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1263 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1264 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1265 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1266 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1267 +
1268 +/*
1269 + * Miscellaneous interrupts, which share IP6.
1270 + */
1271 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+0)
1272 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+1)
1273 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+2)
1274 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+3)
1275 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+4)
1276 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+5)
1277 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+6)
1278 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+7)
1279 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+8)
1280 +#define AR5312_MISC_IRQ_COUNT 9
1281 +
1282 +/*
1283 + * Address Map
1284 + */
1285 +#define AR5312_WLAN0 0x18000000
1286 +#define AR5312_WLAN1 0x18500000
1287 +#define AR5312_ENET0 0x18100000
1288 +#define AR5312_ENET1 0x18200000
1289 +#define AR5312_SDRAMCTL 0x18300000
1290 +#define AR5312_FLASHCTL 0x18400000
1291 +#define AR5312_APBBASE 0x1c000000
1292 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1293 +#define AR5312_FLASH 0x1e000000
1294 +
1295 +/*
1296 + * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
1297 + * should be considered available. The AR5312 supports 2 enet MACS,
1298 + * even though many reference boards only actually use 1 of them
1299 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1300 + * The AR2312 supports 1 enet MAC.
1301 + */
1302 +#define AR5312_NUM_ENET_MAC 2
1303 +
1304 +/*
1305 + * Need these defines to determine true number of ethernet MACs
1306 + */
1307 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1308 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1309 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1310 +
1311 +/* MII registers offset inside Ethernet MMR region */
1312 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1313 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1314 +
1315 +/*
1316 + * AR5312_NUM_WMAC defines the number of Wireless MACs that\
1317 + * should be considered available.
1318 + */
1319 +#define AR5312_NUM_WMAC 2
1320 +
1321 +/* Reset/Timer Block Address Map */
1322 +#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
1323 +#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
1324 +#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
1325 +#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
1326 +#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
1327 +#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
1328 +#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
1329 +#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
1330 +#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
1331 +#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
1332 +#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
1333 +#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
1334 +#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
1335 +#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
1336 +#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
1337 +
1338 +/* AR5312_WD_CTRL register bit field definitions */
1339 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1340 +#define AR5312_WD_CTRL_NMI 0x0001
1341 +#define AR5312_WD_CTRL_RESET 0x0002
1342 +
1343 +/* AR5312_ISR register bit field definitions */
1344 +#define AR5312_ISR_TIMER 0x0001
1345 +#define AR5312_ISR_AHBPROC 0x0002
1346 +#define AR5312_ISR_AHBDMA 0x0004
1347 +#define AR5312_ISR_GPIO 0x0008
1348 +#define AR5312_ISR_UART0 0x0010
1349 +#define AR5312_ISR_UART0DMA 0x0020
1350 +#define AR5312_ISR_WD 0x0040
1351 +#define AR5312_ISR_LOCAL 0x0080
1352 +
1353 +/* AR5312_RESET register bit field definitions */
1354 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1355 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1356 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1357 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1358 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1359 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1360 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1361 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1362 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1363 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1364 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1365 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1366 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1367 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1368 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1369 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1370 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1371 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1372 +
1373 +#define AR5312_RESET_WMAC0_BITS \
1374 + (AR5312_RESET_WLAN0 |\
1375 + AR5312_RESET_WARM_WLAN0_MAC |\
1376 + AR5312_RESET_WARM_WLAN0_BB)
1377 +
1378 +#define AR5312_RESET_WMAC1_BITS \
1379 + (AR5312_RESET_WLAN1 |\
1380 + AR5312_RESET_WARM_WLAN1_MAC |\
1381 + AR5312_RESET_WARM_WLAN1_BB)
1382 +
1383 +/* AR5312_CLOCKCTL1 register bit field definitions */
1384 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1385 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1386 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1387 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1388 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1389 +
1390 +/* Valid for AR5312 and AR2312 */
1391 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1392 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1393 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1394 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1395 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1396 +
1397 +/* Valid for AR2313 */
1398 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1399 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1400 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1401 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1402 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1403 +
1404 +/* AR5312_ENABLE register bit field definitions */
1405 +#define AR5312_ENABLE_WLAN0 0x0001
1406 +#define AR5312_ENABLE_ENET0 0x0002
1407 +#define AR5312_ENABLE_ENET1 0x0004
1408 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1409 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1410 +#define AR5312_ENABLE_WLAN1 \
1411 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1412 + AR5312_ENABLE_WLAN1_DMA)
1413 +
1414 +/* AR5312_REV register bit field definitions */
1415 +#define AR5312_REV_WMAC_MAJ 0xf000
1416 +#define AR5312_REV_WMAC_MAJ_S 12
1417 +#define AR5312_REV_WMAC_MIN 0x0f00
1418 +#define AR5312_REV_WMAC_MIN_S 8
1419 +#define AR5312_REV_MAJ 0x00f0
1420 +#define AR5312_REV_MAJ_S 4
1421 +#define AR5312_REV_MIN 0x000f
1422 +#define AR5312_REV_MIN_S 0
1423 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1424 +
1425 +/* Major revision numbers, bits 7..4 of Revision ID register */
1426 +#define AR5312_REV_MAJ_AR5312 0x4
1427 +#define AR5312_REV_MAJ_AR2313 0x5
1428 +
1429 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1430 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1431 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1432 +
1433 +/* AR5312_FLASHCTL register bit field definitions */
1434 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1435 +#define FLASHCTL_IDCY_S 0
1436 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1437 +#define FLASHCTL_WST1_S 5
1438 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1439 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1440 +#define FLASHCTL_WST2_S 11
1441 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1442 +#define FLASHCTL_AC_S 16
1443 +#define FLASHCTL_AC_128K 0x00000000
1444 +#define FLASHCTL_AC_256K 0x00010000
1445 +#define FLASHCTL_AC_512K 0x00020000
1446 +#define FLASHCTL_AC_1M 0x00030000
1447 +#define FLASHCTL_AC_2M 0x00040000
1448 +#define FLASHCTL_AC_4M 0x00050000
1449 +#define FLASHCTL_AC_8M 0x00060000
1450 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1451 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1452 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1453 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1454 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1455 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1456 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1457 +#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
1458 +#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
1459 +#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
1460 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1461 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1462 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1463 +
1464 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1465 +#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
1466 +#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
1467 +#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
1468 +
1469 +/* ARM SDRAM Controller -- just enough to determine memory size */
1470 +#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
1471 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1472 +#define MEM_CFG1_AC0_S 8
1473 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1474 +#define MEM_CFG1_AC1_S 12
1475 +
1476 +#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
1477 +
1478 +#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
1479 --- /dev/null
1480 +++ b/arch/mips/ath25/ar5312.c
1481 @@ -0,0 +1,474 @@
1482 +/*
1483 + * This file is subject to the terms and conditions of the GNU General Public
1484 + * License. See the file "COPYING" in the main directory of this archive
1485 + * for more details.
1486 + *
1487 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1488 + * Copyright (C) 2006 FON Technology, SL.
1489 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1490 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1491 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1492 + */
1493 +
1494 +/*
1495 + * Platform devices for Atheros SoCs
1496 + */
1497 +
1498 +#include <generated/autoconf.h>
1499 +#include <linux/init.h>
1500 +#include <linux/module.h>
1501 +#include <linux/types.h>
1502 +#include <linux/string.h>
1503 +#include <linux/mtd/physmap.h>
1504 +#include <linux/platform_device.h>
1505 +#include <linux/kernel.h>
1506 +#include <linux/reboot.h>
1507 +#include <linux/leds.h>
1508 +#include <linux/gpio.h>
1509 +#include <asm/bootinfo.h>
1510 +#include <asm/reboot.h>
1511 +#include <asm/time.h>
1512 +#include <linux/irq.h>
1513 +#include <linux/io.h>
1514 +
1515 +#include <ath25_platform.h>
1516 +#include <ar5312_regs.h>
1517 +#include <ar231x.h>
1518 +#include "devices.h"
1519 +#include "ar5312.h"
1520 +
1521 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1522 +{
1523 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
1524 + ar231x_read_reg(AR5312_IMR);
1525 +
1526 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1527 + generic_handle_irq(AR5312_MISC_IRQ_TIMER);
1528 + (void)ar231x_read_reg(AR5312_TIMER);
1529 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1530 + generic_handle_irq(AR5312_MISC_IRQ_AHB_PROC);
1531 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1532 + generic_handle_irq(AR5312_MISC_IRQ_UART0);
1533 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1534 + generic_handle_irq(AR5312_MISC_IRQ_WATCHDOG);
1535 + else
1536 + spurious_interrupt();
1537 +}
1538 +
1539 +static asmlinkage void
1540 +ar5312_irq_dispatch(void)
1541 +{
1542 + int pending = read_c0_status() & read_c0_cause();
1543 +
1544 + if (pending & CAUSEF_IP2)
1545 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1546 + else if (pending & CAUSEF_IP3)
1547 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1548 + else if (pending & CAUSEF_IP4)
1549 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1550 + else if (pending & CAUSEF_IP5)
1551 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1552 + else if (pending & CAUSEF_IP6)
1553 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1554 + else if (pending & CAUSEF_IP7)
1555 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1556 + else
1557 + spurious_interrupt();
1558 +}
1559 +
1560 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1561 +static void
1562 +ar5312_misc_irq_unmask(struct irq_data *d)
1563 +{
1564 + unsigned int imr;
1565 +
1566 + imr = ar231x_read_reg(AR5312_IMR);
1567 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
1568 + ar231x_write_reg(AR5312_IMR, imr);
1569 +}
1570 +
1571 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1572 +static void
1573 +ar5312_misc_irq_mask(struct irq_data *d)
1574 +{
1575 + unsigned int imr;
1576 +
1577 + imr = ar231x_read_reg(AR5312_IMR);
1578 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
1579 + ar231x_write_reg(AR5312_IMR, imr);
1580 + ar231x_read_reg(AR5312_IMR); /* flush write buffer */
1581 +}
1582 +
1583 +static struct irq_chip ar5312_misc_irq_chip = {
1584 + .name = "AR5312-MISC",
1585 + .irq_unmask = ar5312_misc_irq_unmask,
1586 + .irq_mask = ar5312_misc_irq_mask,
1587 +};
1588 +
1589 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1590 +{
1591 + u32 proc1 = ar231x_read_reg(AR5312_PROC1);
1592 + u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
1593 + u32 dma1 = ar231x_read_reg(AR5312_DMA1);
1594 + u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
1595 +
1596 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1597 + proc_addr, proc1, dma_addr, dma1);
1598 +
1599 + machine_restart("AHB error"); /* Catastrophic failure */
1600 + return IRQ_HANDLED;
1601 +}
1602 +
1603 +static struct irqaction ar5312_ahb_proc_interrupt = {
1604 + .handler = ar5312_ahb_proc_handler,
1605 + .name = "ar5312_ahb_proc_interrupt",
1606 +};
1607 +
1608 +void __init ar5312_irq_init(void)
1609 +{
1610 + int i;
1611 +
1612 + if (!is_5312())
1613 + return;
1614 +
1615 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1616 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1617 + int irq = AR231X_MISC_IRQ_BASE + i;
1618 +
1619 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1620 + handle_level_irq);
1621 + }
1622 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1623 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1624 +}
1625 +
1626 +static void ar5312_device_reset_set(u32 mask)
1627 +{
1628 + u32 val;
1629 +
1630 + val = ar231x_read_reg(AR5312_RESET);
1631 + ar231x_write_reg(AR5312_RESET, val | mask);
1632 +}
1633 +
1634 +static void ar5312_device_reset_clear(u32 mask)
1635 +{
1636 + u32 val;
1637 +
1638 + val = ar231x_read_reg(AR5312_RESET);
1639 + ar231x_write_reg(AR5312_RESET, val & ~mask);
1640 +}
1641 +
1642 +static struct physmap_flash_data ar5312_flash_data = {
1643 + .width = 2,
1644 +};
1645 +
1646 +static struct resource ar5312_flash_resource = {
1647 + .start = AR5312_FLASH,
1648 + .end = AR5312_FLASH + 0x800000 - 1,
1649 + .flags = IORESOURCE_MEM,
1650 +};
1651 +
1652 +static struct ar231x_eth ar5312_eth0_data = {
1653 + .reset_set = ar5312_device_reset_set,
1654 + .reset_clear = ar5312_device_reset_clear,
1655 + .reset_mac = AR5312_RESET_ENET0,
1656 + .reset_phy = AR5312_RESET_EPHY0,
1657 +};
1658 +
1659 +static struct ar231x_eth ar5312_eth1_data = {
1660 + .reset_set = ar5312_device_reset_set,
1661 + .reset_clear = ar5312_device_reset_clear,
1662 + .reset_mac = AR5312_RESET_ENET1,
1663 + .reset_phy = AR5312_RESET_EPHY1,
1664 +};
1665 +
1666 +static struct platform_device ar5312_physmap_flash = {
1667 + .name = "physmap-flash",
1668 + .id = 0,
1669 + .dev.platform_data = &ar5312_flash_data,
1670 + .resource = &ar5312_flash_resource,
1671 + .num_resources = 1,
1672 +};
1673 +
1674 +#ifdef CONFIG_LEDS_GPIO
1675 +static struct gpio_led ar5312_leds[] = {
1676 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1677 +};
1678 +
1679 +static const struct gpio_led_platform_data ar5312_led_data = {
1680 + .num_leds = ARRAY_SIZE(ar5312_leds),
1681 + .leds = (void *)ar5312_leds,
1682 +};
1683 +
1684 +static struct platform_device ar5312_gpio_leds = {
1685 + .name = "leds-gpio",
1686 + .id = -1,
1687 + .dev.platform_data = (void *)&ar5312_led_data,
1688 +};
1689 +#endif
1690 +
1691 +/*
1692 + * NB: This mapping size is larger than the actual flash size,
1693 + * but this shouldn't be a problem here, because the flash
1694 + * will simply be mapped multiple times.
1695 + */
1696 +static char __init *ar5312_flash_limit(void)
1697 +{
1698 + u32 ctl;
1699 + /*
1700 + * Configure flash bank 0.
1701 + * Assume 8M window size. Flash will be aliased if it's smaller
1702 + */
1703 + ctl = FLASHCTL_E |
1704 + FLASHCTL_AC_8M |
1705 + FLASHCTL_RBLE |
1706 + (0x01 << FLASHCTL_IDCY_S) |
1707 + (0x07 << FLASHCTL_WST1_S) |
1708 + (0x07 << FLASHCTL_WST2_S) |
1709 + (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
1710 +
1711 + ar231x_write_reg(AR5312_FLASHCTL0, ctl);
1712 +
1713 + /* Disable other flash banks */
1714 + ar231x_write_reg(AR5312_FLASHCTL1,
1715 + ar231x_read_reg(AR5312_FLASHCTL1) &
1716 + ~(FLASHCTL_E | FLASHCTL_AC));
1717 +
1718 + ar231x_write_reg(AR5312_FLASHCTL2,
1719 + ar231x_read_reg(AR5312_FLASHCTL2) &
1720 + ~(FLASHCTL_E | FLASHCTL_AC));
1721 +
1722 + return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
1723 +}
1724 +
1725 +int __init ar5312_init_devices(void)
1726 +{
1727 + struct ar231x_boarddata *config;
1728 + u32 fctl = 0;
1729 + u8 *c;
1730 +
1731 + if (!is_5312())
1732 + return 0;
1733 +
1734 + /* Locate board/radio config data */
1735 + ar231x_find_config(ar5312_flash_limit());
1736 + config = ar231x_board.config;
1737 +
1738 + /* AR2313 has CPU minor rev. 10 */
1739 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1740 + ar231x_devtype = DEV_TYPE_AR2313;
1741 +
1742 + /* AR2312 shares the same Silicon ID as AR5312 */
1743 + else if (config->flags & BD_ISCASPER)
1744 + ar231x_devtype = DEV_TYPE_AR2312;
1745 +
1746 + /* Everything else is probably AR5312 or compatible */
1747 + else
1748 + ar231x_devtype = DEV_TYPE_AR5312;
1749 +
1750 + /* fixup flash width */
1751 + fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
1752 + switch (fctl) {
1753 + case FLASHCTL_MW16:
1754 + ar5312_flash_data.width = 2;
1755 + break;
1756 + case FLASHCTL_MW8:
1757 + default:
1758 + ar5312_flash_data.width = 1;
1759 + break;
1760 + }
1761 +
1762 + platform_device_register(&ar5312_physmap_flash);
1763 +
1764 +#ifdef CONFIG_LEDS_GPIO
1765 + ar5312_leds[0].gpio = config->sys_led_gpio;
1766 + platform_device_register(&ar5312_gpio_leds);
1767 +#endif
1768 +
1769 + /* Fix up MAC addresses if necessary */
1770 + if (is_broadcast_ether_addr(config->enet0_mac))
1771 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1772 +
1773 + /* If ENET0 and ENET1 have the same mac address,
1774 + * increment the one from ENET1 */
1775 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1776 + c = config->enet1_mac + 5;
1777 + while ((c >= config->enet1_mac) && !(++(*c)))
1778 + c--;
1779 + }
1780 +
1781 + switch (ar231x_devtype) {
1782 + case DEV_TYPE_AR5312:
1783 + ar5312_eth0_data.macaddr = config->enet0_mac;
1784 + ar231x_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1785 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1786 + &ar5312_eth0_data);
1787 +
1788 + ar5312_eth1_data.macaddr = config->enet1_mac;
1789 + ar231x_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1790 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1791 + &ar5312_eth1_data);
1792 +
1793 + if (!ar231x_board.radio)
1794 + return 0;
1795 +
1796 + if (!(config->flags & BD_WLAN0))
1797 + break;
1798 +
1799 + ar231x_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1800 + break;
1801 + /*
1802 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1803 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1804 + */
1805 + case DEV_TYPE_AR2312:
1806 + case DEV_TYPE_AR2313:
1807 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1808 + ar5312_eth1_data.macaddr = config->enet0_mac;
1809 + ar231x_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1810 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1811 + &ar5312_eth1_data);
1812 +
1813 + if (!ar231x_board.radio)
1814 + return 0;
1815 + break;
1816 + default:
1817 + break;
1818 + }
1819 +
1820 + if (config->flags & BD_WLAN1)
1821 + ar231x_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1822 +
1823 + return 0;
1824 +}
1825 +
1826 +static void ar5312_restart(char *command)
1827 +{
1828 + /* reset the system */
1829 + local_irq_disable();
1830 + while (1)
1831 + ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
1832 +}
1833 +
1834 +/*
1835 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1836 + * to determine the predevisor value.
1837 + */
1838 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1839 +
1840 +static int __init
1841 +ar5312_cpu_frequency(void)
1842 +{
1843 + unsigned int scratch;
1844 + unsigned int predivide_mask, predivide_shift;
1845 + unsigned int multiplier_mask, multiplier_shift;
1846 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1847 + unsigned int doubler_mask;
1848 + u16 devid;
1849 +
1850 + /* Trust the bootrom's idea of cpu frequency. */
1851 + scratch = ar231x_read_reg(AR5312_SCRATCH);
1852 + if (scratch)
1853 + return scratch;
1854 +
1855 + devid = ar231x_read_reg(AR5312_REV);
1856 + devid &= AR5312_REV_MAJ;
1857 + devid >>= AR5312_REV_MAJ_S;
1858 + if (devid == AR5312_REV_MAJ_AR2313) {
1859 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1860 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1861 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1862 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1863 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1864 + } else { /* AR5312 and AR2312 */
1865 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1866 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1867 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1868 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1869 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1870 + }
1871 +
1872 + /*
1873 + * Clocking is derived from a fixed 40MHz input clock.
1874 + *
1875 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
1876 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
1877 + * flash, Timer, Watchdog Timer)
1878 + *
1879 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
1880 + *
1881 + * So, for example, with a PLL multiplier of 5, we have
1882 + *
1883 + * cpu_freq = 200MHz
1884 + * sys_freq = 50MHz
1885 + * cnt_freq = 100MHz
1886 + *
1887 + * We compute the CPU frequency, based on PLL settings.
1888 + */
1889 +
1890 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
1891 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
1892 + predivisor = clockctl1_predivide_table[predivide_select];
1893 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
1894 +
1895 + if (clock_ctl1 & doubler_mask)
1896 + multiplier = multiplier << 1;
1897 +
1898 + return (40000000 / predivisor) * multiplier;
1899 +}
1900 +
1901 +static inline int
1902 +ar5312_sys_frequency(void)
1903 +{
1904 + return ar5312_cpu_frequency() / 4;
1905 +}
1906 +
1907 +void __init
1908 +ar5312_time_init(void)
1909 +{
1910 + if (!is_5312())
1911 + return;
1912 +
1913 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
1914 +}
1915 +
1916 +void __init
1917 +ar5312_prom_init(void)
1918 +{
1919 + u32 memsize, memcfg, bank0AC, bank1AC;
1920 + u32 devid;
1921 +
1922 + if (!is_5312())
1923 + return;
1924 +
1925 + /* Detect memory size */
1926 + memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
1927 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
1928 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
1929 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
1930 + (bank1AC ? (1 << (bank1AC+1)) : 0);
1931 + memsize <<= 20;
1932 + add_memory_region(0, memsize, BOOT_MEM_RAM);
1933 +
1934 + devid = ar231x_read_reg(AR5312_REV);
1935 + devid >>= AR5312_REV_WMAC_MIN_S;
1936 + devid &= AR5312_REV_CHIP;
1937 + ar231x_board.devid = (u16)devid;
1938 +}
1939 +
1940 +void __init
1941 +ar5312_plat_setup(void)
1942 +{
1943 + if (!is_5312())
1944 + return;
1945 +
1946 + /* Clear any lingering AHB errors */
1947 + ar231x_read_reg(AR5312_PROCADDR);
1948 + ar231x_read_reg(AR5312_DMAADDR);
1949 + ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
1950 +
1951 + _machine_restart = ar5312_restart;
1952 + ar231x_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
1953 + ar5312_sys_frequency());
1954 +}
1955 +
1956 --- /dev/null
1957 +++ b/arch/mips/ath25/ar2315.c
1958 @@ -0,0 +1,430 @@
1959 +/*
1960 + * This file is subject to the terms and conditions of the GNU General Public
1961 + * License. See the file "COPYING" in the main directory of this archive
1962 + * for more details.
1963 + *
1964 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1965 + * Copyright (C) 2006 FON Technology, SL.
1966 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1967 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1968 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1969 + */
1970 +
1971 +/*
1972 + * Platform devices for Atheros SoCs
1973 + */
1974 +
1975 +#include <generated/autoconf.h>
1976 +#include <linux/init.h>
1977 +#include <linux/module.h>
1978 +#include <linux/types.h>
1979 +#include <linux/string.h>
1980 +#include <linux/platform_device.h>
1981 +#include <linux/kernel.h>
1982 +#include <linux/reboot.h>
1983 +#include <linux/delay.h>
1984 +#include <linux/leds.h>
1985 +#include <linux/gpio.h>
1986 +#include <asm/bootinfo.h>
1987 +#include <asm/reboot.h>
1988 +#include <asm/time.h>
1989 +#include <linux/irq.h>
1990 +#include <linux/io.h>
1991 +
1992 +#include <ath25_platform.h>
1993 +#include <ar2315_regs.h>
1994 +#include <ar231x.h>
1995 +#include "devices.h"
1996 +#include "ar2315.h"
1997 +
1998 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1999 +{
2000 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
2001 + ar231x_read_reg(AR2315_IMR);
2002 +
2003 + if (misc_intr & AR2315_ISR_SPI)
2004 + generic_handle_irq(AR2315_MISC_IRQ_SPI);
2005 + else if (misc_intr & AR2315_ISR_TIMER)
2006 + generic_handle_irq(AR2315_MISC_IRQ_TIMER);
2007 + else if (misc_intr & AR2315_ISR_AHB)
2008 + generic_handle_irq(AR2315_MISC_IRQ_AHB);
2009 + else if (misc_intr & AR2315_ISR_GPIO) {
2010 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2011 + generic_handle_irq(AR2315_MISC_IRQ_GPIO);
2012 + } else if (misc_intr & AR2315_ISR_UART0)
2013 + generic_handle_irq(AR2315_MISC_IRQ_UART0);
2014 + else if (misc_intr & AR2315_ISR_WD) {
2015 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
2016 + generic_handle_irq(AR2315_MISC_IRQ_WATCHDOG);
2017 + } else
2018 + spurious_interrupt();
2019 +}
2020 +
2021 +/*
2022 + * Called when an interrupt is received, this function
2023 + * determines exactly which interrupt it was, and it
2024 + * invokes the appropriate handler.
2025 + *
2026 + * Implicitly, we also define interrupt priority by
2027 + * choosing which to dispatch first.
2028 + */
2029 +static asmlinkage void
2030 +ar2315_irq_dispatch(void)
2031 +{
2032 + int pending = read_c0_status() & read_c0_cause();
2033 +
2034 + if (pending & CAUSEF_IP3)
2035 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2036 + else if (pending & CAUSEF_IP4)
2037 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2038 + else if (pending & CAUSEF_IP2)
2039 + do_IRQ(AR2315_IRQ_MISC_INTRS);
2040 + else if (pending & CAUSEF_IP7)
2041 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
2042 + else
2043 + spurious_interrupt();
2044 +}
2045 +
2046 +static void
2047 +ar2315_misc_irq_unmask(struct irq_data *d)
2048 +{
2049 + unsigned int imr;
2050 +
2051 + imr = ar231x_read_reg(AR2315_IMR);
2052 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
2053 + ar231x_write_reg(AR2315_IMR, imr);
2054 +}
2055 +
2056 +static void
2057 +ar2315_misc_irq_mask(struct irq_data *d)
2058 +{
2059 + unsigned int imr;
2060 +
2061 + imr = ar231x_read_reg(AR2315_IMR);
2062 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
2063 + ar231x_write_reg(AR2315_IMR, imr);
2064 +}
2065 +
2066 +static struct irq_chip ar2315_misc_irq_chip = {
2067 + .name = "AR2315-MISC",
2068 + .irq_unmask = ar2315_misc_irq_unmask,
2069 + .irq_mask = ar2315_misc_irq_mask,
2070 +};
2071 +
2072 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2073 +{
2074 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2075 + ar231x_read_reg(AR2315_AHB_ERR1);
2076 +
2077 + pr_emerg("AHB fatal error\n");
2078 + machine_restart("AHB error"); /* Catastrophic failure */
2079 +
2080 + return IRQ_HANDLED;
2081 +}
2082 +
2083 +static struct irqaction ar2315_ahb_proc_interrupt = {
2084 + .handler = ar2315_ahb_proc_handler,
2085 + .name = "ar2315_ahb_proc_interrupt",
2086 +};
2087 +
2088 +void
2089 +ar2315_irq_init(void)
2090 +{
2091 + int i;
2092 +
2093 + if (!is_2315())
2094 + return;
2095 +
2096 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2097 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
2098 + int irq = AR231X_MISC_IRQ_BASE + i;
2099 +
2100 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
2101 + handle_level_irq);
2102 + }
2103 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
2104 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
2105 +}
2106 +
2107 +static void ar2315_device_reset_set(u32 mask)
2108 +{
2109 + u32 val;
2110 +
2111 + val = ar231x_read_reg(AR2315_RESET);
2112 + ar231x_write_reg(AR2315_RESET, val | mask);
2113 +}
2114 +
2115 +static void ar2315_device_reset_clear(u32 mask)
2116 +{
2117 + u32 val;
2118 +
2119 + val = ar231x_read_reg(AR2315_RESET);
2120 + ar231x_write_reg(AR2315_RESET, val & ~mask);
2121 +}
2122 +
2123 +static struct ar231x_eth ar2315_eth_data = {
2124 + .reset_set = ar2315_device_reset_set,
2125 + .reset_clear = ar2315_device_reset_clear,
2126 + .reset_mac = AR2315_RESET_ENET0,
2127 + .reset_phy = AR2315_RESET_EPHY0,
2128 +};
2129 +
2130 +static struct resource ar2315_spiflash_res[] = {
2131 + {
2132 + .name = "spiflash_read",
2133 + .flags = IORESOURCE_MEM,
2134 + .start = AR2315_SPI_READ,
2135 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2136 + },
2137 + {
2138 + .name = "spiflash_mmr",
2139 + .flags = IORESOURCE_MEM,
2140 + .start = AR2315_SPI_MMR,
2141 + .end = AR2315_SPI_MMR + 12 - 1,
2142 + },
2143 +};
2144 +
2145 +static struct platform_device ar2315_spiflash = {
2146 + .id = 0,
2147 + .name = "ar2315-spiflash",
2148 + .resource = ar2315_spiflash_res,
2149 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2150 +};
2151 +
2152 +static struct resource ar2315_wdt_res[] = {
2153 + {
2154 + .flags = IORESOURCE_MEM,
2155 + .start = AR2315_WD,
2156 + .end = AR2315_WD + 8 - 1,
2157 + },
2158 + {
2159 + .flags = IORESOURCE_IRQ,
2160 + .start = AR2315_MISC_IRQ_WATCHDOG,
2161 + .end = AR2315_MISC_IRQ_WATCHDOG,
2162 + }
2163 +};
2164 +
2165 +static struct platform_device ar2315_wdt = {
2166 + .id = 0,
2167 + .name = "ar2315-wdt",
2168 + .resource = ar2315_wdt_res,
2169 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2170 +};
2171 +
2172 +/*
2173 + * NB: We use mapping size that is larger than the actual flash size,
2174 + * but this shouldn't be a problem here, because the flash will simply
2175 + * be mapped multiple times.
2176 + */
2177 +static u8 __init *ar2315_flash_limit(void)
2178 +{
2179 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2180 +}
2181 +
2182 +#ifdef CONFIG_LEDS_GPIO
2183 +static struct gpio_led ar2315_leds[6];
2184 +static struct gpio_led_platform_data ar2315_led_data = {
2185 + .leds = (void *)ar2315_leds,
2186 +};
2187 +
2188 +static struct platform_device ar2315_gpio_leds = {
2189 + .name = "leds-gpio",
2190 + .id = -1,
2191 + .dev = {
2192 + .platform_data = (void *)&ar2315_led_data,
2193 + }
2194 +};
2195 +
2196 +static void __init
2197 +ar2315_init_gpio_leds(void)
2198 +{
2199 + static char led_names[6][6];
2200 + int i, led = 0;
2201 +
2202 + ar2315_led_data.num_leds = 0;
2203 + for (i = 1; i < 8; i++) {
2204 + if ((i == AR2315_RESET_GPIO) ||
2205 + (i == ar231x_board.config->reset_config_gpio))
2206 + continue;
2207 +
2208 + if (i == ar231x_board.config->sys_led_gpio)
2209 + strcpy(led_names[led], "wlan");
2210 + else
2211 + sprintf(led_names[led], "gpio%d", i);
2212 +
2213 + ar2315_leds[led].name = led_names[led];
2214 + ar2315_leds[led].gpio = i;
2215 + ar2315_leds[led].active_low = 0;
2216 + led++;
2217 + }
2218 + ar2315_led_data.num_leds = led;
2219 + platform_device_register(&ar2315_gpio_leds);
2220 +}
2221 +#else
2222 +static inline void ar2315_init_gpio_leds(void)
2223 +{
2224 +}
2225 +#endif
2226 +
2227 +int __init
2228 +ar2315_init_devices(void)
2229 +{
2230 + if (!is_2315())
2231 + return 0;
2232 +
2233 + /* Find board configuration */
2234 + ar231x_find_config(ar2315_flash_limit());
2235 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2236 +
2237 + ar2315_init_gpio_leds();
2238 + platform_device_register(&ar2315_wdt);
2239 + platform_device_register(&ar2315_spiflash);
2240 + ar231x_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2241 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2242 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2243 +
2244 + return 0;
2245 +}
2246 +
2247 +static void
2248 +ar2315_restart(char *command)
2249 +{
2250 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2251 +
2252 + local_irq_disable();
2253 +
2254 + /* try reset the system via reset control */
2255 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2256 +
2257 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2258 + * a workaround. Give it some time to attempt a gpio based hardware
2259 + * reset (atheros reference design workaround) */
2260 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2261 + mdelay(100);
2262 +
2263 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2264 + * workaround. Attempt to jump to the mips reset location -
2265 + * the boot loader itself might be able to recover the system */
2266 + mips_reset_vec();
2267 +}
2268 +
2269 +/*
2270 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2271 + * to determine the predevisor value.
2272 + */
2273 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2274 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2275 +
2276 +static unsigned int __init
2277 +ar2315_sys_clk(unsigned int clock_ctl)
2278 +{
2279 + unsigned int pllc_ctrl, cpu_div;
2280 + unsigned int pllc_out, refdiv, fdiv, divby2;
2281 + unsigned int clk_div;
2282 +
2283 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2284 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2285 + refdiv = clockctl1_predivide_table[refdiv];
2286 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2287 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2288 + divby2 += 1;
2289 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2290 +
2291 + /* clkm input selected */
2292 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2293 + case 0:
2294 + case 1:
2295 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2296 + PLLC_CLKM_DIV_S];
2297 + break;
2298 + case 2:
2299 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2300 + PLLC_CLKC_DIV_S];
2301 + break;
2302 + default:
2303 + pllc_out = 40000000;
2304 + clk_div = 1;
2305 + break;
2306 + }
2307 +
2308 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2309 + cpu_div = cpu_div * 2 ?: 1;
2310 +
2311 + return pllc_out / (clk_div * cpu_div);
2312 +}
2313 +
2314 +static inline unsigned int
2315 +ar2315_cpu_frequency(void)
2316 +{
2317 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2318 +}
2319 +
2320 +static inline unsigned int
2321 +ar2315_apb_frequency(void)
2322 +{
2323 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2324 +}
2325 +
2326 +void __init
2327 +ar2315_time_init(void)
2328 +{
2329 + if (!is_2315())
2330 + return;
2331 +
2332 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2333 +}
2334 +
2335 +void __init
2336 +ar2315_prom_init(void)
2337 +{
2338 + u32 memsize, memcfg, devid;
2339 +
2340 + if (!is_2315())
2341 + return;
2342 +
2343 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2344 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2345 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2346 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2347 + memsize <<= 3;
2348 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2349 +
2350 + /* Detect the hardware based on the device ID */
2351 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2352 + switch (devid) {
2353 + case 0x91: /* Need to check */
2354 + ar231x_devtype = DEV_TYPE_AR2318;
2355 + break;
2356 + case 0x90:
2357 + ar231x_devtype = DEV_TYPE_AR2317;
2358 + break;
2359 + case 0x87:
2360 + ar231x_devtype = DEV_TYPE_AR2316;
2361 + break;
2362 + case 0x86:
2363 + default:
2364 + ar231x_devtype = DEV_TYPE_AR2315;
2365 + break;
2366 + }
2367 + ar231x_board.devid = devid;
2368 +}
2369 +
2370 +void __init
2371 +ar2315_plat_setup(void)
2372 +{
2373 + u32 config;
2374 +
2375 + if (!is_2315())
2376 + return;
2377 +
2378 + /* Clear any lingering AHB errors */
2379 + config = read_c0_config();
2380 + write_c0_config(config & ~0x3);
2381 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2382 + ar231x_read_reg(AR2315_AHB_ERR1);
2383 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2384 +
2385 + _machine_restart = ar2315_restart;
2386 + ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2387 + ar2315_apb_frequency());
2388 +}
2389 --- /dev/null
2390 +++ b/arch/mips/ath25/ar2315.h
2391 @@ -0,0 +1,37 @@
2392 +#ifndef __AR2315_H
2393 +#define __AR2315_H
2394 +
2395 +#ifdef CONFIG_SOC_AR2315
2396 +
2397 +void ar2315_irq_init(void);
2398 +int ar2315_init_devices(void);
2399 +void ar2315_prom_init(void);
2400 +void ar2315_plat_setup(void);
2401 +void ar2315_time_init(void);
2402 +
2403 +#else
2404 +
2405 +static inline void ar2315_irq_init(void)
2406 +{
2407 +}
2408 +
2409 +static inline int ar2315_init_devices(void)
2410 +{
2411 + return 0;
2412 +}
2413 +
2414 +static inline void ar2315_prom_init(void)
2415 +{
2416 +}
2417 +
2418 +static inline void ar2315_plat_setup(void)
2419 +{
2420 +}
2421 +
2422 +static inline void ar2315_time_init(void)
2423 +{
2424 +}
2425 +
2426 +#endif
2427 +
2428 +#endif
2429 --- /dev/null
2430 +++ b/arch/mips/ath25/ar5312.h
2431 @@ -0,0 +1,37 @@
2432 +#ifndef __AR5312_H
2433 +#define __AR5312_H
2434 +
2435 +#ifdef CONFIG_SOC_AR5312
2436 +
2437 +void ar5312_irq_init(void);
2438 +int ar5312_init_devices(void);
2439 +void ar5312_prom_init(void);
2440 +void ar5312_plat_setup(void);
2441 +void ar5312_time_init(void);
2442 +
2443 +#else
2444 +
2445 +static inline void ar5312_irq_init(void)
2446 +{
2447 +}
2448 +
2449 +static inline int ar5312_init_devices(void)
2450 +{
2451 + return 0;
2452 +}
2453 +
2454 +static inline void ar5312_prom_init(void)
2455 +{
2456 +}
2457 +
2458 +static inline void ar5312_plat_setup(void)
2459 +{
2460 +}
2461 +
2462 +static inline void ar5312_time_init(void)
2463 +{
2464 +}
2465 +
2466 +#endif
2467 +
2468 +#endif
2469 --- /dev/null
2470 +++ b/arch/mips/include/asm/mach-ath25/ar231x.h
2471 @@ -0,0 +1,38 @@
2472 +#ifndef __ASM_MACH_ATH25_AR231X_H
2473 +#define __ASM_MACH_ATH25_AR231X_H
2474 +
2475 +#include <linux/types.h>
2476 +#include <linux/io.h>
2477 +
2478 +#define AR231X_MISC_IRQ_BASE 0x20
2479 +#define AR231X_GPIO_IRQ_BASE 0x30
2480 +
2481 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2482 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2483 +
2484 +static inline u32
2485 +ar231x_read_reg(u32 reg)
2486 +{
2487 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2488 +}
2489 +
2490 +static inline void
2491 +ar231x_write_reg(u32 reg, u32 val)
2492 +{
2493 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2494 +}
2495 +
2496 +static inline u32
2497 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2498 +{
2499 + u32 ret;
2500 +
2501 + ret = ar231x_read_reg(reg);
2502 + ret &= ~mask;
2503 + ret |= val;
2504 + ar231x_write_reg(reg, ret);
2505 +
2506 + return ret;
2507 +}
2508 +
2509 +#endif /* __ASM_MACH_ATH25_AR231X_H */
2510 --- /dev/null
2511 +++ b/arch/mips/ath25/devices.h
2512 @@ -0,0 +1,39 @@
2513 +#ifndef __ATH25_DEVICES_H
2514 +#define __ATH25_DEVICES_H
2515 +
2516 +enum {
2517 + /* handled by ar5312.c */
2518 + DEV_TYPE_AR2312,
2519 + DEV_TYPE_AR2313,
2520 + DEV_TYPE_AR5312,
2521 +
2522 + /* handled by ar2315.c */
2523 + DEV_TYPE_AR2315,
2524 + DEV_TYPE_AR2316,
2525 + DEV_TYPE_AR2317,
2526 + DEV_TYPE_AR2318,
2527 +
2528 + DEV_TYPE_UNKNOWN
2529 +};
2530 +
2531 +extern int ar231x_devtype;
2532 +extern struct ar231x_board_config ar231x_board;
2533 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2534 +
2535 +int ar231x_find_config(u8 *flash_limit);
2536 +void ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2537 +int ar231x_add_wmac(int nr, u32 base, int irq);
2538 +int ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2539 + int irq, void *pdata);
2540 +
2541 +static inline bool is_2315(void)
2542 +{
2543 + return (current_cpu_data.cputype == CPU_4KEC);
2544 +}
2545 +
2546 +static inline bool is_5312(void)
2547 +{
2548 + return !is_2315();
2549 +}
2550 +
2551 +#endif
2552 --- /dev/null
2553 +++ b/arch/mips/ath25/devices.c
2554 @@ -0,0 +1,181 @@
2555 +#include <linux/kernel.h>
2556 +#include <linux/init.h>
2557 +#include <linux/serial.h>
2558 +#include <linux/serial_core.h>
2559 +#include <linux/serial_8250.h>
2560 +#include <linux/platform_device.h>
2561 +#include <asm/bootinfo.h>
2562 +
2563 +#include <ath25_platform.h>
2564 +#include <ar231x.h>
2565 +#include "devices.h"
2566 +#include "ar5312.h"
2567 +#include "ar2315.h"
2568 +
2569 +struct ar231x_board_config ar231x_board;
2570 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2571 +
2572 +static struct resource ar231x_eth0_res[] = {
2573 + {
2574 + .name = "eth0_membase",
2575 + .flags = IORESOURCE_MEM,
2576 + },
2577 + {
2578 + .name = "eth0_mii",
2579 + .flags = IORESOURCE_MEM,
2580 + },
2581 + {
2582 + .name = "eth0_irq",
2583 + .flags = IORESOURCE_IRQ,
2584 + }
2585 +};
2586 +
2587 +static struct resource ar231x_eth1_res[] = {
2588 + {
2589 + .name = "eth1_membase",
2590 + .flags = IORESOURCE_MEM,
2591 + },
2592 + {
2593 + .name = "eth1_mii",
2594 + .flags = IORESOURCE_MEM,
2595 + },
2596 + {
2597 + .name = "eth1_irq",
2598 + .flags = IORESOURCE_IRQ,
2599 + }
2600 +};
2601 +
2602 +static struct platform_device ar231x_eth[] = {
2603 + {
2604 + .id = 0,
2605 + .name = "ar231x-eth",
2606 + .resource = ar231x_eth0_res,
2607 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
2608 + },
2609 + {
2610 + .id = 1,
2611 + .name = "ar231x-eth",
2612 + .resource = ar231x_eth1_res,
2613 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
2614 + }
2615 +};
2616 +
2617 +static struct resource ar231x_wmac0_res[] = {
2618 + {
2619 + .name = "wmac0_membase",
2620 + .flags = IORESOURCE_MEM,
2621 + },
2622 + {
2623 + .name = "wmac0_irq",
2624 + .flags = IORESOURCE_IRQ,
2625 + }
2626 +};
2627 +
2628 +static struct resource ar231x_wmac1_res[] = {
2629 + {
2630 + .name = "wmac1_membase",
2631 + .flags = IORESOURCE_MEM,
2632 + },
2633 + {
2634 + .name = "wmac1_irq",
2635 + .flags = IORESOURCE_IRQ,
2636 + }
2637 +};
2638 +
2639 +static struct platform_device ar231x_wmac[] = {
2640 + {
2641 + .id = 0,
2642 + .name = "ar231x-wmac",
2643 + .resource = ar231x_wmac0_res,
2644 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
2645 + .dev.platform_data = &ar231x_board,
2646 + },
2647 + {
2648 + .id = 1,
2649 + .name = "ar231x-wmac",
2650 + .resource = ar231x_wmac1_res,
2651 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
2652 + .dev.platform_data = &ar231x_board,
2653 + },
2654 +};
2655 +
2656 +static const char * const devtype_strings[] = {
2657 + [DEV_TYPE_AR5312] = "Atheros AR5312",
2658 + [DEV_TYPE_AR2312] = "Atheros AR2312",
2659 + [DEV_TYPE_AR2313] = "Atheros AR2313",
2660 + [DEV_TYPE_AR2315] = "Atheros AR2315",
2661 + [DEV_TYPE_AR2316] = "Atheros AR2316",
2662 + [DEV_TYPE_AR2317] = "Atheros AR2317",
2663 + [DEV_TYPE_AR2318] = "Atheros AR2318",
2664 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
2665 +};
2666 +
2667 +const char *get_system_type(void)
2668 +{
2669 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
2670 + !devtype_strings[ar231x_devtype])
2671 + return devtype_strings[DEV_TYPE_UNKNOWN];
2672 + return devtype_strings[ar231x_devtype];
2673 +}
2674 +
2675 +int __init
2676 +ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2677 + int irq, void *pdata)
2678 +{
2679 + struct resource *res;
2680 +
2681 + ar231x_eth[nr].dev.platform_data = pdata;
2682 + res = &ar231x_eth[nr].resource[0];
2683 + res->start = base;
2684 + res->end = base + 0x2000 - 1;
2685 + res++;
2686 + res->name = mii_name;
2687 + res->start = mii_base;
2688 + res->end = mii_base + 8 - 1;
2689 + res++;
2690 + res->start = irq;
2691 + res->end = irq;
2692 + return platform_device_register(&ar231x_eth[nr]);
2693 +}
2694 +
2695 +void __init
2696 +ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2697 +{
2698 + struct uart_port s;
2699 +
2700 + memset(&s, 0, sizeof(s));
2701 +
2702 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2703 + s.iotype = UPIO_MEM32;
2704 + s.irq = irq;
2705 + s.regshift = 2;
2706 + s.mapbase = mapbase;
2707 + s.uartclk = uartclk;
2708 +
2709 + early_serial_setup(&s);
2710 +}
2711 +
2712 +int __init
2713 +ar231x_add_wmac(int nr, u32 base, int irq)
2714 +{
2715 + struct resource *res;
2716 +
2717 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
2718 + res = &ar231x_wmac[nr].resource[0];
2719 + res->start = base;
2720 + res->end = base + 0x10000 - 1;
2721 + res++;
2722 + res->start = irq;
2723 + res->end = irq;
2724 + return platform_device_register(&ar231x_wmac[nr]);
2725 +}
2726 +
2727 +static int __init ar231x_register_devices(void)
2728 +{
2729 + ar5312_init_devices();
2730 + ar2315_init_devices();
2731 +
2732 + return 0;
2733 +}
2734 +
2735 +device_initcall(ar231x_register_devices);
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