target/linux/bcm27xx/patches-5.15/950-0859-clk-bcm-rpi-Set-a-default-minimum-rate.patch

   1 From ac0b202c0bae166810c63e2ac5067b6ea3f4af43 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Mon, 17 Jan 2022 17:31:06 +0100
   4 Subject: [PATCH] clk: bcm: rpi: Set a default minimum rate
   5
   6 The M2MC clock provides the state machine clock for both HDMI
   7 controllers.
   8
   9 However, if no HDMI monitor is plugged in at boot, its clock rate will
  10 be left at 0 by the firmware and will make any register access end up in
  11 a CPU stall, even though the clock was enabled.
  12
  13 We had some code in the HDMI controller to deal with this before, but it
  14 makes more sense to have it in the clock driver. Move it there.
  15
  16 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  17 ---
  18  drivers/clk/bcm/clk-raspberrypi.c | 26 ++++++++++++++++++++++++++
  19  1 file changed, 26 insertions(+)
  20
  21 --- a/drivers/clk/bcm/clk-raspberrypi.c
  22 +++ b/drivers/clk/bcm/clk-raspberrypi.c
  23 @@ -78,6 +78,7 @@ struct raspberrypi_clk_data {
  24  struct raspberrypi_clk_variant {
  25         bool            export;
  26         char            *clkdev;
  27 +       unsigned long   min_rate;
  28  };
  29
  30  static struct raspberrypi_clk_variant
  31 @@ -91,6 +92,18 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NU
  32         },
  33         [RPI_FIRMWARE_M2MC_CLK_ID] = {
  34                 .export = true,
  35 +
  36 +               /*
  37 +                * If we boot without any cable connected to any of the
  38 +                * HDMI connector, the firmware will skip the HSM
  39 +                * initialization and leave it with a rate of 0,
  40 +                * resulting in a bus lockup when we're accessing the
  41 +                * registers even if it's enabled.
  42 +                *
  43 +                * Let's put a sensible default so that we don't end up
  44 +                * in this situation.
  45 +                */
  46 +               .min_rate = 120000000,
  47         },
  48         [RPI_FIRMWARE_V3D_CLK_ID] = {
  49                 .export = true,
  50 @@ -278,6 +291,19 @@ static struct clk_hw *raspberrypi_clk_re
  51                 }
  52         }
  53
  54 +       if (variant->min_rate) {
  55 +               unsigned long rate;
  56 +
  57 +               clk_hw_set_rate_range(&data->hw, variant->min_rate, max_rate);
  58 +
  59 +               rate = raspberrypi_fw_get_rate(&data->hw, 0);
  60 +               if (rate < variant->min_rate) {
  61 +                       ret = raspberrypi_fw_set_rate(&data->hw, variant->min_rate, 0);
  62 +                       if (ret)
  63 +                               return ERR_PTR(ret);
  64 +               }
  65 +       }
  66 +
  67         return &data->hw;
  68  }
  69