target/linux/bcm53xx/patches-3.18/812-USB-bcma-add-USB-3.0-support.patch

   1 From 78008c94c253963454a9f6d3d2e0324acef3f20a Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
   3 Date: Tue, 16 Jun 2015 17:14:26 +0200
   4 Subject: [PATCH] USB: bcma: add USB 3.0 support
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
  10 ---
  11  drivers/usb/host/bcma-hcd.c | 218 ++++++++++++++++++++++++++++++++++++++++++++
  12  1 file changed, 218 insertions(+)
  13
  14 diff --git a/drivers/usb/host/bcma-hcd.c b/drivers/usb/host/bcma-hcd.c
  15 index 0b4d0e8..71fa06d 100644
  16 --- a/drivers/usb/host/bcma-hcd.c
  17 +++ b/drivers/usb/host/bcma-hcd.c
  18 @@ -37,6 +37,7 @@ struct bcma_hcd_device {
  19         struct bcma_device *core;
  20         struct platform_device *ehci_dev;
  21         struct platform_device *ohci_dev;
  22 +       struct platform_device *xhci_dev;
  23  };
  24
  25  /* Wait for bitmask in a register to get set or cleared.
  26 @@ -343,6 +344,217 @@ err_unregister_ohci_dev:
  27         return err;
  28  }
  29
  30 +static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask,
  31 +                         u32 value, int timeout)
  32 +{
  33 +       unsigned long deadline = jiffies + timeout;
  34 +       u32 val;
  35 +
  36 +       do {
  37 +               val = readl(addr);
  38 +               if ((val & mask) == value)
  39 +                       return true;
  40 +               cpu_relax();
  41 +               udelay(10);
  42 +       } while (!time_after_eq(jiffies, deadline));
  43 +
  44 +       pr_err("Timeout waiting for register %p\n", addr);
  45 +
  46 +       return false;
  47 +}
  48 +
  49 +static void bcma_hcd_usb30_phy_init(struct bcma_hcd_device *bcma_hcd)
  50 +{
  51 +       struct bcma_device *core = bcma_hcd->core;
  52 +       struct bcma_bus *bus = core->bus;
  53 +       struct bcma_chipinfo *chipinfo = &bus->chipinfo;
  54 +       struct bcma_drv_cc_b *ccb = &bus->drv_cc_b;
  55 +       struct bcma_device *arm_core;
  56 +       void __iomem *dmu = NULL;
  57 +       u32 cru_straps_ctrl;
  58 +
  59 +       if (chipinfo->id != BCMA_CHIP_ID_BCM4707 &&
  60 +           chipinfo->id != BCMA_CHIP_ID_BCM53018)
  61 +               return;
  62 +
  63 +       arm_core = bcma_find_core(bus, BCMA_CORE_ARMCA9);
  64 +       if (!arm_core)
  65 +               return;
  66 +
  67 +       dmu = ioremap_nocache(arm_core->addr_s[0], 0x1000);
  68 +       if (!dmu)
  69 +               goto out;
  70 +
  71 +       /* Check strapping of PCIE/USB3 SEL */
  72 +       cru_straps_ctrl = ioread32(dmu + 0x2a0);
  73 +       if ((cru_straps_ctrl & 0x10) == 0)
  74 +               goto out;
  75 +
  76 +       /* Perform USB3 system soft reset */
  77 +       bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
  78 +
  79 +       /* Enable MDIO. Setting MDCDIV as 26  */
  80 +       iowrite32(0x0000009a, ccb->mii + 0x000);
  81 +       udelay(2);
  82 +
  83 +       switch (chipinfo->id) {
  84 +       case BCMA_CHIP_ID_BCM4707:
  85 +               if (chipinfo->rev == 4) {
  86 +                       /* For NS-B0, USB3 PLL Block */
  87 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
  88 +                       iowrite32(0x587e8000, ccb->mii + 0x004);
  89 +
  90 +                       /* Clear ana_pllSeqStart */
  91 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
  92 +                       iowrite32(0x58061000, ccb->mii + 0x004);
  93 +
  94 +                       /* CMOS Divider ratio to 25 */
  95 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
  96 +                       iowrite32(0x582a6400, ccb->mii + 0x004);
  97 +
  98 +                       /* Asserting PLL Reset */
  99 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 100 +                       iowrite32(0x582ec000, ccb->mii + 0x004);
 101 +
 102 +                       /* Deaaserting PLL Reset */
 103 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 104 +                       iowrite32(0x582e8000, ccb->mii + 0x004);
 105 +
 106 +                       /* Deasserting USB3 system reset */
 107 +                       bcma_awrite32(core, BCMA_RESET_CTL, 0);
 108 +
 109 +                       /* Set ana_pllSeqStart */
 110 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 111 +                       iowrite32(0x58069000, ccb->mii + 0x004);
 112 +
 113 +                       /* RXPMD block */
 114 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 115 +                       iowrite32(0x587e8020, ccb->mii + 0x004);
 116 +
 117 +                       /* CDR int loop locking BW to 1 */
 118 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 119 +                       iowrite32(0x58120049, ccb->mii + 0x004);
 120 +
 121 +                       /* CDR int loop acquisition BW to 1 */
 122 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 123 +                       iowrite32(0x580e0049, ccb->mii + 0x004);
 124 +
 125 +                       /* CDR prop loop BW to 1 */
 126 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 127 +                       iowrite32(0x580a005c, ccb->mii + 0x004);
 128 +
 129 +                       /* Waiting MII Mgt interface idle */
 130 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 131 +               } else {
 132 +                       /* PLL30 block */
 133 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 134 +                       iowrite32(0x587e8000, ccb->mii + 0x004);
 135 +
 136 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 137 +                       iowrite32(0x582a6400, ccb->mii + 0x004);
 138 +
 139 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 140 +                       iowrite32(0x587e80e0, ccb->mii + 0x004);
 141 +
 142 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 143 +                       iowrite32(0x580a009c, ccb->mii + 0x004);
 144 +
 145 +                       /* Enable SSC */
 146 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 147 +                       iowrite32(0x587e8040, ccb->mii + 0x004);
 148 +
 149 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 150 +                       iowrite32(0x580a21d3, ccb->mii + 0x004);
 151 +
 152 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 153 +                       iowrite32(0x58061003, ccb->mii + 0x004);
 154 +
 155 +                       /* Waiting MII Mgt interface idle */
 156 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 157 +
 158 +                       /* Deasserting USB3 system reset */
 159 +                       bcma_awrite32(core, BCMA_RESET_CTL, 0);
 160 +               }
 161 +               break;
 162 +       case BCMA_CHIP_ID_BCM53018:
 163 +               /* USB3 PLL Block */
 164 +               bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 165 +               iowrite32(0x587e8000, ccb->mii + 0x004);
 166 +
 167 +               /* Assert Ana_Pllseq start */
 168 +               bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 169 +               iowrite32(0x58061000, ccb->mii + 0x004);
 170 +
 171 +               /* Assert CML Divider ratio to 26 */
 172 +               bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 173 +               iowrite32(0x582a6400, ccb->mii + 0x004);
 174 +
 175 +               /* Asserting PLL Reset */
 176 +               bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 177 +               iowrite32(0x582ec000, ccb->mii + 0x004);
 178 +
 179 +               /* Deaaserting PLL Reset */
 180 +               bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 181 +               iowrite32(0x582e8000, ccb->mii + 0x004);
 182 +
 183 +               /* Waiting MII Mgt interface idle */
 184 +               bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 185 +
 186 +               /* Deasserting USB3 system reset */
 187 +               bcma_awrite32(core, BCMA_RESET_CTL, 0);
 188 +
 189 +               /* PLL frequency monitor enable */
 190 +               bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 191 +               iowrite32(0x58069000, ccb->mii + 0x004);
 192 +
 193 +               /* PIPE Block */
 194 +               bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 195 +               iowrite32(0x587e8060, ccb->mii + 0x004);
 196 +
 197 +               /* CMPMAX & CMPMINTH setting */
 198 +               bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 199 +               iowrite32(0x580af30d, ccb->mii + 0x004);
 200 +
 201 +               /* DEGLITCH MIN & MAX setting */
 202 +               bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 203 +               iowrite32(0x580e6302, ccb->mii + 0x004);
 204 +
 205 +               /* TXPMD block */
 206 +               bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 207 +               iowrite32(0x587e8040, ccb->mii + 0x004);
 208 +
 209 +               /* Enabling SSC */
 210 +               bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 211 +               iowrite32(0x58061003, ccb->mii + 0x004);
 212 +
 213 +               /* Waiting MII Mgt interface idle */
 214 +               bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 215 +
 216 +               break;
 217 +       }
 218 +
 219 +       pr_info("[%s:%d] DONE\n", __FUNCTION__, __LINE__);
 220 +out:
 221 +       if (dmu)
 222 +               iounmap(dmu);
 223 +}
 224 +
 225 +static int bcma_hcd_usb30_init(struct bcma_hcd_device *bcma_hcd)
 226 +{
 227 +       struct bcma_device *core = bcma_hcd->core;
 228 +
 229 +       bcma_core_enable(core, 0);
 230 +
 231 +       bcma_hcd_usb30_phy_init(bcma_hcd);
 232 +
 233 +       bcma_hcd->xhci_dev = bcma_hcd_create_pdev(core, "xhci-hcd", core->addr,
 234 +                                                 NULL, 0);
 235 +       if (IS_ERR(bcma_hcd->ohci_dev))
 236 +               return PTR_ERR(bcma_hcd->ohci_dev);
 237 +
 238 +       return 0;
 239 +}
 240 +
 241  static int bcma_hcd_probe(struct bcma_device *dev)
 242  {
 243         int err;
 244 @@ -365,6 +577,11 @@ static int bcma_hcd_probe(struct bcma_device *dev)
 245                 if (err)
 246                         return err;
 247                 break;
 248 +       case BCMA_CORE_NS_USB30:
 249 +               err = bcma_hcd_usb30_init(usb_dev);
 250 +               if (err)
 251 +                       return err;
 252 +               break;
 253         default:
 254                 return -ENODEV;
 255         }
 256 @@ -419,6 +636,7 @@ static int bcma_hcd_resume(struct bcma_device *dev)
 257  static const struct bcma_device_id bcma_hcd_table[] = {
 258         BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_USB20_HOST, BCMA_ANY_REV, BCMA_ANY_CLASS),
 259         BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB20, BCMA_ANY_REV, BCMA_ANY_CLASS),
 260 +       BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB30, BCMA_ANY_REV, BCMA_ANY_CLASS),
 261         BCMA_CORETABLE_END
 262  };
 263  MODULE_DEVICE_TABLE(bcma, bcma_hcd_table);
 264 --
 265 1.8.4.5
 266