target/linux/brcm2708/patches-3.10/002-Main-bcm2708-linux-port.patch

   1 --- /dev/null
   2 +++ b/arch/arm/configs/bcmrpi_cutdown_defconfig
   3 @@ -0,0 +1,504 @@
   4 +CONFIG_EXPERIMENTAL=y
   5 +# CONFIG_LOCALVERSION_AUTO is not set
   6 +CONFIG_SYSVIPC=y
   7 +CONFIG_POSIX_MQUEUE=y
   8 +CONFIG_IKCONFIG=y
   9 +CONFIG_IKCONFIG_PROC=y
  10 +# CONFIG_UID16 is not set
  11 +# CONFIG_KALLSYMS is not set
  12 +CONFIG_EMBEDDED=y
  13 +# CONFIG_VM_EVENT_COUNTERS is not set
  14 +# CONFIG_COMPAT_BRK is not set
  15 +CONFIG_SLAB=y
  16 +CONFIG_MODULES=y
  17 +CONFIG_MODULE_UNLOAD=y
  18 +CONFIG_MODVERSIONS=y
  19 +CONFIG_MODULE_SRCVERSION_ALL=y
  20 +# CONFIG_BLK_DEV_BSG is not set
  21 +CONFIG_ARCH_BCM2708=y
  22 +CONFIG_NO_HZ=y
  23 +CONFIG_HIGH_RES_TIMERS=y
  24 +CONFIG_AEABI=y
  25 +CONFIG_ZBOOT_ROM_TEXT=0x0
  26 +CONFIG_ZBOOT_ROM_BSS=0x0
  27 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
  28 +CONFIG_CPU_IDLE=y
  29 +CONFIG_VFP=y
  30 +CONFIG_BINFMT_MISC=m
  31 +CONFIG_NET=y
  32 +CONFIG_PACKET=y
  33 +CONFIG_UNIX=y
  34 +CONFIG_XFRM_USER=y
  35 +CONFIG_NET_KEY=m
  36 +CONFIG_INET=y
  37 +CONFIG_IP_MULTICAST=y
  38 +CONFIG_IP_PNP=y
  39 +CONFIG_IP_PNP_DHCP=y
  40 +CONFIG_IP_PNP_RARP=y
  41 +CONFIG_SYN_COOKIES=y
  42 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
  43 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
  44 +# CONFIG_INET_XFRM_MODE_BEET is not set
  45 +# CONFIG_INET_LRO is not set
  46 +# CONFIG_INET_DIAG is not set
  47 +# CONFIG_IPV6 is not set
  48 +CONFIG_NET_PKTGEN=m
  49 +CONFIG_IRDA=m
  50 +CONFIG_IRLAN=m
  51 +CONFIG_IRCOMM=m
  52 +CONFIG_IRDA_ULTRA=y
  53 +CONFIG_IRDA_CACHE_LAST_LSAP=y
  54 +CONFIG_IRDA_FAST_RR=y
  55 +CONFIG_IRTTY_SIR=m
  56 +CONFIG_KINGSUN_DONGLE=m
  57 +CONFIG_KSDAZZLE_DONGLE=m
  58 +CONFIG_KS959_DONGLE=m
  59 +CONFIG_USB_IRDA=m
  60 +CONFIG_SIGMATEL_FIR=m
  61 +CONFIG_MCS_FIR=m
  62 +CONFIG_BT=m
  63 +CONFIG_BT_L2CAP=y
  64 +CONFIG_BT_SCO=y
  65 +CONFIG_BT_RFCOMM=m
  66 +CONFIG_BT_RFCOMM_TTY=y
  67 +CONFIG_BT_BNEP=m
  68 +CONFIG_BT_BNEP_MC_FILTER=y
  69 +CONFIG_BT_BNEP_PROTO_FILTER=y
  70 +CONFIG_BT_HIDP=m
  71 +CONFIG_BT_HCIBTUSB=m
  72 +CONFIG_BT_HCIBCM203X=m
  73 +CONFIG_BT_HCIBPA10X=m
  74 +CONFIG_BT_HCIBFUSB=m
  75 +CONFIG_BT_HCIVHCI=m
  76 +CONFIG_BT_MRVL=m
  77 +CONFIG_BT_MRVL_SDIO=m
  78 +CONFIG_BT_ATH3K=m
  79 +CONFIG_CFG80211=m
  80 +CONFIG_MAC80211=m
  81 +CONFIG_MAC80211_RC_PID=y
  82 +CONFIG_MAC80211_MESH=y
  83 +CONFIG_WIMAX=m
  84 +CONFIG_NET_9P=m
  85 +CONFIG_NFC=m
  86 +CONFIG_NFC_PN533=m
  87 +CONFIG_DEVTMPFS=y
  88 +CONFIG_BLK_DEV_LOOP=y
  89 +CONFIG_BLK_DEV_CRYPTOLOOP=m
  90 +CONFIG_BLK_DEV_NBD=m
  91 +CONFIG_BLK_DEV_RAM=y
  92 +CONFIG_CDROM_PKTCDVD=m
  93 +CONFIG_MISC_DEVICES=y
  94 +CONFIG_SCSI=y
  95 +# CONFIG_SCSI_PROC_FS is not set
  96 +CONFIG_BLK_DEV_SD=m
  97 +CONFIG_BLK_DEV_SR=m
  98 +CONFIG_SCSI_MULTI_LUN=y
  99 +# CONFIG_SCSI_LOWLEVEL is not set
 100 +CONFIG_NETDEVICES=y
 101 +CONFIG_TUN=m
 102 +CONFIG_PHYLIB=m
 103 +CONFIG_MDIO_BITBANG=m
 104 +CONFIG_NET_ETHERNET=y
 105 +# CONFIG_NETDEV_1000 is not set
 106 +# CONFIG_NETDEV_10000 is not set
 107 +CONFIG_LIBERTAS_THINFIRM=m
 108 +CONFIG_LIBERTAS_THINFIRM_USB=m
 109 +CONFIG_AT76C50X_USB=m
 110 +CONFIG_USB_ZD1201=m
 111 +CONFIG_USB_NET_RNDIS_WLAN=m
 112 +CONFIG_RTL8187=m
 113 +CONFIG_MAC80211_HWSIM=m
 114 +CONFIG_ATH_COMMON=m
 115 +CONFIG_ATH9K=m
 116 +CONFIG_ATH9K_HTC=m
 117 +CONFIG_CARL9170=m
 118 +CONFIG_B43=m
 119 +CONFIG_B43LEGACY=m
 120 +CONFIG_HOSTAP=m
 121 +CONFIG_IWM=m
 122 +CONFIG_LIBERTAS=m
 123 +CONFIG_LIBERTAS_USB=m
 124 +CONFIG_LIBERTAS_SDIO=m
 125 +CONFIG_P54_COMMON=m
 126 +CONFIG_P54_USB=m
 127 +CONFIG_RT2X00=m
 128 +CONFIG_RT2500USB=m
 129 +CONFIG_RT73USB=m
 130 +CONFIG_RT2800USB=m
 131 +CONFIG_RT2800USB_RT53XX=y
 132 +CONFIG_RTL8192CU=m
 133 +CONFIG_WL1251=m
 134 +CONFIG_WL12XX_MENU=m
 135 +CONFIG_ZD1211RW=m
 136 +CONFIG_MWIFIEX=m
 137 +CONFIG_MWIFIEX_SDIO=m
 138 +CONFIG_WIMAX_I2400M_USB=m
 139 +CONFIG_USB_CATC=m
 140 +CONFIG_USB_KAWETH=m
 141 +CONFIG_USB_PEGASUS=m
 142 +CONFIG_USB_RTL8150=m
 143 +CONFIG_USB_USBNET=y
 144 +CONFIG_USB_NET_AX8817X=m
 145 +CONFIG_USB_NET_CDCETHER=m
 146 +CONFIG_USB_NET_CDC_EEM=m
 147 +CONFIG_USB_NET_DM9601=m
 148 +CONFIG_USB_NET_SMSC75XX=m
 149 +CONFIG_USB_NET_SMSC95XX=y
 150 +CONFIG_USB_NET_GL620A=m
 151 +CONFIG_USB_NET_NET1080=m
 152 +CONFIG_USB_NET_PLUSB=m
 153 +CONFIG_USB_NET_MCS7830=m
 154 +CONFIG_USB_NET_CDC_SUBSET=m
 155 +CONFIG_USB_ALI_M5632=y
 156 +CONFIG_USB_AN2720=y
 157 +CONFIG_USB_KC2190=y
 158 +# CONFIG_USB_NET_ZAURUS is not set
 159 +CONFIG_USB_NET_CX82310_ETH=m
 160 +CONFIG_USB_NET_KALMIA=m
 161 +CONFIG_USB_NET_INT51X1=m
 162 +CONFIG_USB_IPHETH=m
 163 +CONFIG_USB_SIERRA_NET=m
 164 +CONFIG_USB_VL600=m
 165 +CONFIG_PPP=m
 166 +CONFIG_PPP_ASYNC=m
 167 +CONFIG_PPP_SYNC_TTY=m
 168 +CONFIG_PPP_DEFLATE=m
 169 +CONFIG_PPP_BSDCOMP=m
 170 +CONFIG_SLIP=m
 171 +CONFIG_SLIP_COMPRESSED=y
 172 +CONFIG_NETCONSOLE=m
 173 +CONFIG_INPUT_POLLDEV=m
 174 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 175 +CONFIG_INPUT_JOYDEV=m
 176 +CONFIG_INPUT_EVDEV=m
 177 +# CONFIG_INPUT_KEYBOARD is not set
 178 +# CONFIG_INPUT_MOUSE is not set
 179 +CONFIG_INPUT_MISC=y
 180 +CONFIG_INPUT_AD714X=m
 181 +CONFIG_INPUT_ATI_REMOTE=m
 182 +CONFIG_INPUT_ATI_REMOTE2=m
 183 +CONFIG_INPUT_KEYSPAN_REMOTE=m
 184 +CONFIG_INPUT_POWERMATE=m
 185 +CONFIG_INPUT_YEALINK=m
 186 +CONFIG_INPUT_CM109=m
 187 +CONFIG_INPUT_UINPUT=m
 188 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
 189 +CONFIG_INPUT_ADXL34X=m
 190 +CONFIG_INPUT_CMA3000=m
 191 +CONFIG_SERIO=m
 192 +CONFIG_SERIO_RAW=m
 193 +CONFIG_GAMEPORT=m
 194 +CONFIG_GAMEPORT_NS558=m
 195 +CONFIG_GAMEPORT_L4=m
 196 +CONFIG_VT_HW_CONSOLE_BINDING=y
 197 +# CONFIG_LEGACY_PTYS is not set
 198 +# CONFIG_DEVKMEM is not set
 199 +CONFIG_SERIAL_AMBA_PL011=y
 200 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 201 +# CONFIG_HW_RANDOM is not set
 202 +CONFIG_RAW_DRIVER=y
 203 +CONFIG_GPIO_SYSFS=y
 204 +# CONFIG_HWMON is not set
 205 +CONFIG_WATCHDOG=y
 206 +CONFIG_BCM2708_WDT=m
 207 +# CONFIG_MFD_SUPPORT is not set
 208 +CONFIG_FB=y
 209 +CONFIG_FB_BCM2708=y
 210 +CONFIG_FRAMEBUFFER_CONSOLE=y
 211 +CONFIG_LOGO=y
 212 +# CONFIG_LOGO_LINUX_MONO is not set
 213 +# CONFIG_LOGO_LINUX_VGA16 is not set
 214 +CONFIG_SOUND=y
 215 +CONFIG_SND=m
 216 +CONFIG_SND_SEQUENCER=m
 217 +CONFIG_SND_SEQ_DUMMY=m
 218 +CONFIG_SND_MIXER_OSS=m
 219 +CONFIG_SND_PCM_OSS=m
 220 +CONFIG_SND_SEQUENCER_OSS=y
 221 +CONFIG_SND_HRTIMER=m
 222 +CONFIG_SND_DUMMY=m
 223 +CONFIG_SND_ALOOP=m
 224 +CONFIG_SND_VIRMIDI=m
 225 +CONFIG_SND_MTPAV=m
 226 +CONFIG_SND_SERIAL_U16550=m
 227 +CONFIG_SND_MPU401=m
 228 +CONFIG_SND_BCM2835=m
 229 +CONFIG_SND_USB_AUDIO=m
 230 +CONFIG_SND_USB_UA101=m
 231 +CONFIG_SND_USB_CAIAQ=m
 232 +CONFIG_SND_USB_6FIRE=m
 233 +CONFIG_SOUND_PRIME=m
 234 +CONFIG_HID_PID=y
 235 +CONFIG_USB_HIDDEV=y
 236 +CONFIG_HID_A4TECH=m
 237 +CONFIG_HID_ACRUX=m
 238 +CONFIG_HID_APPLE=m
 239 +CONFIG_HID_BELKIN=m
 240 +CONFIG_HID_CHERRY=m
 241 +CONFIG_HID_CHICONY=m
 242 +CONFIG_HID_CYPRESS=m
 243 +CONFIG_HID_DRAGONRISE=m
 244 +CONFIG_HID_EMS_FF=m
 245 +CONFIG_HID_ELECOM=m
 246 +CONFIG_HID_EZKEY=m
 247 +CONFIG_HID_HOLTEK=m
 248 +CONFIG_HID_KEYTOUCH=m
 249 +CONFIG_HID_KYE=m
 250 +CONFIG_HID_UCLOGIC=m
 251 +CONFIG_HID_WALTOP=m
 252 +CONFIG_HID_GYRATION=m
 253 +CONFIG_HID_TWINHAN=m
 254 +CONFIG_HID_KENSINGTON=m
 255 +CONFIG_HID_LCPOWER=m
 256 +CONFIG_HID_LOGITECH=m
 257 +CONFIG_HID_MAGICMOUSE=m
 258 +CONFIG_HID_MICROSOFT=m
 259 +CONFIG_HID_MONTEREY=m
 260 +CONFIG_HID_MULTITOUCH=m
 261 +CONFIG_HID_NTRIG=m
 262 +CONFIG_HID_ORTEK=m
 263 +CONFIG_HID_PANTHERLORD=m
 264 +CONFIG_HID_PETALYNX=m
 265 +CONFIG_HID_PICOLCD=m
 266 +CONFIG_HID_QUANTA=m
 267 +CONFIG_HID_ROCCAT=m
 268 +CONFIG_HID_SAMSUNG=m
 269 +CONFIG_HID_SONY=m
 270 +CONFIG_HID_SPEEDLINK=m
 271 +CONFIG_HID_SUNPLUS=m
 272 +CONFIG_HID_GREENASIA=m
 273 +CONFIG_HID_SMARTJOYPLUS=m
 274 +CONFIG_HID_TOPSEED=m
 275 +CONFIG_HID_THRUSTMASTER=m
 276 +CONFIG_HID_WACOM=m
 277 +CONFIG_HID_WIIMOTE=m
 278 +CONFIG_HID_ZEROPLUS=m
 279 +CONFIG_HID_ZYDACRON=m
 280 +CONFIG_USB=y
 281 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 282 +CONFIG_USB_MON=m
 283 +CONFIG_USB_DWCOTG=y
 284 +CONFIG_USB_STORAGE=y
 285 +CONFIG_USB_STORAGE_REALTEK=m
 286 +CONFIG_USB_STORAGE_DATAFAB=m
 287 +CONFIG_USB_STORAGE_FREECOM=m
 288 +CONFIG_USB_STORAGE_ISD200=m
 289 +CONFIG_USB_STORAGE_USBAT=m
 290 +CONFIG_USB_STORAGE_SDDR09=m
 291 +CONFIG_USB_STORAGE_SDDR55=m
 292 +CONFIG_USB_STORAGE_JUMPSHOT=m
 293 +CONFIG_USB_STORAGE_ALAUDA=m
 294 +CONFIG_USB_STORAGE_ONETOUCH=m
 295 +CONFIG_USB_STORAGE_KARMA=m
 296 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
 297 +CONFIG_USB_STORAGE_ENE_UB6250=m
 298 +CONFIG_USB_UAS=m
 299 +CONFIG_USB_LIBUSUAL=y
 300 +CONFIG_USB_MDC800=m
 301 +CONFIG_USB_MICROTEK=m
 302 +CONFIG_USB_SERIAL=m
 303 +CONFIG_USB_SERIAL_GENERIC=y
 304 +CONFIG_USB_SERIAL_AIRCABLE=m
 305 +CONFIG_USB_SERIAL_ARK3116=m
 306 +CONFIG_USB_SERIAL_BELKIN=m
 307 +CONFIG_USB_SERIAL_CH341=m
 308 +CONFIG_USB_SERIAL_WHITEHEAT=m
 309 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
 310 +CONFIG_USB_SERIAL_CP210X=m
 311 +CONFIG_USB_SERIAL_CYPRESS_M8=m
 312 +CONFIG_USB_SERIAL_EMPEG=m
 313 +CONFIG_USB_SERIAL_FTDI_SIO=m
 314 +CONFIG_USB_SERIAL_FUNSOFT=m
 315 +CONFIG_USB_SERIAL_VISOR=m
 316 +CONFIG_USB_SERIAL_IPAQ=m
 317 +CONFIG_USB_SERIAL_IR=m
 318 +CONFIG_USB_SERIAL_EDGEPORT=m
 319 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
 320 +CONFIG_USB_SERIAL_GARMIN=m
 321 +CONFIG_USB_SERIAL_IPW=m
 322 +CONFIG_USB_SERIAL_IUU=m
 323 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
 324 +CONFIG_USB_SERIAL_KEYSPAN=m
 325 +CONFIG_USB_SERIAL_KLSI=m
 326 +CONFIG_USB_SERIAL_KOBIL_SCT=m
 327 +CONFIG_USB_SERIAL_MCT_U232=m
 328 +CONFIG_USB_SERIAL_MOS7720=m
 329 +CONFIG_USB_SERIAL_MOS7840=m
 330 +CONFIG_USB_SERIAL_MOTOROLA=m
 331 +CONFIG_USB_SERIAL_NAVMAN=m
 332 +CONFIG_USB_SERIAL_PL2303=m
 333 +CONFIG_USB_SERIAL_OTI6858=m
 334 +CONFIG_USB_SERIAL_QCAUX=m
 335 +CONFIG_USB_SERIAL_QUALCOMM=m
 336 +CONFIG_USB_SERIAL_SPCP8X5=m
 337 +CONFIG_USB_SERIAL_HP4X=m
 338 +CONFIG_USB_SERIAL_SAFE=m
 339 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
 340 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
 341 +CONFIG_USB_SERIAL_SYMBOL=m
 342 +CONFIG_USB_SERIAL_TI=m
 343 +CONFIG_USB_SERIAL_CYBERJACK=m
 344 +CONFIG_USB_SERIAL_XIRCOM=m
 345 +CONFIG_USB_SERIAL_OPTION=m
 346 +CONFIG_USB_SERIAL_OMNINET=m
 347 +CONFIG_USB_SERIAL_OPTICON=m
 348 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
 349 +CONFIG_USB_SERIAL_ZIO=m
 350 +CONFIG_USB_SERIAL_SSU100=m
 351 +CONFIG_USB_SERIAL_DEBUG=m
 352 +CONFIG_USB_EMI62=m
 353 +CONFIG_USB_EMI26=m
 354 +CONFIG_USB_ADUTUX=m
 355 +CONFIG_USB_SEVSEG=m
 356 +CONFIG_USB_RIO500=m
 357 +CONFIG_USB_LEGOTOWER=m
 358 +CONFIG_USB_LCD=m
 359 +CONFIG_USB_LED=m
 360 +CONFIG_USB_CYPRESS_CY7C63=m
 361 +CONFIG_USB_CYTHERM=m
 362 +CONFIG_USB_IDMOUSE=m
 363 +CONFIG_USB_FTDI_ELAN=m
 364 +CONFIG_USB_APPLEDISPLAY=m
 365 +CONFIG_USB_LD=m
 366 +CONFIG_USB_TRANCEVIBRATOR=m
 367 +CONFIG_USB_IOWARRIOR=m
 368 +CONFIG_USB_TEST=m
 369 +CONFIG_USB_ISIGHTFW=m
 370 +CONFIG_USB_YUREX=m
 371 +CONFIG_MMC=y
 372 +CONFIG_MMC_SDHCI=y
 373 +CONFIG_MMC_SDHCI_PLTFM=y
 374 +CONFIG_MMC_SDHCI_BCM2708=y
 375 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
 376 +CONFIG_LEDS_GPIO=y
 377 +CONFIG_LEDS_TRIGGER_TIMER=m
 378 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
 379 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
 380 +CONFIG_UIO=m
 381 +CONFIG_UIO_PDRV=m
 382 +CONFIG_UIO_PDRV_GENIRQ=m
 383 +# CONFIG_IOMMU_SUPPORT is not set
 384 +CONFIG_EXT4_FS=y
 385 +CONFIG_EXT4_FS_POSIX_ACL=y
 386 +CONFIG_EXT4_FS_SECURITY=y
 387 +CONFIG_REISERFS_FS=m
 388 +CONFIG_REISERFS_FS_XATTR=y
 389 +CONFIG_REISERFS_FS_POSIX_ACL=y
 390 +CONFIG_REISERFS_FS_SECURITY=y
 391 +CONFIG_JFS_FS=m
 392 +CONFIG_JFS_POSIX_ACL=y
 393 +CONFIG_JFS_SECURITY=y
 394 +CONFIG_XFS_FS=m
 395 +CONFIG_XFS_QUOTA=y
 396 +CONFIG_XFS_POSIX_ACL=y
 397 +CONFIG_XFS_RT=y
 398 +CONFIG_GFS2_FS=m
 399 +CONFIG_OCFS2_FS=m
 400 +CONFIG_BTRFS_FS=m
 401 +CONFIG_BTRFS_FS_POSIX_ACL=y
 402 +CONFIG_NILFS2_FS=m
 403 +CONFIG_AUTOFS4_FS=y
 404 +CONFIG_FUSE_FS=m
 405 +CONFIG_CUSE=m
 406 +CONFIG_FSCACHE=y
 407 +CONFIG_CACHEFILES=y
 408 +CONFIG_ISO9660_FS=m
 409 +CONFIG_JOLIET=y
 410 +CONFIG_ZISOFS=y
 411 +CONFIG_UDF_FS=m
 412 +CONFIG_MSDOS_FS=y
 413 +CONFIG_VFAT_FS=y
 414 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 415 +CONFIG_NTFS_FS=m
 416 +CONFIG_TMPFS=y
 417 +CONFIG_TMPFS_POSIX_ACL=y
 418 +CONFIG_CONFIGFS_FS=y
 419 +CONFIG_SQUASHFS=m
 420 +CONFIG_SQUASHFS_XATTR=y
 421 +CONFIG_SQUASHFS_LZO=y
 422 +CONFIG_SQUASHFS_XZ=y
 423 +CONFIG_NFS_FS=y
 424 +CONFIG_NFS_V3=y
 425 +CONFIG_NFS_V3_ACL=y
 426 +CONFIG_NFS_V4=y
 427 +CONFIG_ROOT_NFS=y
 428 +CONFIG_NFS_FSCACHE=y
 429 +CONFIG_CIFS=m
 430 +CONFIG_CIFS_WEAK_PW_HASH=y
 431 +CONFIG_CIFS_XATTR=y
 432 +CONFIG_CIFS_POSIX=y
 433 +CONFIG_9P_FS=m
 434 +CONFIG_PARTITION_ADVANCED=y
 435 +CONFIG_MAC_PARTITION=y
 436 +CONFIG_EFI_PARTITION=y
 437 +CONFIG_NLS_DEFAULT="utf8"
 438 +CONFIG_NLS_CODEPAGE_437=y
 439 +CONFIG_NLS_CODEPAGE_737=m
 440 +CONFIG_NLS_CODEPAGE_775=m
 441 +CONFIG_NLS_CODEPAGE_850=m
 442 +CONFIG_NLS_CODEPAGE_852=m
 443 +CONFIG_NLS_CODEPAGE_855=m
 444 +CONFIG_NLS_CODEPAGE_857=m
 445 +CONFIG_NLS_CODEPAGE_860=m
 446 +CONFIG_NLS_CODEPAGE_861=m
 447 +CONFIG_NLS_CODEPAGE_862=m
 448 +CONFIG_NLS_CODEPAGE_863=m
 449 +CONFIG_NLS_CODEPAGE_864=m
 450 +CONFIG_NLS_CODEPAGE_865=m
 451 +CONFIG_NLS_CODEPAGE_866=m
 452 +CONFIG_NLS_CODEPAGE_869=m
 453 +CONFIG_NLS_CODEPAGE_936=m
 454 +CONFIG_NLS_CODEPAGE_950=m
 455 +CONFIG_NLS_CODEPAGE_932=m
 456 +CONFIG_NLS_CODEPAGE_949=m
 457 +CONFIG_NLS_CODEPAGE_874=m
 458 +CONFIG_NLS_ISO8859_8=m
 459 +CONFIG_NLS_CODEPAGE_1250=m
 460 +CONFIG_NLS_CODEPAGE_1251=m
 461 +CONFIG_NLS_ASCII=y
 462 +CONFIG_NLS_ISO8859_1=m
 463 +CONFIG_NLS_ISO8859_2=m
 464 +CONFIG_NLS_ISO8859_3=m
 465 +CONFIG_NLS_ISO8859_4=m
 466 +CONFIG_NLS_ISO8859_5=m
 467 +CONFIG_NLS_ISO8859_6=m
 468 +CONFIG_NLS_ISO8859_7=m
 469 +CONFIG_NLS_ISO8859_9=m
 470 +CONFIG_NLS_ISO8859_13=m
 471 +CONFIG_NLS_ISO8859_14=m
 472 +CONFIG_NLS_ISO8859_15=m
 473 +CONFIG_NLS_KOI8_R=m
 474 +CONFIG_NLS_KOI8_U=m
 475 +CONFIG_NLS_UTF8=m
 476 +# CONFIG_SCHED_DEBUG is not set
 477 +# CONFIG_DEBUG_BUGVERBOSE is not set
 478 +# CONFIG_FTRACE is not set
 479 +# CONFIG_ARM_UNWIND is not set
 480 +CONFIG_CRYPTO_AUTHENC=m
 481 +CONFIG_CRYPTO_SEQIV=m
 482 +CONFIG_CRYPTO_CBC=y
 483 +CONFIG_CRYPTO_HMAC=y
 484 +CONFIG_CRYPTO_XCBC=m
 485 +CONFIG_CRYPTO_MD5=y
 486 +CONFIG_CRYPTO_SHA1=y
 487 +CONFIG_CRYPTO_SHA256=m
 488 +CONFIG_CRYPTO_SHA512=m
 489 +CONFIG_CRYPTO_TGR192=m
 490 +CONFIG_CRYPTO_WP512=m
 491 +CONFIG_CRYPTO_CAST5=m
 492 +CONFIG_CRYPTO_DES=y
 493 +CONFIG_CRYPTO_DEFLATE=m
 494 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
 495 +# CONFIG_CRYPTO_HW is not set
 496 +CONFIG_CRC_ITU_T=y
 497 +CONFIG_LIBCRC32C=y
 498 +CONFIG_I2C=y
 499 +CONFIG_I2C_BOARDINFO=y
 500 +CONFIG_I2C_COMPAT=y
 501 +CONFIG_I2C_CHARDEV=m
 502 +CONFIG_I2C_HELPER_AUTO=y
 503 +CONFIG_I2C_BCM2708=m
 504 +CONFIG_SPI=y
 505 +CONFIG_SPI_MASTER=y
 506 +CONFIG_SPI_BCM2708=m
 507 +
 508 --- /dev/null
 509 +++ b/arch/arm/configs/bcmrpi_defconfig
 510 @@ -0,0 +1,743 @@
 511 +# CONFIG_ARM_PATCH_PHYS_VIRT is not set
 512 +# CONFIG_LOCALVERSION_AUTO is not set
 513 +CONFIG_SYSVIPC=y
 514 +CONFIG_POSIX_MQUEUE=y
 515 +CONFIG_FHANDLE=y
 516 +CONFIG_AUDIT=y
 517 +CONFIG_NO_HZ=y
 518 +CONFIG_HIGH_RES_TIMERS=y
 519 +CONFIG_BSD_PROCESS_ACCT=y
 520 +CONFIG_BSD_PROCESS_ACCT_V3=y
 521 +CONFIG_IKCONFIG=y
 522 +CONFIG_IKCONFIG_PROC=y
 523 +CONFIG_CGROUP_FREEZER=y
 524 +CONFIG_CGROUP_DEVICE=y
 525 +CONFIG_CGROUP_CPUACCT=y
 526 +CONFIG_RESOURCE_COUNTERS=y
 527 +CONFIG_BLK_CGROUP=y
 528 +CONFIG_NAMESPACES=y
 529 +CONFIG_SCHED_AUTOGROUP=y
 530 +CONFIG_EMBEDDED=y
 531 +# CONFIG_COMPAT_BRK is not set
 532 +CONFIG_SLAB=y
 533 +CONFIG_PROFILING=y
 534 +CONFIG_OPROFILE=m
 535 +CONFIG_KPROBES=y
 536 +CONFIG_MODULES=y
 537 +CONFIG_MODULE_UNLOAD=y
 538 +CONFIG_MODVERSIONS=y
 539 +CONFIG_MODULE_SRCVERSION_ALL=y
 540 +# CONFIG_BLK_DEV_BSG is not set
 541 +CONFIG_BLK_DEV_THROTTLING=y
 542 +CONFIG_PARTITION_ADVANCED=y
 543 +CONFIG_MAC_PARTITION=y
 544 +CONFIG_CFQ_GROUP_IOSCHED=y
 545 +CONFIG_ARCH_BCM2708=y
 546 +CONFIG_AEABI=y
 547 +CONFIG_SECCOMP=y
 548 +CONFIG_CC_STACKPROTECTOR=y
 549 +CONFIG_ZBOOT_ROM_TEXT=0x0
 550 +CONFIG_ZBOOT_ROM_BSS=0x0
 551 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
 552 +CONFIG_KEXEC=y
 553 +CONFIG_CPU_FREQ=y
 554 +CONFIG_CPU_FREQ_STAT=m
 555 +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
 556 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
 557 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
 558 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
 559 +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
 560 +CONFIG_CPU_IDLE=y
 561 +CONFIG_VFP=y
 562 +CONFIG_BINFMT_MISC=m
 563 +CONFIG_NET=y
 564 +CONFIG_PACKET=y
 565 +CONFIG_UNIX=y
 566 +CONFIG_XFRM_USER=y
 567 +CONFIG_NET_KEY=m
 568 +CONFIG_INET=y
 569 +CONFIG_IP_MULTICAST=y
 570 +CONFIG_IP_PNP=y
 571 +CONFIG_IP_PNP_DHCP=y
 572 +CONFIG_IP_PNP_RARP=y
 573 +CONFIG_SYN_COOKIES=y
 574 +CONFIG_INET_AH=m
 575 +CONFIG_INET_ESP=m
 576 +CONFIG_INET_IPCOMP=m
 577 +CONFIG_INET_XFRM_MODE_TRANSPORT=m
 578 +CONFIG_INET_XFRM_MODE_TUNNEL=m
 579 +CONFIG_INET_XFRM_MODE_BEET=m
 580 +CONFIG_INET_LRO=m
 581 +CONFIG_INET_DIAG=m
 582 +CONFIG_IPV6_PRIVACY=y
 583 +CONFIG_INET6_AH=m
 584 +CONFIG_INET6_ESP=m
 585 +CONFIG_INET6_IPCOMP=m
 586 +CONFIG_IPV6_MULTIPLE_TABLES=y
 587 +CONFIG_NETFILTER=y
 588 +CONFIG_NF_CONNTRACK=m
 589 +CONFIG_NF_CONNTRACK_ZONES=y
 590 +CONFIG_NF_CONNTRACK_EVENTS=y
 591 +CONFIG_NF_CONNTRACK_TIMESTAMP=y
 592 +CONFIG_NF_CT_PROTO_DCCP=m
 593 +CONFIG_NF_CT_PROTO_SCTP=m
 594 +CONFIG_NF_CT_PROTO_UDPLITE=m
 595 +CONFIG_NF_CONNTRACK_AMANDA=m
 596 +CONFIG_NF_CONNTRACK_FTP=m
 597 +CONFIG_NF_CONNTRACK_H323=m
 598 +CONFIG_NF_CONNTRACK_IRC=m
 599 +CONFIG_NF_CONNTRACK_NETBIOS_NS=m
 600 +CONFIG_NF_CONNTRACK_SNMP=m
 601 +CONFIG_NF_CONNTRACK_PPTP=m
 602 +CONFIG_NF_CONNTRACK_SANE=m
 603 +CONFIG_NF_CONNTRACK_SIP=m
 604 +CONFIG_NF_CONNTRACK_TFTP=m
 605 +CONFIG_NF_CT_NETLINK=m
 606 +CONFIG_NETFILTER_TPROXY=m
 607 +CONFIG_NETFILTER_XT_SET=m
 608 +CONFIG_NETFILTER_XT_TARGET_AUDIT=m
 609 +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
 610 +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 611 +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 612 +CONFIG_NETFILTER_XT_TARGET_DSCP=m
 613 +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
 614 +CONFIG_NETFILTER_XT_TARGET_MARK=m
 615 +CONFIG_NETFILTER_XT_TARGET_NFLOG=m
 616 +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
 617 +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
 618 +CONFIG_NETFILTER_XT_TARGET_TEE=m
 619 +CONFIG_NETFILTER_XT_TARGET_TPROXY=m
 620 +CONFIG_NETFILTER_XT_TARGET_TRACE=m
 621 +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 622 +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
 623 +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
 624 +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
 625 +CONFIG_NETFILTER_XT_MATCH_COMMENT=m
 626 +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
 627 +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
 628 +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
 629 +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
 630 +CONFIG_NETFILTER_XT_MATCH_CPU=m
 631 +CONFIG_NETFILTER_XT_MATCH_DCCP=m
 632 +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
 633 +CONFIG_NETFILTER_XT_MATCH_DSCP=m
 634 +CONFIG_NETFILTER_XT_MATCH_ESP=m
 635 +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
 636 +CONFIG_NETFILTER_XT_MATCH_HELPER=m
 637 +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
 638 +CONFIG_NETFILTER_XT_MATCH_LENGTH=m
 639 +CONFIG_NETFILTER_XT_MATCH_LIMIT=m
 640 +CONFIG_NETFILTER_XT_MATCH_MAC=m
 641 +CONFIG_NETFILTER_XT_MATCH_MARK=m
 642 +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
 643 +CONFIG_NETFILTER_XT_MATCH_OSF=m
 644 +CONFIG_NETFILTER_XT_MATCH_OWNER=m
 645 +CONFIG_NETFILTER_XT_MATCH_POLICY=m
 646 +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
 647 +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
 648 +CONFIG_NETFILTER_XT_MATCH_QUOTA=m
 649 +CONFIG_NETFILTER_XT_MATCH_RATEEST=m
 650 +CONFIG_NETFILTER_XT_MATCH_REALM=m
 651 +CONFIG_NETFILTER_XT_MATCH_RECENT=m
 652 +CONFIG_NETFILTER_XT_MATCH_SCTP=m
 653 +CONFIG_NETFILTER_XT_MATCH_SOCKET=m
 654 +CONFIG_NETFILTER_XT_MATCH_STATE=m
 655 +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
 656 +CONFIG_NETFILTER_XT_MATCH_STRING=m
 657 +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 658 +CONFIG_NETFILTER_XT_MATCH_TIME=m
 659 +CONFIG_NETFILTER_XT_MATCH_U32=m
 660 +CONFIG_IP_SET=m
 661 +CONFIG_IP_SET_BITMAP_IP=m
 662 +CONFIG_IP_SET_BITMAP_IPMAC=m
 663 +CONFIG_IP_SET_BITMAP_PORT=m
 664 +CONFIG_IP_SET_HASH_IP=m
 665 +CONFIG_IP_SET_HASH_IPPORT=m
 666 +CONFIG_IP_SET_HASH_IPPORTIP=m
 667 +CONFIG_IP_SET_HASH_IPPORTNET=m
 668 +CONFIG_IP_SET_HASH_NET=m
 669 +CONFIG_IP_SET_HASH_NETPORT=m
 670 +CONFIG_IP_SET_HASH_NETIFACE=m
 671 +CONFIG_IP_SET_LIST_SET=m
 672 +CONFIG_NF_CONNTRACK_IPV4=m
 673 +CONFIG_IP_NF_IPTABLES=m
 674 +CONFIG_IP_NF_MATCH_AH=m
 675 +CONFIG_IP_NF_MATCH_ECN=m
 676 +CONFIG_IP_NF_MATCH_TTL=m
 677 +CONFIG_IP_NF_FILTER=m
 678 +CONFIG_IP_NF_TARGET_REJECT=m
 679 +CONFIG_IP_NF_TARGET_ULOG=m
 680 +CONFIG_IP_NF_MANGLE=m
 681 +CONFIG_IP_NF_TARGET_ECN=m
 682 +CONFIG_IP_NF_TARGET_TTL=m
 683 +CONFIG_IP_NF_RAW=m
 684 +CONFIG_IP_NF_ARPTABLES=m
 685 +CONFIG_IP_NF_ARPFILTER=m
 686 +CONFIG_IP_NF_ARP_MANGLE=m
 687 +CONFIG_NF_CONNTRACK_IPV6=m
 688 +CONFIG_IP6_NF_IPTABLES=m
 689 +CONFIG_IP6_NF_MATCH_AH=m
 690 +CONFIG_IP6_NF_MATCH_EUI64=m
 691 +CONFIG_IP6_NF_MATCH_FRAG=m
 692 +CONFIG_IP6_NF_MATCH_OPTS=m
 693 +CONFIG_IP6_NF_MATCH_HL=m
 694 +CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 695 +CONFIG_IP6_NF_MATCH_MH=m
 696 +CONFIG_IP6_NF_MATCH_RT=m
 697 +CONFIG_IP6_NF_TARGET_HL=m
 698 +CONFIG_IP6_NF_FILTER=m
 699 +CONFIG_IP6_NF_TARGET_REJECT=m
 700 +CONFIG_IP6_NF_MANGLE=m
 701 +CONFIG_IP6_NF_RAW=m
 702 +CONFIG_BRIDGE_NF_EBTABLES=m
 703 +CONFIG_BRIDGE_EBT_BROUTE=m
 704 +CONFIG_BRIDGE_EBT_T_FILTER=m
 705 +CONFIG_BRIDGE_EBT_T_NAT=m
 706 +CONFIG_BRIDGE_EBT_802_3=m
 707 +CONFIG_BRIDGE_EBT_AMONG=m
 708 +CONFIG_BRIDGE_EBT_ARP=m
 709 +CONFIG_BRIDGE_EBT_IP=m
 710 +CONFIG_BRIDGE_EBT_IP6=m
 711 +CONFIG_BRIDGE_EBT_LIMIT=m
 712 +CONFIG_BRIDGE_EBT_MARK=m
 713 +CONFIG_BRIDGE_EBT_PKTTYPE=m
 714 +CONFIG_BRIDGE_EBT_STP=m
 715 +CONFIG_BRIDGE_EBT_VLAN=m
 716 +CONFIG_BRIDGE_EBT_ARPREPLY=m
 717 +CONFIG_BRIDGE_EBT_DNAT=m
 718 +CONFIG_BRIDGE_EBT_MARK_T=m
 719 +CONFIG_BRIDGE_EBT_REDIRECT=m
 720 +CONFIG_BRIDGE_EBT_SNAT=m
 721 +CONFIG_BRIDGE_EBT_LOG=m
 722 +CONFIG_BRIDGE_EBT_ULOG=m
 723 +CONFIG_BRIDGE_EBT_NFLOG=m
 724 +CONFIG_L2TP=m
 725 +CONFIG_BRIDGE=m
 726 +CONFIG_VLAN_8021Q=m
 727 +CONFIG_VLAN_8021Q_GVRP=y
 728 +CONFIG_NET_SCHED=y
 729 +CONFIG_NET_SCH_CBQ=m
 730 +CONFIG_NET_SCH_HTB=m
 731 +CONFIG_NET_SCH_HFSC=m
 732 +CONFIG_NET_SCH_PRIO=m
 733 +CONFIG_NET_SCH_MULTIQ=m
 734 +CONFIG_NET_SCH_RED=m
 735 +CONFIG_NET_SCH_SFB=m
 736 +CONFIG_NET_SCH_SFQ=m
 737 +CONFIG_NET_SCH_TEQL=m
 738 +CONFIG_NET_SCH_TBF=m
 739 +CONFIG_NET_SCH_GRED=m
 740 +CONFIG_NET_SCH_DSMARK=m
 741 +CONFIG_NET_SCH_NETEM=m
 742 +CONFIG_NET_SCH_DRR=m
 743 +CONFIG_NET_SCH_MQPRIO=m
 744 +CONFIG_NET_SCH_CHOKE=m
 745 +CONFIG_NET_SCH_QFQ=m
 746 +CONFIG_NET_CLS_BASIC=m
 747 +CONFIG_NET_CLS_TCINDEX=m
 748 +CONFIG_NET_CLS_ROUTE4=m
 749 +CONFIG_NET_CLS_FW=m
 750 +CONFIG_NET_CLS_U32=m
 751 +CONFIG_CLS_U32_MARK=y
 752 +CONFIG_NET_CLS_RSVP=m
 753 +CONFIG_NET_CLS_RSVP6=m
 754 +CONFIG_NET_CLS_FLOW=m
 755 +CONFIG_NET_CLS_CGROUP=m
 756 +CONFIG_NET_EMATCH=y
 757 +CONFIG_NET_EMATCH_CMP=m
 758 +CONFIG_NET_EMATCH_NBYTE=m
 759 +CONFIG_NET_EMATCH_U32=m
 760 +CONFIG_NET_EMATCH_META=m
 761 +CONFIG_NET_EMATCH_TEXT=m
 762 +CONFIG_NET_CLS_ACT=y
 763 +CONFIG_NET_ACT_POLICE=m
 764 +CONFIG_NET_ACT_GACT=m
 765 +CONFIG_GACT_PROB=y
 766 +CONFIG_NET_ACT_MIRRED=m
 767 +CONFIG_NET_ACT_IPT=m
 768 +CONFIG_NET_ACT_NAT=m
 769 +CONFIG_NET_ACT_PEDIT=m
 770 +CONFIG_NET_ACT_SIMP=m
 771 +CONFIG_NET_ACT_SKBEDIT=m
 772 +CONFIG_NET_ACT_CSUM=m
 773 +CONFIG_NET_PKTGEN=m
 774 +CONFIG_IRDA=m
 775 +CONFIG_IRLAN=m
 776 +CONFIG_IRCOMM=m
 777 +CONFIG_IRDA_ULTRA=y
 778 +CONFIG_IRDA_CACHE_LAST_LSAP=y
 779 +CONFIG_IRDA_FAST_RR=y
 780 +CONFIG_IRTTY_SIR=m
 781 +CONFIG_KINGSUN_DONGLE=m
 782 +CONFIG_KSDAZZLE_DONGLE=m
 783 +CONFIG_KS959_DONGLE=m
 784 +CONFIG_USB_IRDA=m
 785 +CONFIG_SIGMATEL_FIR=m
 786 +CONFIG_MCS_FIR=m
 787 +CONFIG_BT=m
 788 +CONFIG_BT_RFCOMM=m
 789 +CONFIG_BT_RFCOMM_TTY=y
 790 +CONFIG_BT_BNEP=m
 791 +CONFIG_BT_BNEP_MC_FILTER=y
 792 +CONFIG_BT_BNEP_PROTO_FILTER=y
 793 +CONFIG_BT_HIDP=m
 794 +CONFIG_BT_HCIBTUSB=m
 795 +CONFIG_BT_HCIBCM203X=m
 796 +CONFIG_BT_HCIBPA10X=m
 797 +CONFIG_BT_HCIBFUSB=m
 798 +CONFIG_BT_HCIVHCI=m
 799 +CONFIG_BT_MRVL=m
 800 +CONFIG_BT_MRVL_SDIO=m
 801 +CONFIG_BT_ATH3K=m
 802 +CONFIG_CFG80211=m
 803 +CONFIG_MAC80211=m
 804 +CONFIG_MAC80211_RC_PID=y
 805 +CONFIG_MAC80211_MESH=y
 806 +CONFIG_WIMAX=m
 807 +CONFIG_NET_9P=m
 808 +CONFIG_NFC=m
 809 +CONFIG_NFC_PN533=m
 810 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 811 +CONFIG_DEVTMPFS=y
 812 +CONFIG_DEVTMPFS_MOUNT=y
 813 +CONFIG_BLK_DEV_LOOP=y
 814 +CONFIG_BLK_DEV_CRYPTOLOOP=m
 815 +CONFIG_BLK_DEV_DRBD=m
 816 +CONFIG_BLK_DEV_NBD=m
 817 +CONFIG_BLK_DEV_RAM=y
 818 +CONFIG_CDROM_PKTCDVD=m
 819 +CONFIG_SCSI=y
 820 +# CONFIG_SCSI_PROC_FS is not set
 821 +CONFIG_BLK_DEV_SD=m
 822 +CONFIG_BLK_DEV_SR=m
 823 +CONFIG_SCSI_MULTI_LUN=y
 824 +# CONFIG_SCSI_LOWLEVEL is not set
 825 +CONFIG_MD=y
 826 +CONFIG_NETDEVICES=y
 827 +CONFIG_NETCONSOLE=m
 828 +CONFIG_TUN=m
 829 +CONFIG_MDIO_BITBANG=m
 830 +CONFIG_PPP=m
 831 +CONFIG_PPP_BSDCOMP=m
 832 +CONFIG_PPP_DEFLATE=m
 833 +CONFIG_PPP_ASYNC=m
 834 +CONFIG_PPP_SYNC_TTY=m
 835 +CONFIG_SLIP=m
 836 +CONFIG_SLIP_COMPRESSED=y
 837 +CONFIG_USB_CATC=m
 838 +CONFIG_USB_KAWETH=m
 839 +CONFIG_USB_PEGASUS=m
 840 +CONFIG_USB_RTL8150=m
 841 +CONFIG_USB_USBNET=y
 842 +CONFIG_USB_NET_AX8817X=m
 843 +CONFIG_USB_NET_CDCETHER=m
 844 +CONFIG_USB_NET_CDC_EEM=m
 845 +CONFIG_USB_NET_DM9601=m
 846 +CONFIG_USB_NET_SMSC75XX=m
 847 +CONFIG_USB_NET_SMSC95XX=y
 848 +CONFIG_USB_NET_GL620A=m
 849 +CONFIG_USB_NET_NET1080=m
 850 +CONFIG_USB_NET_PLUSB=m
 851 +CONFIG_USB_NET_MCS7830=m
 852 +CONFIG_USB_NET_CDC_SUBSET=m
 853 +CONFIG_USB_ALI_M5632=y
 854 +CONFIG_USB_AN2720=y
 855 +CONFIG_USB_KC2190=y
 856 +# CONFIG_USB_NET_ZAURUS is not set
 857 +CONFIG_USB_NET_CX82310_ETH=m
 858 +CONFIG_USB_NET_KALMIA=m
 859 +CONFIG_USB_NET_INT51X1=m
 860 +CONFIG_USB_IPHETH=m
 861 +CONFIG_USB_SIERRA_NET=m
 862 +CONFIG_USB_VL600=m
 863 +CONFIG_LIBERTAS_THINFIRM=m
 864 +CONFIG_LIBERTAS_THINFIRM_USB=m
 865 +CONFIG_AT76C50X_USB=m
 866 +CONFIG_USB_ZD1201=m
 867 +CONFIG_USB_NET_RNDIS_WLAN=m
 868 +CONFIG_RTL8187=m
 869 +CONFIG_MAC80211_HWSIM=m
 870 +CONFIG_B43=m
 871 +CONFIG_B43LEGACY=m
 872 +CONFIG_HOSTAP=m
 873 +CONFIG_LIBERTAS=m
 874 +CONFIG_LIBERTAS_USB=m
 875 +CONFIG_LIBERTAS_SDIO=m
 876 +CONFIG_P54_COMMON=m
 877 +CONFIG_P54_USB=m
 878 +CONFIG_RT2X00=m
 879 +CONFIG_RT2500USB=m
 880 +CONFIG_RT73USB=m
 881 +CONFIG_RT2800USB=m
 882 +CONFIG_RT2800USB_RT53XX=y
 883 +CONFIG_RT2800USB_UNKNOWN=y
 884 +CONFIG_ZD1211RW=m
 885 +CONFIG_MWIFIEX=m
 886 +CONFIG_MWIFIEX_SDIO=m
 887 +CONFIG_WIMAX_I2400M_USB=m
 888 +CONFIG_INPUT_POLLDEV=m
 889 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 890 +CONFIG_INPUT_JOYDEV=m
 891 +CONFIG_INPUT_EVDEV=m
 892 +# CONFIG_INPUT_KEYBOARD is not set
 893 +# CONFIG_INPUT_MOUSE is not set
 894 +CONFIG_INPUT_MISC=y
 895 +CONFIG_INPUT_AD714X=m
 896 +CONFIG_INPUT_ATI_REMOTE2=m
 897 +CONFIG_INPUT_KEYSPAN_REMOTE=m
 898 +CONFIG_INPUT_POWERMATE=m
 899 +CONFIG_INPUT_YEALINK=m
 900 +CONFIG_INPUT_CM109=m
 901 +CONFIG_INPUT_UINPUT=m
 902 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
 903 +CONFIG_INPUT_ADXL34X=m
 904 +CONFIG_INPUT_CMA3000=m
 905 +CONFIG_SERIO=m
 906 +CONFIG_SERIO_RAW=m
 907 +CONFIG_GAMEPORT=m
 908 +CONFIG_GAMEPORT_NS558=m
 909 +CONFIG_GAMEPORT_L4=m
 910 +CONFIG_VT_HW_CONSOLE_BINDING=y
 911 +# CONFIG_LEGACY_PTYS is not set
 912 +# CONFIG_DEVKMEM is not set
 913 +CONFIG_SERIAL_AMBA_PL011=y
 914 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 915 +# CONFIG_HW_RANDOM is not set
 916 +CONFIG_RAW_DRIVER=y
 917 +CONFIG_I2C=y
 918 +CONFIG_I2C_CHARDEV=m
 919 +CONFIG_I2C_BCM2708=m
 920 +CONFIG_SPI=y
 921 +CONFIG_SPI_BCM2708=m
 922 +CONFIG_SPI_SPIDEV=m
 923 +CONFIG_GPIO_SYSFS=y
 924 +# CONFIG_HWMON is not set
 925 +CONFIG_THERMAL=y
 926 +CONFIG_THERMAL_BCM2835=y
 927 +CONFIG_WATCHDOG=y
 928 +CONFIG_BCM2708_WDT=m
 929 +CONFIG_MEDIA_SUPPORT=m
 930 +CONFIG_FB=y
 931 +CONFIG_FB_BCM2708=y
 932 +CONFIG_FRAMEBUFFER_CONSOLE=y
 933 +CONFIG_LOGO=y
 934 +# CONFIG_LOGO_LINUX_MONO is not set
 935 +# CONFIG_LOGO_LINUX_VGA16 is not set
 936 +CONFIG_SOUND=y
 937 +CONFIG_SND=m
 938 +CONFIG_SND_SEQUENCER=m
 939 +CONFIG_SND_SEQ_DUMMY=m
 940 +CONFIG_SND_MIXER_OSS=m
 941 +CONFIG_SND_PCM_OSS=m
 942 +CONFIG_SND_SEQUENCER_OSS=y
 943 +CONFIG_SND_HRTIMER=m
 944 +CONFIG_SND_DUMMY=m
 945 +CONFIG_SND_ALOOP=m
 946 +CONFIG_SND_VIRMIDI=m
 947 +CONFIG_SND_MTPAV=m
 948 +CONFIG_SND_SERIAL_U16550=m
 949 +CONFIG_SND_MPU401=m
 950 +CONFIG_SND_BCM2835=m
 951 +CONFIG_SND_USB_AUDIO=m
 952 +CONFIG_SND_USB_UA101=m
 953 +CONFIG_SND_USB_CAIAQ=m
 954 +CONFIG_SND_USB_6FIRE=m
 955 +CONFIG_SOUND_PRIME=m
 956 +CONFIG_HID_A4TECH=m
 957 +CONFIG_HID_ACRUX=m
 958 +CONFIG_HID_APPLE=m
 959 +CONFIG_HID_BELKIN=m
 960 +CONFIG_HID_CHERRY=m
 961 +CONFIG_HID_CHICONY=m
 962 +CONFIG_HID_CYPRESS=m
 963 +CONFIG_HID_DRAGONRISE=m
 964 +CONFIG_HID_EMS_FF=m
 965 +CONFIG_HID_ELECOM=m
 966 +CONFIG_HID_EZKEY=m
 967 +CONFIG_HID_HOLTEK=m
 968 +CONFIG_HID_KEYTOUCH=m
 969 +CONFIG_HID_KYE=m
 970 +CONFIG_HID_UCLOGIC=m
 971 +CONFIG_HID_WALTOP=m
 972 +CONFIG_HID_GYRATION=m
 973 +CONFIG_HID_TWINHAN=m
 974 +CONFIG_HID_KENSINGTON=m
 975 +CONFIG_HID_LCPOWER=m
 976 +CONFIG_HID_LOGITECH=m
 977 +CONFIG_HID_MAGICMOUSE=m
 978 +CONFIG_HID_MICROSOFT=m
 979 +CONFIG_HID_MONTEREY=m
 980 +CONFIG_HID_MULTITOUCH=m
 981 +CONFIG_HID_NTRIG=m
 982 +CONFIG_HID_ORTEK=m
 983 +CONFIG_HID_PANTHERLORD=m
 984 +CONFIG_HID_PETALYNX=m
 985 +CONFIG_HID_PICOLCD=m
 986 +CONFIG_HID_ROCCAT=m
 987 +CONFIG_HID_SAMSUNG=m
 988 +CONFIG_HID_SONY=m
 989 +CONFIG_HID_SPEEDLINK=m
 990 +CONFIG_HID_SUNPLUS=m
 991 +CONFIG_HID_GREENASIA=m
 992 +CONFIG_HID_SMARTJOYPLUS=m
 993 +CONFIG_HID_TOPSEED=m
 994 +CONFIG_HID_THRUSTMASTER=m
 995 +CONFIG_HID_ZEROPLUS=m
 996 +CONFIG_HID_ZYDACRON=m
 997 +CONFIG_HID_PID=y
 998 +CONFIG_USB_HIDDEV=y
 999 +CONFIG_USB=y
1000 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1001 +CONFIG_USB_MON=m
1002 +CONFIG_USB_DWCOTG=y
1003 +CONFIG_USB_STORAGE=y
1004 +CONFIG_USB_STORAGE_REALTEK=m
1005 +CONFIG_USB_STORAGE_DATAFAB=m
1006 +CONFIG_USB_STORAGE_FREECOM=m
1007 +CONFIG_USB_STORAGE_ISD200=m
1008 +CONFIG_USB_STORAGE_USBAT=m
1009 +CONFIG_USB_STORAGE_SDDR09=m
1010 +CONFIG_USB_STORAGE_SDDR55=m
1011 +CONFIG_USB_STORAGE_JUMPSHOT=m
1012 +CONFIG_USB_STORAGE_ALAUDA=m
1013 +CONFIG_USB_STORAGE_ONETOUCH=m
1014 +CONFIG_USB_STORAGE_KARMA=m
1015 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
1016 +CONFIG_USB_STORAGE_ENE_UB6250=m
1017 +CONFIG_USB_MDC800=m
1018 +CONFIG_USB_MICROTEK=m
1019 +CONFIG_USB_SERIAL=m
1020 +CONFIG_USB_SERIAL_GENERIC=y
1021 +CONFIG_USB_SERIAL_AIRCABLE=m
1022 +CONFIG_USB_SERIAL_ARK3116=m
1023 +CONFIG_USB_SERIAL_BELKIN=m
1024 +CONFIG_USB_SERIAL_CH341=m
1025 +CONFIG_USB_SERIAL_WHITEHEAT=m
1026 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
1027 +CONFIG_USB_SERIAL_CP210X=m
1028 +CONFIG_USB_SERIAL_CYPRESS_M8=m
1029 +CONFIG_USB_SERIAL_EMPEG=m
1030 +CONFIG_USB_SERIAL_FTDI_SIO=m
1031 +CONFIG_USB_SERIAL_FUNSOFT=m
1032 +CONFIG_USB_SERIAL_VISOR=m
1033 +CONFIG_USB_SERIAL_IPAQ=m
1034 +CONFIG_USB_SERIAL_IR=m
1035 +CONFIG_USB_SERIAL_EDGEPORT=m
1036 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
1037 +CONFIG_USB_SERIAL_GARMIN=m
1038 +CONFIG_USB_SERIAL_IPW=m
1039 +CONFIG_USB_SERIAL_IUU=m
1040 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
1041 +CONFIG_USB_SERIAL_KEYSPAN=m
1042 +CONFIG_USB_SERIAL_KLSI=m
1043 +CONFIG_USB_SERIAL_KOBIL_SCT=m
1044 +CONFIG_USB_SERIAL_MCT_U232=m
1045 +CONFIG_USB_SERIAL_MOS7720=m
1046 +CONFIG_USB_SERIAL_MOS7840=m
1047 +CONFIG_USB_SERIAL_MOTOROLA=m
1048 +CONFIG_USB_SERIAL_NAVMAN=m
1049 +CONFIG_USB_SERIAL_PL2303=m
1050 +CONFIG_USB_SERIAL_OTI6858=m
1051 +CONFIG_USB_SERIAL_QCAUX=m
1052 +CONFIG_USB_SERIAL_QUALCOMM=m
1053 +CONFIG_USB_SERIAL_SPCP8X5=m
1054 +CONFIG_USB_SERIAL_HP4X=m
1055 +CONFIG_USB_SERIAL_SAFE=m
1056 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
1057 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
1058 +CONFIG_USB_SERIAL_SYMBOL=m
1059 +CONFIG_USB_SERIAL_TI=m
1060 +CONFIG_USB_SERIAL_CYBERJACK=m
1061 +CONFIG_USB_SERIAL_XIRCOM=m
1062 +CONFIG_USB_SERIAL_OPTION=m
1063 +CONFIG_USB_SERIAL_OMNINET=m
1064 +CONFIG_USB_SERIAL_OPTICON=m
1065 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
1066 +CONFIG_USB_SERIAL_ZIO=m
1067 +CONFIG_USB_SERIAL_SSU100=m
1068 +CONFIG_USB_SERIAL_DEBUG=m
1069 +CONFIG_USB_EMI62=m
1070 +CONFIG_USB_EMI26=m
1071 +CONFIG_USB_ADUTUX=m
1072 +CONFIG_USB_SEVSEG=m
1073 +CONFIG_USB_RIO500=m
1074 +CONFIG_USB_LEGOTOWER=m
1075 +CONFIG_USB_LCD=m
1076 +CONFIG_USB_LED=m
1077 +CONFIG_USB_CYPRESS_CY7C63=m
1078 +CONFIG_USB_CYTHERM=m
1079 +CONFIG_USB_IDMOUSE=m
1080 +CONFIG_USB_FTDI_ELAN=m
1081 +CONFIG_USB_APPLEDISPLAY=m
1082 +CONFIG_USB_LD=m
1083 +CONFIG_USB_TRANCEVIBRATOR=m
1084 +CONFIG_USB_IOWARRIOR=m
1085 +CONFIG_USB_TEST=m
1086 +CONFIG_USB_ISIGHTFW=m
1087 +CONFIG_USB_YUREX=m
1088 +CONFIG_MMC=y
1089 +CONFIG_MMC_SDHCI=y
1090 +CONFIG_MMC_SDHCI_PLTFM=y
1091 +CONFIG_MMC_SDHCI_BCM2708=y
1092 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1093 +CONFIG_RTC_CLASS=y
1094 +CONFIG_RTC_DRV_DS1307=m
1095 +CONFIG_RTC_DRV_DS1374=m
1096 +CONFIG_RTC_DRV_DS1672=m
1097 +CONFIG_RTC_DRV_DS3232=m
1098 +CONFIG_RTC_DRV_MAX6900=m
1099 +CONFIG_RTC_DRV_RS5C372=m
1100 +CONFIG_RTC_DRV_ISL1208=m
1101 +CONFIG_RTC_DRV_ISL12022=m
1102 +CONFIG_RTC_DRV_X1205=m
1103 +CONFIG_RTC_DRV_PCF8563=m
1104 +CONFIG_RTC_DRV_PCF8583=m
1105 +CONFIG_RTC_DRV_M41T80=m
1106 +CONFIG_RTC_DRV_BQ32K=m
1107 +CONFIG_RTC_DRV_S35390A=m
1108 +CONFIG_RTC_DRV_FM3130=m
1109 +CONFIG_RTC_DRV_RX8581=m
1110 +CONFIG_RTC_DRV_RX8025=m
1111 +CONFIG_RTC_DRV_EM3027=m
1112 +CONFIG_RTC_DRV_RV3029C2=m
1113 +CONFIG_RTC_DRV_M41T93=m
1114 +CONFIG_RTC_DRV_M41T94=m
1115 +CONFIG_RTC_DRV_DS1305=m
1116 +CONFIG_RTC_DRV_DS1390=m
1117 +CONFIG_RTC_DRV_MAX6902=m
1118 +CONFIG_RTC_DRV_R9701=m
1119 +CONFIG_RTC_DRV_RS5C348=m
1120 +CONFIG_RTC_DRV_DS3234=m
1121 +CONFIG_RTC_DRV_PCF2123=m
1122 +CONFIG_UIO=m
1123 +CONFIG_UIO_PDRV=m
1124 +CONFIG_UIO_PDRV_GENIRQ=m
1125 +# CONFIG_IOMMU_SUPPORT is not set
1126 +CONFIG_EXT4_FS=y
1127 +CONFIG_EXT4_FS_POSIX_ACL=y
1128 +CONFIG_EXT4_FS_SECURITY=y
1129 +CONFIG_REISERFS_FS=m
1130 +CONFIG_REISERFS_FS_XATTR=y
1131 +CONFIG_REISERFS_FS_POSIX_ACL=y
1132 +CONFIG_REISERFS_FS_SECURITY=y
1133 +CONFIG_JFS_FS=m
1134 +CONFIG_JFS_POSIX_ACL=y
1135 +CONFIG_JFS_SECURITY=y
1136 +CONFIG_JFS_STATISTICS=y
1137 +CONFIG_XFS_FS=m
1138 +CONFIG_XFS_QUOTA=y
1139 +CONFIG_XFS_POSIX_ACL=y
1140 +CONFIG_XFS_RT=y
1141 +CONFIG_GFS2_FS=m
1142 +CONFIG_OCFS2_FS=m
1143 +CONFIG_BTRFS_FS=m
1144 +CONFIG_BTRFS_FS_POSIX_ACL=y
1145 +CONFIG_NILFS2_FS=m
1146 +CONFIG_FANOTIFY=y
1147 +CONFIG_AUTOFS4_FS=y
1148 +CONFIG_FUSE_FS=m
1149 +CONFIG_CUSE=m
1150 +CONFIG_FSCACHE=y
1151 +CONFIG_FSCACHE_STATS=y
1152 +CONFIG_FSCACHE_HISTOGRAM=y
1153 +CONFIG_CACHEFILES=y
1154 +CONFIG_ISO9660_FS=m
1155 +CONFIG_JOLIET=y
1156 +CONFIG_ZISOFS=y
1157 +CONFIG_UDF_FS=m
1158 +CONFIG_MSDOS_FS=y
1159 +CONFIG_VFAT_FS=y
1160 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1161 +CONFIG_NTFS_FS=m
1162 +CONFIG_TMPFS=y
1163 +CONFIG_TMPFS_POSIX_ACL=y
1164 +CONFIG_CONFIGFS_FS=y
1165 +CONFIG_SQUASHFS=m
1166 +CONFIG_SQUASHFS_XATTR=y
1167 +CONFIG_SQUASHFS_LZO=y
1168 +CONFIG_SQUASHFS_XZ=y
1169 +CONFIG_NFS_FS=y
1170 +CONFIG_NFS_V3_ACL=y
1171 +CONFIG_NFS_V4=y
1172 +CONFIG_ROOT_NFS=y
1173 +CONFIG_NFS_FSCACHE=y
1174 +CONFIG_NFSD=m
1175 +CONFIG_NFSD_V3_ACL=y
1176 +CONFIG_NFSD_V4=y
1177 +CONFIG_CIFS=m
1178 +CONFIG_CIFS_WEAK_PW_HASH=y
1179 +CONFIG_CIFS_XATTR=y
1180 +CONFIG_CIFS_POSIX=y
1181 +CONFIG_9P_FS=m
1182 +CONFIG_9P_FS_POSIX_ACL=y
1183 +CONFIG_NLS_DEFAULT="utf8"
1184 +CONFIG_NLS_CODEPAGE_437=y
1185 +CONFIG_NLS_CODEPAGE_737=m
1186 +CONFIG_NLS_CODEPAGE_775=m
1187 +CONFIG_NLS_CODEPAGE_850=m
1188 +CONFIG_NLS_CODEPAGE_852=m
1189 +CONFIG_NLS_CODEPAGE_855=m
1190 +CONFIG_NLS_CODEPAGE_857=m
1191 +CONFIG_NLS_CODEPAGE_860=m
1192 +CONFIG_NLS_CODEPAGE_861=m
1193 +CONFIG_NLS_CODEPAGE_862=m
1194 +CONFIG_NLS_CODEPAGE_863=m
1195 +CONFIG_NLS_CODEPAGE_864=m
1196 +CONFIG_NLS_CODEPAGE_865=m
1197 +CONFIG_NLS_CODEPAGE_866=m
1198 +CONFIG_NLS_CODEPAGE_869=m
1199 +CONFIG_NLS_CODEPAGE_936=m
1200 +CONFIG_NLS_CODEPAGE_950=m
1201 +CONFIG_NLS_CODEPAGE_932=m
1202 +CONFIG_NLS_CODEPAGE_949=m
1203 +CONFIG_NLS_CODEPAGE_874=m
1204 +CONFIG_NLS_ISO8859_8=m
1205 +CONFIG_NLS_CODEPAGE_1250=m
1206 +CONFIG_NLS_CODEPAGE_1251=m
1207 +CONFIG_NLS_ASCII=y
1208 +CONFIG_NLS_ISO8859_1=m
1209 +CONFIG_NLS_ISO8859_2=m
1210 +CONFIG_NLS_ISO8859_3=m
1211 +CONFIG_NLS_ISO8859_4=m
1212 +CONFIG_NLS_ISO8859_5=m
1213 +CONFIG_NLS_ISO8859_6=m
1214 +CONFIG_NLS_ISO8859_7=m
1215 +CONFIG_NLS_ISO8859_9=m
1216 +CONFIG_NLS_ISO8859_13=m
1217 +CONFIG_NLS_ISO8859_14=m
1218 +CONFIG_NLS_ISO8859_15=m
1219 +CONFIG_NLS_KOI8_R=m
1220 +CONFIG_NLS_KOI8_U=m
1221 +CONFIG_NLS_UTF8=m
1222 +CONFIG_PRINTK_TIME=y
1223 +CONFIG_DETECT_HUNG_TASK=y
1224 +CONFIG_TIMER_STATS=y
1225 +CONFIG_DEBUG_STACK_USAGE=y
1226 +CONFIG_DEBUG_INFO=y
1227 +CONFIG_DEBUG_MEMORY_INIT=y
1228 +CONFIG_BOOT_PRINTK_DELAY=y
1229 +CONFIG_LATENCYTOP=y
1230 +CONFIG_IRQSOFF_TRACER=y
1231 +CONFIG_SCHED_TRACER=y
1232 +CONFIG_STACK_TRACER=y
1233 +CONFIG_BLK_DEV_IO_TRACE=y
1234 +CONFIG_FUNCTION_PROFILER=y
1235 +CONFIG_KGDB=y
1236 +CONFIG_KGDB_KDB=y
1237 +CONFIG_KDB_KEYBOARD=y
1238 +CONFIG_STRICT_DEVMEM=y
1239 +CONFIG_CRYPTO_SEQIV=m
1240 +CONFIG_CRYPTO_CBC=y
1241 +CONFIG_CRYPTO_HMAC=y
1242 +CONFIG_CRYPTO_XCBC=m
1243 +CONFIG_CRYPTO_MD5=y
1244 +CONFIG_CRYPTO_SHA1=y
1245 +CONFIG_CRYPTO_SHA512=m
1246 +CONFIG_CRYPTO_TGR192=m
1247 +CONFIG_CRYPTO_WP512=m
1248 +CONFIG_CRYPTO_CAST5=m
1249 +CONFIG_CRYPTO_DES=y
1250 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1251 +# CONFIG_CRYPTO_HW is not set
1252 +CONFIG_CRC_ITU_T=y
1253 +CONFIG_LIBCRC32C=y
1254 --- /dev/null
1255 +++ b/arch/arm/configs/bcmrpi_emergency_defconfig
1256 @@ -0,0 +1,532 @@
1257 +CONFIG_EXPERIMENTAL=y
1258 +# CONFIG_LOCALVERSION_AUTO is not set
1259 +CONFIG_SYSVIPC=y
1260 +CONFIG_POSIX_MQUEUE=y
1261 +CONFIG_BSD_PROCESS_ACCT=y
1262 +CONFIG_BSD_PROCESS_ACCT_V3=y
1263 +CONFIG_FHANDLE=y
1264 +CONFIG_AUDIT=y
1265 +CONFIG_IKCONFIG=y
1266 +CONFIG_IKCONFIG_PROC=y
1267 +CONFIG_BLK_DEV_INITRD=y
1268 +CONFIG_INITRAMFS_SOURCE="../target_fs"
1269 +CONFIG_CGROUP_FREEZER=y
1270 +CONFIG_CGROUP_DEVICE=y
1271 +CONFIG_CGROUP_CPUACCT=y
1272 +CONFIG_RESOURCE_COUNTERS=y
1273 +CONFIG_BLK_CGROUP=y
1274 +CONFIG_NAMESPACES=y
1275 +CONFIG_SCHED_AUTOGROUP=y
1276 +CONFIG_EMBEDDED=y
1277 +# CONFIG_COMPAT_BRK is not set
1278 +CONFIG_SLAB=y
1279 +CONFIG_PROFILING=y
1280 +CONFIG_OPROFILE=m
1281 +CONFIG_KPROBES=y
1282 +CONFIG_MODULES=y
1283 +CONFIG_MODULE_UNLOAD=y
1284 +CONFIG_MODVERSIONS=y
1285 +CONFIG_MODULE_SRCVERSION_ALL=y
1286 +# CONFIG_BLK_DEV_BSG is not set
1287 +CONFIG_BLK_DEV_THROTTLING=y
1288 +CONFIG_CFQ_GROUP_IOSCHED=y
1289 +CONFIG_ARCH_BCM2708=y
1290 +CONFIG_NO_HZ=y
1291 +CONFIG_HIGH_RES_TIMERS=y
1292 +CONFIG_AEABI=y
1293 +CONFIG_SECCOMP=y
1294 +CONFIG_CC_STACKPROTECTOR=y
1295 +CONFIG_ZBOOT_ROM_TEXT=0x0
1296 +CONFIG_ZBOOT_ROM_BSS=0x0
1297 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
1298 +CONFIG_KEXEC=y
1299 +CONFIG_CPU_IDLE=y
1300 +CONFIG_VFP=y
1301 +CONFIG_BINFMT_MISC=m
1302 +CONFIG_NET=y
1303 +CONFIG_PACKET=y
1304 +CONFIG_UNIX=y
1305 +CONFIG_XFRM_USER=y
1306 +CONFIG_NET_KEY=m
1307 +CONFIG_INET=y
1308 +CONFIG_IP_MULTICAST=y
1309 +CONFIG_IP_PNP=y
1310 +CONFIG_IP_PNP_DHCP=y
1311 +CONFIG_IP_PNP_RARP=y
1312 +CONFIG_SYN_COOKIES=y
1313 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
1314 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
1315 +# CONFIG_INET_XFRM_MODE_BEET is not set
1316 +# CONFIG_INET_LRO is not set
1317 +# CONFIG_INET_DIAG is not set
1318 +# CONFIG_IPV6 is not set
1319 +CONFIG_NET_PKTGEN=m
1320 +CONFIG_IRDA=m
1321 +CONFIG_IRLAN=m
1322 +CONFIG_IRCOMM=m
1323 +CONFIG_IRDA_ULTRA=y
1324 +CONFIG_IRDA_CACHE_LAST_LSAP=y
1325 +CONFIG_IRDA_FAST_RR=y
1326 +CONFIG_IRTTY_SIR=m
1327 +CONFIG_KINGSUN_DONGLE=m
1328 +CONFIG_KSDAZZLE_DONGLE=m
1329 +CONFIG_KS959_DONGLE=m
1330 +CONFIG_USB_IRDA=m
1331 +CONFIG_SIGMATEL_FIR=m
1332 +CONFIG_MCS_FIR=m
1333 +CONFIG_BT=m
1334 +CONFIG_BT_L2CAP=y
1335 +CONFIG_BT_SCO=y
1336 +CONFIG_BT_RFCOMM=m
1337 +CONFIG_BT_RFCOMM_TTY=y
1338 +CONFIG_BT_BNEP=m
1339 +CONFIG_BT_BNEP_MC_FILTER=y
1340 +CONFIG_BT_BNEP_PROTO_FILTER=y
1341 +CONFIG_BT_HIDP=m
1342 +CONFIG_BT_HCIBTUSB=m
1343 +CONFIG_BT_HCIBCM203X=m
1344 +CONFIG_BT_HCIBPA10X=m
1345 +CONFIG_BT_HCIBFUSB=m
1346 +CONFIG_BT_HCIVHCI=m
1347 +CONFIG_BT_MRVL=m
1348 +CONFIG_BT_MRVL_SDIO=m
1349 +CONFIG_BT_ATH3K=m
1350 +CONFIG_CFG80211=m
1351 +CONFIG_MAC80211=m
1352 +CONFIG_MAC80211_RC_PID=y
1353 +CONFIG_MAC80211_MESH=y
1354 +CONFIG_WIMAX=m
1355 +CONFIG_NET_9P=m
1356 +CONFIG_NFC=m
1357 +CONFIG_NFC_PN533=m
1358 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
1359 +CONFIG_BLK_DEV_LOOP=y
1360 +CONFIG_BLK_DEV_CRYPTOLOOP=m
1361 +CONFIG_BLK_DEV_NBD=m
1362 +CONFIG_BLK_DEV_RAM=y
1363 +CONFIG_CDROM_PKTCDVD=m
1364 +CONFIG_MISC_DEVICES=y
1365 +CONFIG_SCSI=y
1366 +# CONFIG_SCSI_PROC_FS is not set
1367 +CONFIG_BLK_DEV_SD=y
1368 +CONFIG_BLK_DEV_SR=m
1369 +CONFIG_SCSI_MULTI_LUN=y
1370 +# CONFIG_SCSI_LOWLEVEL is not set
1371 +CONFIG_MD=y
1372 +CONFIG_NETDEVICES=y
1373 +CONFIG_TUN=m
1374 +CONFIG_PHYLIB=m
1375 +CONFIG_MDIO_BITBANG=m
1376 +CONFIG_NET_ETHERNET=y
1377 +# CONFIG_NETDEV_1000 is not set
1378 +# CONFIG_NETDEV_10000 is not set
1379 +CONFIG_LIBERTAS_THINFIRM=m
1380 +CONFIG_LIBERTAS_THINFIRM_USB=m
1381 +CONFIG_AT76C50X_USB=m
1382 +CONFIG_USB_ZD1201=m
1383 +CONFIG_USB_NET_RNDIS_WLAN=m
1384 +CONFIG_RTL8187=m
1385 +CONFIG_MAC80211_HWSIM=m
1386 +CONFIG_ATH_COMMON=m
1387 +CONFIG_ATH9K=m
1388 +CONFIG_ATH9K_HTC=m
1389 +CONFIG_CARL9170=m
1390 +CONFIG_B43=m
1391 +CONFIG_B43LEGACY=m
1392 +CONFIG_HOSTAP=m
1393 +CONFIG_IWM=m
1394 +CONFIG_LIBERTAS=m
1395 +CONFIG_LIBERTAS_USB=m
1396 +CONFIG_LIBERTAS_SDIO=m
1397 +CONFIG_P54_COMMON=m
1398 +CONFIG_P54_USB=m
1399 +CONFIG_RT2X00=m
1400 +CONFIG_RT2500USB=m
1401 +CONFIG_RT73USB=m
1402 +CONFIG_RT2800USB=m
1403 +CONFIG_RT2800USB_RT53XX=y
1404 +CONFIG_RTL8192CU=m
1405 +CONFIG_WL1251=m
1406 +CONFIG_WL12XX_MENU=m
1407 +CONFIG_ZD1211RW=m
1408 +CONFIG_MWIFIEX=m
1409 +CONFIG_MWIFIEX_SDIO=m
1410 +CONFIG_WIMAX_I2400M_USB=m
1411 +CONFIG_USB_CATC=m
1412 +CONFIG_USB_KAWETH=m
1413 +CONFIG_USB_PEGASUS=m
1414 +CONFIG_USB_RTL8150=m
1415 +CONFIG_USB_USBNET=y
1416 +CONFIG_USB_NET_AX8817X=m
1417 +CONFIG_USB_NET_CDCETHER=m
1418 +CONFIG_USB_NET_CDC_EEM=m
1419 +CONFIG_USB_NET_DM9601=m
1420 +CONFIG_USB_NET_SMSC75XX=m
1421 +CONFIG_USB_NET_SMSC95XX=y
1422 +CONFIG_USB_NET_GL620A=m
1423 +CONFIG_USB_NET_NET1080=m
1424 +CONFIG_USB_NET_PLUSB=m
1425 +CONFIG_USB_NET_MCS7830=m
1426 +CONFIG_USB_NET_CDC_SUBSET=m
1427 +CONFIG_USB_ALI_M5632=y
1428 +CONFIG_USB_AN2720=y
1429 +CONFIG_USB_KC2190=y
1430 +# CONFIG_USB_NET_ZAURUS is not set
1431 +CONFIG_USB_NET_CX82310_ETH=m
1432 +CONFIG_USB_NET_KALMIA=m
1433 +CONFIG_USB_NET_INT51X1=m
1434 +CONFIG_USB_IPHETH=m
1435 +CONFIG_USB_SIERRA_NET=m
1436 +CONFIG_USB_VL600=m
1437 +CONFIG_PPP=m
1438 +CONFIG_PPP_ASYNC=m
1439 +CONFIG_PPP_SYNC_TTY=m
1440 +CONFIG_PPP_DEFLATE=m
1441 +CONFIG_PPP_BSDCOMP=m
1442 +CONFIG_SLIP=m
1443 +CONFIG_SLIP_COMPRESSED=y
1444 +CONFIG_NETCONSOLE=m
1445 +CONFIG_INPUT_POLLDEV=m
1446 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
1447 +CONFIG_INPUT_JOYDEV=m
1448 +CONFIG_INPUT_EVDEV=m
1449 +# CONFIG_INPUT_KEYBOARD is not set
1450 +# CONFIG_INPUT_MOUSE is not set
1451 +CONFIG_INPUT_MISC=y
1452 +CONFIG_INPUT_AD714X=m
1453 +CONFIG_INPUT_ATI_REMOTE=m
1454 +CONFIG_INPUT_ATI_REMOTE2=m
1455 +CONFIG_INPUT_KEYSPAN_REMOTE=m
1456 +CONFIG_INPUT_POWERMATE=m
1457 +CONFIG_INPUT_YEALINK=m
1458 +CONFIG_INPUT_CM109=m
1459 +CONFIG_INPUT_UINPUT=m
1460 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
1461 +CONFIG_INPUT_ADXL34X=m
1462 +CONFIG_INPUT_CMA3000=m
1463 +CONFIG_SERIO=m
1464 +CONFIG_SERIO_RAW=m
1465 +CONFIG_GAMEPORT=m
1466 +CONFIG_GAMEPORT_NS558=m
1467 +CONFIG_GAMEPORT_L4=m
1468 +CONFIG_VT_HW_CONSOLE_BINDING=y
1469 +# CONFIG_LEGACY_PTYS is not set
1470 +# CONFIG_DEVKMEM is not set
1471 +CONFIG_SERIAL_AMBA_PL011=y
1472 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1473 +# CONFIG_HW_RANDOM is not set
1474 +CONFIG_RAW_DRIVER=y
1475 +CONFIG_GPIO_SYSFS=y
1476 +# CONFIG_HWMON is not set
1477 +CONFIG_WATCHDOG=y
1478 +CONFIG_BCM2708_WDT=m
1479 +# CONFIG_MFD_SUPPORT is not set
1480 +CONFIG_FB=y
1481 +CONFIG_FB_BCM2708=y
1482 +CONFIG_FRAMEBUFFER_CONSOLE=y
1483 +CONFIG_LOGO=y
1484 +# CONFIG_LOGO_LINUX_MONO is not set
1485 +# CONFIG_LOGO_LINUX_VGA16 is not set
1486 +CONFIG_SOUND=y
1487 +CONFIG_SND=m
1488 +CONFIG_SND_SEQUENCER=m
1489 +CONFIG_SND_SEQ_DUMMY=m
1490 +CONFIG_SND_MIXER_OSS=m
1491 +CONFIG_SND_PCM_OSS=m
1492 +CONFIG_SND_SEQUENCER_OSS=y
1493 +CONFIG_SND_HRTIMER=m
1494 +CONFIG_SND_DUMMY=m
1495 +CONFIG_SND_ALOOP=m
1496 +CONFIG_SND_VIRMIDI=m
1497 +CONFIG_SND_MTPAV=m
1498 +CONFIG_SND_SERIAL_U16550=m
1499 +CONFIG_SND_MPU401=m
1500 +CONFIG_SND_BCM2835=m
1501 +CONFIG_SND_USB_AUDIO=m
1502 +CONFIG_SND_USB_UA101=m
1503 +CONFIG_SND_USB_CAIAQ=m
1504 +CONFIG_SND_USB_6FIRE=m
1505 +CONFIG_SOUND_PRIME=m
1506 +CONFIG_HID_PID=y
1507 +CONFIG_USB_HIDDEV=y
1508 +CONFIG_HID_A4TECH=m
1509 +CONFIG_HID_ACRUX=m
1510 +CONFIG_HID_APPLE=m
1511 +CONFIG_HID_BELKIN=m
1512 +CONFIG_HID_CHERRY=m
1513 +CONFIG_HID_CHICONY=m
1514 +CONFIG_HID_CYPRESS=m
1515 +CONFIG_HID_DRAGONRISE=m
1516 +CONFIG_HID_EMS_FF=m
1517 +CONFIG_HID_ELECOM=m
1518 +CONFIG_HID_EZKEY=m
1519 +CONFIG_HID_HOLTEK=m
1520 +CONFIG_HID_KEYTOUCH=m
1521 +CONFIG_HID_KYE=m
1522 +CONFIG_HID_UCLOGIC=m
1523 +CONFIG_HID_WALTOP=m
1524 +CONFIG_HID_GYRATION=m
1525 +CONFIG_HID_TWINHAN=m
1526 +CONFIG_HID_KENSINGTON=m
1527 +CONFIG_HID_LCPOWER=m
1528 +CONFIG_HID_LOGITECH=m
1529 +CONFIG_HID_MAGICMOUSE=m
1530 +CONFIG_HID_MICROSOFT=m
1531 +CONFIG_HID_MONTEREY=m
1532 +CONFIG_HID_MULTITOUCH=m
1533 +CONFIG_HID_NTRIG=m
1534 +CONFIG_HID_ORTEK=m
1535 +CONFIG_HID_PANTHERLORD=m
1536 +CONFIG_HID_PETALYNX=m
1537 +CONFIG_HID_PICOLCD=m
1538 +CONFIG_HID_QUANTA=m
1539 +CONFIG_HID_ROCCAT=m
1540 +CONFIG_HID_SAMSUNG=m
1541 +CONFIG_HID_SONY=m
1542 +CONFIG_HID_SPEEDLINK=m
1543 +CONFIG_HID_SUNPLUS=m
1544 +CONFIG_HID_GREENASIA=m
1545 +CONFIG_HID_SMARTJOYPLUS=m
1546 +CONFIG_HID_TOPSEED=m
1547 +CONFIG_HID_THRUSTMASTER=m
1548 +CONFIG_HID_WACOM=m
1549 +CONFIG_HID_WIIMOTE=m
1550 +CONFIG_HID_ZEROPLUS=m
1551 +CONFIG_HID_ZYDACRON=m
1552 +CONFIG_USB=y
1553 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1554 +CONFIG_USB_MON=m
1555 +CONFIG_USB_DWCOTG=y
1556 +CONFIG_USB_STORAGE=y
1557 +CONFIG_USB_STORAGE_REALTEK=m
1558 +CONFIG_USB_STORAGE_DATAFAB=m
1559 +CONFIG_USB_STORAGE_FREECOM=m
1560 +CONFIG_USB_STORAGE_ISD200=m
1561 +CONFIG_USB_STORAGE_USBAT=m
1562 +CONFIG_USB_STORAGE_SDDR09=m
1563 +CONFIG_USB_STORAGE_SDDR55=m
1564 +CONFIG_USB_STORAGE_JUMPSHOT=m
1565 +CONFIG_USB_STORAGE_ALAUDA=m
1566 +CONFIG_USB_STORAGE_ONETOUCH=m
1567 +CONFIG_USB_STORAGE_KARMA=m
1568 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
1569 +CONFIG_USB_STORAGE_ENE_UB6250=m
1570 +CONFIG_USB_UAS=y
1571 +CONFIG_USB_LIBUSUAL=y
1572 +CONFIG_USB_MDC800=m
1573 +CONFIG_USB_MICROTEK=m
1574 +CONFIG_USB_SERIAL=m
1575 +CONFIG_USB_SERIAL_GENERIC=y
1576 +CONFIG_USB_SERIAL_AIRCABLE=m
1577 +CONFIG_USB_SERIAL_ARK3116=m
1578 +CONFIG_USB_SERIAL_BELKIN=m
1579 +CONFIG_USB_SERIAL_CH341=m
1580 +CONFIG_USB_SERIAL_WHITEHEAT=m
1581 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
1582 +CONFIG_USB_SERIAL_CP210X=m
1583 +CONFIG_USB_SERIAL_CYPRESS_M8=m
1584 +CONFIG_USB_SERIAL_EMPEG=m
1585 +CONFIG_USB_SERIAL_FTDI_SIO=m
1586 +CONFIG_USB_SERIAL_FUNSOFT=m
1587 +CONFIG_USB_SERIAL_VISOR=m
1588 +CONFIG_USB_SERIAL_IPAQ=m
1589 +CONFIG_USB_SERIAL_IR=m
1590 +CONFIG_USB_SERIAL_EDGEPORT=m
1591 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
1592 +CONFIG_USB_SERIAL_GARMIN=m
1593 +CONFIG_USB_SERIAL_IPW=m
1594 +CONFIG_USB_SERIAL_IUU=m
1595 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
1596 +CONFIG_USB_SERIAL_KEYSPAN=m
1597 +CONFIG_USB_SERIAL_KLSI=m
1598 +CONFIG_USB_SERIAL_KOBIL_SCT=m
1599 +CONFIG_USB_SERIAL_MCT_U232=m
1600 +CONFIG_USB_SERIAL_MOS7720=m
1601 +CONFIG_USB_SERIAL_MOS7840=m
1602 +CONFIG_USB_SERIAL_MOTOROLA=m
1603 +CONFIG_USB_SERIAL_NAVMAN=m
1604 +CONFIG_USB_SERIAL_PL2303=m
1605 +CONFIG_USB_SERIAL_OTI6858=m
1606 +CONFIG_USB_SERIAL_QCAUX=m
1607 +CONFIG_USB_SERIAL_QUALCOMM=m
1608 +CONFIG_USB_SERIAL_SPCP8X5=m
1609 +CONFIG_USB_SERIAL_HP4X=m
1610 +CONFIG_USB_SERIAL_SAFE=m
1611 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
1612 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
1613 +CONFIG_USB_SERIAL_SYMBOL=m
1614 +CONFIG_USB_SERIAL_TI=m
1615 +CONFIG_USB_SERIAL_CYBERJACK=m
1616 +CONFIG_USB_SERIAL_XIRCOM=m
1617 +CONFIG_USB_SERIAL_OPTION=m
1618 +CONFIG_USB_SERIAL_OMNINET=m
1619 +CONFIG_USB_SERIAL_OPTICON=m
1620 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
1621 +CONFIG_USB_SERIAL_ZIO=m
1622 +CONFIG_USB_SERIAL_SSU100=m
1623 +CONFIG_USB_SERIAL_DEBUG=m
1624 +CONFIG_USB_EMI62=m
1625 +CONFIG_USB_EMI26=m
1626 +CONFIG_USB_ADUTUX=m
1627 +CONFIG_USB_SEVSEG=m
1628 +CONFIG_USB_RIO500=m
1629 +CONFIG_USB_LEGOTOWER=m
1630 +CONFIG_USB_LCD=m
1631 +CONFIG_USB_LED=m
1632 +CONFIG_USB_CYPRESS_CY7C63=m
1633 +CONFIG_USB_CYTHERM=m
1634 +CONFIG_USB_IDMOUSE=m
1635 +CONFIG_USB_FTDI_ELAN=m
1636 +CONFIG_USB_APPLEDISPLAY=m
1637 +CONFIG_USB_LD=m
1638 +CONFIG_USB_TRANCEVIBRATOR=m
1639 +CONFIG_USB_IOWARRIOR=m
1640 +CONFIG_USB_TEST=m
1641 +CONFIG_USB_ISIGHTFW=m
1642 +CONFIG_USB_YUREX=m
1643 +CONFIG_MMC=y
1644 +CONFIG_MMC_SDHCI=y
1645 +CONFIG_MMC_SDHCI_PLTFM=y
1646 +CONFIG_MMC_SDHCI_BCM2708=y
1647 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1648 +CONFIG_LEDS_GPIO=y
1649 +CONFIG_LEDS_TRIGGER_TIMER=m
1650 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1651 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
1652 +CONFIG_UIO=m
1653 +CONFIG_UIO_PDRV=m
1654 +CONFIG_UIO_PDRV_GENIRQ=m
1655 +# CONFIG_IOMMU_SUPPORT is not set
1656 +CONFIG_EXT4_FS=y
1657 +CONFIG_EXT4_FS_POSIX_ACL=y
1658 +CONFIG_EXT4_FS_SECURITY=y
1659 +CONFIG_REISERFS_FS=m
1660 +CONFIG_REISERFS_FS_XATTR=y
1661 +CONFIG_REISERFS_FS_POSIX_ACL=y
1662 +CONFIG_REISERFS_FS_SECURITY=y
1663 +CONFIG_JFS_FS=m
1664 +CONFIG_JFS_POSIX_ACL=y
1665 +CONFIG_JFS_SECURITY=y
1666 +CONFIG_JFS_STATISTICS=y
1667 +CONFIG_XFS_FS=m
1668 +CONFIG_XFS_QUOTA=y
1669 +CONFIG_XFS_POSIX_ACL=y
1670 +CONFIG_XFS_RT=y
1671 +CONFIG_GFS2_FS=m
1672 +CONFIG_OCFS2_FS=m
1673 +CONFIG_BTRFS_FS=m
1674 +CONFIG_BTRFS_FS_POSIX_ACL=y
1675 +CONFIG_NILFS2_FS=m
1676 +CONFIG_FANOTIFY=y
1677 +CONFIG_AUTOFS4_FS=y
1678 +CONFIG_FUSE_FS=m
1679 +CONFIG_CUSE=m
1680 +CONFIG_FSCACHE=y
1681 +CONFIG_FSCACHE_STATS=y
1682 +CONFIG_FSCACHE_HISTOGRAM=y
1683 +CONFIG_CACHEFILES=y
1684 +CONFIG_ISO9660_FS=m
1685 +CONFIG_JOLIET=y
1686 +CONFIG_ZISOFS=y
1687 +CONFIG_UDF_FS=m
1688 +CONFIG_MSDOS_FS=y
1689 +CONFIG_VFAT_FS=y
1690 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1691 +CONFIG_NTFS_FS=m
1692 +CONFIG_TMPFS=y
1693 +CONFIG_TMPFS_POSIX_ACL=y
1694 +CONFIG_CONFIGFS_FS=y
1695 +CONFIG_SQUASHFS=m
1696 +CONFIG_SQUASHFS_XATTR=y
1697 +CONFIG_SQUASHFS_LZO=y
1698 +CONFIG_SQUASHFS_XZ=y
1699 +CONFIG_NFS_FS=y
1700 +CONFIG_NFS_V3=y
1701 +CONFIG_NFS_V3_ACL=y
1702 +CONFIG_NFS_V4=y
1703 +CONFIG_ROOT_NFS=y
1704 +CONFIG_NFS_FSCACHE=y
1705 +CONFIG_CIFS=m
1706 +CONFIG_CIFS_WEAK_PW_HASH=y
1707 +CONFIG_CIFS_XATTR=y
1708 +CONFIG_CIFS_POSIX=y
1709 +CONFIG_9P_FS=m
1710 +CONFIG_9P_FS_POSIX_ACL=y
1711 +CONFIG_PARTITION_ADVANCED=y
1712 +CONFIG_MAC_PARTITION=y
1713 +CONFIG_EFI_PARTITION=y
1714 +CONFIG_NLS_DEFAULT="utf8"
1715 +CONFIG_NLS_CODEPAGE_437=y
1716 +CONFIG_NLS_CODEPAGE_737=m
1717 +CONFIG_NLS_CODEPAGE_775=m
1718 +CONFIG_NLS_CODEPAGE_850=m
1719 +CONFIG_NLS_CODEPAGE_852=m
1720 +CONFIG_NLS_CODEPAGE_855=m
1721 +CONFIG_NLS_CODEPAGE_857=m
1722 +CONFIG_NLS_CODEPAGE_860=m
1723 +CONFIG_NLS_CODEPAGE_861=m
1724 +CONFIG_NLS_CODEPAGE_862=m
1725 +CONFIG_NLS_CODEPAGE_863=m
1726 +CONFIG_NLS_CODEPAGE_864=m
1727 +CONFIG_NLS_CODEPAGE_865=m
1728 +CONFIG_NLS_CODEPAGE_866=m
1729 +CONFIG_NLS_CODEPAGE_869=m
1730 +CONFIG_NLS_CODEPAGE_936=m
1731 +CONFIG_NLS_CODEPAGE_950=m
1732 +CONFIG_NLS_CODEPAGE_932=m
1733 +CONFIG_NLS_CODEPAGE_949=m
1734 +CONFIG_NLS_CODEPAGE_874=m
1735 +CONFIG_NLS_ISO8859_8=m
1736 +CONFIG_NLS_CODEPAGE_1250=m
1737 +CONFIG_NLS_CODEPAGE_1251=m
1738 +CONFIG_NLS_ASCII=y
1739 +CONFIG_NLS_ISO8859_1=m
1740 +CONFIG_NLS_ISO8859_2=m
1741 +CONFIG_NLS_ISO8859_3=m
1742 +CONFIG_NLS_ISO8859_4=m
1743 +CONFIG_NLS_ISO8859_5=m
1744 +CONFIG_NLS_ISO8859_6=m
1745 +CONFIG_NLS_ISO8859_7=m
1746 +CONFIG_NLS_ISO8859_9=m
1747 +CONFIG_NLS_ISO8859_13=m
1748 +CONFIG_NLS_ISO8859_14=m
1749 +CONFIG_NLS_ISO8859_15=m
1750 +CONFIG_NLS_KOI8_R=m
1751 +CONFIG_NLS_KOI8_U=m
1752 +CONFIG_NLS_UTF8=m
1753 +CONFIG_PRINTK_TIME=y
1754 +CONFIG_DETECT_HUNG_TASK=y
1755 +CONFIG_TIMER_STATS=y
1756 +CONFIG_DEBUG_STACK_USAGE=y
1757 +CONFIG_DEBUG_INFO=y
1758 +CONFIG_DEBUG_MEMORY_INIT=y
1759 +CONFIG_BOOT_PRINTK_DELAY=y
1760 +CONFIG_LATENCYTOP=y
1761 +CONFIG_SYSCTL_SYSCALL_CHECK=y
1762 +CONFIG_IRQSOFF_TRACER=y
1763 +CONFIG_SCHED_TRACER=y
1764 +CONFIG_STACK_TRACER=y
1765 +CONFIG_BLK_DEV_IO_TRACE=y
1766 +CONFIG_FUNCTION_PROFILER=y
1767 +CONFIG_KGDB=y
1768 +CONFIG_KGDB_KDB=y
1769 +CONFIG_KDB_KEYBOARD=y
1770 +CONFIG_STRICT_DEVMEM=y
1771 +CONFIG_CRYPTO_AUTHENC=m
1772 +CONFIG_CRYPTO_SEQIV=m
1773 +CONFIG_CRYPTO_CBC=y
1774 +CONFIG_CRYPTO_HMAC=y
1775 +CONFIG_CRYPTO_XCBC=m
1776 +CONFIG_CRYPTO_MD5=y
1777 +CONFIG_CRYPTO_SHA1=y
1778 +CONFIG_CRYPTO_SHA256=m
1779 +CONFIG_CRYPTO_SHA512=m
1780 +CONFIG_CRYPTO_TGR192=m
1781 +CONFIG_CRYPTO_WP512=m
1782 +CONFIG_CRYPTO_CAST5=m
1783 +CONFIG_CRYPTO_DES=y
1784 +CONFIG_CRYPTO_DEFLATE=m
1785 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1786 +# CONFIG_CRYPTO_HW is not set
1787 +CONFIG_CRC_ITU_T=y
1788 +CONFIG_LIBCRC32C=y
1789 --- /dev/null
1790 +++ b/arch/arm/configs/bcmrpi_quick_defconfig
1791 @@ -0,0 +1,197 @@
1792 +# CONFIG_ARM_PATCH_PHYS_VIRT is not set
1793 +CONFIG_LOCALVERSION="-quick"
1794 +# CONFIG_LOCALVERSION_AUTO is not set
1795 +# CONFIG_SWAP is not set
1796 +CONFIG_SYSVIPC=y
1797 +CONFIG_POSIX_MQUEUE=y
1798 +CONFIG_NO_HZ=y
1799 +CONFIG_HIGH_RES_TIMERS=y
1800 +CONFIG_IKCONFIG=y
1801 +CONFIG_IKCONFIG_PROC=y
1802 +CONFIG_KALLSYMS_ALL=y
1803 +CONFIG_EMBEDDED=y
1804 +CONFIG_PERF_EVENTS=y
1805 +# CONFIG_COMPAT_BRK is not set
1806 +CONFIG_SLAB=y
1807 +CONFIG_MODULES=y
1808 +CONFIG_MODULE_UNLOAD=y
1809 +CONFIG_MODVERSIONS=y
1810 +CONFIG_MODULE_SRCVERSION_ALL=y
1811 +# CONFIG_BLK_DEV_BSG is not set
1812 +CONFIG_ARCH_BCM2708=y
1813 +CONFIG_PREEMPT=y
1814 +CONFIG_AEABI=y
1815 +CONFIG_UACCESS_WITH_MEMCPY=y
1816 +CONFIG_ZBOOT_ROM_TEXT=0x0
1817 +CONFIG_ZBOOT_ROM_BSS=0x0
1818 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
1819 +CONFIG_CPU_FREQ=y
1820 +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
1821 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
1822 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
1823 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
1824 +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
1825 +CONFIG_CPU_IDLE=y
1826 +CONFIG_VFP=y
1827 +CONFIG_BINFMT_MISC=y
1828 +CONFIG_NET=y
1829 +CONFIG_PACKET=y
1830 +CONFIG_UNIX=y
1831 +CONFIG_INET=y
1832 +CONFIG_IP_MULTICAST=y
1833 +CONFIG_IP_PNP=y
1834 +CONFIG_IP_PNP_DHCP=y
1835 +CONFIG_IP_PNP_RARP=y
1836 +CONFIG_SYN_COOKIES=y
1837 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
1838 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
1839 +# CONFIG_INET_XFRM_MODE_BEET is not set
1840 +# CONFIG_INET_LRO is not set
1841 +# CONFIG_INET_DIAG is not set
1842 +# CONFIG_IPV6 is not set
1843 +# CONFIG_WIRELESS is not set
1844 +CONFIG_DEVTMPFS=y
1845 +CONFIG_DEVTMPFS_MOUNT=y
1846 +CONFIG_BLK_DEV_LOOP=y
1847 +CONFIG_BLK_DEV_RAM=y
1848 +CONFIG_SCSI=y
1849 +# CONFIG_SCSI_PROC_FS is not set
1850 +# CONFIG_SCSI_LOWLEVEL is not set
1851 +CONFIG_NETDEVICES=y
1852 +# CONFIG_NET_VENDOR_BROADCOM is not set
1853 +# CONFIG_NET_VENDOR_CIRRUS is not set
1854 +# CONFIG_NET_VENDOR_FARADAY is not set
1855 +# CONFIG_NET_VENDOR_INTEL is not set
1856 +# CONFIG_NET_VENDOR_MARVELL is not set
1857 +# CONFIG_NET_VENDOR_MICREL is not set
1858 +# CONFIG_NET_VENDOR_NATSEMI is not set
1859 +# CONFIG_NET_VENDOR_SEEQ is not set
1860 +# CONFIG_NET_VENDOR_STMICRO is not set
1861 +# CONFIG_NET_VENDOR_WIZNET is not set
1862 +CONFIG_USB_USBNET=y
1863 +# CONFIG_USB_NET_AX8817X is not set
1864 +# CONFIG_USB_NET_CDCETHER is not set
1865 +# CONFIG_USB_NET_CDC_NCM is not set
1866 +CONFIG_USB_NET_SMSC95XX=y
1867 +# CONFIG_USB_NET_NET1080 is not set
1868 +# CONFIG_USB_NET_CDC_SUBSET is not set
1869 +# CONFIG_USB_NET_ZAURUS is not set
1870 +# CONFIG_WLAN is not set
1871 +# CONFIG_INPUT_MOUSEDEV is not set
1872 +CONFIG_INPUT_EVDEV=y
1873 +# CONFIG_INPUT_KEYBOARD is not set
1874 +# CONFIG_INPUT_MOUSE is not set
1875 +# CONFIG_SERIO is not set
1876 +CONFIG_VT_HW_CONSOLE_BINDING=y
1877 +# CONFIG_LEGACY_PTYS is not set
1878 +# CONFIG_DEVKMEM is not set
1879 +CONFIG_SERIAL_AMBA_PL011=y
1880 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1881 +CONFIG_TTY_PRINTK=y
1882 +CONFIG_HW_RANDOM=y
1883 +CONFIG_HW_RANDOM_BCM2708=y
1884 +CONFIG_RAW_DRIVER=y
1885 +CONFIG_THERMAL=y
1886 +CONFIG_THERMAL_BCM2835=y
1887 +CONFIG_WATCHDOG=y
1888 +CONFIG_BCM2708_WDT=y
1889 +CONFIG_REGULATOR=y
1890 +CONFIG_REGULATOR_DEBUG=y
1891 +CONFIG_REGULATOR_FIXED_VOLTAGE=y
1892 +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
1893 +CONFIG_REGULATOR_USERSPACE_CONSUMER=y
1894 +CONFIG_FB=y
1895 +CONFIG_FB_BCM2708=y
1896 +CONFIG_FRAMEBUFFER_CONSOLE=y
1897 +CONFIG_LOGO=y
1898 +# CONFIG_LOGO_LINUX_MONO is not set
1899 +# CONFIG_LOGO_LINUX_VGA16 is not set
1900 +CONFIG_SOUND=y
1901 +CONFIG_SND=y
1902 +CONFIG_SND_BCM2835=y
1903 +# CONFIG_SND_USB is not set
1904 +CONFIG_USB=y
1905 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1906 +CONFIG_USB_DWCOTG=y
1907 +CONFIG_MMC=y
1908 +CONFIG_MMC_SDHCI=y
1909 +CONFIG_MMC_SDHCI_PLTFM=y
1910 +CONFIG_MMC_SDHCI_BCM2708=y
1911 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1912 +CONFIG_NEW_LEDS=y
1913 +CONFIG_LEDS_CLASS=y
1914 +CONFIG_LEDS_TRIGGERS=y
1915 +# CONFIG_IOMMU_SUPPORT is not set
1916 +CONFIG_EXT4_FS=y
1917 +CONFIG_EXT4_FS_POSIX_ACL=y
1918 +CONFIG_EXT4_FS_SECURITY=y
1919 +CONFIG_AUTOFS4_FS=y
1920 +CONFIG_FSCACHE=y
1921 +CONFIG_CACHEFILES=y
1922 +CONFIG_MSDOS_FS=y
1923 +CONFIG_VFAT_FS=y
1924 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1925 +CONFIG_TMPFS=y
1926 +CONFIG_TMPFS_POSIX_ACL=y
1927 +CONFIG_CONFIGFS_FS=y
1928 +# CONFIG_MISC_FILESYSTEMS is not set
1929 +CONFIG_NFS_FS=y
1930 +CONFIG_NFS_V3_ACL=y
1931 +CONFIG_NFS_V4=y
1932 +CONFIG_ROOT_NFS=y
1933 +CONFIG_NFS_FSCACHE=y
1934 +CONFIG_NLS_DEFAULT="utf8"
1935 +CONFIG_NLS_CODEPAGE_437=y
1936 +CONFIG_NLS_CODEPAGE_737=y
1937 +CONFIG_NLS_CODEPAGE_775=y
1938 +CONFIG_NLS_CODEPAGE_850=y
1939 +CONFIG_NLS_CODEPAGE_852=y
1940 +CONFIG_NLS_CODEPAGE_855=y
1941 +CONFIG_NLS_CODEPAGE_857=y
1942 +CONFIG_NLS_CODEPAGE_860=y
1943 +CONFIG_NLS_CODEPAGE_861=y
1944 +CONFIG_NLS_CODEPAGE_862=y
1945 +CONFIG_NLS_CODEPAGE_863=y
1946 +CONFIG_NLS_CODEPAGE_864=y
1947 +CONFIG_NLS_CODEPAGE_865=y
1948 +CONFIG_NLS_CODEPAGE_866=y
1949 +CONFIG_NLS_CODEPAGE_869=y
1950 +CONFIG_NLS_CODEPAGE_936=y
1951 +CONFIG_NLS_CODEPAGE_950=y
1952 +CONFIG_NLS_CODEPAGE_932=y
1953 +CONFIG_NLS_CODEPAGE_949=y
1954 +CONFIG_NLS_CODEPAGE_874=y
1955 +CONFIG_NLS_ISO8859_8=y
1956 +CONFIG_NLS_CODEPAGE_1250=y
1957 +CONFIG_NLS_CODEPAGE_1251=y
1958 +CONFIG_NLS_ASCII=y
1959 +CONFIG_NLS_ISO8859_1=y
1960 +CONFIG_NLS_ISO8859_2=y
1961 +CONFIG_NLS_ISO8859_3=y
1962 +CONFIG_NLS_ISO8859_4=y
1963 +CONFIG_NLS_ISO8859_5=y
1964 +CONFIG_NLS_ISO8859_6=y
1965 +CONFIG_NLS_ISO8859_7=y
1966 +CONFIG_NLS_ISO8859_9=y
1967 +CONFIG_NLS_ISO8859_13=y
1968 +CONFIG_NLS_ISO8859_14=y
1969 +CONFIG_NLS_ISO8859_15=y
1970 +CONFIG_NLS_UTF8=y
1971 +CONFIG_PRINTK_TIME=y
1972 +CONFIG_DEBUG_FS=y
1973 +CONFIG_DETECT_HUNG_TASK=y
1974 +# CONFIG_DEBUG_PREEMPT is not set
1975 +# CONFIG_DEBUG_BUGVERBOSE is not set
1976 +# CONFIG_FTRACE is not set
1977 +CONFIG_KGDB=y
1978 +CONFIG_KGDB_KDB=y
1979 +# CONFIG_ARM_UNWIND is not set
1980 +CONFIG_CRYPTO_CBC=y
1981 +CONFIG_CRYPTO_HMAC=y
1982 +CONFIG_CRYPTO_MD5=y
1983 +CONFIG_CRYPTO_SHA1=y
1984 +CONFIG_CRYPTO_DES=y
1985 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1986 +# CONFIG_CRYPTO_HW is not set
1987 +CONFIG_CRC_ITU_T=y
1988 +CONFIG_LIBCRC32C=y
1989 --- a/arch/arm/include/asm/fiq.h
1990 +++ b/arch/arm/include/asm/fiq.h
1991 @@ -42,6 +42,7 @@ extern void disable_fiq(int fiq);
1992  /* helpers defined in fiqasm.S: */
1993  extern void __set_fiq_regs(unsigned long const *regs);
1994  extern void __get_fiq_regs(unsigned long *regs);
1995 +extern void __FIQ_Branch(unsigned long *regs);
1996
1997  static inline void set_fiq_regs(struct pt_regs const *regs)
1998  {
1999 --- a/arch/arm/Kconfig
2000 +++ b/arch/arm/Kconfig
2001 @@ -361,6 +361,23 @@ config ARCH_AT91
2002           This enables support for systems based on Atmel
2003           AT91RM9200 and AT91SAM9* processors.
2004
2005 +config ARCH_BCM2708
2006 +       bool "Broadcom BCM2708 family"
2007 +       select CPU_V6
2008 +       select ARM_AMBA
2009 +       select HAVE_CLK
2010 +       select HAVE_SCHED_CLOCK
2011 +       select NEED_MACH_MEMORY_H
2012 +       select CLKDEV_LOOKUP
2013 +       select ARCH_HAS_CPUFREQ
2014 +       select GENERIC_CLOCKEVENTS
2015 +       select ARM_ERRATA_411920
2016 +       select MACH_BCM2708
2017 +       select VC4
2018 +       select FIQ
2019 +       help
2020 +         This enables support for Broadcom BCM2708 boards.
2021 +
2022  config ARCH_CLPS711X
2023         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
2024         select ARCH_REQUIRE_GPIOLIB
2025 @@ -1025,6 +1042,7 @@ source "arch/arm/mach-virt/Kconfig"
2026  source "arch/arm/mach-vt8500/Kconfig"
2027
2028  source "arch/arm/mach-w90x900/Kconfig"
2029 +source "arch/arm/mach-bcm2708/Kconfig"
2030
2031  source "arch/arm/mach-zynq/Kconfig"
2032
2033 --- a/arch/arm/Kconfig.debug
2034 +++ b/arch/arm/Kconfig.debug
2035 @@ -519,6 +519,14 @@ choice
2036                   For more details about semihosting, please see
2037                   chapter 8 of DUI0203I_rvct_developer_guide.pdf from ARM Ltd.
2038
2039 +       config DEBUG_BCM2708_UART0
2040 +               bool "Broadcom BCM2708 UART0 (PL011)"
2041 +               depends on MACH_BCM2708
2042 +               help
2043 +                 Say Y here if you want the debug print routines to direct
2044 +                 their output to UART 0. The port must have been initialised
2045 +                 by the boot-loader before use.
2046 +
2047  endchoice
2048
2049  config DEBUG_EXYNOS_UART
2050 --- a/arch/arm/kernel/armksyms.c
2051 +++ b/arch/arm/kernel/armksyms.c
2052 @@ -156,3 +156,7 @@ EXPORT_SYMBOL(__gnu_mcount_nc);
2053  #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
2054  EXPORT_SYMBOL(__pv_phys_offset);
2055  #endif
2056 +
2057 +extern void v6wbi_flush_kern_tlb_range(void);
2058 +EXPORT_SYMBOL(v6wbi_flush_kern_tlb_range);
2059 +
2060 --- a/arch/arm/kernel/fiqasm.S
2061 +++ b/arch/arm/kernel/fiqasm.S
2062 @@ -25,6 +25,9 @@
2063  ENTRY(__set_fiq_regs)
2064         mov     r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
2065         mrs     r1, cpsr
2066 +@@@@@@@@@@@@@@@ hack: enable the fiq here to keep usb driver happy
2067 +       and     r1, #~PSR_F_BIT
2068 +@@@@@@@@@@@@@@@ endhack: (need to find better place for this to happen)
2069         msr     cpsr_c, r2      @ select FIQ mode
2070         mov     r0, r0          @ avoid hazard prior to ARMv4
2071         ldmia   r0!, {r8 - r12}
2072 @@ -47,3 +50,7 @@ ENTRY(__get_fiq_regs)
2073         mov     r0, r0          @ avoid hazard prior to ARMv4
2074         mov     pc, lr
2075  ENDPROC(__get_fiq_regs)
2076 +
2077 +ENTRY(__FIQ_Branch)
2078 +       mov pc, r8
2079 +ENDPROC(__FIQ_Branch)
2080 --- a/arch/arm/kernel/fiq.c
2081 +++ b/arch/arm/kernel/fiq.c
2082 @@ -145,6 +145,7 @@ void disable_fiq(int fiq)
2083  EXPORT_SYMBOL(set_fiq_handler);
2084  EXPORT_SYMBOL(__set_fiq_regs); /* defined in fiqasm.S */
2085  EXPORT_SYMBOL(__get_fiq_regs); /* defined in fiqasm.S */
2086 +EXPORT_SYMBOL(__FIQ_Branch);   /* defined in fiqasm.S */
2087  EXPORT_SYMBOL(claim_fiq);
2088  EXPORT_SYMBOL(release_fiq);
2089  EXPORT_SYMBOL(enable_fiq);
2090 --- /dev/null
2091 +++ b/arch/arm/mach-bcm2708/armctrl.c
2092 @@ -0,0 +1,219 @@
2093 +/*
2094 + *  linux/arch/arm/mach-bcm2708/armctrl.c
2095 + *
2096 + *  Copyright (C) 2010 Broadcom
2097 + *
2098 + * This program is free software; you can redistribute it and/or modify
2099 + * it under the terms of the GNU General Public License as published by
2100 + * the Free Software Foundation; either version 2 of the License, or
2101 + * (at your option) any later version.
2102 + *
2103 + * This program is distributed in the hope that it will be useful,
2104 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2105 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2106 + * GNU General Public License for more details.
2107 + *
2108 + * You should have received a copy of the GNU General Public License
2109 + * along with this program; if not, write to the Free Software
2110 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
2111 + */
2112 +#include <linux/init.h>
2113 +#include <linux/list.h>
2114 +#include <linux/io.h>
2115 +#include <linux/version.h>
2116 +#include <linux/syscore_ops.h>
2117 +#include <linux/interrupt.h>
2118 +
2119 +#include <asm/mach/irq.h>
2120 +#include <mach/hardware.h>
2121 +#include "armctrl.h"
2122 +
2123 +/* For support of kernels >= 3.0 assume only one VIC for now*/
2124 +static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
2125 +       INTERRUPT_VC_JPEG,
2126 +       INTERRUPT_VC_USB,
2127 +       INTERRUPT_VC_3D,
2128 +       INTERRUPT_VC_DMA2,
2129 +       INTERRUPT_VC_DMA3,
2130 +       INTERRUPT_VC_I2C,
2131 +       INTERRUPT_VC_SPI,
2132 +       INTERRUPT_VC_I2SPCM,
2133 +       INTERRUPT_VC_SDIO,
2134 +       INTERRUPT_VC_UART,
2135 +       INTERRUPT_VC_ARASANSDIO
2136 +};
2137 +
2138 +static void armctrl_mask_irq(struct irq_data *d)
2139 +{
2140 +       static const unsigned int disables[4] = {
2141 +               ARM_IRQ_DIBL1,
2142 +               ARM_IRQ_DIBL2,
2143 +               ARM_IRQ_DIBL3,
2144 +               0
2145 +       };
2146 +
2147 +       if (d->irq >= FIQ_START) {
2148 +               writel(0, __io_address(ARM_IRQ_FAST));
2149 +       } else {
2150 +               unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
2151 +               writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
2152 +       }
2153 +}
2154 +
2155 +static void armctrl_unmask_irq(struct irq_data *d)
2156 +{
2157 +       static const unsigned int enables[4] = {
2158 +               ARM_IRQ_ENBL1,
2159 +               ARM_IRQ_ENBL2,
2160 +               ARM_IRQ_ENBL3,
2161 +               0
2162 +       };
2163 +
2164 +       if (d->irq >= FIQ_START) {
2165 +               unsigned int data =
2166 +                   (unsigned int)irq_get_chip_data(d->irq) - FIQ_START;
2167 +               writel(0x80 | data, __io_address(ARM_IRQ_FAST));
2168 +       } else {
2169 +               unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
2170 +               writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
2171 +       }
2172 +}
2173 +
2174 +#if defined(CONFIG_PM)
2175 +
2176 +/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
2177 +
2178 +/* Static defines
2179 + * struct armctrl_device - VIC PM device (< 3.xx)
2180 + * @sysdev: The system device which is registered. (< 3.xx)
2181 + * @irq: The IRQ number for the base of the VIC.
2182 + * @base: The register base for the VIC.
2183 + * @resume_sources: A bitmask of interrupts for resume.
2184 + * @resume_irqs: The IRQs enabled for resume.
2185 + * @int_select: Save for VIC_INT_SELECT.
2186 + * @int_enable: Save for VIC_INT_ENABLE.
2187 + * @soft_int: Save for VIC_INT_SOFT.
2188 + * @protect: Save for VIC_PROTECT.
2189 + */
2190 +struct armctrl_info {
2191 +       void __iomem *base;
2192 +       int irq;
2193 +       u32 resume_sources;
2194 +       u32 resume_irqs;
2195 +       u32 int_select;
2196 +       u32 int_enable;
2197 +       u32 soft_int;
2198 +       u32 protect;
2199 +} armctrl;
2200 +
2201 +static int armctrl_suspend(void)
2202 +{
2203 +       return 0;
2204 +}
2205 +
2206 +static void armctrl_resume(void)
2207 +{
2208 +       return;
2209 +}
2210 +
2211 +/**
2212 + * armctrl_pm_register - Register a VIC for later power management control
2213 + * @base: The base address of the VIC.
2214 + * @irq: The base IRQ for the VIC.
2215 + * @resume_sources: bitmask of interrupts allowed for resume sources.
2216 + *
2217 + * For older kernels (< 3.xx) do -
2218 + * Register the VIC with the system device tree so that it can be notified
2219 + * of suspend and resume requests and ensure that the correct actions are
2220 + * taken to re-instate the settings on resume.
2221 + */
2222 +static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
2223 +                                      u32 resume_sources)
2224 +{
2225 +       armctrl.base = base;
2226 +       armctrl.resume_sources = resume_sources;
2227 +       armctrl.irq = irq;
2228 +}
2229 +
2230 +static int armctrl_set_wake(struct irq_data *d, unsigned int on)
2231 +{
2232 +       unsigned int off = d->irq & 31;
2233 +       u32 bit = 1 << off;
2234 +
2235 +       if (!(bit & armctrl.resume_sources))
2236 +               return -EINVAL;
2237 +
2238 +       if (on)
2239 +               armctrl.resume_irqs |= bit;
2240 +       else
2241 +               armctrl.resume_irqs &= ~bit;
2242 +
2243 +       return 0;
2244 +}
2245 +
2246 +#else
2247 +static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
2248 +                                      u32 arg1)
2249 +{
2250 +}
2251 +
2252 +#define armctrl_suspend NULL
2253 +#define armctrl_resume NULL
2254 +#define armctrl_set_wake NULL
2255 +#endif /* CONFIG_PM */
2256 +
2257 +static struct syscore_ops armctrl_syscore_ops = {
2258 +       .suspend = armctrl_suspend,
2259 +       .resume = armctrl_resume,
2260 +};
2261 +
2262 +/**
2263 + * armctrl_syscore_init - initicall to register VIC pm functions
2264 + *
2265 + * This is called via late_initcall() to register
2266 + * the resources for the VICs due to the early
2267 + * nature of the VIC's registration.
2268 +*/
2269 +static int __init armctrl_syscore_init(void)
2270 +{
2271 +       register_syscore_ops(&armctrl_syscore_ops);
2272 +       return 0;
2273 +}
2274 +
2275 +late_initcall(armctrl_syscore_init);
2276 +
2277 +static struct irq_chip armctrl_chip = {
2278 +       .name = "ARMCTRL",
2279 +       .irq_ack = armctrl_mask_irq,
2280 +       .irq_mask = armctrl_mask_irq,
2281 +       .irq_unmask = armctrl_unmask_irq,
2282 +       .irq_set_wake = armctrl_set_wake,
2283 +};
2284 +
2285 +/**
2286 + * armctrl_init - initialise a vectored interrupt controller
2287 + * @base: iomem base address
2288 + * @irq_start: starting interrupt number, must be muliple of 32
2289 + * @armctrl_sources: bitmask of interrupt sources to allow
2290 + * @resume_sources: bitmask of interrupt sources to allow for resume
2291 + */
2292 +int __init armctrl_init(void __iomem * base, unsigned int irq_start,
2293 +                       u32 armctrl_sources, u32 resume_sources)
2294 +{
2295 +       unsigned int irq;
2296 +
2297 +       for (irq = 0; irq < NR_IRQS; irq++) {
2298 +               unsigned int data = irq;
2299 +               if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
2300 +                       data = remap_irqs[irq - INTERRUPT_JPEG];
2301 +
2302 +               irq_set_chip(irq, &armctrl_chip);
2303 +               irq_set_chip_data(irq, (void *)data);
2304 +               irq_set_handler(irq, handle_level_irq);
2305 +               set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_DISABLED);
2306 +       }
2307 +
2308 +       armctrl_pm_register(base, irq_start, resume_sources);
2309 +       init_FIQ(FIQ_START);
2310 +       return 0;
2311 +}
2312 --- /dev/null
2313 +++ b/arch/arm/mach-bcm2708/armctrl.h
2314 @@ -0,0 +1,27 @@
2315 +/*
2316 + *  linux/arch/arm/mach-bcm2708/armctrl.h
2317 + *
2318 + *  Copyright (C) 2010 Broadcom
2319 + *
2320 + * This program is free software; you can redistribute it and/or modify
2321 + * it under the terms of the GNU General Public License as published by
2322 + * the Free Software Foundation; either version 2 of the License, or
2323 + * (at your option) any later version.
2324 + *
2325 + * This program is distributed in the hope that it will be useful,
2326 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2327 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2328 + * GNU General Public License for more details.
2329 + *
2330 + * You should have received a copy of the GNU General Public License
2331 + * along with this program; if not, write to the Free Software
2332 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
2333 + */
2334 +
2335 +#ifndef __BCM2708_ARMCTRL_H
2336 +#define __BCM2708_ARMCTRL_H
2337 +
2338 +extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
2339 +                              u32 armctrl_sources, u32 resume_sources);
2340 +
2341 +#endif
2342 --- /dev/null
2343 +++ b/arch/arm/mach-bcm2708/bcm2708.c
2344 @@ -0,0 +1,885 @@
2345 +/*
2346 + *  linux/arch/arm/mach-bcm2708/bcm2708.c
2347 + *
2348 + *  Copyright (C) 2010 Broadcom
2349 + *
2350 + * This program is free software; you can redistribute it and/or modify
2351 + * it under the terms of the GNU General Public License as published by
2352 + * the Free Software Foundation; either version 2 of the License, or
2353 + * (at your option) any later version.
2354 + *
2355 + * This program is distributed in the hope that it will be useful,
2356 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2357 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2358 + * GNU General Public License for more details.
2359 + *
2360 + * You should have received a copy of the GNU General Public License
2361 + * along with this program; if not, write to the Free Software
2362 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
2363 + */
2364 +
2365 +#include <linux/init.h>
2366 +#include <linux/device.h>
2367 +#include <linux/dma-mapping.h>
2368 +#include <linux/serial_8250.h>
2369 +#include <linux/platform_device.h>
2370 +#include <linux/syscore_ops.h>
2371 +#include <linux/interrupt.h>
2372 +#include <linux/amba/bus.h>
2373 +#include <linux/amba/clcd.h>
2374 +#include <linux/clockchips.h>
2375 +#include <linux/cnt32_to_63.h>
2376 +#include <linux/io.h>
2377 +#include <linux/module.h>
2378 +#include <linux/spi/spi.h>
2379 +#include <linux/w1-gpio.h>
2380 +
2381 +#include <linux/version.h>
2382 +#include <linux/clkdev.h>
2383 +#include <asm/system.h>
2384 +#include <mach/hardware.h>
2385 +#include <asm/irq.h>
2386 +#include <linux/leds.h>
2387 +#include <asm/mach-types.h>
2388 +#include <asm/sched_clock.h>
2389 +
2390 +#include <asm/mach/arch.h>
2391 +#include <asm/mach/flash.h>
2392 +#include <asm/mach/irq.h>
2393 +#include <asm/mach/time.h>
2394 +#include <asm/mach/map.h>
2395 +
2396 +#include <mach/timex.h>
2397 +#include <mach/dma.h>
2398 +#include <mach/vcio.h>
2399 +#include <mach/system.h>
2400 +
2401 +#include <linux/delay.h>
2402 +
2403 +#include "bcm2708.h"
2404 +#include "armctrl.h"
2405 +#include "clock.h"
2406 +
2407 +#ifdef CONFIG_BCM_VC_CMA
2408 +#include <linux/broadcom/vc_cma.h>
2409 +#endif
2410 +
2411 +
2412 +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
2413 + * give us IO access only to 64Mbytes of physical memory (26 bits).  We could
2414 + * represent this window by setting our dmamasks to 26 bits but, in fact
2415 + * we're not going to use addresses outside this range (they're not in real
2416 + * memory) so we don't bother.
2417 + *
2418 + * In the future we might include code to use this IOMMU to remap other
2419 + * physical addresses onto VideoCore memory then the use of 32-bits would be
2420 + * more legitimate.
2421 + */
2422 +#define DMA_MASK_BITS_COMMON 32
2423 +
2424 +// use GPIO 4 for the one-wire GPIO pin, if enabled
2425 +#define W1_GPIO 4
2426 +
2427 +/* command line parameters */
2428 +static unsigned boardrev, serial;
2429 +static unsigned uart_clock;
2430 +
2431 +static void __init bcm2708_init_led(void);
2432 +
2433 +void __init bcm2708_init_irq(void)
2434 +{
2435 +       armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
2436 +}
2437 +
2438 +static struct map_desc bcm2708_io_desc[] __initdata = {
2439 +       {
2440 +        .virtual = IO_ADDRESS(ARMCTRL_BASE),
2441 +        .pfn = __phys_to_pfn(ARMCTRL_BASE),
2442 +        .length = SZ_4K,
2443 +        .type = MT_DEVICE},
2444 +       {
2445 +        .virtual = IO_ADDRESS(UART0_BASE),
2446 +        .pfn = __phys_to_pfn(UART0_BASE),
2447 +        .length = SZ_4K,
2448 +        .type = MT_DEVICE},
2449 +       {
2450 +        .virtual = IO_ADDRESS(UART1_BASE),
2451 +        .pfn = __phys_to_pfn(UART1_BASE),
2452 +        .length = SZ_4K,
2453 +        .type = MT_DEVICE},
2454 +       {
2455 +        .virtual = IO_ADDRESS(DMA_BASE),
2456 +        .pfn = __phys_to_pfn(DMA_BASE),
2457 +        .length = SZ_4K,
2458 +        .type = MT_DEVICE},
2459 +       {
2460 +        .virtual = IO_ADDRESS(MCORE_BASE),
2461 +        .pfn = __phys_to_pfn(MCORE_BASE),
2462 +        .length = SZ_4K,
2463 +        .type = MT_DEVICE},
2464 +       {
2465 +        .virtual = IO_ADDRESS(ST_BASE),
2466 +        .pfn = __phys_to_pfn(ST_BASE),
2467 +        .length = SZ_4K,
2468 +        .type = MT_DEVICE},
2469 +       {
2470 +        .virtual = IO_ADDRESS(USB_BASE),
2471 +        .pfn = __phys_to_pfn(USB_BASE),
2472 +        .length = SZ_128K,
2473 +        .type = MT_DEVICE},
2474 +       {
2475 +        .virtual = IO_ADDRESS(PM_BASE),
2476 +        .pfn = __phys_to_pfn(PM_BASE),
2477 +        .length = SZ_4K,
2478 +        .type = MT_DEVICE},
2479 +       {
2480 +        .virtual = IO_ADDRESS(GPIO_BASE),
2481 +        .pfn = __phys_to_pfn(GPIO_BASE),
2482 +        .length = SZ_4K,
2483 +        .type = MT_DEVICE}
2484 +};
2485 +
2486 +void __init bcm2708_map_io(void)
2487 +{
2488 +       iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc));
2489 +}
2490 +
2491 +/* The STC is a free running counter that increments at the rate of 1MHz */
2492 +#define STC_FREQ_HZ 1000000
2493 +
2494 +static inline uint32_t timer_read(void)
2495 +{
2496 +       /* STC: a free running counter that increments at the rate of 1MHz */
2497 +       return readl(__io_address(ST_BASE + 0x04));
2498 +}
2499 +
2500 +static unsigned long bcm2708_read_current_timer(void)
2501 +{
2502 +       return timer_read();
2503 +}
2504 +
2505 +static u32 notrace bcm2708_read_sched_clock(void)
2506 +{
2507 +       return timer_read();
2508 +}
2509 +
2510 +static cycle_t clksrc_read(struct clocksource *cs)
2511 +{
2512 +       return timer_read();
2513 +}
2514 +
2515 +static struct clocksource clocksource_stc = {
2516 +       .name = "stc",
2517 +       .rating = 300,
2518 +       .read = clksrc_read,
2519 +       .mask = CLOCKSOURCE_MASK(32),
2520 +       .flags = CLOCK_SOURCE_IS_CONTINUOUS,
2521 +};
2522 +
2523 +unsigned long frc_clock_ticks32(void)
2524 +{
2525 +       return timer_read();
2526 +}
2527 +
2528 +static void __init bcm2708_clocksource_init(void)
2529 +{
2530 +       if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
2531 +               printk(KERN_ERR "timer: failed to initialize clock "
2532 +                      "source %s\n", clocksource_stc.name);
2533 +       }
2534 +}
2535 +
2536 +
2537 +/*
2538 + * These are fixed clocks.
2539 + */
2540 +static struct clk ref24_clk = {
2541 +       .rate = UART0_CLOCK,    /* The UART is clocked at 3MHz via APB_CLK */
2542 +};
2543 +
2544 +static struct clk osc_clk = {
2545 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
2546 +       .rate = 27000000,
2547 +#else
2548 +       .rate = 500000000,      /* ARM clock is set from the VideoCore booter */
2549 +#endif
2550 +};
2551 +
2552 +/* warning - the USB needs a clock > 34MHz */
2553 +
2554 +static struct clk sdhost_clk = {
2555 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
2556 +       .rate = 4000000,        /* 4MHz */
2557 +#else
2558 +       .rate = 250000000,      /* 250MHz */
2559 +#endif
2560 +};
2561 +
2562 +static struct clk_lookup lookups[] = {
2563 +       {                       /* UART0 */
2564 +        .dev_id = "dev:f1",
2565 +        .clk = &ref24_clk,
2566 +        },
2567 +       {                       /* USB */
2568 +        .dev_id = "bcm2708_usb",
2569 +        .clk = &osc_clk,
2570 +        }, {   /* SPI */
2571 +                .dev_id = "bcm2708_spi.0",
2572 +                .clk = &sdhost_clk,
2573 +        }, {   /* BSC0 */
2574 +                .dev_id = "bcm2708_i2c.0",
2575 +                .clk = &sdhost_clk,
2576 +        }, {   /* BSC1 */
2577 +                .dev_id = "bcm2708_i2c.1",
2578 +                .clk = &sdhost_clk,
2579 +        }
2580 +};
2581 +
2582 +#define UART0_IRQ      { IRQ_UART, 0 /*NO_IRQ*/ }
2583 +#define UART0_DMA      { 15, 14 }
2584 +
2585 +AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
2586 +
2587 +static struct amba_device *amba_devs[] __initdata = {
2588 +       &uart0_device,
2589 +};
2590 +
2591 +static struct resource bcm2708_dmaman_resources[] = {
2592 +       {
2593 +        .start = DMA_BASE,
2594 +        .end = DMA_BASE + SZ_4K - 1,
2595 +        .flags = IORESOURCE_MEM,
2596 +        }
2597 +};
2598 +
2599 +static struct platform_device bcm2708_dmaman_device = {
2600 +       .name = BCM_DMAMAN_DRIVER_NAME,
2601 +       .id = 0,                /* first bcm2708_dma */
2602 +       .resource = bcm2708_dmaman_resources,
2603 +       .num_resources = ARRAY_SIZE(bcm2708_dmaman_resources),
2604 +};
2605 +
2606 +#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
2607 +static struct w1_gpio_platform_data w1_gpio_pdata = {
2608 +       .pin = W1_GPIO,
2609 +       .is_open_drain = 0,
2610 +};
2611 +
2612 +static struct platform_device w1_device = {
2613 +       .name = "w1-gpio",
2614 +       .id = -1,
2615 +       .dev.platform_data = &w1_gpio_pdata,
2616 +};
2617 +#endif
2618 +
2619 +static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2620 +
2621 +static struct platform_device bcm2708_fb_device = {
2622 +       .name = "bcm2708_fb",
2623 +       .id = -1,               /* only one bcm2708_fb */
2624 +       .resource = NULL,
2625 +       .num_resources = 0,
2626 +       .dev = {
2627 +               .dma_mask = &fb_dmamask,
2628 +               .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2629 +               },
2630 +};
2631 +
2632 +static struct plat_serial8250_port bcm2708_uart1_platform_data[] = {
2633 +       {
2634 +        .mapbase = UART1_BASE + 0x40,
2635 +        .irq = IRQ_AUX,
2636 +        .uartclk = 125000000,
2637 +        .regshift = 2,
2638 +        .iotype = UPIO_MEM,
2639 +        .flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_SKIP_TEST,
2640 +        .type = PORT_8250,
2641 +        },
2642 +       {},
2643 +};
2644 +
2645 +static struct platform_device bcm2708_uart1_device = {
2646 +       .name = "serial8250",
2647 +       .id = PLAT8250_DEV_PLATFORM,
2648 +       .dev = {
2649 +               .platform_data = bcm2708_uart1_platform_data,
2650 +               },
2651 +};
2652 +
2653 +static struct resource bcm2708_usb_resources[] = {
2654 +       [0] = {
2655 +              .start = USB_BASE,
2656 +              .end = USB_BASE + SZ_128K - 1,
2657 +              .flags = IORESOURCE_MEM,
2658 +              },
2659 +       [1] = {
2660 +               .start = MPHI_BASE,
2661 +               .end = MPHI_BASE + SZ_4K - 1,
2662 +               .flags = IORESOURCE_MEM,
2663 +             },
2664 +       [2] = {
2665 +              .start = IRQ_HOSTPORT,
2666 +              .end = IRQ_HOSTPORT,
2667 +              .flags = IORESOURCE_IRQ,
2668 +              },
2669 +};
2670 +
2671 +bool fiq_fix_enable = true;
2672 +
2673 +static struct resource bcm2708_usb_resources_no_fiq_fix[] = {
2674 +       [0] = {
2675 +               .start = USB_BASE,
2676 +               .end = USB_BASE + SZ_128K - 1,
2677 +               .flags = IORESOURCE_MEM,
2678 +               },
2679 +       [1] = {
2680 +               .start = IRQ_USB,
2681 +               .end = IRQ_USB,
2682 +               .flags = IORESOURCE_IRQ,
2683 +               },
2684 +};
2685 +
2686 +static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2687 +
2688 +static struct platform_device bcm2708_usb_device = {
2689 +       .name = "bcm2708_usb",
2690 +       .id = -1,               /* only one bcm2708_usb */
2691 +       .resource = bcm2708_usb_resources,
2692 +       .num_resources = ARRAY_SIZE(bcm2708_usb_resources),
2693 +       .dev = {
2694 +               .dma_mask = &usb_dmamask,
2695 +               .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2696 +               },
2697 +};
2698 +
2699 +static struct resource bcm2708_vcio_resources[] = {
2700 +       [0] = {                 /* mailbox/semaphore/doorbell access */
2701 +              .start = MCORE_BASE,
2702 +              .end = MCORE_BASE + SZ_4K - 1,
2703 +              .flags = IORESOURCE_MEM,
2704 +              },
2705 +};
2706 +
2707 +static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2708 +
2709 +static struct platform_device bcm2708_vcio_device = {
2710 +       .name = BCM_VCIO_DRIVER_NAME,
2711 +       .id = -1,               /* only one VideoCore I/O area */
2712 +       .resource = bcm2708_vcio_resources,
2713 +       .num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
2714 +       .dev = {
2715 +               .dma_mask = &vcio_dmamask,
2716 +               .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2717 +               },
2718 +};
2719 +
2720 +#ifdef CONFIG_BCM2708_GPIO
2721 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
2722 +
2723 +static struct resource bcm2708_gpio_resources[] = {
2724 +       [0] = {                 /* general purpose I/O */
2725 +              .start = GPIO_BASE,
2726 +              .end = GPIO_BASE + SZ_4K - 1,
2727 +              .flags = IORESOURCE_MEM,
2728 +              },
2729 +};
2730 +
2731 +static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2732 +
2733 +static struct platform_device bcm2708_gpio_device = {
2734 +       .name = BCM_GPIO_DRIVER_NAME,
2735 +       .id = -1,               /* only one VideoCore I/O area */
2736 +       .resource = bcm2708_gpio_resources,
2737 +       .num_resources = ARRAY_SIZE(bcm2708_gpio_resources),
2738 +       .dev = {
2739 +               .dma_mask = &gpio_dmamask,
2740 +               .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2741 +               },
2742 +};
2743 +#endif
2744 +
2745 +static struct resource bcm2708_systemtimer_resources[] = {
2746 +       [0] = {                 /* system timer access */
2747 +              .start = ST_BASE,
2748 +              .end = ST_BASE + SZ_4K - 1,
2749 +              .flags = IORESOURCE_MEM,
2750 +              },
2751 +       {
2752 +        .start = IRQ_TIMER3,
2753 +        .end = IRQ_TIMER3,
2754 +        .flags = IORESOURCE_IRQ,
2755 +        }
2756 +
2757 +};
2758 +
2759 +static u64 systemtimer_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2760 +
2761 +static struct platform_device bcm2708_systemtimer_device = {
2762 +       .name = "bcm2708_systemtimer",
2763 +       .id = -1,               /* only one VideoCore I/O area */
2764 +       .resource = bcm2708_systemtimer_resources,
2765 +       .num_resources = ARRAY_SIZE(bcm2708_systemtimer_resources),
2766 +       .dev = {
2767 +               .dma_mask = &systemtimer_dmamask,
2768 +               .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2769 +               },
2770 +};
2771 +
2772 +#ifdef CONFIG_MMC_SDHCI_BCM2708        /* Arasan emmc SD */
2773 +static struct resource bcm2708_emmc_resources[] = {
2774 +       [0] = {
2775 +              .start = EMMC_BASE,
2776 +              .end = EMMC_BASE + SZ_256 - 1,   /* we only need this area */
2777 +              /* the memory map actually makes SZ_4K available  */
2778 +              .flags = IORESOURCE_MEM,
2779 +              },
2780 +       [1] = {
2781 +              .start = IRQ_ARASANSDIO,
2782 +              .end = IRQ_ARASANSDIO,
2783 +              .flags = IORESOURCE_IRQ,
2784 +              },
2785 +};
2786 +
2787 +static u64 bcm2708_emmc_dmamask = 0xffffffffUL;
2788 +
2789 +struct platform_device bcm2708_emmc_device = {
2790 +       .name = "bcm2708_sdhci",
2791 +       .id = 0,
2792 +       .num_resources = ARRAY_SIZE(bcm2708_emmc_resources),
2793 +       .resource = bcm2708_emmc_resources,
2794 +       .dev = {
2795 +               .dma_mask = &bcm2708_emmc_dmamask,
2796 +               .coherent_dma_mask = 0xffffffffUL},
2797 +};
2798 +#endif /* CONFIG_MMC_SDHCI_BCM2708 */
2799 +
2800 +static struct resource bcm2708_powerman_resources[] = {
2801 +       [0] = {
2802 +              .start = PM_BASE,
2803 +              .end = PM_BASE + SZ_256 - 1,
2804 +              .flags = IORESOURCE_MEM,
2805 +              },
2806 +};
2807 +
2808 +static u64 powerman_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2809 +
2810 +struct platform_device bcm2708_powerman_device = {
2811 +       .name = "bcm2708_powerman",
2812 +       .id = 0,
2813 +       .num_resources = ARRAY_SIZE(bcm2708_powerman_resources),
2814 +       .resource = bcm2708_powerman_resources,
2815 +       .dev = {
2816 +               .dma_mask = &powerman_dmamask,
2817 +               .coherent_dma_mask = 0xffffffffUL},
2818 +};
2819 +
2820 +
2821 +static struct platform_device bcm2708_alsa_devices[] = {
2822 +       [0] = {
2823 +              .name = "bcm2835_AUD0",
2824 +              .id = 0,         /* first audio device */
2825 +              .resource = 0,
2826 +              .num_resources = 0,
2827 +              },
2828 +       [1] = {
2829 +              .name = "bcm2835_AUD1",
2830 +              .id = 1,         /* second audio device */
2831 +              .resource = 0,
2832 +              .num_resources = 0,
2833 +              },
2834 +       [2] = {
2835 +              .name = "bcm2835_AUD2",
2836 +              .id = 2,         /* third audio device */
2837 +              .resource = 0,
2838 +              .num_resources = 0,
2839 +              },
2840 +       [3] = {
2841 +              .name = "bcm2835_AUD3",
2842 +              .id = 3,         /* forth audio device */
2843 +              .resource = 0,
2844 +              .num_resources = 0,
2845 +              },
2846 +       [4] = {
2847 +              .name = "bcm2835_AUD4",
2848 +              .id = 4,         /* fifth audio device */
2849 +              .resource = 0,
2850 +              .num_resources = 0,
2851 +              },
2852 +       [5] = {
2853 +              .name = "bcm2835_AUD5",
2854 +              .id = 5,         /* sixth audio device */
2855 +              .resource = 0,
2856 +              .num_resources = 0,
2857 +              },
2858 +       [6] = {
2859 +              .name = "bcm2835_AUD6",
2860 +              .id = 6,         /* seventh audio device */
2861 +              .resource = 0,
2862 +              .num_resources = 0,
2863 +              },
2864 +       [7] = {
2865 +              .name = "bcm2835_AUD7",
2866 +              .id = 7,         /* eighth audio device */
2867 +              .resource = 0,
2868 +              .num_resources = 0,
2869 +              },
2870 +};
2871 +
2872 +static struct resource bcm2708_spi_resources[] = {
2873 +       {
2874 +               .start = SPI0_BASE,
2875 +               .end = SPI0_BASE + SZ_256 - 1,
2876 +               .flags = IORESOURCE_MEM,
2877 +       }, {
2878 +               .start = IRQ_SPI,
2879 +               .end = IRQ_SPI,
2880 +               .flags = IORESOURCE_IRQ,
2881 +       }
2882 +};
2883 +
2884 +
2885 +static struct platform_device bcm2708_spi_device = {
2886 +       .name = "bcm2708_spi",
2887 +       .id = 0,
2888 +       .num_resources = ARRAY_SIZE(bcm2708_spi_resources),
2889 +       .resource = bcm2708_spi_resources,
2890 +};
2891 +
2892 +#ifdef CONFIG_BCM2708_SPIDEV
2893 +static struct spi_board_info bcm2708_spi_devices[] = {
2894 +#ifdef CONFIG_SPI_SPIDEV
2895 +       {
2896 +               .modalias = "spidev",
2897 +               .max_speed_hz = 500000,
2898 +               .bus_num = 0,
2899 +               .chip_select = 0,
2900 +               .mode = SPI_MODE_0,
2901 +       }, {
2902 +               .modalias = "spidev",
2903 +               .max_speed_hz = 500000,
2904 +               .bus_num = 0,
2905 +               .chip_select = 1,
2906 +               .mode = SPI_MODE_0,
2907 +       }
2908 +#endif
2909 +};
2910 +#endif
2911 +
2912 +static struct resource bcm2708_bsc0_resources[] = {
2913 +       {
2914 +               .start = BSC0_BASE,
2915 +               .end = BSC0_BASE + SZ_256 - 1,
2916 +               .flags = IORESOURCE_MEM,
2917 +       }, {
2918 +               .start = INTERRUPT_I2C,
2919 +               .end = INTERRUPT_I2C,
2920 +               .flags = IORESOURCE_IRQ,
2921 +       }
2922 +};
2923 +
2924 +static struct platform_device bcm2708_bsc0_device = {
2925 +       .name = "bcm2708_i2c",
2926 +       .id = 0,
2927 +       .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources),
2928 +       .resource = bcm2708_bsc0_resources,
2929 +};
2930 +
2931 +
2932 +static struct resource bcm2708_bsc1_resources[] = {
2933 +       {
2934 +               .start = BSC1_BASE,
2935 +               .end = BSC1_BASE + SZ_256 - 1,
2936 +               .flags = IORESOURCE_MEM,
2937 +       }, {
2938 +               .start = INTERRUPT_I2C,
2939 +               .end = INTERRUPT_I2C,
2940 +               .flags = IORESOURCE_IRQ,
2941 +       }
2942 +};
2943 +
2944 +static struct platform_device bcm2708_bsc1_device = {
2945 +       .name = "bcm2708_i2c",
2946 +       .id = 1,
2947 +       .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources),
2948 +       .resource = bcm2708_bsc1_resources,
2949 +};
2950 +
2951 +static struct platform_device bcm2835_hwmon_device = {
2952 +       .name = "bcm2835_hwmon",
2953 +};
2954 +
2955 +static struct platform_device bcm2835_thermal_device = {
2956 +       .name = "bcm2835_thermal",
2957 +};
2958 +
2959 +int __init bcm_register_device(struct platform_device *pdev)
2960 +{
2961 +       int ret;
2962 +
2963 +       ret = platform_device_register(pdev);
2964 +       if (ret)
2965 +               pr_debug("Unable to register platform device '%s': %d\n",
2966 +                        pdev->name, ret);
2967 +
2968 +       return ret;
2969 +}
2970 +
2971 +static void bcm2708_restart(char mode, const char *cmd)
2972 +{
2973 +       uint32_t pm_rstc, pm_wdog;
2974 +       uint32_t timeout = 10;
2975 +
2976 +       /* For quick reset notification add reboot=q to cmdline
2977 +        */
2978 +       if(mode == 'q')
2979 +       {
2980 +               uint32_t pm_rsts = readl(__io_address(PM_RSTS));
2981 +               pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
2982 +               writel(pm_rsts, __io_address(PM_RSTS));
2983 +       }
2984 +
2985 +       /* Setup watchdog for reset */
2986 +       pm_rstc = readl(__io_address(PM_RSTC));
2987 +
2988 +       pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
2989 +       pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
2990 +
2991 +       writel(pm_wdog, __io_address(PM_WDOG));
2992 +       writel(pm_rstc, __io_address(PM_RSTC));
2993 +}
2994 +
2995 +/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
2996 +static void bcm2708_power_off(void)
2997 +{
2998 +       /* we set the watchdog hard reset bit here to distinguish this reset from the normal (full) reset. bootcode.bin will not reboot after a hard reset */
2999 +       uint32_t pm_rsts = readl(__io_address(PM_RSTS));
3000 +       pm_rsts = PM_PASSWORD | (pm_rsts & PM_RSTC_WRCFG_CLR) | PM_RSTS_HADWRH_SET;
3001 +       writel(pm_rsts, __io_address(PM_RSTS));
3002 +       /* continue with normal reset mechanism */
3003 +       bcm2708_restart(0, "");
3004 +}
3005 +
3006 +void __init bcm2708_init(void)
3007 +{
3008 +       int i;
3009 +
3010 +#if defined(CONFIG_BCM_VC_CMA)
3011 +       vc_cma_early_init();
3012 +#endif
3013 +       printk("bcm2708.uart_clock = %d\n", uart_clock);
3014 +       pm_power_off = bcm2708_power_off;
3015 +
3016 +       if (uart_clock)
3017 +               lookups[0].clk->rate = uart_clock;
3018 +
3019 +       for (i = 0; i < ARRAY_SIZE(lookups); i++)
3020 +               clkdev_add(&lookups[i]);
3021 +
3022 +       bcm_register_device(&bcm2708_dmaman_device);
3023 +       bcm_register_device(&bcm2708_vcio_device);
3024 +#ifdef CONFIG_BCM2708_GPIO
3025 +       bcm_register_device(&bcm2708_gpio_device);
3026 +#endif
3027 +#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
3028 +       platform_device_register(&w1_device);
3029 +#endif
3030 +       bcm_register_device(&bcm2708_systemtimer_device);
3031 +       bcm_register_device(&bcm2708_fb_device);
3032 +       if (!fiq_fix_enable)
3033 +       {
3034 +               bcm2708_usb_device.resource = bcm2708_usb_resources_no_fiq_fix;
3035 +               bcm2708_usb_device.num_resources = ARRAY_SIZE(bcm2708_usb_resources_no_fiq_fix);
3036 +       }
3037 +       bcm_register_device(&bcm2708_usb_device);
3038 +       bcm_register_device(&bcm2708_uart1_device);
3039 +       bcm_register_device(&bcm2708_powerman_device);
3040 +
3041 +#ifdef CONFIG_MMC_SDHCI_BCM2708
3042 +       bcm_register_device(&bcm2708_emmc_device);
3043 +#endif
3044 +       bcm2708_init_led();
3045 +       for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++)
3046 +               bcm_register_device(&bcm2708_alsa_devices[i]);
3047 +
3048 +       bcm_register_device(&bcm2708_spi_device);
3049 +       bcm_register_device(&bcm2708_bsc0_device);
3050 +       bcm_register_device(&bcm2708_bsc1_device);
3051 +
3052 +       bcm_register_device(&bcm2835_hwmon_device);
3053 +       bcm_register_device(&bcm2835_thermal_device);
3054 +
3055 +       for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
3056 +               struct amba_device *d = amba_devs[i];
3057 +               amba_device_register(d, &iomem_resource);
3058 +       }
3059 +       system_rev = boardrev;
3060 +       system_serial_low = serial;
3061 +
3062 +#ifdef CONFIG_BCM2708_SPIDEV
3063 +       spi_register_board_info(bcm2708_spi_devices,
3064 +                       ARRAY_SIZE(bcm2708_spi_devices));
3065 +#endif
3066 +}
3067 +
3068 +static void timer_set_mode(enum clock_event_mode mode,
3069 +                          struct clock_event_device *clk)
3070 +{
3071 +       switch (mode) {
3072 +       case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
3073 +       case CLOCK_EVT_MODE_SHUTDOWN:
3074 +               break;
3075 +       case CLOCK_EVT_MODE_PERIODIC:
3076 +
3077 +       case CLOCK_EVT_MODE_UNUSED:
3078 +       case CLOCK_EVT_MODE_RESUME:
3079 +
3080 +       default:
3081 +               printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
3082 +                      (int)mode);
3083 +               break;
3084 +       }
3085 +
3086 +}
3087 +
3088 +static int timer_set_next_event(unsigned long cycles,
3089 +                               struct clock_event_device *unused)
3090 +{
3091 +       unsigned long stc;
3092 +
3093 +       stc = readl(__io_address(ST_BASE + 0x04));
3094 +       writel(stc + cycles, __io_address(ST_BASE + 0x18));     /* stc3 */
3095 +       return 0;
3096 +}
3097 +
3098 +static struct clock_event_device timer0_clockevent = {
3099 +       .name = "timer0",
3100 +       .shift = 32,
3101 +       .features = CLOCK_EVT_FEAT_ONESHOT,
3102 +       .set_mode = timer_set_mode,
3103 +       .set_next_event = timer_set_next_event,
3104 +};
3105 +
3106 +/*
3107 + * IRQ handler for the timer
3108 + */
3109 +static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id)
3110 +{
3111 +       struct clock_event_device *evt = &timer0_clockevent;
3112 +
3113 +       writel(1 << 3, __io_address(ST_BASE + 0x00));   /* stcs clear timer int */
3114 +
3115 +       evt->event_handler(evt);
3116 +
3117 +       return IRQ_HANDLED;
3118 +}
3119 +
3120 +static struct irqaction bcm2708_timer_irq = {
3121 +       .name = "BCM2708 Timer Tick",
3122 +       .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
3123 +       .handler = bcm2708_timer_interrupt,
3124 +};
3125 +
3126 +/*
3127 + * Set up timer interrupt, and return the current time in seconds.
3128 + */
3129 +
3130 +static struct delay_timer bcm2708_delay_timer = {
3131 +       .read_current_timer = bcm2708_read_current_timer,
3132 +       .freq = STC_FREQ_HZ,
3133 +};
3134 +
3135 +static void __init bcm2708_timer_init(void)
3136 +{
3137 +       /* init high res timer */
3138 +       bcm2708_clocksource_init();
3139 +
3140 +       /*
3141 +        * Initialise to a known state (all timers off)
3142 +        */
3143 +       writel(0, __io_address(ARM_T_CONTROL));
3144 +       /*
3145 +        * Make irqs happen for the system timer
3146 +        */
3147 +       setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
3148 +
3149 +       setup_sched_clock(bcm2708_read_sched_clock, 32, STC_FREQ_HZ);
3150 +
3151 +       timer0_clockevent.mult =
3152 +           div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
3153 +       timer0_clockevent.max_delta_ns =
3154 +           clockevent_delta2ns(0xffffffff, &timer0_clockevent);
3155 +       timer0_clockevent.min_delta_ns =
3156 +           clockevent_delta2ns(0xf, &timer0_clockevent);
3157 +
3158 +       timer0_clockevent.cpumask = cpumask_of(0);
3159 +       clockevents_register_device(&timer0_clockevent);
3160 +
3161 +       register_current_timer_delay(&bcm2708_delay_timer);
3162 +}
3163 +
3164 +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
3165 +#include <linux/leds.h>
3166 +
3167 +static struct gpio_led bcm2708_leds[] = {
3168 +       [0] = {
3169 +              .gpio = 16,
3170 +              .name = "led0",
3171 +              .default_trigger = "mmc0",
3172 +              .active_low = 1,
3173 +              },
3174 +};
3175 +
3176 +static struct gpio_led_platform_data bcm2708_led_pdata = {
3177 +       .num_leds = ARRAY_SIZE(bcm2708_leds),
3178 +       .leds = bcm2708_leds,
3179 +};
3180 +
3181 +static struct platform_device bcm2708_led_device = {
3182 +       .name = "leds-gpio",
3183 +       .id = -1,
3184 +       .dev = {
3185 +               .platform_data = &bcm2708_led_pdata,
3186 +               },
3187 +};
3188 +
3189 +static void __init bcm2708_init_led(void)
3190 +{
3191 +       platform_device_register(&bcm2708_led_device);
3192 +}
3193 +#else
3194 +static inline void bcm2708_init_led(void)
3195 +{
3196 +}
3197 +#endif
3198 +
3199 +void __init bcm2708_init_early(void)
3200 +{
3201 +       /*
3202 +        * Some devices allocate their coherent buffers from atomic
3203 +        * context. Increase size of atomic coherent pool to make sure such
3204 +        * the allocations won't fail.
3205 +        */
3206 +       init_dma_coherent_pool_size(SZ_4M);
3207 +}
3208 +
3209 +static void __init board_reserve(void)
3210 +{
3211 +#if defined(CONFIG_BCM_VC_CMA)
3212 +       vc_cma_reserve();
3213 +#endif
3214 +}
3215 +
3216 +MACHINE_START(BCM2708, "BCM2708")
3217 +    /* Maintainer: Broadcom Europe Ltd. */
3218 +       .map_io = bcm2708_map_io,
3219 +       .init_irq = bcm2708_init_irq,
3220 +       .init_time = bcm2708_timer_init,
3221 +       .init_machine = bcm2708_init,
3222 +       .init_early = bcm2708_init_early,
3223 +       .reserve = board_reserve,
3224 +       .restart        = bcm2708_restart,
3225 +MACHINE_END
3226 +
3227 +module_param(boardrev, uint, 0644);
3228 +module_param(serial, uint, 0644);
3229 +module_param(uart_clock, uint, 0644);
3230 --- /dev/null
3231 +++ b/arch/arm/mach-bcm2708/bcm2708_gpio.c
3232 @@ -0,0 +1,339 @@
3233 +/*
3234 + *  linux/arch/arm/mach-bcm2708/bcm2708_gpio.c
3235 + *
3236 + *  Copyright (C) 2010 Broadcom
3237 + *
3238 + * This program is free software; you can redistribute it and/or modify
3239 + * it under the terms of the GNU General Public License version 2 as
3240 + * published by the Free Software Foundation.
3241 + *
3242 + */
3243 +
3244 +#include <linux/spinlock.h>
3245 +#include <linux/module.h>
3246 +#include <linux/list.h>
3247 +#include <linux/io.h>
3248 +#include <linux/irq.h>
3249 +#include <linux/interrupt.h>
3250 +#include <linux/slab.h>
3251 +#include <mach/gpio.h>
3252 +#include <linux/gpio.h>
3253 +#include <linux/platform_device.h>
3254 +#include <mach/platform.h>
3255 +
3256 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
3257 +#define DRIVER_NAME BCM_GPIO_DRIVER_NAME
3258 +#define BCM_GPIO_USE_IRQ 1
3259 +
3260 +#define GPIOFSEL(x)  (0x00+(x)*4)
3261 +#define GPIOSET(x)   (0x1c+(x)*4)
3262 +#define GPIOCLR(x)   (0x28+(x)*4)
3263 +#define GPIOLEV(x)   (0x34+(x)*4)
3264 +#define GPIOEDS(x)   (0x40+(x)*4)
3265 +#define GPIOREN(x)   (0x4c+(x)*4)
3266 +#define GPIOFEN(x)   (0x58+(x)*4)
3267 +#define GPIOHEN(x)   (0x64+(x)*4)
3268 +#define GPIOLEN(x)   (0x70+(x)*4)
3269 +#define GPIOAREN(x)  (0x7c+(x)*4)
3270 +#define GPIOAFEN(x)  (0x88+(x)*4)
3271 +#define GPIOUD(x)    (0x94+(x)*4)
3272 +#define GPIOUDCLK(x) (0x98+(x)*4)
3273 +
3274 +enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT,
3275 +       GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4,
3276 +       GPIO_FSEL_ALT0, GPIO_FSEL_ALT1,
3277 +       GPIO_FSEL_ALT2, GPIO_FSEL_ALT3,
3278 +};
3279 +
3280 +       /* Each of the two spinlocks protects a different set of hardware
3281 +        * regiters and data structurs. This decouples the code of the IRQ from
3282 +        * the GPIO code. This also makes the case of a GPIO routine call from
3283 +        * the IRQ code simpler.
3284 +        */
3285 +static DEFINE_SPINLOCK(lock);  /* GPIO registers */
3286 +
3287 +struct bcm2708_gpio {
3288 +       struct list_head list;
3289 +       void __iomem *base;
3290 +       struct gpio_chip gc;
3291 +       unsigned long rising;
3292 +       unsigned long falling;
3293 +};
3294 +
3295 +static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset,
3296 +                               int function)
3297 +{
3298 +       struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
3299 +       unsigned long flags;
3300 +       unsigned gpiodir;
3301 +       unsigned gpio_bank = offset / 10;
3302 +       unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
3303 +
3304 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function);
3305 +       if (offset >= ARCH_NR_GPIOS)
3306 +               return -EINVAL;
3307 +
3308 +       spin_lock_irqsave(&lock, flags);
3309 +
3310 +       gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
3311 +       gpiodir &= ~(7 << gpio_field_offset);
3312 +       gpiodir |= function << gpio_field_offset;
3313 +       writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank));
3314 +       spin_unlock_irqrestore(&lock, flags);
3315 +       gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
3316 +
3317 +       return 0;
3318 +}
3319 +
3320 +static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset)
3321 +{
3322 +       return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT);
3323 +}
3324 +
3325 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
3326 +static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
3327 +                               int value)
3328 +{
3329 +       int ret;
3330 +       ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT);
3331 +       if (ret >= 0)
3332 +               bcm2708_gpio_set(gc, offset, value);
3333 +       return ret;
3334 +}
3335 +
3336 +static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset)
3337 +{
3338 +       struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
3339 +       unsigned gpio_bank = offset / 32;
3340 +       unsigned gpio_field_offset = (offset - 32 * gpio_bank);
3341 +       unsigned lev;
3342 +
3343 +       if (offset >= ARCH_NR_GPIOS)
3344 +               return 0;
3345 +       lev = readl(gpio->base + GPIOLEV(gpio_bank));
3346 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset));
3347 +       return 0x1 & (lev >> gpio_field_offset);
3348 +}
3349 +
3350 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
3351 +{
3352 +       struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
3353 +       unsigned gpio_bank = offset / 32;
3354 +       unsigned gpio_field_offset = (offset - 32 * gpio_bank);
3355 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value);
3356 +       if (offset >= ARCH_NR_GPIOS)
3357 +               return;
3358 +       if (value)
3359 +               writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank));
3360 +       else
3361 +               writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank));
3362 +}
3363 +
3364 +/*************************************************************************************************************************
3365 + * bcm2708 GPIO IRQ
3366 + */
3367 +
3368 +#if BCM_GPIO_USE_IRQ
3369 +
3370 +static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
3371 +{
3372 +       return gpio_to_irq(gpio);
3373 +}
3374 +
3375 +static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type)
3376 +{
3377 +       unsigned irq = d->irq;
3378 +       struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
3379 +
3380 +       if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
3381 +               return -EINVAL;
3382 +
3383 +       if (type & IRQ_TYPE_EDGE_RISING) {
3384 +               gpio->rising |= (1 << irq_to_gpio(irq));
3385 +       } else {
3386 +               gpio->rising &= ~(1 << irq_to_gpio(irq));
3387 +       }
3388 +
3389 +       if (type & IRQ_TYPE_EDGE_FALLING) {
3390 +               gpio->falling |= (1 << irq_to_gpio(irq));
3391 +       } else {
3392 +               gpio->falling &= ~(1 << irq_to_gpio(irq));
3393 +       }
3394 +       return 0;
3395 +}
3396 +
3397 +static void bcm2708_gpio_irq_mask(struct irq_data *d)
3398 +{
3399 +       unsigned irq = d->irq;
3400 +       struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
3401 +       unsigned gn = irq_to_gpio(irq);
3402 +       unsigned gb = gn / 32;
3403 +       unsigned long rising = readl(gpio->base + GPIOREN(gb));
3404 +       unsigned long falling = readl(gpio->base + GPIOFEN(gb));
3405 +
3406 +       gn = gn % 32;
3407 +
3408 +       writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
3409 +       writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
3410 +}
3411 +
3412 +static void bcm2708_gpio_irq_unmask(struct irq_data *d)
3413 +{
3414 +       unsigned irq = d->irq;
3415 +       struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
3416 +       unsigned gn = irq_to_gpio(irq);
3417 +       unsigned gb = gn / 32;
3418 +       unsigned long rising = readl(gpio->base + GPIOREN(gb));
3419 +       unsigned long falling = readl(gpio->base + GPIOFEN(gb));
3420 +
3421 +       gn = gn % 32;
3422 +
3423 +       writel(1 << gn, gpio->base + GPIOEDS(gb));
3424 +
3425 +       if (gpio->rising & (1 << gn)) {
3426 +               writel(rising | (1 << gn), gpio->base + GPIOREN(gb));
3427 +       } else {
3428 +               writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
3429 +       }
3430 +
3431 +       if (gpio->falling & (1 << gn)) {
3432 +               writel(falling | (1 << gn), gpio->base + GPIOFEN(gb));
3433 +       } else {
3434 +               writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
3435 +       }
3436 +}
3437 +
3438 +static struct irq_chip bcm2708_irqchip = {
3439 +       .name = "GPIO",
3440 +       .irq_enable = bcm2708_gpio_irq_unmask,
3441 +       .irq_disable = bcm2708_gpio_irq_mask,
3442 +       .irq_unmask = bcm2708_gpio_irq_unmask,
3443 +       .irq_mask = bcm2708_gpio_irq_mask,
3444 +       .irq_set_type = bcm2708_gpio_irq_set_type,
3445 +};
3446 +
3447 +static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id)
3448 +{
3449 +       unsigned long edsr;
3450 +       unsigned bank;
3451 +       int i;
3452 +       unsigned gpio;
3453 +       for (bank = 0; bank <= 1; bank++) {
3454 +               edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank));
3455 +               for_each_set_bit(i, &edsr, 32) {
3456 +                       gpio = i + bank * 32;
3457 +                       generic_handle_irq(gpio_to_irq(gpio));
3458 +               }
3459 +               writel(0xffffffff, __io_address(GPIO_BASE) + GPIOEDS(bank));
3460 +       }
3461 +       return IRQ_HANDLED;
3462 +}
3463 +
3464 +static struct irqaction bcm2708_gpio_irq = {
3465 +       .name = "BCM2708 GPIO catchall handler",
3466 +       .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
3467 +       .handler = bcm2708_gpio_interrupt,
3468 +};
3469 +
3470 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
3471 +{
3472 +       unsigned irq;
3473 +
3474 +       ucb->gc.to_irq = bcm2708_gpio_to_irq;
3475 +
3476 +       for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) {
3477 +               irq_set_chip_data(irq, ucb);
3478 +               irq_set_chip(irq, &bcm2708_irqchip);
3479 +               set_irq_flags(irq, IRQF_VALID);
3480 +       }
3481 +       setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq);
3482 +}
3483 +
3484 +#else
3485 +
3486 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
3487 +{
3488 +}
3489 +
3490 +#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */
3491 +
3492 +static int bcm2708_gpio_probe(struct platform_device *dev)
3493 +{
3494 +       struct bcm2708_gpio *ucb;
3495 +       struct resource *res;
3496 +       int err = 0;
3497 +
3498 +       printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev);
3499 +
3500 +       ucb = kzalloc(sizeof(*ucb), GFP_KERNEL);
3501 +       if (NULL == ucb) {
3502 +               printk(KERN_ERR DRIVER_NAME ": failed to allocate "
3503 +                      "mailbox memory\n");
3504 +               err = -ENOMEM;
3505 +               goto err;
3506 +       }
3507 +
3508 +       res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3509 +
3510 +       platform_set_drvdata(dev, ucb);
3511 +       ucb->base = __io_address(GPIO_BASE);
3512 +
3513 +       ucb->gc.label = "bcm2708_gpio";
3514 +       ucb->gc.base = 0;
3515 +       ucb->gc.ngpio = ARCH_NR_GPIOS;
3516 +       ucb->gc.owner = THIS_MODULE;
3517 +
3518 +       ucb->gc.direction_input = bcm2708_gpio_dir_in;
3519 +       ucb->gc.direction_output = bcm2708_gpio_dir_out;
3520 +       ucb->gc.get = bcm2708_gpio_get;
3521 +       ucb->gc.set = bcm2708_gpio_set;
3522 +       ucb->gc.can_sleep = 0;
3523 +
3524 +       bcm2708_gpio_irq_init(ucb);
3525 +
3526 +       err = gpiochip_add(&ucb->gc);
3527 +       if (err)
3528 +               goto err;
3529 +
3530 +err:
3531 +       return err;
3532 +
3533 +}
3534 +
3535 +static int bcm2708_gpio_remove(struct platform_device *dev)
3536 +{
3537 +       int err = 0;
3538 +       struct bcm2708_gpio *ucb = platform_get_drvdata(dev);
3539 +
3540 +       printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev);
3541 +
3542 +       err = gpiochip_remove(&ucb->gc);
3543 +
3544 +       platform_set_drvdata(dev, NULL);
3545 +       kfree(ucb);
3546 +
3547 +       return err;
3548 +}
3549 +
3550 +static struct platform_driver bcm2708_gpio_driver = {
3551 +       .probe = bcm2708_gpio_probe,
3552 +       .remove = bcm2708_gpio_remove,
3553 +       .driver = {
3554 +                  .name = "bcm2708_gpio"},
3555 +};
3556 +
3557 +static int __init bcm2708_gpio_init(void)
3558 +{
3559 +       return platform_driver_register(&bcm2708_gpio_driver);
3560 +}
3561 +
3562 +static void __exit bcm2708_gpio_exit(void)
3563 +{
3564 +       platform_driver_unregister(&bcm2708_gpio_driver);
3565 +}
3566 +
3567 +module_init(bcm2708_gpio_init);
3568 +module_exit(bcm2708_gpio_exit);
3569 +
3570 +MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver");
3571 +MODULE_LICENSE("GPL");
3572 --- /dev/null
3573 +++ b/arch/arm/mach-bcm2708/bcm2708.h
3574 @@ -0,0 +1,51 @@
3575 +/*
3576 + * linux/arch/arm/mach-bcm2708/bcm2708.h
3577 + *
3578 + * BCM2708 machine support header
3579 + *
3580 + *  Copyright (C) 2010 Broadcom
3581 + *
3582 + * This program is free software; you can redistribute it and/or modify
3583 + * it under the terms of the GNU General Public License as published by
3584 + * the Free Software Foundation; either version 2 of the License, or
3585 + * (at your option) any later version.
3586 + *
3587 + * This program is distributed in the hope that it will be useful,
3588 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3589 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3590 + * GNU General Public License for more details.
3591 + *
3592 + * You should have received a copy of the GNU General Public License
3593 + * along with this program; if not, write to the Free Software
3594 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
3595 + */
3596 +
3597 +#ifndef __BCM2708_BCM2708_H
3598 +#define __BCM2708_BCM2708_H
3599 +
3600 +#include <linux/amba/bus.h>
3601 +
3602 +extern void __init bcm2708_init(void);
3603 +extern void __init bcm2708_init_irq(void);
3604 +extern void __init bcm2708_map_io(void);
3605 +extern struct sys_timer bcm2708_timer;
3606 +extern unsigned int mmc_status(struct device *dev);
3607 +
3608 +#define AMBA_DEVICE(name, busid, base, plat)                   \
3609 +static struct amba_device name##_device = {                    \
3610 +       .dev            = {                                     \
3611 +               .coherent_dma_mask = ~0,                        \
3612 +               .init_name = busid,                             \
3613 +               .platform_data = plat,                          \
3614 +       },                                                      \
3615 +       .res            = {                                     \
3616 +               .start  = base##_BASE,          \
3617 +               .end    = (base##_BASE) + SZ_4K - 1,\
3618 +               .flags  = IORESOURCE_MEM,                       \
3619 +       },                                                      \
3620 +       .dma_mask       = ~0,                                   \
3621 +       .irq            = base##_IRQ,                           \
3622 +       /* .dma         = base##_DMA,*/                         \
3623 +}
3624 +
3625 +#endif
3626 --- /dev/null
3627 +++ b/arch/arm/mach-bcm2708/clock.c
3628 @@ -0,0 +1,61 @@
3629 +/*
3630 + *  linux/arch/arm/mach-bcm2708/clock.c
3631 + *
3632 + *  Copyright (C) 2010 Broadcom
3633 + *
3634 + * This program is free software; you can redistribute it and/or modify
3635 + * it under the terms of the GNU General Public License as published by
3636 + * the Free Software Foundation; either version 2 of the License, or
3637 + * (at your option) any later version.
3638 + *
3639 + * This program is distributed in the hope that it will be useful,
3640 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3641 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3642 + * GNU General Public License for more details.
3643 + *
3644 + * You should have received a copy of the GNU General Public License
3645 + * along with this program; if not, write to the Free Software
3646 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
3647 + */
3648 +#include <linux/module.h>
3649 +#include <linux/kernel.h>
3650 +#include <linux/device.h>
3651 +#include <linux/list.h>
3652 +#include <linux/errno.h>
3653 +#include <linux/err.h>
3654 +#include <linux/string.h>
3655 +#include <linux/clk.h>
3656 +#include <linux/mutex.h>
3657 +
3658 +#include <asm/clkdev.h>
3659 +
3660 +#include "clock.h"
3661 +
3662 +int clk_enable(struct clk *clk)
3663 +{
3664 +       return 0;
3665 +}
3666 +EXPORT_SYMBOL(clk_enable);
3667 +
3668 +void clk_disable(struct clk *clk)
3669 +{
3670 +}
3671 +EXPORT_SYMBOL(clk_disable);
3672 +
3673 +unsigned long clk_get_rate(struct clk *clk)
3674 +{
3675 +       return clk->rate;
3676 +}
3677 +EXPORT_SYMBOL(clk_get_rate);
3678 +
3679 +long clk_round_rate(struct clk *clk, unsigned long rate)
3680 +{
3681 +       return clk->rate;
3682 +}
3683 +EXPORT_SYMBOL(clk_round_rate);
3684 +
3685 +int clk_set_rate(struct clk *clk, unsigned long rate)
3686 +{
3687 +       return -EIO;
3688 +}
3689 +EXPORT_SYMBOL(clk_set_rate);
3690 --- /dev/null
3691 +++ b/arch/arm/mach-bcm2708/clock.h
3692 @@ -0,0 +1,24 @@
3693 +/*
3694 + *  linux/arch/arm/mach-bcm2708/clock.h
3695 + *
3696 + *  Copyright (C) 2010 Broadcom
3697 + *
3698 + * This program is free software; you can redistribute it and/or modify
3699 + * it under the terms of the GNU General Public License as published by
3700 + * the Free Software Foundation; either version 2 of the License, or
3701 + * (at your option) any later version.
3702 + *
3703 + * This program is distributed in the hope that it will be useful,
3704 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3705 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3706 + * GNU General Public License for more details.
3707 + *
3708 + * You should have received a copy of the GNU General Public License
3709 + * along with this program; if not, write to the Free Software
3710 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
3711 + */
3712 +struct module;
3713 +
3714 +struct clk {
3715 +       unsigned long           rate;
3716 +};
3717 --- /dev/null
3718 +++ b/arch/arm/mach-bcm2708/dma.c
3719 @@ -0,0 +1,399 @@
3720 +/*
3721 + *  linux/arch/arm/mach-bcm2708/dma.c
3722 + *
3723 + *  Copyright (C) 2010 Broadcom
3724 + *
3725 + * This program is free software; you can redistribute it and/or modify
3726 + * it under the terms of the GNU General Public License version 2 as
3727 + * published by the Free Software Foundation.
3728 + */
3729 +
3730 +#include <linux/slab.h>
3731 +#include <linux/device.h>
3732 +#include <linux/platform_device.h>
3733 +#include <linux/module.h>
3734 +#include <linux/scatterlist.h>
3735 +
3736 +#include <mach/dma.h>
3737 +#include <mach/irqs.h>
3738 +
3739 +/*****************************************************************************\
3740 + *                                                                          *
3741 + * Configuration                                                            *
3742 + *                                                                          *
3743 +\*****************************************************************************/
3744 +
3745 +#define CACHE_LINE_MASK 31
3746 +#define DRIVER_NAME BCM_DMAMAN_DRIVER_NAME
3747 +#define DEFAULT_DMACHAN_BITMAP 0x10  /* channel 4 only */
3748 +
3749 +/* valid only for channels 0 - 14, 15 has its own base address */
3750 +#define BCM2708_DMA_CHAN(n)    ((n)<<8) /* base address */
3751 +#define BCM2708_DMA_CHANIO(dma_base, n) \
3752 +   ((void __iomem *)((char *)(dma_base)+BCM2708_DMA_CHAN(n)))
3753 +
3754 +
3755 +/*****************************************************************************\
3756 + *                                                                          *
3757 + * DMA Auxilliary Functions                                                 *
3758 + *                                                                          *
3759 +\*****************************************************************************/
3760 +
3761 +/* A DMA buffer on an arbitrary boundary may separate a cache line into a
3762 +   section inside the DMA buffer and another section outside it.
3763 +   Even if we flush DMA buffers from the cache there is always the chance that
3764 +   during a DMA someone will access the part of a cache line that is outside
3765 +   the DMA buffer - which will then bring in unwelcome data.
3766 +   Without being able to dictate our own buffer pools we must insist that
3767 +   DMA buffers consist of a whole number of cache lines.
3768 +*/
3769 +
3770 +extern int
3771 +bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
3772 +{
3773 +       int i;
3774 +
3775 +       for (i = 0; i < sg_len; i++) {
3776 +               if (sg_ptr[i].offset & CACHE_LINE_MASK ||
3777 +                   sg_ptr[i].length & CACHE_LINE_MASK)
3778 +                       return 0;
3779 +       }
3780 +
3781 +       return 1;
3782 +}
3783 +EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
3784 +
3785 +extern void
3786 +bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block)
3787 +{
3788 +       dsb();  /* ARM data synchronization (push) operation */
3789 +
3790 +       writel(control_block,        dma_chan_base + BCM2708_DMA_ADDR);
3791 +       writel(BCM2708_DMA_ACTIVE,   dma_chan_base + BCM2708_DMA_CS);
3792 +}
3793 +
3794 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
3795 +{
3796 +  dsb();
3797 +
3798 +  /* ugly busy wait only option for now */
3799 +  while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)
3800 +    cpu_relax();
3801 +}
3802 +
3803 +EXPORT_SYMBOL_GPL(bcm_dma_start);
3804 +
3805 +/* Complete an ongoing DMA (assuming its results are to be ignored)
3806 +   Does nothing if there is no DMA in progress.
3807 +   This routine waits for the current AXI transfer to complete before
3808 +   terminating the current DMA.         If the current transfer is hung on a DREQ used
3809 +   by an uncooperative peripheral the AXI transfer may never complete. In this
3810 +   case the routine times out and return a non-zero error code.
3811 +   Use of this routine doesn't guarantee that the ongoing or aborted DMA
3812 +   does not produce an interrupt.
3813 +*/
3814 +extern int
3815 +bcm_dma_abort(void __iomem *dma_chan_base)
3816 +{
3817 +       unsigned long int cs;
3818 +       int rc = 0;
3819 +
3820 +       cs = readl(dma_chan_base + BCM2708_DMA_CS);
3821 +
3822 +       if (BCM2708_DMA_ACTIVE & cs) {
3823 +               long int timeout = 10000;
3824 +
3825 +               /* write 0 to the active bit - pause the DMA */
3826 +               writel(0, dma_chan_base + BCM2708_DMA_CS);
3827 +
3828 +               /* wait for any current AXI transfer to complete */
3829 +               while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
3830 +                       cs = readl(dma_chan_base + BCM2708_DMA_CS);
3831 +
3832 +               if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
3833 +                       /* we'll un-pause when we set of our next DMA */
3834 +                       rc = -ETIMEDOUT;
3835 +
3836 +               } else if (BCM2708_DMA_ACTIVE & cs) {
3837 +                       /* terminate the control block chain */
3838 +                       writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
3839 +
3840 +                       /* abort the whole DMA */
3841 +                       writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
3842 +                              dma_chan_base + BCM2708_DMA_CS);
3843 +               }
3844 +       }
3845 +
3846 +       return rc;
3847 +}
3848 +EXPORT_SYMBOL_GPL(bcm_dma_abort);
3849 +
3850 +
3851 +/***************************************************************************** \
3852 + *                                                                          *
3853 + * DMA Manager Device Methods                                               *
3854 + *                                                                          *
3855 +\*****************************************************************************/
3856 +
3857 +struct vc_dmaman {
3858 +       void __iomem *dma_base;
3859 +       u32 chan_available; /* bitmap of available channels */
3860 +       u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
3861 +};
3862 +
3863 +static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
3864 +                          u32 chans_available)
3865 +{
3866 +       dmaman->dma_base = dma_base;
3867 +       dmaman->chan_available = chans_available;
3868 +       dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c;  /* chans 2 & 3 */
3869 +       dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01;  /* chan 0 */
3870 +}
3871 +
3872 +static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
3873 +                               unsigned preferred_feature_set)
3874 +{
3875 +       u32 chans;
3876 +       int feature;
3877 +
3878 +       chans = dmaman->chan_available;
3879 +       for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
3880 +               /* select the subset of available channels with the desired
3881 +                  feature so long as some of the candidate channels have that
3882 +                  feature */
3883 +               if ((preferred_feature_set & (1 << feature)) &&
3884 +                   (chans & dmaman->has_feature[feature]))
3885 +                       chans &= dmaman->has_feature[feature];
3886 +
3887 +       if (chans) {
3888 +               int chan = 0;
3889 +               /* return the ordinal of the first channel in the bitmap */
3890 +               while (chans != 0 && (chans & 1) == 0) {
3891 +                       chans >>= 1;
3892 +                       chan++;
3893 +               }
3894 +               /* claim the channel */
3895 +               dmaman->chan_available &= ~(1 << chan);
3896 +               return chan;
3897 +       } else
3898 +               return -ENOMEM;
3899 +}
3900 +
3901 +static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
3902 +{
3903 +       if (chan < 0)
3904 +               return -EINVAL;
3905 +       else if ((1 << chan) & dmaman->chan_available)
3906 +               return -EIDRM;
3907 +       else {
3908 +               dmaman->chan_available |= (1 << chan);
3909 +               return 0;
3910 +       }
3911 +}
3912 +
3913 +/*****************************************************************************\
3914 + *                                                                          *
3915 + * DMA IRQs                                                                 *
3916 + *                                                                          *
3917 +\*****************************************************************************/
3918 +
3919 +static unsigned char bcm_dma_irqs[] = {
3920 +       IRQ_DMA0,
3921 +       IRQ_DMA1,
3922 +       IRQ_DMA2,
3923 +       IRQ_DMA3,
3924 +       IRQ_DMA4,
3925 +       IRQ_DMA5,
3926 +       IRQ_DMA6,
3927 +       IRQ_DMA7,
3928 +       IRQ_DMA8,
3929 +       IRQ_DMA9,
3930 +       IRQ_DMA10,
3931 +       IRQ_DMA11,
3932 +       IRQ_DMA12
3933 +};
3934 +
3935 +
3936 +/***************************************************************************** \
3937 + *                                                                          *
3938 + * DMA Manager Monitor                                                      *
3939 + *                                                                          *
3940 +\*****************************************************************************/
3941 +
3942 +static struct device *dmaman_dev;      /* we assume there's only one! */
3943 +
3944 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
3945 +                             void __iomem **out_dma_base, int *out_dma_irq)
3946 +{
3947 +       if (!dmaman_dev)
3948 +               return -ENODEV;
3949 +       else {
3950 +               struct vc_dmaman *dmaman  = dev_get_drvdata(dmaman_dev);
3951 +               int rc;
3952 +
3953 +               device_lock(dmaman_dev);
3954 +               rc = vc_dmaman_chan_alloc(dmaman, preferred_feature_set);
3955 +               if (rc >= 0) {
3956 +                       *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base,
3957 +                                                          rc);
3958 +                       *out_dma_irq = bcm_dma_irqs[rc];
3959 +               }
3960 +               device_unlock(dmaman_dev);
3961 +
3962 +               return rc;
3963 +       }
3964 +}
3965 +EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
3966 +
3967 +extern int bcm_dma_chan_free(int channel)
3968 +{
3969 +       if (dmaman_dev) {
3970 +               struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
3971 +               int rc;
3972 +
3973 +               device_lock(dmaman_dev);
3974 +               rc = vc_dmaman_chan_free(dmaman, channel);
3975 +               device_unlock(dmaman_dev);
3976 +
3977 +               return rc;
3978 +       } else
3979 +               return -ENODEV;
3980 +}
3981 +EXPORT_SYMBOL_GPL(bcm_dma_chan_free);
3982 +
3983 +static int dev_dmaman_register(const char *dev_name, struct device *dev)
3984 +{
3985 +       int rc = dmaman_dev ? -EINVAL : 0;
3986 +       dmaman_dev = dev;
3987 +       return rc;
3988 +}
3989 +
3990 +static void dev_dmaman_deregister(const char *dev_name, struct device *dev)
3991 +{
3992 +       dmaman_dev = NULL;
3993 +}
3994 +
3995 +/*****************************************************************************\
3996 + *                                                                          *
3997 + * DMA Device                                                               *
3998 + *                                                                          *
3999 +\*****************************************************************************/
4000 +
4001 +static int dmachans = -1; /* module parameter */
4002 +
4003 +static int bcm_dmaman_probe(struct platform_device *pdev)
4004 +{
4005 +       int ret = 0;
4006 +       struct vc_dmaman *dmaman;
4007 +       struct resource *dma_res = NULL;
4008 +       void __iomem *dma_base = NULL;
4009 +       int have_dma_region = 0;
4010 +
4011 +       dmaman = kzalloc(sizeof(*dmaman), GFP_KERNEL);
4012 +       if (NULL == dmaman) {
4013 +               printk(KERN_ERR DRIVER_NAME ": failed to allocate "
4014 +                      "DMA management memory\n");
4015 +               ret = -ENOMEM;
4016 +       } else {
4017 +
4018 +               dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4019 +               if (dma_res == NULL) {
4020 +                       printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
4021 +                              "resource\n");
4022 +                       ret = -ENODEV;
4023 +               } else if (!request_mem_region(dma_res->start,
4024 +                                              resource_size(dma_res),
4025 +                                              DRIVER_NAME)) {
4026 +                       dev_err(&pdev->dev, "cannot obtain DMA region\n");
4027 +                       ret = -EBUSY;
4028 +               } else {
4029 +                       have_dma_region = 1;
4030 +                       dma_base = ioremap(dma_res->start,
4031 +                                          resource_size(dma_res));
4032 +                       if (!dma_base) {
4033 +                               dev_err(&pdev->dev, "cannot map DMA region\n");
4034 +                               ret = -ENOMEM;
4035 +                       } else {
4036 +                               /* use module parameter if one was provided */
4037 +                               if (dmachans > 0)
4038 +                                       vc_dmaman_init(dmaman, dma_base,
4039 +                                                      dmachans);
4040 +                               else
4041 +                                       vc_dmaman_init(dmaman, dma_base,
4042 +                                                      DEFAULT_DMACHAN_BITMAP);
4043 +
4044 +                               platform_set_drvdata(pdev, dmaman);
4045 +                               dev_dmaman_register(DRIVER_NAME, &pdev->dev);
4046 +
4047 +                               printk(KERN_INFO DRIVER_NAME ": DMA manager "
4048 +                                      "at %p\n", dma_base);
4049 +                       }
4050 +               }
4051 +       }
4052 +       if (ret != 0) {
4053 +               if (dma_base)
4054 +                       iounmap(dma_base);
4055 +               if (dma_res && have_dma_region)
4056 +                       release_mem_region(dma_res->start,
4057 +                                          resource_size(dma_res));
4058 +               if (dmaman)
4059 +                       kfree(dmaman);
4060 +       }
4061 +       return ret;
4062 +}
4063 +
4064 +static int bcm_dmaman_remove(struct platform_device *pdev)
4065 +{
4066 +       struct vc_dmaman *dmaman = platform_get_drvdata(pdev);
4067 +
4068 +       platform_set_drvdata(pdev, NULL);
4069 +       dev_dmaman_deregister(DRIVER_NAME, &pdev->dev);
4070 +       kfree(dmaman);
4071 +
4072 +       return 0;
4073 +}
4074 +
4075 +static struct platform_driver bcm_dmaman_driver = {
4076 +       .probe = bcm_dmaman_probe,
4077 +       .remove = bcm_dmaman_remove,
4078 +
4079 +       .driver = {
4080 +                  .name = DRIVER_NAME,
4081 +                  .owner = THIS_MODULE,
4082 +                  },
4083 +};
4084 +
4085 +/*****************************************************************************\
4086 + *                                                                          *
4087 + * Driver init/exit                                                         *
4088 + *                                                                          *
4089 +\*****************************************************************************/
4090 +
4091 +static int __init bcm_dmaman_drv_init(void)
4092 +{
4093 +       int ret;
4094 +
4095 +       ret = platform_driver_register(&bcm_dmaman_driver);
4096 +       if (ret != 0) {
4097 +               printk(KERN_ERR DRIVER_NAME ": failed to register "
4098 +                      "on platform\n");
4099 +       }
4100 +
4101 +       return ret;
4102 +}
4103 +
4104 +static void __exit bcm_dmaman_drv_exit(void)
4105 +{
4106 +       platform_driver_unregister(&bcm_dmaman_driver);
4107 +}
4108 +
4109 +module_init(bcm_dmaman_drv_init);
4110 +module_exit(bcm_dmaman_drv_exit);
4111 +
4112 +module_param(dmachans, int, 0644);
4113 +
4114 +MODULE_AUTHOR("Gray Girling <grayg@broadcom.com>");
4115 +MODULE_DESCRIPTION("DMA channel manager driver");
4116 +MODULE_LICENSE("GPL");
4117 +
4118 +MODULE_PARM_DESC(dmachans, "Bitmap of DMA channels available to the ARM");
4119 --- /dev/null
4120 +++ b/arch/arm/mach-bcm2708/dmaer.c
4121 @@ -0,0 +1,887 @@
4122 +#include <linux/init.h>
4123 +#include <linux/sched.h>
4124 +#include <linux/module.h>
4125 +#include <linux/types.h>
4126 +#include <linux/kdev_t.h>
4127 +#include <linux/fs.h>
4128 +#include <linux/cdev.h>
4129 +#include <linux/mm.h>
4130 +#include <linux/slab.h>
4131 +#include <linux/pagemap.h>
4132 +#include <linux/device.h>
4133 +#include <linux/jiffies.h>
4134 +#include <linux/timex.h>
4135 +#include <linux/dma-mapping.h>
4136 +
4137 +#include <asm/uaccess.h>
4138 +#include <asm/atomic.h>
4139 +#include <asm/cacheflush.h>
4140 +#include <asm/io.h>
4141 +
4142 +#include <mach/dma.h>
4143 +#include <mach/vc_support.h>
4144 +
4145 +#ifdef ECLIPSE_IGNORE
4146 +
4147 +#define __user
4148 +#define __init
4149 +#define __exit
4150 +#define __iomem
4151 +#define KERN_DEBUG
4152 +#define KERN_ERR
4153 +#define KERN_WARNING
4154 +#define KERN_INFO
4155 +#define _IOWR(a, b, c) b
4156 +#define _IOW(a, b, c) b
4157 +#define _IO(a, b) b
4158 +
4159 +#endif
4160 +
4161 +//#define inline
4162 +
4163 +#define PRINTK(args...) printk(args)
4164 +//#define PRINTK_VERBOSE(args...) printk(args)
4165 +//#define PRINTK(args...)
4166 +#define PRINTK_VERBOSE(args...)
4167 +
4168 +/***** TYPES ****/
4169 +#define PAGES_PER_LIST 500
4170 +struct PageList
4171 +{
4172 +       struct page *m_pPages[PAGES_PER_LIST];
4173 +       unsigned int m_used;
4174 +       struct PageList *m_pNext;
4175 +};
4176 +
4177 +struct VmaPageList
4178 +{
4179 +       //each vma has a linked list of pages associated with it
4180 +       struct PageList *m_pPageHead;
4181 +       struct PageList *m_pPageTail;
4182 +       unsigned int m_refCount;
4183 +};
4184 +
4185 +struct DmaControlBlock
4186 +{
4187 +       unsigned int m_transferInfo;
4188 +       void __user *m_pSourceAddr;
4189 +       void __user *m_pDestAddr;
4190 +       unsigned int m_xferLen;
4191 +       unsigned int m_tdStride;
4192 +       struct DmaControlBlock *m_pNext;
4193 +       unsigned int m_blank1, m_blank2;
4194 +};
4195 +
4196 +/***** DEFINES ******/
4197 +//magic number defining the module
4198 +#define DMA_MAGIC              0xdd
4199 +
4200 +//do user virtual to physical translation of the CB chain
4201 +#define DMA_PREPARE            _IOWR(DMA_MAGIC, 0, struct DmaControlBlock *)
4202 +
4203 +//kick the pre-prepared CB chain
4204 +#define DMA_KICK               _IOW(DMA_MAGIC, 1, struct DmaControlBlock *)
4205 +
4206 +//prepare it, kick it, wait for it
4207 +#define DMA_PREPARE_KICK_WAIT  _IOWR(DMA_MAGIC, 2, struct DmaControlBlock *)
4208 +
4209 +//prepare it, kick it, don't wait for it
4210 +#define DMA_PREPARE_KICK       _IOWR(DMA_MAGIC, 3, struct DmaControlBlock *)
4211 +
4212 +//not currently implemented
4213 +#define DMA_WAIT_ONE           _IO(DMA_MAGIC, 4, struct DmaControlBlock *)
4214 +
4215 +//wait on all kicked CB chains
4216 +#define DMA_WAIT_ALL           _IO(DMA_MAGIC, 5)
4217 +
4218 +//in order to discover the largest AXI burst that should be programmed into the transfer params
4219 +#define DMA_MAX_BURST          _IO(DMA_MAGIC, 6)
4220 +
4221 +//set the address range through which the user address is assumed to already by a physical address
4222 +#define DMA_SET_MIN_PHYS       _IOW(DMA_MAGIC, 7, unsigned long)
4223 +#define DMA_SET_MAX_PHYS       _IOW(DMA_MAGIC, 8, unsigned long)
4224 +#define DMA_SET_PHYS_OFFSET    _IOW(DMA_MAGIC, 9, unsigned long)
4225 +
4226 +//used to define the size for the CMA-based allocation *in pages*, can only be done once once the file is opened
4227 +#define DMA_CMA_SET_SIZE       _IOW(DMA_MAGIC, 10, unsigned long)
4228 +
4229 +//used to get the version of the module, to test for a capability
4230 +#define DMA_GET_VERSION                _IO(DMA_MAGIC, 99)
4231 +
4232 +#define VERSION_NUMBER 1
4233 +
4234 +#define VIRT_TO_BUS_CACHE_SIZE 8
4235 +
4236 +/***** FILE OPS *****/
4237 +static int Open(struct inode *pInode, struct file *pFile);
4238 +static int Release(struct inode *pInode, struct file *pFile);
4239 +static long Ioctl(struct file *pFile, unsigned int cmd, unsigned long arg);
4240 +static ssize_t Read(struct file *pFile, char __user *pUser, size_t count, loff_t *offp);
4241 +static int Mmap(struct file *pFile, struct vm_area_struct *pVma);
4242 +
4243 +/***** VMA OPS ****/
4244 +static void VmaOpen4k(struct vm_area_struct *pVma);
4245 +static void VmaClose4k(struct vm_area_struct *pVma);
4246 +static int VmaFault4k(struct vm_area_struct *pVma, struct vm_fault *pVmf);
4247 +
4248 +/**** DMA PROTOTYPES */
4249 +static struct DmaControlBlock __user *DmaPrepare(struct DmaControlBlock __user *pUserCB, int *pError);
4250 +static int DmaKick(struct DmaControlBlock __user *pUserCB);
4251 +static void DmaWaitAll(void);
4252 +
4253 +/**** GENERIC ****/
4254 +static int __init dmaer_init(void);
4255 +static void __exit dmaer_exit(void);
4256 +
4257 +/*** OPS ***/
4258 +static struct vm_operations_struct g_vmOps4k = {
4259 +       .open = VmaOpen4k,
4260 +       .close = VmaClose4k,
4261 +       .fault = VmaFault4k,
4262 +};
4263 +
4264 +static struct file_operations g_fOps = {
4265 +       .owner = THIS_MODULE,
4266 +       .llseek = 0,
4267 +       .read = Read,
4268 +       .write = 0,
4269 +       .unlocked_ioctl = Ioctl,
4270 +       .open = Open,
4271 +       .release = Release,
4272 +       .mmap = Mmap,
4273 +};
4274 +
4275 +/***** GLOBALS ******/
4276 +static dev_t g_majorMinor;
4277 +
4278 +//tracking usage of the two files
4279 +static atomic_t g_oneLock4k = ATOMIC_INIT(1);
4280 +
4281 +//device operations
4282 +static struct cdev g_cDev;
4283 +static int g_trackedPages = 0;
4284 +
4285 +//dma control
4286 +static unsigned int *g_pDmaChanBase;
4287 +static int g_dmaIrq;
4288 +static int g_dmaChan;
4289 +
4290 +//cma allocation
4291 +static int g_cmaHandle;
4292 +
4293 +//user virtual to bus address translation acceleration
4294 +static unsigned long g_virtAddr[VIRT_TO_BUS_CACHE_SIZE];
4295 +static unsigned long g_busAddr[VIRT_TO_BUS_CACHE_SIZE];
4296 +static unsigned long g_cbVirtAddr;
4297 +static unsigned long g_cbBusAddr;
4298 +static int g_cacheInsertAt;
4299 +static int g_cacheHit, g_cacheMiss;
4300 +
4301 +//off by default
4302 +static void __user *g_pMinPhys;
4303 +static void __user *g_pMaxPhys;
4304 +static unsigned long g_physOffset;
4305 +
4306 +/****** CACHE OPERATIONS ********/
4307 +static inline void FlushAddrCache(void)
4308 +{
4309 +       int count = 0;
4310 +       for (count = 0; count < VIRT_TO_BUS_CACHE_SIZE; count++)
4311 +               g_virtAddr[count] = 0xffffffff;                 //never going to match as we always chop the bottom bits anyway
4312 +
4313 +       g_cbVirtAddr = 0xffffffff;
4314 +
4315 +       g_cacheInsertAt = 0;
4316 +}
4317 +
4318 +//translate from a user virtual address to a bus address by mapping the page
4319 +//NB this won't lock a page in memory, so to avoid potential paging issues using kernel logical addresses
4320 +static inline void __iomem *UserVirtualToBus(void __user *pUser)
4321 +{
4322 +       int mapped;
4323 +       struct page *pPage;
4324 +       void *phys;
4325 +
4326 +       //map it (requiring that the pointer points to something that does not hang off the page boundary)
4327 +       mapped = get_user_pages(current, current->mm,
4328 +               (unsigned long)pUser, 1,
4329 +               1, 0,
4330 +               &pPage,
4331 +               0);
4332 +
4333 +       if (mapped <= 0)                //error
4334 +               return 0;
4335 +
4336 +       PRINTK_VERBOSE(KERN_DEBUG "user virtual %p arm phys %p bus %p\n",
4337 +                       pUser, page_address(pPage), (void __iomem *)__virt_to_bus(page_address(pPage)));
4338 +
4339 +       //get the arm physical address
4340 +       phys = page_address(pPage) + offset_in_page(pUser);
4341 +       page_cache_release(pPage);
4342 +
4343 +       //and now the bus address
4344 +       return (void __iomem *)__virt_to_bus(phys);
4345 +}
4346 +
4347 +static inline void __iomem *UserVirtualToBusViaCbCache(void __user *pUser)
4348 +{
4349 +       unsigned long virtual_page = (unsigned long)pUser & ~4095;
4350 +       unsigned long page_offset = (unsigned long)pUser & 4095;
4351 +       unsigned long bus_addr;
4352 +
4353 +       if (g_cbVirtAddr == virtual_page)
4354 +       {
4355 +               bus_addr = g_cbBusAddr + page_offset;
4356 +               g_cacheHit++;
4357 +               return (void __iomem *)bus_addr;
4358 +       }
4359 +       else
4360 +       {
4361 +               bus_addr = (unsigned long)UserVirtualToBus(pUser);
4362 +
4363 +               if (!bus_addr)
4364 +                       return 0;
4365 +
4366 +               g_cbVirtAddr = virtual_page;
4367 +               g_cbBusAddr = bus_addr & ~4095;
4368 +               g_cacheMiss++;
4369 +
4370 +               return (void __iomem *)bus_addr;
4371 +       }
4372 +}
4373 +
4374 +//do the same as above, by query our virt->bus cache
4375 +static inline void __iomem *UserVirtualToBusViaCache(void __user *pUser)
4376 +{
4377 +       int count;
4378 +       //get the page and its offset
4379 +       unsigned long virtual_page = (unsigned long)pUser & ~4095;
4380 +       unsigned long page_offset = (unsigned long)pUser & 4095;
4381 +       unsigned long bus_addr;
4382 +
4383 +       if (pUser >= g_pMinPhys && pUser < g_pMaxPhys)
4384 +       {
4385 +               PRINTK_VERBOSE(KERN_DEBUG "user->phys passthrough on %p\n", pUser);
4386 +               return (void __iomem *)((unsigned long)pUser + g_physOffset);
4387 +       }
4388 +
4389 +       //check the cache for our entry
4390 +       for (count = 0; count < VIRT_TO_BUS_CACHE_SIZE; count++)
4391 +               if (g_virtAddr[count] == virtual_page)
4392 +               {
4393 +                       bus_addr = g_busAddr[count] + page_offset;
4394 +                       g_cacheHit++;
4395 +                       return (void __iomem *)bus_addr;
4396 +               }
4397 +
4398 +       //not found, look up manually and then insert its page address
4399 +       bus_addr = (unsigned long)UserVirtualToBus(pUser);
4400 +
4401 +       if (!bus_addr)
4402 +               return 0;
4403 +
4404 +       g_virtAddr[g_cacheInsertAt] = virtual_page;
4405 +       g_busAddr[g_cacheInsertAt] = bus_addr & ~4095;
4406 +
4407 +       //round robin
4408 +       g_cacheInsertAt++;
4409 +       if (g_cacheInsertAt == VIRT_TO_BUS_CACHE_SIZE)
4410 +               g_cacheInsertAt = 0;
4411 +
4412 +       g_cacheMiss++;
4413 +
4414 +       return (void __iomem *)bus_addr;
4415 +}
4416 +
4417 +/***** FILE OPERATIONS ****/
4418 +static int Open(struct inode *pInode, struct file *pFile)
4419 +{
4420 +       PRINTK(KERN_DEBUG "file opening: %d/%d\n", imajor(pInode), iminor(pInode));
4421 +
4422 +       //check which device we are
4423 +       if (iminor(pInode) == 0)                //4k
4424 +       {
4425 +               //only one at a time
4426 +               if (!atomic_dec_and_test(&g_oneLock4k))
4427 +               {
4428 +                       atomic_inc(&g_oneLock4k);
4429 +                       return -EBUSY;
4430 +               }
4431 +       }
4432 +       else
4433 +               return -EINVAL;
4434 +
4435 +       //todo there will be trouble if two different processes open the files
4436 +
4437 +       //reset after any file is opened
4438 +       g_pMinPhys = (void __user *)-1;
4439 +       g_pMaxPhys = (void __user *)0;
4440 +       g_physOffset = 0;
4441 +       g_cmaHandle = 0;
4442 +
4443 +       return 0;
4444 +}
4445 +
4446 +static int Release(struct inode *pInode, struct file *pFile)
4447 +{
4448 +       PRINTK(KERN_DEBUG "file closing, %d pages tracked\n", g_trackedPages);
4449 +       if (g_trackedPages)
4450 +               PRINTK(KERN_ERR "we\'re leaking memory!\n");
4451 +
4452 +       //wait for any dmas to finish
4453 +       DmaWaitAll();
4454 +
4455 +       //free this memory on the application closing the file or it crashing (implicitly closing the file)
4456 +       if (g_cmaHandle)
4457 +       {
4458 +               PRINTK(KERN_DEBUG "unlocking vc memory\n");
4459 +               if (UnlockVcMemory(g_cmaHandle))
4460 +                       PRINTK(KERN_ERR "uh-oh, unable to unlock vc memory!\n");
4461 +               PRINTK(KERN_DEBUG "releasing vc memory\n");
4462 +               if (ReleaseVcMemory(g_cmaHandle))
4463 +                       PRINTK(KERN_ERR "uh-oh, unable to release vc memory!\n");
4464 +       }
4465 +
4466 +       if (iminor(pInode) == 0)
4467 +               atomic_inc(&g_oneLock4k);
4468 +       else
4469 +               return -EINVAL;
4470 +
4471 +       return 0;
4472 +}
4473 +
4474 +static struct DmaControlBlock __user *DmaPrepare(struct DmaControlBlock __user *pUserCB, int *pError)
4475 +{
4476 +       struct DmaControlBlock kernCB;
4477 +       struct DmaControlBlock __user *pUNext;
4478 +       void __iomem *pSourceBus, __iomem *pDestBus;
4479 +
4480 +       //get the control block into kernel memory so we can work on it
4481 +       if (copy_from_user(&kernCB, pUserCB, sizeof(struct DmaControlBlock)) != 0)
4482 +       {
4483 +               PRINTK(KERN_ERR "copy_from_user failed for user cb %p\n", pUserCB);
4484 +               *pError = 1;
4485 +               return 0;
4486 +       }
4487 +
4488 +       if (kernCB.m_pSourceAddr == 0 || kernCB.m_pDestAddr == 0)
4489 +       {
4490 +               PRINTK(KERN_ERR "faulty source (%p) dest (%p) addresses for user cb %p\n",
4491 +                       kernCB.m_pSourceAddr, kernCB.m_pDestAddr, pUserCB);
4492 +               *pError = 1;
4493 +               return 0;
4494 +       }
4495 +
4496 +       pSourceBus = UserVirtualToBusViaCache(kernCB.m_pSourceAddr);
4497 +       pDestBus = UserVirtualToBusViaCache(kernCB.m_pDestAddr);
4498 +
4499 +       if (!pSourceBus || !pDestBus)
4500 +       {
4501 +               PRINTK(KERN_ERR "virtual to bus translation failure for source/dest %p/%p->%p/%p\n",
4502 +                               kernCB.m_pSourceAddr, kernCB.m_pDestAddr,
4503 +                               pSourceBus, pDestBus);
4504 +               *pError = 1;
4505 +               return 0;
4506 +       }
4507 +
4508 +       //update the user structure with the new bus addresses
4509 +       kernCB.m_pSourceAddr = pSourceBus;
4510 +       kernCB.m_pDestAddr = pDestBus;
4511 +
4512 +       PRINTK_VERBOSE(KERN_DEBUG "final source %p dest %p\n", kernCB.m_pSourceAddr, kernCB.m_pDestAddr);
4513 +
4514 +       //sort out the bus address for the next block
4515 +       pUNext = kernCB.m_pNext;
4516 +
4517 +       if (kernCB.m_pNext)
4518 +       {
4519 +               void __iomem *pNextBus;
4520 +               pNextBus = UserVirtualToBusViaCbCache(kernCB.m_pNext);
4521 +
4522 +               if (!pNextBus)
4523 +               {
4524 +                       PRINTK(KERN_ERR "virtual to bus translation failure for m_pNext\n");
4525 +                       *pError = 1;
4526 +                       return 0;
4527 +               }
4528 +
4529 +               //update the pointer with the bus address
4530 +               kernCB.m_pNext = pNextBus;
4531 +       }
4532 +
4533 +       //write it back to user space
4534 +       if (copy_to_user(pUserCB, &kernCB, sizeof(struct DmaControlBlock)) != 0)
4535 +       {
4536 +               PRINTK(KERN_ERR "copy_to_user failed for cb %p\n", pUserCB);
4537 +               *pError = 1;
4538 +               return 0;
4539 +       }
4540 +
4541 +       __cpuc_flush_dcache_area(pUserCB, 32);
4542 +
4543 +       *pError = 0;
4544 +       return pUNext;
4545 +}
4546 +
4547 +static int DmaKick(struct DmaControlBlock __user *pUserCB)
4548 +{
4549 +       void __iomem *pBusCB;
4550 +
4551 +       pBusCB = UserVirtualToBusViaCbCache(pUserCB);
4552 +       if (!pBusCB)
4553 +       {
4554 +               PRINTK(KERN_ERR "virtual to bus translation failure for cb\n");
4555 +               return 1;
4556 +       }
4557 +
4558 +       //flush_cache_all();
4559 +
4560 +       bcm_dma_start(g_pDmaChanBase, (dma_addr_t)pBusCB);
4561 +
4562 +       return 0;
4563 +}
4564 +
4565 +static void DmaWaitAll(void)
4566 +{
4567 +       int counter = 0;
4568 +       volatile int inner_count;
4569 +       volatile unsigned int cs;
4570 +       unsigned long time_before, time_after;
4571 +
4572 +       time_before = jiffies;
4573 +       //bcm_dma_wait_idle(g_pDmaChanBase);
4574 +       dsb();
4575 +
4576 +       cs = readl(g_pDmaChanBase);
4577 +
4578 +       while ((cs & 1) == 1)
4579 +       {
4580 +               cs = readl(g_pDmaChanBase);
4581 +               counter++;
4582 +
4583 +               for (inner_count = 0; inner_count < 32; inner_count++);
4584 +
4585 +               asm volatile ("MCR p15,0,r0,c7,c0,4 \n");
4586 +               //cpu_do_idle();
4587 +               if (counter >= 1000000)
4588 +               {
4589 +                       PRINTK(KERN_WARNING "DMA failed to finish in a timely fashion\n");
4590 +                       break;
4591 +               }
4592 +       }
4593 +       time_after = jiffies;
4594 +       PRINTK_VERBOSE(KERN_DEBUG "done, counter %d, cs %08x", counter, cs);
4595 +       PRINTK_VERBOSE(KERN_DEBUG "took %ld jiffies, %d HZ\n", time_after - time_before, HZ);
4596 +}
4597 +
4598 +static long Ioctl(struct file *pFile, unsigned int cmd, unsigned long arg)
4599 +{
4600 +       int error = 0;
4601 +       PRINTK_VERBOSE(KERN_DEBUG "ioctl cmd %x arg %lx\n", cmd, arg);
4602 +
4603 +       switch (cmd)
4604 +       {
4605 +       case DMA_PREPARE:
4606 +       case DMA_PREPARE_KICK:
4607 +       case DMA_PREPARE_KICK_WAIT:
4608 +               {
4609 +                       struct DmaControlBlock __user *pUCB = (struct DmaControlBlock *)arg;
4610 +                       int steps = 0;
4611 +                       unsigned long start_time = jiffies;
4612 +                       (void)start_time;
4613 +
4614 +                       //flush our address cache
4615 +                       FlushAddrCache();
4616 +
4617 +                       PRINTK_VERBOSE(KERN_DEBUG "dma prepare\n");
4618 +
4619 +                       //do virtual to bus translation for each entry
4620 +                       do
4621 +                       {
4622 +                               pUCB = DmaPrepare(pUCB, &error);
4623 +                       } while (error == 0 && ++steps && pUCB);
4624 +                       PRINTK_VERBOSE(KERN_DEBUG "prepare done in %d steps, %ld\n", steps, jiffies - start_time);
4625 +
4626 +                       //carry straight on if we want to kick too
4627 +                       if (cmd == DMA_PREPARE || error)
4628 +                       {
4629 +                               PRINTK_VERBOSE(KERN_DEBUG "falling out\n");
4630 +                               return error ? -EINVAL : 0;
4631 +                       }
4632 +               }
4633 +       case DMA_KICK:
4634 +               PRINTK_VERBOSE(KERN_DEBUG "dma begin\n");
4635 +
4636 +               if (cmd == DMA_KICK)
4637 +                       FlushAddrCache();
4638 +
4639 +               DmaKick((struct DmaControlBlock __user *)arg);
4640 +
4641 +               if (cmd != DMA_PREPARE_KICK_WAIT)
4642 +                       break;
4643 +/*     case DMA_WAIT_ONE:
4644 +               //PRINTK(KERN_DEBUG "dma wait one\n");
4645 +               break;*/
4646 +       case DMA_WAIT_ALL:
4647 +               //PRINTK(KERN_DEBUG "dma wait all\n");
4648 +               DmaWaitAll();
4649 +               break;
4650 +       case DMA_MAX_BURST:
4651 +               if (g_dmaChan == 0)
4652 +                       return 10;
4653 +               else
4654 +                       return 5;
4655 +       case DMA_SET_MIN_PHYS:
4656 +               g_pMinPhys = (void __user *)arg;
4657 +               PRINTK(KERN_DEBUG "min/max user/phys bypass set to %p %p\n", g_pMinPhys, g_pMaxPhys);
4658 +               break;
4659 +       case DMA_SET_MAX_PHYS:
4660 +               g_pMaxPhys = (void __user *)arg;
4661 +               PRINTK(KERN_DEBUG "min/max user/phys bypass set to %p %p\n", g_pMinPhys, g_pMaxPhys);
4662 +               break;
4663 +       case DMA_SET_PHYS_OFFSET:
4664 +               g_physOffset = arg;
4665 +               PRINTK(KERN_DEBUG "user/phys bypass offset set to %ld\n", g_physOffset);
4666 +               break;
4667 +       case DMA_CMA_SET_SIZE:
4668 +       {
4669 +               unsigned int pBusAddr;
4670 +
4671 +               if (g_cmaHandle)
4672 +               {
4673 +                       PRINTK(KERN_ERR "memory has already been allocated (handle %d)\n", g_cmaHandle);
4674 +                       return -EINVAL;
4675 +               }
4676 +
4677 +               PRINTK(KERN_INFO "allocating %ld bytes of VC memory\n", arg * 4096);
4678 +
4679 +               //get the memory
4680 +               if (AllocateVcMemory(&g_cmaHandle, arg * 4096, 4096, MEM_FLAG_L1_NONALLOCATING | MEM_FLAG_NO_INIT | MEM_FLAG_HINT_PERMALOCK))
4681 +               {
4682 +                       PRINTK(KERN_ERR "failed to allocate %ld bytes of VC memory\n", arg * 4096);
4683 +                       g_cmaHandle = 0;
4684 +                       return -EINVAL;
4685 +               }
4686 +
4687 +               //get an address for it
4688 +               PRINTK(KERN_INFO "trying to map VC memory\n");
4689 +
4690 +               if (LockVcMemory(&pBusAddr, g_cmaHandle))
4691 +               {
4692 +                       PRINTK(KERN_ERR "failed to map CMA handle %d, releasing memory\n", g_cmaHandle);
4693 +                       ReleaseVcMemory(g_cmaHandle);
4694 +                       g_cmaHandle = 0;
4695 +               }
4696 +
4697 +               PRINTK(KERN_INFO "bus address for CMA memory is %x\n", pBusAddr);
4698 +               return pBusAddr;
4699 +       }
4700 +       case DMA_GET_VERSION:
4701 +               PRINTK(KERN_DEBUG "returning version number, %d\n", VERSION_NUMBER);
4702 +               return VERSION_NUMBER;
4703 +       default:
4704 +               PRINTK(KERN_DEBUG "unknown ioctl: %d\n", cmd);
4705 +               return -EINVAL;
4706 +       }
4707 +
4708 +       return 0;
4709 +}
4710 +
4711 +static ssize_t Read(struct file *pFile, char __user *pUser, size_t count, loff_t *offp)
4712 +{
4713 +       return -EIO;
4714 +}
4715 +
4716 +static int Mmap(struct file *pFile, struct vm_area_struct *pVma)
4717 +{
4718 +       struct PageList *pPages;
4719 +       struct VmaPageList *pVmaList;
4720 +
4721 +       PRINTK_VERBOSE(KERN_DEBUG "MMAP vma %p, length %ld (%s %d)\n",
4722 +               pVma, pVma->vm_end - pVma->vm_start,
4723 +               current->comm, current->pid);
4724 +       PRINTK_VERBOSE(KERN_DEBUG "MMAP %p %d (tracked %d)\n", pVma, current->pid, g_trackedPages);
4725 +
4726 +       //make a new page list
4727 +       pPages = (struct PageList *)kmalloc(sizeof(struct PageList), GFP_KERNEL);
4728 +       if (!pPages)
4729 +       {
4730 +               PRINTK(KERN_ERR "couldn\'t allocate a new page list (%s %d)\n",
4731 +                       current->comm, current->pid);
4732 +               return -ENOMEM;
4733 +       }
4734 +
4735 +       //clear the page list
4736 +       pPages->m_used = 0;
4737 +       pPages->m_pNext = 0;
4738 +
4739 +       //insert our vma and new page list somewhere
4740 +       if (!pVma->vm_private_data)
4741 +       {
4742 +               struct VmaPageList *pList;
4743 +
4744 +               PRINTK_VERBOSE(KERN_DEBUG "new vma list, making new one (%s %d)\n",
4745 +                       current->comm, current->pid);
4746 +
4747 +               //make a new vma list
4748 +               pList = (struct VmaPageList *)kmalloc(sizeof(struct VmaPageList), GFP_KERNEL);
4749 +               if (!pList)
4750 +               {
4751 +                       PRINTK(KERN_ERR "couldn\'t allocate vma page list (%s %d)\n",
4752 +                               current->comm, current->pid);
4753 +                       kfree(pPages);
4754 +                       return -ENOMEM;
4755 +               }
4756 +
4757 +               //clear this list
4758 +               pVma->vm_private_data = (void *)pList;
4759 +               pList->m_refCount = 0;
4760 +       }
4761 +
4762 +       pVmaList = (struct VmaPageList *)pVma->vm_private_data;
4763 +
4764 +       //add it to the vma list
4765 +       pVmaList->m_pPageHead = pPages;
4766 +       pVmaList->m_pPageTail = pPages;
4767 +
4768 +       pVma->vm_ops = &g_vmOps4k;
4769 +       pVma->vm_flags |= VM_IO;
4770 +
4771 +       VmaOpen4k(pVma);
4772 +
4773 +       return 0;
4774 +}
4775 +
4776 +/****** VMA OPERATIONS ******/
4777 +
4778 +static void VmaOpen4k(struct vm_area_struct *pVma)
4779 +{
4780 +       struct VmaPageList *pVmaList;
4781 +
4782 +       PRINTK_VERBOSE(KERN_DEBUG "vma open %p private %p (%s %d), %d live pages\n", pVma, pVma->vm_private_data, current->comm, current->pid, g_trackedPages);
4783 +       PRINTK_VERBOSE(KERN_DEBUG "OPEN %p %d %ld pages (tracked pages %d)\n",
4784 +               pVma, current->pid, (pVma->vm_end - pVma->vm_start) >> 12,
4785 +               g_trackedPages);
4786 +
4787 +       pVmaList = (struct VmaPageList *)pVma->vm_private_data;
4788 +
4789 +       if (pVmaList)
4790 +       {
4791 +               pVmaList->m_refCount++;
4792 +               PRINTK_VERBOSE(KERN_DEBUG "ref count is now %d\n", pVmaList->m_refCount);
4793 +       }
4794 +       else
4795 +       {
4796 +               PRINTK_VERBOSE(KERN_DEBUG "err, open but no vma page list\n");
4797 +       }
4798 +}
4799 +
4800 +static void VmaClose4k(struct vm_area_struct *pVma)
4801 +{
4802 +       struct VmaPageList *pVmaList;
4803 +       int freed = 0;
4804 +
4805 +       PRINTK_VERBOSE(KERN_DEBUG "vma close %p private %p (%s %d)\n", pVma, pVma->vm_private_data, current->comm, current->pid);
4806 +
4807 +       //wait for any dmas to finish
4808 +       DmaWaitAll();
4809 +
4810 +       //find our vma in the list
4811 +       pVmaList = (struct VmaPageList *)pVma->vm_private_data;
4812 +
4813 +       //may be a fork
4814 +       if (pVmaList)
4815 +       {
4816 +               struct PageList *pPages;
4817 +
4818 +               pVmaList->m_refCount--;
4819 +
4820 +               if (pVmaList->m_refCount == 0)
4821 +               {
4822 +                       PRINTK_VERBOSE(KERN_DEBUG "found vma, freeing pages (%s %d)\n",
4823 +                               current->comm, current->pid);
4824 +
4825 +                       pPages = pVmaList->m_pPageHead;
4826 +
4827 +                       if (!pPages)
4828 +                       {
4829 +                               PRINTK(KERN_ERR "no page list (%s %d)!\n",
4830 +                                       current->comm, current->pid);
4831 +                               return;
4832 +                       }
4833 +
4834 +                       while (pPages)
4835 +                       {
4836 +                               struct PageList *next;
4837 +                               int count;
4838 +
4839 +                               PRINTK_VERBOSE(KERN_DEBUG "page list (%s %d)\n",
4840 +                                       current->comm, current->pid);
4841 +
4842 +                               next = pPages->m_pNext;
4843 +                               for (count = 0; count < pPages->m_used; count++)
4844 +                               {
4845 +                                       PRINTK_VERBOSE(KERN_DEBUG "freeing page %p (%s %d)\n",
4846 +                                               pPages->m_pPages[count],
4847 +                                               current->comm, current->pid);
4848 +                                       __free_pages(pPages->m_pPages[count], 0);
4849 +                                       g_trackedPages--;
4850 +                                       freed++;
4851 +                               }
4852 +
4853 +                               PRINTK_VERBOSE(KERN_DEBUG "freeing page list (%s %d)\n",
4854 +                                       current->comm, current->pid);
4855 +                               kfree(pPages);
4856 +                               pPages = next;
4857 +                       }
4858 +
4859 +                       //remove our vma from the list
4860 +                       kfree(pVmaList);
4861 +                       pVma->vm_private_data = 0;
4862 +               }
4863 +               else
4864 +               {
4865 +                       PRINTK_VERBOSE(KERN_DEBUG "ref count is %d, not closing\n", pVmaList->m_refCount);
4866 +               }
4867 +       }
4868 +       else
4869 +       {
4870 +               PRINTK_VERBOSE(KERN_ERR "uh-oh, vma %p not found (%s %d)!\n", pVma, current->comm, current->pid);
4871 +               PRINTK_VERBOSE(KERN_ERR "CLOSE ERR\n");
4872 +       }
4873 +
4874 +       PRINTK_VERBOSE(KERN_DEBUG "CLOSE %p %d %d pages (tracked pages %d)",
4875 +               pVma, current->pid, freed, g_trackedPages);
4876 +
4877 +       PRINTK_VERBOSE(KERN_DEBUG "%d pages open\n", g_trackedPages);
4878 +}
4879 +
4880 +static int VmaFault4k(struct vm_area_struct *pVma, struct vm_fault *pVmf)
4881 +{
4882 +       PRINTK_VERBOSE(KERN_DEBUG "vma fault for vma %p private %p at offset %ld (%s %d)\n", pVma, pVma->vm_private_data, pVmf->pgoff,
4883 +               current->comm, current->pid);
4884 +       PRINTK_VERBOSE(KERN_DEBUG "FAULT\n");
4885 +       pVmf->page = alloc_page(GFP_KERNEL);
4886 +
4887 +       if (pVmf->page)
4888 +       {
4889 +               PRINTK_VERBOSE(KERN_DEBUG "alloc page virtual %p\n", page_address(pVmf->page));
4890 +       }
4891 +
4892 +       if (!pVmf->page)
4893 +       {
4894 +               PRINTK(KERN_ERR "vma fault oom (%s %d)\n", current->comm, current->pid);
4895 +               return VM_FAULT_OOM;
4896 +       }
4897 +       else
4898 +       {
4899 +               struct VmaPageList *pVmaList;
4900 +
4901 +               get_page(pVmf->page);
4902 +               g_trackedPages++;
4903 +
4904 +               //find our vma in the list
4905 +               pVmaList = (struct VmaPageList *)pVma->vm_private_data;
4906 +
4907 +               if (pVmaList)
4908 +               {
4909 +                       PRINTK_VERBOSE(KERN_DEBUG "vma found (%s %d)\n", current->comm, current->pid);
4910 +
4911 +                       if (pVmaList->m_pPageTail->m_used == PAGES_PER_LIST)
4912 +                       {
4913 +                               PRINTK_VERBOSE(KERN_DEBUG "making new page list (%s %d)\n", current->comm, current->pid);
4914 +                               //making a new page list
4915 +                               pVmaList->m_pPageTail->m_pNext = (struct PageList *)kmalloc(sizeof(struct PageList), GFP_KERNEL);
4916 +                               if (!pVmaList->m_pPageTail->m_pNext)
4917 +                                       return -ENOMEM;
4918 +
4919 +                               //update the tail pointer
4920 +                               pVmaList->m_pPageTail = pVmaList->m_pPageTail->m_pNext;
4921 +                               pVmaList->m_pPageTail->m_used = 0;
4922 +                               pVmaList->m_pPageTail->m_pNext = 0;
4923 +                       }
4924 +
4925 +                       PRINTK_VERBOSE(KERN_DEBUG "adding page to list (%s %d)\n", current->comm, current->pid);
4926 +
4927 +                       pVmaList->m_pPageTail->m_pPages[pVmaList->m_pPageTail->m_used] = pVmf->page;
4928 +                       pVmaList->m_pPageTail->m_used++;
4929 +               }
4930 +               else
4931 +                       PRINTK(KERN_ERR "returned page for vma we don\'t know %p (%s %d)\n", pVma, current->comm, current->pid);
4932 +
4933 +               return 0;
4934 +       }
4935 +}
4936 +
4937 +/****** GENERIC FUNCTIONS ******/
4938 +static int __init dmaer_init(void)
4939 +{
4940 +       int result = alloc_chrdev_region(&g_majorMinor, 0, 1, "dmaer");
4941 +       if (result < 0)
4942 +       {
4943 +               PRINTK(KERN_ERR "unable to get major device number\n");
4944 +               return result;
4945 +       }
4946 +       else
4947 +               PRINTK(KERN_DEBUG "major device number %d\n", MAJOR(g_majorMinor));
4948 +
4949 +       PRINTK(KERN_DEBUG "vma list size %d, page list size %d, page size %ld\n",
4950 +               sizeof(struct VmaPageList), sizeof(struct PageList), PAGE_SIZE);
4951 +
4952 +       //get a dma channel to work with
4953 +       result = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST, (void **)&g_pDmaChanBase, &g_dmaIrq);
4954 +
4955 +       //uncomment to force to channel 0
4956 +       //result = 0;
4957 +       //g_pDmaChanBase = 0xce808000;
4958 +
4959 +       if (result < 0)
4960 +       {
4961 +               PRINTK(KERN_ERR "failed to allocate dma channel\n");
4962 +               cdev_del(&g_cDev);
4963 +               unregister_chrdev_region(g_majorMinor, 1);
4964 +       }
4965 +
4966 +       //reset the channel
4967 +       PRINTK(KERN_DEBUG "allocated dma channel %d (%p), initial state %08x\n", result, g_pDmaChanBase, *g_pDmaChanBase);
4968 +       *g_pDmaChanBase = 1 << 31;
4969 +       PRINTK(KERN_DEBUG "post-reset %08x\n", *g_pDmaChanBase);
4970 +
4971 +       g_dmaChan = result;
4972 +
4973 +       //clear the cache stats
4974 +       g_cacheHit = 0;
4975 +       g_cacheMiss = 0;
4976 +
4977 +       //register our device - after this we are go go go
4978 +       cdev_init(&g_cDev, &g_fOps);
4979 +       g_cDev.owner = THIS_MODULE;
4980 +       g_cDev.ops = &g_fOps;
4981 +
4982 +       result = cdev_add(&g_cDev, g_majorMinor, 1);
4983 +       if (result < 0)
4984 +       {
4985 +               PRINTK(KERN_ERR "failed to add character device\n");
4986 +               unregister_chrdev_region(g_majorMinor, 1);
4987 +               bcm_dma_chan_free(g_dmaChan);
4988 +               return result;
4989 +       }
4990 +
4991 +       return 0;
4992 +}
4993 +
4994 +static void __exit dmaer_exit(void)
4995 +{
4996 +       PRINTK(KERN_INFO "closing dmaer device, cache stats: %d hits %d misses\n", g_cacheHit, g_cacheMiss);
4997 +       //unregister the device
4998 +       cdev_del(&g_cDev);
4999 +       unregister_chrdev_region(g_majorMinor, 1);
5000 +       //free the dma channel
5001 +       bcm_dma_chan_free(g_dmaChan);
5002 +}
5003 +
5004 +MODULE_LICENSE("Dual BSD/GPL");
5005 +MODULE_AUTHOR("Simon Hall");
5006 +module_init(dmaer_init);
5007 +module_exit(dmaer_exit);
5008 +
5009 --- /dev/null
5010 +++ b/arch/arm/mach-bcm2708/include/mach/arm_control.h
5011 @@ -0,0 +1,419 @@
5012 +/*
5013 + *  linux/arch/arm/mach-bcm2708/arm_control.h
5014 + *
5015 + *  Copyright (C) 2010 Broadcom
5016 + *
5017 + * This program is free software; you can redistribute it and/or modify
5018 + * it under the terms of the GNU General Public License as published by
5019 + * the Free Software Foundation; either version 2 of the License, or
5020 + * (at your option) any later version.
5021 + *
5022 + * This program is distributed in the hope that it will be useful,
5023 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5024 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5025 + * GNU General Public License for more details.
5026 + *
5027 + * You should have received a copy of the GNU General Public License
5028 + * along with this program; if not, write to the Free Software
5029 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5030 + */
5031 +
5032 +#ifndef __BCM2708_ARM_CONTROL_H
5033 +#define __BCM2708_ARM_CONTROL_H
5034 +
5035 +/*
5036 + * Definitions and addresses for the ARM CONTROL logic
5037 + * This file is manually generated.
5038 + */
5039 +
5040 +#define ARM_BASE  0x7E00B000
5041 +
5042 +/* Basic configuration */
5043 +#define ARM_CONTROL0  HW_REGISTER_RW(ARM_BASE+0x000)
5044 +#define ARM_C0_SIZ128M   0x00000000
5045 +#define ARM_C0_SIZ256M   0x00000001
5046 +#define ARM_C0_SIZ512M   0x00000002
5047 +#define ARM_C0_SIZ1G     0x00000003
5048 +#define ARM_C0_BRESP0    0x00000000
5049 +#define ARM_C0_BRESP1    0x00000004
5050 +#define ARM_C0_BRESP2    0x00000008
5051 +#define ARM_C0_BOOTHI    0x00000010
5052 +#define ARM_C0_UNUSED05  0x00000020 /* free */
5053 +#define ARM_C0_FULLPERI  0x00000040
5054 +#define ARM_C0_UNUSED78  0x00000180 /* free */
5055 +#define ARM_C0_JTAGMASK  0x00000E00
5056 +#define ARM_C0_JTAGOFF   0x00000000
5057 +#define ARM_C0_JTAGBASH  0x00000800 /* Debug on GPIO off */
5058 +#define ARM_C0_JTAGGPIO  0x00000C00 /* Debug on GPIO on */
5059 +#define ARM_C0_APROTMSK  0x0000F000
5060 +#define ARM_C0_DBG0SYNC  0x00010000 /* VPU0 halt sync */
5061 +#define ARM_C0_DBG1SYNC  0x00020000 /* VPU1 halt sync */
5062 +#define ARM_C0_SWDBGREQ  0x00040000 /* HW debug request */
5063 +#define ARM_C0_PASSHALT  0x00080000 /* ARM halt passed to debugger */
5064 +#define ARM_C0_PRIO_PER  0x00F00000 /* per priority mask */
5065 +#define ARM_C0_PRIO_L2   0x0F000000
5066 +#define ARM_C0_PRIO_UC   0xF0000000
5067 +
5068 +#define ARM_C0_APROTPASS  0x0000A000 /* Translate 1:1 */
5069 +#define ARM_C0_APROTUSER  0x00000000 /* Only user mode */
5070 +#define ARM_C0_APROTSYST  0x0000F000 /* Only system mode */
5071 +
5072 +
5073 +#define ARM_CONTROL1  HW_REGISTER_RW(ARM_BASE+0x440)
5074 +#define ARM_C1_TIMER     0x00000001 /* re-route timer IRQ  to VC */
5075 +#define ARM_C1_MAIL      0x00000002 /* re-route Mail IRQ   to VC */
5076 +#define ARM_C1_BELL0     0x00000004 /* re-route Doorbell 0 to VC */
5077 +#define ARM_C1_BELL1     0x00000008 /* re-route Doorbell 1 to VC */
5078 +#define ARM_C1_PERSON    0x00000100 /* peripherals on */
5079 +#define ARM_C1_REQSTOP   0x00000200 /* ASYNC bridge request stop */
5080 +
5081 +#define ARM_STATUS    HW_REGISTER_RW(ARM_BASE+0x444)
5082 +#define ARM_S_ACKSTOP    0x80000000 /* Bridge stopped */
5083 +#define ARM_S_READPEND   0x000003FF /* pending reads counter */
5084 +#define ARM_S_WRITPEND   0x000FFC00 /* pending writes counter */
5085 +
5086 +#define ARM_ERRHALT   HW_REGISTER_RW(ARM_BASE+0x448)
5087 +#define ARM_EH_PERIBURST  0x00000001 /* Burst write seen on peri bus */
5088 +#define ARM_EH_ILLADDRS1  0x00000002 /* Address bits 25-27 error */
5089 +#define ARM_EH_ILLADDRS2  0x00000004 /* Address bits 31-28 error */
5090 +#define ARM_EH_VPU0HALT   0x00000008 /* VPU0 halted & in debug mode */
5091 +#define ARM_EH_VPU1HALT   0x00000010 /* VPU1 halted & in debug mode */
5092 +#define ARM_EH_ARMHALT    0x00000020 /* ARM in halted debug mode */
5093 +
5094 +#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
5095 +#define ARM_ID        HW_REGISTER_RW(ARM_BASE+0x44C)
5096 +#define ARM_IDVAL        0x364D5241
5097 +
5098 +/* Translation memory */
5099 +#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
5100 +/* 32 locations: 0x100.. 0x17F */
5101 +/* 32 spare means we CAN go to 64 pages.... */
5102 +
5103 +
5104 +/* Interrupts */
5105 +#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200)        /* Top IRQ bits */
5106 +#define ARM_I0_TIMER    0x00000001 /* timer IRQ */
5107 +#define ARM_I0_MAIL     0x00000002 /* Mail IRQ */
5108 +#define ARM_I0_BELL0    0x00000004 /* Doorbell 0 */
5109 +#define ARM_I0_BELL1    0x00000008 /* Doorbell 1 */
5110 +#define ARM_I0_BANK1    0x00000100 /* Bank1 IRQ */
5111 +#define ARM_I0_BANK2    0x00000200 /* Bank2 IRQ */
5112 +
5113 +#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
5114 +/* todo: all I1_interrupt sources */
5115 +#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
5116 +/* todo: all I2_interrupt sources */
5117 +
5118 +#define ARM_IRQ_FAST  HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
5119 +#define ARM_IF_INDEX    0x0000007F     /* FIQ select */
5120 +#define ARM_IF_ENABLE   0x00000080     /* FIQ enable */
5121 +#define ARM_IF_VCMASK   0x0000003F     /* FIQ = (index from VC source) */
5122 +#define ARM_IF_TIMER    0x00000040     /* FIQ = ARM timer */
5123 +#define ARM_IF_MAIL     0x00000041     /* FIQ = ARM Mail */
5124 +#define ARM_IF_BELL0    0x00000042     /* FIQ = ARM Doorbell 0 */
5125 +#define ARM_IF_BELL1    0x00000043     /* FIQ = ARM Doorbell 1 */
5126 +#define ARM_IF_VP0HALT  0x00000044     /* FIQ = VPU0 Halt seen */
5127 +#define ARM_IF_VP1HALT  0x00000045     /* FIQ = VPU1 Halt seen */
5128 +#define ARM_IF_ILLEGAL  0x00000046     /* FIQ = Illegal access seen */
5129 +
5130 +#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
5131 +#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
5132 +#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
5133 +#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
5134 +#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
5135 +#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
5136 +#define ARM_IE_TIMER    0x00000001     /* Timer IRQ */
5137 +#define ARM_IE_MAIL     0x00000002     /* Mail IRQ */
5138 +#define ARM_IE_BELL0    0x00000004     /* Doorbell 0 */
5139 +#define ARM_IE_BELL1    0x00000008     /* Doorbell 1 */
5140 +#define ARM_IE_VP0HALT  0x00000010     /* VPU0 Halt */
5141 +#define ARM_IE_VP1HALT  0x00000020     /* VPU1 Halt */
5142 +#define ARM_IE_ILLEGAL  0x00000040     /* Illegal access seen */
5143 +
5144 +/* Timer */
5145 +/* For reg. fields see sp804 spec. */
5146 +#define ARM_T_LOAD    HW_REGISTER_RW(ARM_BASE+0x400)
5147 +#define ARM_T_VALUE   HW_REGISTER_RW(ARM_BASE+0x404)
5148 +#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
5149 +#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
5150 +#define ARM_T_RAWIRQ  HW_REGISTER_RW(ARM_BASE+0x410)
5151 +#define ARM_T_MSKIRQ  HW_REGISTER_RW(ARM_BASE+0x414)
5152 +#define ARM_T_RELOAD  HW_REGISTER_RW(ARM_BASE+0x418)
5153 +#define ARM_T_PREDIV  HW_REGISTER_RW(ARM_BASE+0x41c)
5154 +#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
5155 +
5156 +#define TIMER_CTRL_ONESHOT  (1 << 0)
5157 +#define TIMER_CTRL_32BIT    (1 << 1)
5158 +#define TIMER_CTRL_DIV1     (0 << 2)
5159 +#define TIMER_CTRL_DIV16    (1 << 2)
5160 +#define TIMER_CTRL_DIV256   (2 << 2)
5161 +#define TIMER_CTRL_IE       (1 << 5)
5162 +#define TIMER_CTRL_PERIODIC (1 << 6)
5163 +#define TIMER_CTRL_ENABLE   (1 << 7)
5164 +#define TIMER_CTRL_DBGHALT  (1 << 8)
5165 +#define TIMER_CTRL_ENAFREE  (1 << 9)
5166 +#define TIMER_CTRL_FREEDIV_SHIFT 16)
5167 +#define TIMER_CTRL_FREEDIV_MASK  0xff
5168 +
5169 +/* Semaphores, Doorbells, Mailboxes */
5170 +#define ARM_SBM_OWN0  (ARM_BASE+0x800)
5171 +#define ARM_SBM_OWN1  (ARM_BASE+0x900)
5172 +#define ARM_SBM_OWN2  (ARM_BASE+0xA00)
5173 +#define ARM_SBM_OWN3  (ARM_BASE+0xB00)
5174 +
5175 +/* MAILBOXES
5176 + * Register flags are common across all
5177 + * owner registers. See end of this section
5178 + *
5179 + * Semaphores, Doorbells, Mailboxes Owner 0
5180 + *
5181 + */
5182 +
5183 +#define ARM_0_SEMS       HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
5184 +#define ARM_0_SEM0       HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
5185 +#define ARM_0_SEM1       HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
5186 +#define ARM_0_SEM2       HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
5187 +#define ARM_0_SEM3       HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
5188 +#define ARM_0_SEM4       HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
5189 +#define ARM_0_SEM5       HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
5190 +#define ARM_0_SEM6       HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
5191 +#define ARM_0_SEM7       HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
5192 +#define ARM_0_BELL0      HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
5193 +#define ARM_0_BELL1      HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
5194 +#define ARM_0_BELL2      HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
5195 +#define ARM_0_BELL3      HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
5196 +/* MAILBOX 0 access in Owner 0 area */
5197 +/* Some addresses should ONLY be used by owner 0 */
5198 +#define ARM_0_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN0+0x80)  /* .. 0x8C (4 locations) */
5199 +#define ARM_0_MAIL0_RD   HW_REGISTER_RW(ARM_SBM_OWN0+0x80)  /* .. 0x8C (4 locations) Normal read */
5200 +#define ARM_0_MAIL0_POL  HW_REGISTER_RW(ARM_SBM_OWN0+0x90)  /* none-pop read */
5201 +#define ARM_0_MAIL0_SND  HW_REGISTER_RW(ARM_SBM_OWN0+0x94)  /* Sender read (only LS 2 bits) */
5202 +#define ARM_0_MAIL0_STA  HW_REGISTER_RW(ARM_SBM_OWN0+0x98)  /* Status read */
5203 +#define ARM_0_MAIL0_CNF  HW_REGISTER_RW(ARM_SBM_OWN0+0x9C)  /* Config read/write */
5204 +/* MAILBOX 1 access in Owner 0 area */
5205 +/* Owner 0 should only WRITE to this mailbox */
5206 +#define ARM_0_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN0+0xA0)   /* .. 0xAC (4 locations) */
5207 +/*#define ARM_0_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
5208 +/*#define ARM_0_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
5209 +/*#define ARM_0_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
5210 +#define ARM_0_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN0+0xB8)   /* Status read */
5211 +/*#define ARM_0_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
5212 +/* General SEM, BELL, MAIL config/status */
5213 +#define ARM_0_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN0+0xE0)  /* semaphore clear/debug register */
5214 +#define ARM_0_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN0+0xE4)  /* Doorbells clear/debug register */
5215 +#define ARM_0_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN0+0xF8)  /* ALL interrupts */
5216 +#define ARM_0_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN0+0xFC)  /* IRQS pending for owner 0 */
5217 +
5218 +/* Semaphores, Doorbells, Mailboxes Owner 1 */
5219 +#define ARM_1_SEMS       HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
5220 +#define ARM_1_SEM0       HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
5221 +#define ARM_1_SEM1       HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
5222 +#define ARM_1_SEM2       HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
5223 +#define ARM_1_SEM3       HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
5224 +#define ARM_1_SEM4       HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
5225 +#define ARM_1_SEM5       HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
5226 +#define ARM_1_SEM6       HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
5227 +#define ARM_1_SEM7       HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
5228 +#define ARM_1_BELL0      HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
5229 +#define ARM_1_BELL1      HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
5230 +#define ARM_1_BELL2      HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
5231 +#define ARM_1_BELL3      HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
5232 +/* MAILBOX 0 access in Owner 0 area */
5233 +/* Owner 1 should only WRITE to this mailbox */
5234 +#define ARM_1_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN1+0x80)  /* .. 0x8C (4 locations) */
5235 +/*#define ARM_1_MAIL0_RD  HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
5236 +/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
5237 +/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
5238 +#define ARM_1_MAIL0_STA  HW_REGISTER_RW(ARM_SBM_OWN1+0x98)  /* Status read */
5239 +/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
5240 +/* MAILBOX 1 access in Owner 0 area */
5241 +#define ARM_1_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN1+0xA0)  /* .. 0xAC (4 locations) */
5242 +#define ARM_1_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN1+0xA0)  /* .. 0xAC (4 locations) Normal read */
5243 +#define ARM_1_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN1+0xB0)  /* none-pop read */
5244 +#define ARM_1_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN1+0xB4)  /* Sender read (only LS 2 bits) */
5245 +#define ARM_1_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN1+0xB8)  /* Status read */
5246 +#define ARM_1_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
5247 +/* General SEM, BELL, MAIL config/status */
5248 +#define ARM_1_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN1+0xE0)  /* semaphore clear/debug register */
5249 +#define ARM_1_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN1+0xE4)  /* Doorbells clear/debug register */
5250 +#define ARM_1_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN1+0xFC)  /* IRQS pending for owner 1 */
5251 +#define ARM_1_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN1+0xF8)  /* ALL interrupts */
5252 +
5253 +/* Semaphores, Doorbells, Mailboxes Owner 2 */
5254 +#define ARM_2_SEMS       HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
5255 +#define ARM_2_SEM0       HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
5256 +#define ARM_2_SEM1       HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
5257 +#define ARM_2_SEM2       HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
5258 +#define ARM_2_SEM3       HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
5259 +#define ARM_2_SEM4       HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
5260 +#define ARM_2_SEM5       HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
5261 +#define ARM_2_SEM6       HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
5262 +#define ARM_2_SEM7       HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
5263 +#define ARM_2_BELL0      HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
5264 +#define ARM_2_BELL1      HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
5265 +#define ARM_2_BELL2      HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
5266 +#define ARM_2_BELL3      HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
5267 +/* MAILBOX 0 access in Owner 2 area */
5268 +/* Owner 2 should only WRITE to this mailbox */
5269 +#define ARM_2_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN2+0x80)   /* .. 0x8C (4 locations) */
5270 +/*#define ARM_2_MAIL0_RD  HW_REGISTER_RW(ARM_SBM_OWN2+0x80)  */ /* DO NOT USE THIS !!!!! */
5271 +/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90)  */ /* DO NOT USE THIS !!!!! */
5272 +/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94)  */ /* DO NOT USE THIS !!!!! */
5273 +#define ARM_2_MAIL0_STA  HW_REGISTER_RW(ARM_SBM_OWN2+0x98)   /* Status read */
5274 +/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C)  */ /* DO NOT USE THIS !!!!! */
5275 +/* MAILBOX 1 access in Owner 2 area */
5276 +/* Owner 2 should only WRITE to this mailbox */
5277 +#define ARM_2_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN2+0xA0)   /* .. 0xAC (4 locations) */
5278 +/*#define ARM_2_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
5279 +/*#define ARM_2_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
5280 +/*#define ARM_2_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
5281 +#define ARM_2_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN2+0xB8)   /* Status read */
5282 +/*#define ARM_2_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
5283 +/* General SEM, BELL, MAIL config/status */
5284 +#define ARM_2_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN2+0xE0)  /* semaphore clear/debug register */
5285 +#define ARM_2_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN2+0xE4)  /* Doorbells clear/debug register */
5286 +#define ARM_2_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN2+0xFC)  /* IRQS pending for owner 2 */
5287 +#define ARM_2_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN2+0xF8)  /* ALL interrupts */
5288 +
5289 +/* Semaphores, Doorbells, Mailboxes Owner 3 */
5290 +#define ARM_3_SEMS       HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
5291 +#define ARM_3_SEM0       HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
5292 +#define ARM_3_SEM1       HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
5293 +#define ARM_3_SEM2       HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
5294 +#define ARM_3_SEM3       HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
5295 +#define ARM_3_SEM4       HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
5296 +#define ARM_3_SEM5       HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
5297 +#define ARM_3_SEM6       HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
5298 +#define ARM_3_SEM7       HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
5299 +#define ARM_3_BELL0      HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
5300 +#define ARM_3_BELL1      HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
5301 +#define ARM_3_BELL2      HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
5302 +#define ARM_3_BELL3      HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
5303 +/* MAILBOX 0 access in Owner 3 area */
5304 +/* Owner 3 should only WRITE to this mailbox */
5305 +#define ARM_3_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN3+0x80)   /* .. 0x8C (4 locations) */
5306 +/*#define ARM_3_MAIL0_RD  HW_REGISTER_RW(ARM_SBM_OWN3+0x80)  */ /* DO NOT USE THIS !!!!! */
5307 +/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90)  */ /* DO NOT USE THIS !!!!! */
5308 +/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94)  */ /* DO NOT USE THIS !!!!! */
5309 +#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98)    /* Status read */
5310 +/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C)  */ /* DO NOT USE THIS !!!!! */
5311 +/* MAILBOX 1 access in Owner 3 area */
5312 +/* Owner 3 should only WRITE to this mailbox */
5313 +#define ARM_3_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN3+0xA0)   /* .. 0xAC (4 locations) */
5314 +/*#define ARM_3_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
5315 +/*#define ARM_3_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
5316 +/*#define ARM_3_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
5317 +#define ARM_3_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN3+0xB8)   /* Status read */
5318 +/*#define ARM_3_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
5319 +/* General SEM, BELL, MAIL config/status */
5320 +#define ARM_3_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN3+0xE0)  /* semaphore clear/debug register */
5321 +#define ARM_3_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN3+0xE4)  /* Doorbells clear/debug register */
5322 +#define ARM_3_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN3+0xFC)  /* IRQS pending for owner 3 */
5323 +#define ARM_3_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN3+0xF8)  /* ALL interrupts */
5324 +
5325 +
5326 +
5327 +/*  Mailbox flags. Valid for all owners */
5328 +
5329 +/* Mailbox status register (...0x98) */
5330 +#define ARM_MS_FULL       0x80000000
5331 +#define ARM_MS_EMPTY      0x40000000
5332 +#define ARM_MS_LEVEL      0x400000FF /* Max. value depdnds on mailbox depth parameter */
5333 +
5334 +/* MAILBOX config/status register (...0x9C) */
5335 +/* ANY write to this register clears the error bits! */
5336 +#define ARM_MC_IHAVEDATAIRQEN    0x00000001 /* mailbox irq enable:  has data */
5337 +#define ARM_MC_IHAVESPACEIRQEN   0x00000002 /* mailbox irq enable:  has space */
5338 +#define ARM_MC_OPPISEMPTYIRQEN   0x00000004 /* mailbox irq enable: Opp. is empty */
5339 +#define ARM_MC_MAIL_CLEAR        0x00000008 /* mailbox clear write 1, then  0 */
5340 +#define ARM_MC_IHAVEDATAIRQPEND  0x00000010 /* mailbox irq pending:  has space */
5341 +#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
5342 +#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
5343 +/* Bit 7 is unused */
5344 +#define ARM_MC_ERRNOOWN   0x00000100 /* error : none owner read from mailbox */
5345 +#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
5346 +#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
5347 +
5348 +/* Semaphore clear/debug register (...0xE0) */
5349 +#define ARM_SD_OWN0      0x00000003  /* Owner of sem 0 */
5350 +#define ARM_SD_OWN1      0x0000000C  /* Owner of sem 1 */
5351 +#define ARM_SD_OWN2      0x00000030  /* Owner of sem 2 */
5352 +#define ARM_SD_OWN3      0x000000C0  /* Owner of sem 3 */
5353 +#define ARM_SD_OWN4      0x00000300  /* Owner of sem 4 */
5354 +#define ARM_SD_OWN5      0x00000C00  /* Owner of sem 5 */
5355 +#define ARM_SD_OWN6      0x00003000  /* Owner of sem 6 */
5356 +#define ARM_SD_OWN7      0x0000C000  /* Owner of sem 7 */
5357 +#define ARM_SD_SEM0      0x00010000  /* Status of sem 0 */
5358 +#define ARM_SD_SEM1      0x00020000  /* Status of sem 1 */
5359 +#define ARM_SD_SEM2      0x00040000  /* Status of sem 2 */
5360 +#define ARM_SD_SEM3      0x00080000  /* Status of sem 3 */
5361 +#define ARM_SD_SEM4      0x00100000  /* Status of sem 4 */
5362 +#define ARM_SD_SEM5      0x00200000  /* Status of sem 5 */
5363 +#define ARM_SD_SEM6      0x00400000  /* Status of sem 6 */
5364 +#define ARM_SD_SEM7      0x00800000  /* Status of sem 7 */
5365 +
5366 +/* Doorbells clear/debug register (...0xE4) */
5367 +#define ARM_BD_OWN0      0x00000003  /* Owner of doorbell 0 */
5368 +#define ARM_BD_OWN1      0x0000000C  /* Owner of doorbell 1 */
5369 +#define ARM_BD_OWN2      0x00000030  /* Owner of doorbell 2 */
5370 +#define ARM_BD_OWN3      0x000000C0  /* Owner of doorbell 3 */
5371 +#define ARM_BD_BELL0     0x00000100  /* Status of doorbell 0 */
5372 +#define ARM_BD_BELL1     0x00000200  /* Status of doorbell 1 */
5373 +#define ARM_BD_BELL2     0x00000400  /* Status of doorbell 2 */
5374 +#define ARM_BD_BELL3     0x00000800  /* Status of doorbell 3 */
5375 +
5376 +/* MY IRQS register (...0xF8) */
5377 +#define ARM_MYIRQ_BELL   0x00000001  /* This owner has a doorbell IRQ */
5378 +#define ARM_MYIRQ_MAIL   0x00000002  /* This owner has a mailbox  IRQ */
5379 +
5380 +/* ALL IRQS register (...0xF8) */
5381 +#define ARM_AIS_BELL0 0x00000001  /* Doorbell 0 IRQ pending */
5382 +#define ARM_AIS_BELL1 0x00000002  /* Doorbell 1 IRQ pending */
5383 +#define ARM_AIS_BELL2 0x00000004  /* Doorbell 2 IRQ pending */
5384 +#define ARM_AIS_BELL3 0x00000008  /* Doorbell 3 IRQ pending */
5385 +#define ARM_AIS0_HAVEDATA 0x00000010  /* MAIL 0 has data IRQ pending */
5386 +#define ARM_AIS0_HAVESPAC 0x00000020  /* MAIL 0 has space IRQ pending */
5387 +#define ARM_AIS0_OPPEMPTY 0x00000040  /* MAIL 0 opposite is empty IRQ */
5388 +#define ARM_AIS1_HAVEDATA 0x00000080  /* MAIL 1 has data IRQ pending */
5389 +#define ARM_AIS1_HAVESPAC 0x00000100  /* MAIL 1 has space IRQ pending */
5390 +#define ARM_AIS1_OPPEMPTY 0x00000200  /* MAIL 1 opposite is empty IRQ */
5391 +/* Note   that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
5392 +/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
5393 +/* */
5394 +/* ARM JTAG BASH */
5395 +/* */
5396 +#define AJB_BASE 0x7e2000c0
5397 +
5398 +#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
5399 +#define   AJB_BITS0    0x000000
5400 +#define   AJB_BITS4    0x000004
5401 +#define   AJB_BITS8    0x000008
5402 +#define   AJB_BITS12   0x00000C
5403 +#define   AJB_BITS16   0x000010
5404 +#define   AJB_BITS20   0x000014
5405 +#define   AJB_BITS24   0x000018
5406 +#define   AJB_BITS28   0x00001C
5407 +#define   AJB_BITS32   0x000020
5408 +#define   AJB_BITS34   0x000022
5409 +#define   AJB_OUT_MS   0x000040
5410 +#define   AJB_OUT_LS   0x000000
5411 +#define   AJB_INV_CLK  0x000080
5412 +#define   AJB_D0_RISE  0x000100
5413 +#define   AJB_D0_FALL  0x000000
5414 +#define   AJB_D1_RISE  0x000200
5415 +#define   AJB_D1_FALL  0x000000
5416 +#define   AJB_IN_RISE  0x000400
5417 +#define   AJB_IN_FALL  0x000000
5418 +#define   AJB_ENABLE   0x000800
5419 +#define   AJB_HOLD0    0x000000
5420 +#define   AJB_HOLD1    0x001000
5421 +#define   AJB_HOLD2    0x002000
5422 +#define   AJB_HOLD3    0x003000
5423 +#define   AJB_RESETN   0x004000
5424 +#define   AJB_CLKSHFT  16
5425 +#define   AJB_BUSY     0x80000000
5426 +#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
5427 +#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
5428 +#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
5429 +
5430 +#endif
5431 --- /dev/null
5432 +++ b/arch/arm/mach-bcm2708/include/mach/arm_power.h
5433 @@ -0,0 +1,60 @@
5434 +/*
5435 + *  linux/arch/arm/mach-bcm2708/include/mach/arm_power.h
5436 + *
5437 + *  Copyright (C) 2010 Broadcom
5438 + *
5439 + * This program is free software; you can redistribute it and/or modify
5440 + * it under the terms of the GNU General Public License as published by
5441 + * the Free Software Foundation; either version 2 of the License, or
5442 + * (at your option) any later version.
5443 + *
5444 + * This program is distributed in the hope that it will be useful,
5445 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5446 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5447 + * GNU General Public License for more details.
5448 + *
5449 + * You should have received a copy of the GNU General Public License
5450 + * along with this program; if not, write to the Free Software
5451 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5452 + */
5453 +
5454 +#ifndef _ARM_POWER_H
5455 +#define _ARM_POWER_H
5456 +
5457 +/* Use meaningful names on each side */
5458 +#ifdef __VIDEOCORE__
5459 +#define PREFIX(x) ARM_##x
5460 +#else
5461 +#define PREFIX(x) BCM_##x
5462 +#endif
5463 +
5464 +enum {
5465 +       PREFIX(POWER_SDCARD_BIT),
5466 +       PREFIX(POWER_UART_BIT),
5467 +       PREFIX(POWER_MINIUART_BIT),
5468 +       PREFIX(POWER_USB_BIT),
5469 +       PREFIX(POWER_I2C0_BIT),
5470 +       PREFIX(POWER_I2C1_BIT),
5471 +       PREFIX(POWER_I2C2_BIT),
5472 +       PREFIX(POWER_SPI_BIT),
5473 +       PREFIX(POWER_CCP2TX_BIT),
5474 +
5475 +       PREFIX(POWER_MAX)
5476 +};
5477 +
5478 +enum {
5479 +       PREFIX(POWER_SDCARD) = (1 << PREFIX(POWER_SDCARD_BIT)),
5480 +       PREFIX(POWER_UART) = (1 << PREFIX(POWER_UART_BIT)),
5481 +       PREFIX(POWER_MINIUART) = (1 << PREFIX(POWER_MINIUART_BIT)),
5482 +       PREFIX(POWER_USB) = (1 << PREFIX(POWER_USB_BIT)),
5483 +       PREFIX(POWER_I2C0) = (1 << PREFIX(POWER_I2C0_BIT)),
5484 +       PREFIX(POWER_I2C1_MASK) = (1 << PREFIX(POWER_I2C1_BIT)),
5485 +       PREFIX(POWER_I2C2_MASK) = (1 << PREFIX(POWER_I2C2_BIT)),
5486 +       PREFIX(POWER_SPI_MASK) = (1 << PREFIX(POWER_SPI_BIT)),
5487 +       PREFIX(POWER_CCP2TX_MASK) = (1 << PREFIX(POWER_CCP2TX_BIT)),
5488 +
5489 +       PREFIX(POWER_MASK) = (1 << PREFIX(POWER_MAX)) - 1,
5490 +       PREFIX(POWER_NONE) = 0
5491 +};
5492 +
5493 +#endif
5494 --- /dev/null
5495 +++ b/arch/arm/mach-bcm2708/include/mach/clkdev.h
5496 @@ -0,0 +1,7 @@
5497 +#ifndef __ASM_MACH_CLKDEV_H
5498 +#define __ASM_MACH_CLKDEV_H
5499 +
5500 +#define __clk_get(clk) ({ 1; })
5501 +#define __clk_put(clk) do { } while (0)
5502 +
5503 +#endif
5504 --- /dev/null
5505 +++ b/arch/arm/mach-bcm2708/include/mach/debug-macro.S
5506 @@ -0,0 +1,22 @@
5507 +/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
5508 + *
5509 + * Debugging macro include header
5510 + *
5511 + *  Copyright (C) 2010 Broadcom
5512 + *  Copyright (C) 1994-1999 Russell King
5513 + *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
5514 + *
5515 + * This program is free software; you can redistribute it and/or modify
5516 + * it under the terms of the GNU General Public License version 2 as
5517 + * published by the Free Software Foundation.
5518 + *
5519 +*/
5520 +
5521 +#include <mach/platform.h>
5522 +
5523 +               .macro  addruart, rp, rv, tmp
5524 +               ldr     \rp, =UART0_BASE
5525 +               ldr     \rv, =IO_ADDRESS(UART0_BASE)
5526 +               .endm
5527 +
5528 +#include <asm/hardware/debug-pl01x.S>
5529 --- /dev/null
5530 +++ b/arch/arm/mach-bcm2708/include/mach/dma.h
5531 @@ -0,0 +1,86 @@
5532 +/*
5533 + *  linux/arch/arm/mach-bcm2708/include/mach/dma.h
5534 + *
5535 + *  Copyright (C) 2010 Broadcom
5536 + *
5537 + * This program is free software; you can redistribute it and/or modify
5538 + * it under the terms of the GNU General Public License version 2 as
5539 + * published by the Free Software Foundation.
5540 + */
5541 +
5542 +
5543 +#ifndef _MACH_BCM2708_DMA_H
5544 +#define _MACH_BCM2708_DMA_H
5545 +
5546 +#define BCM_DMAMAN_DRIVER_NAME "bcm2708_dma"
5547 +
5548 +/* DMA CS Control and Status bits */
5549 +#define BCM2708_DMA_ACTIVE     (1 << 0)
5550 +#define BCM2708_DMA_INT                (1 << 2)
5551 +#define BCM2708_DMA_ISPAUSED   (1 << 4)  /* Pause requested or not active */
5552 +#define BCM2708_DMA_ISHELD     (1 << 5)  /* Is held by DREQ flow control */
5553 +#define BCM2708_DMA_ERR                (1 << 8)
5554 +#define BCM2708_DMA_ABORT      (1 << 30) /* stop current CB, go to next, WO */
5555 +#define BCM2708_DMA_RESET      (1 << 31) /* WO, self clearing */
5556 +
5557 +/* DMA control block "info" field bits */
5558 +#define BCM2708_DMA_INT_EN     (1 << 0)
5559 +#define BCM2708_DMA_TDMODE     (1 << 1)
5560 +#define BCM2708_DMA_WAIT_RESP  (1 << 3)
5561 +#define BCM2708_DMA_D_INC      (1 << 4)
5562 +#define BCM2708_DMA_D_WIDTH    (1 << 5)
5563 +#define BCM2708_DMA_D_DREQ     (1 << 6)
5564 +#define BCM2708_DMA_S_INC      (1 << 8)
5565 +#define BCM2708_DMA_S_WIDTH    (1 << 9)
5566 +#define BCM2708_DMA_S_DREQ     (1 << 10)
5567 +
5568 +#define        BCM2708_DMA_BURST(x)    (((x)&0xf) << 12)
5569 +#define        BCM2708_DMA_PER_MAP(x)  ((x) << 16)
5570 +#define        BCM2708_DMA_WAITS(x)    (((x)&0x1f) << 21)
5571 +
5572 +#define BCM2708_DMA_DREQ_EMMC  11
5573 +#define BCM2708_DMA_DREQ_SDHOST        13
5574 +
5575 +#define BCM2708_DMA_CS         0x00 /* Control and Status */
5576 +#define BCM2708_DMA_ADDR       0x04
5577 +/* the current control block appears in the following registers - read only */
5578 +#define BCM2708_DMA_INFO       0x08
5579 +#define BCM2708_DMA_NEXTCB     0x1C
5580 +#define BCM2708_DMA_DEBUG      0x20
5581 +
5582 +#define BCM2708_DMA4_CS                (BCM2708_DMA_CHAN(4)+BCM2708_DMA_CS)
5583 +#define BCM2708_DMA4_ADDR      (BCM2708_DMA_CHAN(4)+BCM2708_DMA_ADDR)
5584 +
5585 +#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
5586 +
5587 +struct bcm2708_dma_cb {
5588 +       unsigned long info;
5589 +       unsigned long src;
5590 +       unsigned long dst;
5591 +       unsigned long length;
5592 +       unsigned long stride;
5593 +       unsigned long next;
5594 +       unsigned long pad[2];
5595 +};
5596 +
5597 +extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
5598 +extern void bcm_dma_start(void __iomem *dma_chan_base,
5599 +                         dma_addr_t control_block);
5600 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base);
5601 +extern int /*rc*/ bcm_dma_abort(void __iomem *dma_chan_base);
5602 +
5603 +/* When listing features we can ask for when allocating DMA channels give
5604 +   those with higher priority smaller ordinal numbers */
5605 +#define BCM_DMA_FEATURE_FAST_ORD 0
5606 +#define BCM_DMA_FEATURE_BULK_ORD 1
5607 +#define BCM_DMA_FEATURE_FAST    (1<<BCM_DMA_FEATURE_FAST_ORD)
5608 +#define BCM_DMA_FEATURE_BULK    (1<<BCM_DMA_FEATURE_BULK_ORD)
5609 +#define BCM_DMA_FEATURE_COUNT   2
5610 +
5611 +/* return channel no or -ve error */
5612 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
5613 +                             void __iomem **out_dma_base, int *out_dma_irq);
5614 +extern int bcm_dma_chan_free(int channel);
5615 +
5616 +
5617 +#endif /* _MACH_BCM2708_DMA_H */
5618 --- /dev/null
5619 +++ b/arch/arm/mach-bcm2708/include/mach/entry-macro.S
5620 @@ -0,0 +1,69 @@
5621 +/*
5622 + * arch/arm/mach-bcm2708/include/mach/entry-macro.S
5623 + *
5624 + * Low-level IRQ helper macros for BCM2708 platforms
5625 + *
5626 + *  Copyright (C) 2010 Broadcom
5627 + *
5628 + * This program is free software; you can redistribute it and/or modify
5629 + * it under the terms of the GNU General Public License as published by
5630 + * the Free Software Foundation; either version 2 of the License, or
5631 + * (at your option) any later version.
5632 + *
5633 + * This program is distributed in the hope that it will be useful,
5634 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5635 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5636 + * GNU General Public License for more details.
5637 + *
5638 + * You should have received a copy of the GNU General Public License
5639 + * along with this program; if not, write to the Free Software
5640 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5641 + */
5642 +#include <mach/hardware.h>
5643 +
5644 +               .macro  disable_fiq
5645 +               .endm
5646 +
5647 +               .macro  get_irqnr_preamble, base, tmp
5648 +               ldr     \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
5649 +               .endm
5650 +
5651 +               .macro  arch_ret_to_user, tmp1, tmp2
5652 +               .endm
5653 +
5654 +               .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
5655 +               /* get masked status */
5656 +               ldr     \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
5657 +               mov     \irqnr, #(ARM_IRQ0_BASE + 31)
5658 +               and     \tmp, \irqstat, #0x300           @ save bits 8 and 9
5659 +               /* clear bits 8 and 9, and test */
5660 +               bics    \irqstat, \irqstat, #0x300
5661 +               bne     1010f
5662 +
5663 +               tst     \tmp, #0x100
5664 +               ldrne   \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
5665 +               movne \irqnr, #(ARM_IRQ1_BASE + 31)
5666 +               @ Mask out the interrupts also present in PEND0 - see SW-5809
5667 +               bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
5668 +               bicne \irqstat, #((1<<18) | (1<<19))
5669 +               bne     1010f
5670 +
5671 +               tst     \tmp, #0x200
5672 +               ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
5673 +               movne \irqnr, #(ARM_IRQ2_BASE + 31)
5674 +               @ Mask out the interrupts also present in PEND0 - see SW-5809
5675 +               bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
5676 +               bicne \irqstat, #((1<<30))
5677 +               beq 1020f
5678 +
5679 +1010:
5680 +               @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
5681 +               @ N.B. CLZ is an ARM5 instruction.
5682 +               sub     \tmp, \irqstat, #1
5683 +               eor     \irqstat, \irqstat, \tmp
5684 +               clz     \tmp, \irqstat
5685 +               sub     \irqnr, \tmp
5686 +
5687 +1020:  @ EQ will be set if no irqs pending
5688 +
5689 +               .endm
5690 --- /dev/null
5691 +++ b/arch/arm/mach-bcm2708/include/mach/frc.h
5692 @@ -0,0 +1,38 @@
5693 +/*
5694 + *  arch/arm/mach-bcm2708/include/mach/timex.h
5695 + *
5696 + *  BCM2708 free running counter (timer)
5697 + *
5698 + *  Copyright (C) 2010 Broadcom
5699 + *
5700 + * This program is free software; you can redistribute it and/or modify
5701 + * it under the terms of the GNU General Public License as published by
5702 + * the Free Software Foundation; either version 2 of the License, or
5703 + * (at your option) any later version.
5704 + *
5705 + * This program is distributed in the hope that it will be useful,
5706 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5707 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5708 + * GNU General Public License for more details.
5709 + *
5710 + * You should have received a copy of the GNU General Public License
5711 + * along with this program; if not, write to the Free Software
5712 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5713 + */
5714 +
5715 +#ifndef _MACH_FRC_H
5716 +#define _MACH_FRC_H
5717 +
5718 +#define FRC_TICK_RATE          (1000000)
5719 +
5720 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
5721 +    (slightly faster than frc_clock_ticks63()
5722 + */
5723 +extern unsigned long frc_clock_ticks32(void);
5724 +
5725 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
5726 + *  Note - top bit should be ignored (see cnt32_to_63)
5727 + */
5728 +extern unsigned long long frc_clock_ticks63(void);
5729 +
5730 +#endif
5731 --- /dev/null
5732 +++ b/arch/arm/mach-bcm2708/include/mach/gpio.h
5733 @@ -0,0 +1,18 @@
5734 +/*
5735 + * arch/arm/mach-bcm2708/include/mach/gpio.h
5736 + *
5737 + * This file is licensed under the terms of the GNU General Public
5738 + * License version 2.  This program is licensed "as is" without any
5739 + * warranty of any kind, whether express or implied.
5740 + */
5741 +
5742 +#ifndef __ASM_ARCH_GPIO_H
5743 +#define __ASM_ARCH_GPIO_H
5744 +
5745 +#define ARCH_NR_GPIOS 54 // number of gpio lines
5746 +
5747 +#define gpio_to_irq(x) ((x) + GPIO_IRQ_START)
5748 +#define irq_to_gpio(x) ((x) - GPIO_IRQ_START)
5749 +
5750 +#endif
5751 +
5752 --- /dev/null
5753 +++ b/arch/arm/mach-bcm2708/include/mach/hardware.h
5754 @@ -0,0 +1,28 @@
5755 +/*
5756 + *  arch/arm/mach-bcm2708/include/mach/hardware.h
5757 + *
5758 + *  This file contains the hardware definitions of the BCM2708 devices.
5759 + *
5760 + *  Copyright (C) 2010 Broadcom
5761 + *
5762 + * This program is free software; you can redistribute it and/or modify
5763 + * it under the terms of the GNU General Public License as published by
5764 + * the Free Software Foundation; either version 2 of the License, or
5765 + * (at your option) any later version.
5766 + *
5767 + * This program is distributed in the hope that it will be useful,
5768 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5769 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5770 + * GNU General Public License for more details.
5771 + *
5772 + * You should have received a copy of the GNU General Public License
5773 + * along with this program; if not, write to the Free Software
5774 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5775 + */
5776 +#ifndef __ASM_ARCH_HARDWARE_H
5777 +#define __ASM_ARCH_HARDWARE_H
5778 +
5779 +#include <asm/sizes.h>
5780 +#include <mach/platform.h>
5781 +
5782 +#endif
5783 --- /dev/null
5784 +++ b/arch/arm/mach-bcm2708/include/mach/io.h
5785 @@ -0,0 +1,27 @@
5786 +/*
5787 + *  arch/arm/mach-bcm2708/include/mach/io.h
5788 + *
5789 + *  Copyright (C) 2003 ARM Limited
5790 + *
5791 + * This program is free software; you can redistribute it and/or modify
5792 + * it under the terms of the GNU General Public License as published by
5793 + * the Free Software Foundation; either version 2 of the License, or
5794 + * (at your option) any later version.
5795 + *
5796 + * This program is distributed in the hope that it will be useful,
5797 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5798 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5799 + * GNU General Public License for more details.
5800 + *
5801 + * You should have received a copy of the GNU General Public License
5802 + * along with this program; if not, write to the Free Software
5803 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5804 + */
5805 +#ifndef __ASM_ARM_ARCH_IO_H
5806 +#define __ASM_ARM_ARCH_IO_H
5807 +
5808 +#define IO_SPACE_LIMIT 0xffffffff
5809 +
5810 +#define __io(a)                __typesafe_io(a)
5811 +
5812 +#endif
5813 --- /dev/null
5814 +++ b/arch/arm/mach-bcm2708/include/mach/irqs.h
5815 @@ -0,0 +1,199 @@
5816 +/*
5817 + *  arch/arm/mach-bcm2708/include/mach/irqs.h
5818 + *
5819 + *  Copyright (C) 2010 Broadcom
5820 + *  Copyright (C) 2003 ARM Limited
5821 + *  Copyright (C) 2000 Deep Blue Solutions Ltd.
5822 + *
5823 + * This program is free software; you can redistribute it and/or modify
5824 + * it under the terms of the GNU General Public License as published by
5825 + * the Free Software Foundation; either version 2 of the License, or
5826 + * (at your option) any later version.
5827 + *
5828 + * This program is distributed in the hope that it will be useful,
5829 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5830 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5831 + * GNU General Public License for more details.
5832 + *
5833 + * You should have received a copy of the GNU General Public License
5834 + * along with this program; if not, write to the Free Software
5835 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5836 + */
5837 +
5838 +#ifndef _BCM2708_IRQS_H_
5839 +#define _BCM2708_IRQS_H_
5840 +
5841 +#include <mach/platform.h>
5842 +
5843 +/*
5844 + *  IRQ interrupts definitions are the same as the INT definitions
5845 + *  held within platform.h
5846 + */
5847 +#define IRQ_ARMCTRL_START     0
5848 +#define IRQ_TIMER0            (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
5849 +#define IRQ_TIMER1            (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
5850 +#define IRQ_TIMER2            (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
5851 +#define IRQ_TIMER3            (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
5852 +#define IRQ_CODEC0            (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
5853 +#define IRQ_CODEC1            (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
5854 +#define IRQ_CODEC2            (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
5855 +#define IRQ_JPEG              (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
5856 +#define IRQ_ISP               (IRQ_ARMCTRL_START + INTERRUPT_ISP)
5857 +#define IRQ_USB               (IRQ_ARMCTRL_START + INTERRUPT_USB)
5858 +#define IRQ_3D                (IRQ_ARMCTRL_START + INTERRUPT_3D)
5859 +#define IRQ_TRANSPOSER        (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
5860 +#define IRQ_MULTICORESYNC0    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
5861 +#define IRQ_MULTICORESYNC1    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
5862 +#define IRQ_MULTICORESYNC2    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
5863 +#define IRQ_MULTICORESYNC3    (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
5864 +#define IRQ_DMA0              (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
5865 +#define IRQ_DMA1              (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
5866 +#define IRQ_DMA2              (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
5867 +#define IRQ_DMA3              (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
5868 +#define IRQ_DMA4              (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
5869 +#define IRQ_DMA5              (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
5870 +#define IRQ_DMA6              (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
5871 +#define IRQ_DMA7              (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
5872 +#define IRQ_DMA8              (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
5873 +#define IRQ_DMA9              (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
5874 +#define IRQ_DMA10             (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
5875 +#define IRQ_DMA11             (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
5876 +#define IRQ_DMA12             (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
5877 +#define IRQ_AUX               (IRQ_ARMCTRL_START + INTERRUPT_AUX)
5878 +#define IRQ_ARM               (IRQ_ARMCTRL_START + INTERRUPT_ARM)
5879 +#define IRQ_VPUDMA            (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
5880 +#define IRQ_HOSTPORT          (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
5881 +#define IRQ_VIDEOSCALER       (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
5882 +#define IRQ_CCP2TX            (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
5883 +#define IRQ_SDC               (IRQ_ARMCTRL_START + INTERRUPT_SDC)
5884 +#define IRQ_DSI0              (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
5885 +#define IRQ_AVE               (IRQ_ARMCTRL_START + INTERRUPT_AVE)
5886 +#define IRQ_CAM0              (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
5887 +#define IRQ_CAM1              (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
5888 +#define IRQ_HDMI0             (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
5889 +#define IRQ_HDMI1             (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
5890 +#define IRQ_PIXELVALVE1       (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
5891 +#define IRQ_I2CSPISLV         (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
5892 +#define IRQ_DSI1              (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
5893 +#define IRQ_PWA0              (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
5894 +#define IRQ_PWA1              (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
5895 +#define IRQ_CPR               (IRQ_ARMCTRL_START + INTERRUPT_CPR)
5896 +#define IRQ_SMI               (IRQ_ARMCTRL_START + INTERRUPT_SMI)
5897 +#define IRQ_GPIO0             (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
5898 +#define IRQ_GPIO1             (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
5899 +#define IRQ_GPIO2             (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
5900 +#define IRQ_GPIO3             (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
5901 +#define IRQ_I2C               (IRQ_ARMCTRL_START + INTERRUPT_I2C)
5902 +#define IRQ_SPI               (IRQ_ARMCTRL_START + INTERRUPT_SPI)
5903 +#define IRQ_I2SPCM            (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
5904 +#define IRQ_SDIO              (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
5905 +#define IRQ_UART              (IRQ_ARMCTRL_START + INTERRUPT_UART)
5906 +#define IRQ_SLIMBUS           (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
5907 +#define IRQ_VEC               (IRQ_ARMCTRL_START + INTERRUPT_VEC)
5908 +#define IRQ_CPG               (IRQ_ARMCTRL_START + INTERRUPT_CPG)
5909 +#define IRQ_RNG               (IRQ_ARMCTRL_START + INTERRUPT_RNG)
5910 +#define IRQ_ARASANSDIO        (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
5911 +#define IRQ_AVSPMON           (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
5912 +
5913 +#define IRQ_ARM_TIMER         (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
5914 +#define IRQ_ARM_MAILBOX       (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
5915 +#define IRQ_ARM_DOORBELL_0    (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
5916 +#define IRQ_ARM_DOORBELL_1    (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
5917 +#define IRQ_VPU0_HALTED       (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
5918 +#define IRQ_VPU1_HALTED       (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
5919 +#define IRQ_ILLEGAL_TYPE0     (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
5920 +#define IRQ_ILLEGAL_TYPE1     (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
5921 +#define IRQ_PENDING1          (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
5922 +#define IRQ_PENDING2          (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
5923 +
5924 +#define FIQ_START             HARD_IRQS
5925 +
5926 +/*
5927 + *  FIQ interrupts definitions are the same as the INT definitions.
5928 + */
5929 +#define FIQ_TIMER0            (FIQ_START+INTERRUPT_TIMER0)
5930 +#define FIQ_TIMER1            (FIQ_START+INTERRUPT_TIMER1)
5931 +#define FIQ_TIMER2            (FIQ_START+INTERRUPT_TIMER2)
5932 +#define FIQ_TIMER3            (FIQ_START+INTERRUPT_TIMER3)
5933 +#define FIQ_CODEC0            (FIQ_START+INTERRUPT_CODEC0)
5934 +#define FIQ_CODEC1            (FIQ_START+INTERRUPT_CODEC1)
5935 +#define FIQ_CODEC2            (FIQ_START+INTERRUPT_CODEC2)
5936 +#define FIQ_JPEG              (FIQ_START+INTERRUPT_JPEG)
5937 +#define FIQ_ISP               (FIQ_START+INTERRUPT_ISP)
5938 +#define FIQ_USB               (FIQ_START+INTERRUPT_USB)
5939 +#define FIQ_3D                (FIQ_START+INTERRUPT_3D)
5940 +#define FIQ_TRANSPOSER        (FIQ_START+INTERRUPT_TRANSPOSER)
5941 +#define FIQ_MULTICORESYNC0    (FIQ_START+INTERRUPT_MULTICORESYNC0)
5942 +#define FIQ_MULTICORESYNC1    (FIQ_START+INTERRUPT_MULTICORESYNC1)
5943 +#define FIQ_MULTICORESYNC2    (FIQ_START+INTERRUPT_MULTICORESYNC2)
5944 +#define FIQ_MULTICORESYNC3    (FIQ_START+INTERRUPT_MULTICORESYNC3)
5945 +#define FIQ_DMA0              (FIQ_START+INTERRUPT_DMA0)
5946 +#define FIQ_DMA1              (FIQ_START+INTERRUPT_DMA1)
5947 +#define FIQ_DMA2              (FIQ_START+INTERRUPT_DMA2)
5948 +#define FIQ_DMA3              (FIQ_START+INTERRUPT_DMA3)
5949 +#define FIQ_DMA4              (FIQ_START+INTERRUPT_DMA4)
5950 +#define FIQ_DMA5              (FIQ_START+INTERRUPT_DMA5)
5951 +#define FIQ_DMA6              (FIQ_START+INTERRUPT_DMA6)
5952 +#define FIQ_DMA7              (FIQ_START+INTERRUPT_DMA7)
5953 +#define FIQ_DMA8              (FIQ_START+INTERRUPT_DMA8)
5954 +#define FIQ_DMA9              (FIQ_START+INTERRUPT_DMA9)
5955 +#define FIQ_DMA10             (FIQ_START+INTERRUPT_DMA10)
5956 +#define FIQ_DMA11             (FIQ_START+INTERRUPT_DMA11)
5957 +#define FIQ_DMA12             (FIQ_START+INTERRUPT_DMA12)
5958 +#define FIQ_AUX               (FIQ_START+INTERRUPT_AUX)
5959 +#define FIQ_ARM               (FIQ_START+INTERRUPT_ARM)
5960 +#define FIQ_VPUDMA            (FIQ_START+INTERRUPT_VPUDMA)
5961 +#define FIQ_HOSTPORT          (FIQ_START+INTERRUPT_HOSTPORT)
5962 +#define FIQ_VIDEOSCALER       (FIQ_START+INTERRUPT_VIDEOSCALER)
5963 +#define FIQ_CCP2TX            (FIQ_START+INTERRUPT_CCP2TX)
5964 +#define FIQ_SDC               (FIQ_START+INTERRUPT_SDC)
5965 +#define FIQ_DSI0              (FIQ_START+INTERRUPT_DSI0)
5966 +#define FIQ_AVE               (FIQ_START+INTERRUPT_AVE)
5967 +#define FIQ_CAM0              (FIQ_START+INTERRUPT_CAM0)
5968 +#define FIQ_CAM1              (FIQ_START+INTERRUPT_CAM1)
5969 +#define FIQ_HDMI0             (FIQ_START+INTERRUPT_HDMI0)
5970 +#define FIQ_HDMI1             (FIQ_START+INTERRUPT_HDMI1)
5971 +#define FIQ_PIXELVALVE1       (FIQ_START+INTERRUPT_PIXELVALVE1)
5972 +#define FIQ_I2CSPISLV         (FIQ_START+INTERRUPT_I2CSPISLV)
5973 +#define FIQ_DSI1              (FIQ_START+INTERRUPT_DSI1)
5974 +#define FIQ_PWA0              (FIQ_START+INTERRUPT_PWA0)
5975 +#define FIQ_PWA1              (FIQ_START+INTERRUPT_PWA1)
5976 +#define FIQ_CPR               (FIQ_START+INTERRUPT_CPR)
5977 +#define FIQ_SMI               (FIQ_START+INTERRUPT_SMI)
5978 +#define FIQ_GPIO0             (FIQ_START+INTERRUPT_GPIO0)
5979 +#define FIQ_GPIO1             (FIQ_START+INTERRUPT_GPIO1)
5980 +#define FIQ_GPIO2             (FIQ_START+INTERRUPT_GPIO2)
5981 +#define FIQ_GPIO3             (FIQ_START+INTERRUPT_GPIO3)
5982 +#define FIQ_I2C               (FIQ_START+INTERRUPT_I2C)
5983 +#define FIQ_SPI               (FIQ_START+INTERRUPT_SPI)
5984 +#define FIQ_I2SPCM            (FIQ_START+INTERRUPT_I2SPCM)
5985 +#define FIQ_SDIO              (FIQ_START+INTERRUPT_SDIO)
5986 +#define FIQ_UART              (FIQ_START+INTERRUPT_UART)
5987 +#define FIQ_SLIMBUS           (FIQ_START+INTERRUPT_SLIMBUS)
5988 +#define FIQ_VEC               (FIQ_START+INTERRUPT_VEC)
5989 +#define FIQ_CPG               (FIQ_START+INTERRUPT_CPG)
5990 +#define FIQ_RNG               (FIQ_START+INTERRUPT_RNG)
5991 +#define FIQ_ARASANSDIO        (FIQ_START+INTERRUPT_ARASANSDIO)
5992 +#define FIQ_AVSPMON           (FIQ_START+INTERRUPT_AVSPMON)
5993 +
5994 +#define FIQ_ARM_TIMER         (FIQ_START+INTERRUPT_ARM_TIMER)
5995 +#define FIQ_ARM_MAILBOX       (FIQ_START+INTERRUPT_ARM_MAILBOX)
5996 +#define FIQ_ARM_DOORBELL_0    (FIQ_START+INTERRUPT_ARM_DOORBELL_0)
5997 +#define FIQ_ARM_DOORBELL_1    (FIQ_START+INTERRUPT_ARM_DOORBELL_1)
5998 +#define FIQ_VPU0_HALTED       (FIQ_START+INTERRUPT_VPU0_HALTED)
5999 +#define FIQ_VPU1_HALTED       (FIQ_START+INTERRUPT_VPU1_HALTED)
6000 +#define FIQ_ILLEGAL_TYPE0     (FIQ_START+INTERRUPT_ILLEGAL_TYPE0)
6001 +#define FIQ_ILLEGAL_TYPE1     (FIQ_START+INTERRUPT_ILLEGAL_TYPE1)
6002 +#define FIQ_PENDING1          (FIQ_START+INTERRUPT_PENDING1)
6003 +#define FIQ_PENDING2          (FIQ_START+INTERRUPT_PENDING2)
6004 +
6005 +#define GPIO_IRQ_START       (HARD_IRQS + FIQ_IRQS)
6006 +
6007 +#define HARD_IRQS            (64 + 21)
6008 +#define FIQ_IRQS              (64 + 21)
6009 +#define GPIO_IRQS            (32*5)
6010 +
6011 +#define NR_IRQS                      HARD_IRQS+FIQ_IRQS+GPIO_IRQS
6012 +
6013 +
6014 +#endif /* _BCM2708_IRQS_H_ */
6015 --- /dev/null
6016 +++ b/arch/arm/mach-bcm2708/include/mach/memory.h
6017 @@ -0,0 +1,57 @@
6018 +/*
6019 + *  arch/arm/mach-bcm2708/include/mach/memory.h
6020 + *
6021 + *  Copyright (C) 2010 Broadcom
6022 + *
6023 + * This program is free software; you can redistribute it and/or modify
6024 + * it under the terms of the GNU General Public License as published by
6025 + * the Free Software Foundation; either version 2 of the License, or
6026 + * (at your option) any later version.
6027 + *
6028 + * This program is distributed in the hope that it will be useful,
6029 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6030 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6031 + * GNU General Public License for more details.
6032 + *
6033 + * You should have received a copy of the GNU General Public License
6034 + * along with this program; if not, write to the Free Software
6035 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6036 + */
6037 +#ifndef __ASM_ARCH_MEMORY_H
6038 +#define __ASM_ARCH_MEMORY_H
6039 +
6040 +/* Memory overview:
6041 +
6042 +   [ARMcore] <--virtual addr-->
6043 +   [ARMmmu] <--physical addr-->
6044 +   [GERTmap] <--bus add-->
6045 +   [VCperiph]
6046 +
6047 +*/
6048 +
6049 +/*
6050 + * Physical DRAM offset.
6051 + */
6052 +#define PLAT_PHYS_OFFSET       UL(0x00000000)
6053 +#define VC_ARMMEM_OFFSET       UL(0x00000000)   /* offset in VC of ARM memory */
6054 +
6055 +#ifdef CONFIG_BCM2708_NOL2CACHE
6056 + #define _REAL_BUS_OFFSET UL(0xC0000000)   /* don't use L1 or L2 caches */
6057 +#else
6058 + #define _REAL_BUS_OFFSET UL(0x40000000)   /* use L2 cache */
6059 +#endif
6060 +
6061 +/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
6062 + * will provide the offset into this area as well as setting the bits that
6063 + * stop the L1 and L2 cache from being used
6064 + *
6065 + * WARNING: this only works because the ARM is given memory at a fixed location
6066 + *          (ARMMEM_OFFSET)
6067 + */
6068 +#define BUS_OFFSET          (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
6069 +#define __virt_to_bus(x)    ((x) + (BUS_OFFSET - PAGE_OFFSET))
6070 +#define __bus_to_virt(x)    ((x) - (BUS_OFFSET - PAGE_OFFSET))
6071 +#define __pfn_to_bus(x)     (__pfn_to_phys(x) + (BUS_OFFSET - PLAT_PHYS_OFFSET))
6072 +#define __bus_to_pfn(x)     __phys_to_pfn((x) - (BUS_OFFSET - PLAT_PHYS_OFFSET))
6073 +
6074 +#endif
6075 --- /dev/null
6076 +++ b/arch/arm/mach-bcm2708/include/mach/platform.h
6077 @@ -0,0 +1,226 @@
6078 +/*
6079 + * arch/arm/mach-bcm2708/include/mach/platform.h
6080 + *
6081 + * Copyright (C) 2010 Broadcom
6082 + *
6083 + * This program is free software; you can redistribute it and/or modify
6084 + * it under the terms of the GNU General Public License as published by
6085 + * the Free Software Foundation; either version 2 of the License, or
6086 + * (at your option) any later version.
6087 + *
6088 + * This program is distributed in the hope that it will be useful,
6089 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6090 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6091 + * GNU General Public License for more details.
6092 + *
6093 + * You should have received a copy of the GNU General Public License
6094 + * along with this program; if not, write to the Free Software
6095 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6096 + */
6097 +
6098 +#ifndef _BCM2708_PLATFORM_H
6099 +#define _BCM2708_PLATFORM_H
6100 +
6101 +
6102 +/* macros to get at IO space when running virtually */
6103 +#define IO_ADDRESS(x)  (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
6104 +
6105 +#define __io_address(n)     IOMEM(IO_ADDRESS(n))
6106 +
6107 +
6108 +/*
6109 + *  SDRAM
6110 + */
6111 +#define BCM2708_SDRAM_BASE           0x00000000
6112 +
6113 +/*
6114 + *  Logic expansion modules
6115 + *
6116 + */
6117 +
6118 +
6119 +/* ------------------------------------------------------------------------
6120 + *  BCM2708 ARMCTRL Registers
6121 + * ------------------------------------------------------------------------
6122 + */
6123 +
6124 +#define HW_REGISTER_RW(addr) (addr)
6125 +#define HW_REGISTER_RO(addr) (addr)
6126 +
6127 +#include "arm_control.h"
6128 +#undef ARM_BASE
6129 +
6130 +/*
6131 + * Definitions and addresses for the ARM CONTROL logic
6132 + * This file is manually generated.
6133 + */
6134 +
6135 +#define BCM2708_PERI_BASE        0x20000000
6136 +#define IC0_BASE                 (BCM2708_PERI_BASE + 0x2000)
6137 +#define ST_BASE                  (BCM2708_PERI_BASE + 0x3000)   /* System Timer */
6138 +#define MPHI_BASE               (BCM2708_PERI_BASE + 0x6000)   /* Message -based Parallel Host Interface */
6139 +#define DMA_BASE                (BCM2708_PERI_BASE + 0x7000)   /* DMA controller */
6140 +#define ARM_BASE                 (BCM2708_PERI_BASE + 0xB000)   /* BCM2708 ARM control block */
6141 +#define PM_BASE                         (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
6142 +#define RNG_BASE                 (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
6143 +#define GPIO_BASE                (BCM2708_PERI_BASE + 0x200000) /* GPIO */
6144 +#define UART0_BASE               (BCM2708_PERI_BASE + 0x201000)        /* Uart 0 */
6145 +#define MMCI0_BASE               (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
6146 +#define SPI0_BASE               (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
6147 +#define BSC0_BASE               (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
6148 +#define UART1_BASE               (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
6149 +#define EMMC_BASE                (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
6150 +#define SMI_BASE                (BCM2708_PERI_BASE + 0x600000) /* SMI */
6151 +#define BSC1_BASE               (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
6152 +#define USB_BASE                 (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
6153 +#define MCORE_BASE               (BCM2708_PERI_BASE + 0x0000)   /* Fake frame buffer device (actually the multicore sync block*/
6154 +
6155 +#define ARMCTRL_BASE             (ARM_BASE + 0x000)
6156 +#define ARMCTRL_IC_BASE          (ARM_BASE + 0x200)           /* ARM interrupt controller */
6157 +#define ARMCTRL_TIMER0_1_BASE    (ARM_BASE + 0x400)           /* Timer 0 and 1 */
6158 +#define ARMCTRL_0_SBM_BASE       (ARM_BASE + 0x800)           /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
6159 +
6160 +
6161 +/*
6162 + * Interrupt assignments
6163 + */
6164 +
6165 +#define ARM_IRQ1_BASE                  0
6166 +#define INTERRUPT_TIMER0               (ARM_IRQ1_BASE + 0)
6167 +#define INTERRUPT_TIMER1               (ARM_IRQ1_BASE + 1)
6168 +#define INTERRUPT_TIMER2               (ARM_IRQ1_BASE + 2)
6169 +#define INTERRUPT_TIMER3               (ARM_IRQ1_BASE + 3)
6170 +#define INTERRUPT_CODEC0               (ARM_IRQ1_BASE + 4)
6171 +#define INTERRUPT_CODEC1               (ARM_IRQ1_BASE + 5)
6172 +#define INTERRUPT_CODEC2               (ARM_IRQ1_BASE + 6)
6173 +#define INTERRUPT_VC_JPEG              (ARM_IRQ1_BASE + 7)
6174 +#define INTERRUPT_ISP                  (ARM_IRQ1_BASE + 8)
6175 +#define INTERRUPT_VC_USB               (ARM_IRQ1_BASE + 9)
6176 +#define INTERRUPT_VC_3D                (ARM_IRQ1_BASE + 10)
6177 +#define INTERRUPT_TRANSPOSER           (ARM_IRQ1_BASE + 11)
6178 +#define INTERRUPT_MULTICORESYNC0       (ARM_IRQ1_BASE + 12)
6179 +#define INTERRUPT_MULTICORESYNC1       (ARM_IRQ1_BASE + 13)
6180 +#define INTERRUPT_MULTICORESYNC2       (ARM_IRQ1_BASE + 14)
6181 +#define INTERRUPT_MULTICORESYNC3       (ARM_IRQ1_BASE + 15)
6182 +#define INTERRUPT_DMA0                 (ARM_IRQ1_BASE + 16)
6183 +#define INTERRUPT_DMA1                 (ARM_IRQ1_BASE + 17)
6184 +#define INTERRUPT_VC_DMA2              (ARM_IRQ1_BASE + 18)
6185 +#define INTERRUPT_VC_DMA3              (ARM_IRQ1_BASE + 19)
6186 +#define INTERRUPT_DMA4                 (ARM_IRQ1_BASE + 20)
6187 +#define INTERRUPT_DMA5                 (ARM_IRQ1_BASE + 21)
6188 +#define INTERRUPT_DMA6                 (ARM_IRQ1_BASE + 22)
6189 +#define INTERRUPT_DMA7                 (ARM_IRQ1_BASE + 23)
6190 +#define INTERRUPT_DMA8                 (ARM_IRQ1_BASE + 24)
6191 +#define INTERRUPT_DMA9                 (ARM_IRQ1_BASE + 25)
6192 +#define INTERRUPT_DMA10                (ARM_IRQ1_BASE + 26)
6193 +#define INTERRUPT_DMA11                (ARM_IRQ1_BASE + 27)
6194 +#define INTERRUPT_DMA12                (ARM_IRQ1_BASE + 28)
6195 +#define INTERRUPT_AUX                (ARM_IRQ1_BASE + 29)
6196 +#define INTERRUPT_ARM                  (ARM_IRQ1_BASE + 30)
6197 +#define INTERRUPT_VPUDMA               (ARM_IRQ1_BASE + 31)
6198 +
6199 +#define ARM_IRQ2_BASE                  32
6200 +#define INTERRUPT_HOSTPORT             (ARM_IRQ2_BASE + 0)
6201 +#define INTERRUPT_VIDEOSCALER          (ARM_IRQ2_BASE + 1)
6202 +#define INTERRUPT_CCP2TX               (ARM_IRQ2_BASE + 2)
6203 +#define INTERRUPT_SDC                  (ARM_IRQ2_BASE + 3)
6204 +#define INTERRUPT_DSI0                 (ARM_IRQ2_BASE + 4)
6205 +#define INTERRUPT_AVE                  (ARM_IRQ2_BASE + 5)
6206 +#define INTERRUPT_CAM0                 (ARM_IRQ2_BASE + 6)
6207 +#define INTERRUPT_CAM1                 (ARM_IRQ2_BASE + 7)
6208 +#define INTERRUPT_HDMI0                (ARM_IRQ2_BASE + 8)
6209 +#define INTERRUPT_HDMI1                (ARM_IRQ2_BASE + 9)
6210 +#define INTERRUPT_PIXELVALVE1          (ARM_IRQ2_BASE + 10)
6211 +#define INTERRUPT_I2CSPISLV            (ARM_IRQ2_BASE + 11)
6212 +#define INTERRUPT_DSI1                 (ARM_IRQ2_BASE + 12)
6213 +#define INTERRUPT_PWA0                 (ARM_IRQ2_BASE + 13)
6214 +#define INTERRUPT_PWA1                 (ARM_IRQ2_BASE + 14)
6215 +#define INTERRUPT_CPR                  (ARM_IRQ2_BASE + 15)
6216 +#define INTERRUPT_SMI                  (ARM_IRQ2_BASE + 16)
6217 +#define INTERRUPT_GPIO0                (ARM_IRQ2_BASE + 17)
6218 +#define INTERRUPT_GPIO1                (ARM_IRQ2_BASE + 18)
6219 +#define INTERRUPT_GPIO2                (ARM_IRQ2_BASE + 19)
6220 +#define INTERRUPT_GPIO3                (ARM_IRQ2_BASE + 20)
6221 +#define INTERRUPT_VC_I2C               (ARM_IRQ2_BASE + 21)
6222 +#define INTERRUPT_VC_SPI               (ARM_IRQ2_BASE + 22)
6223 +#define INTERRUPT_VC_I2SPCM            (ARM_IRQ2_BASE + 23)
6224 +#define INTERRUPT_VC_SDIO              (ARM_IRQ2_BASE + 24)
6225 +#define INTERRUPT_VC_UART              (ARM_IRQ2_BASE + 25)
6226 +#define INTERRUPT_SLIMBUS              (ARM_IRQ2_BASE + 26)
6227 +#define INTERRUPT_VEC                  (ARM_IRQ2_BASE + 27)
6228 +#define INTERRUPT_CPG                  (ARM_IRQ2_BASE + 28)
6229 +#define INTERRUPT_RNG                  (ARM_IRQ2_BASE + 29)
6230 +#define INTERRUPT_VC_ARASANSDIO        (ARM_IRQ2_BASE + 30)
6231 +#define INTERRUPT_AVSPMON              (ARM_IRQ2_BASE + 31)
6232 +
6233 +#define ARM_IRQ0_BASE                  64
6234 +#define INTERRUPT_ARM_TIMER            (ARM_IRQ0_BASE + 0)
6235 +#define INTERRUPT_ARM_MAILBOX          (ARM_IRQ0_BASE + 1)
6236 +#define INTERRUPT_ARM_DOORBELL_0       (ARM_IRQ0_BASE + 2)
6237 +#define INTERRUPT_ARM_DOORBELL_1       (ARM_IRQ0_BASE + 3)
6238 +#define INTERRUPT_VPU0_HALTED          (ARM_IRQ0_BASE + 4)
6239 +#define INTERRUPT_VPU1_HALTED          (ARM_IRQ0_BASE + 5)
6240 +#define INTERRUPT_ILLEGAL_TYPE0        (ARM_IRQ0_BASE + 6)
6241 +#define INTERRUPT_ILLEGAL_TYPE1        (ARM_IRQ0_BASE + 7)
6242 +#define INTERRUPT_PENDING1             (ARM_IRQ0_BASE + 8)
6243 +#define INTERRUPT_PENDING2             (ARM_IRQ0_BASE + 9)
6244 +#define INTERRUPT_JPEG                 (ARM_IRQ0_BASE + 10)
6245 +#define INTERRUPT_USB                  (ARM_IRQ0_BASE + 11)
6246 +#define INTERRUPT_3D                   (ARM_IRQ0_BASE + 12)
6247 +#define INTERRUPT_DMA2                 (ARM_IRQ0_BASE + 13)
6248 +#define INTERRUPT_DMA3                 (ARM_IRQ0_BASE + 14)
6249 +#define INTERRUPT_I2C                  (ARM_IRQ0_BASE + 15)
6250 +#define INTERRUPT_SPI                  (ARM_IRQ0_BASE + 16)
6251 +#define INTERRUPT_I2SPCM               (ARM_IRQ0_BASE + 17)
6252 +#define INTERRUPT_SDIO                 (ARM_IRQ0_BASE + 18)
6253 +#define INTERRUPT_UART                 (ARM_IRQ0_BASE + 19)
6254 +#define INTERRUPT_ARASANSDIO           (ARM_IRQ0_BASE + 20)
6255 +
6256 +#define MAXIRQNUM                      (32 + 32 + 20)
6257 +#define MAXFIQNUM                      (32 + 32 + 20)
6258 +
6259 +#define MAX_TIMER                       2
6260 +#define MAX_PERIOD                      699050
6261 +#define TICKS_PER_uSEC                  1
6262 +
6263 +/*
6264 + *  These are useconds NOT ticks.
6265 + *
6266 + */
6267 +#define mSEC_1                          1000
6268 +#define mSEC_5                          (mSEC_1 * 5)
6269 +#define mSEC_10                         (mSEC_1 * 10)
6270 +#define mSEC_25                         (mSEC_1 * 25)
6271 +#define SEC_1                           (mSEC_1 * 1000)
6272 +
6273 +/*
6274 + * Watchdog
6275 + */
6276 +#define PM_RSTC                               (PM_BASE+0x1c)
6277 +#define PM_RSTS                               (PM_BASE+0x20)
6278 +#define PM_WDOG                               (PM_BASE+0x24)
6279 +
6280 +#define PM_WDOG_RESET                                         0000000000
6281 +#define PM_PASSWORD                   0x5a000000
6282 +#define PM_WDOG_TIME_SET              0x000fffff
6283 +#define PM_RSTC_WRCFG_CLR              0xffffffcf
6284 +#define PM_RSTC_WRCFG_SET              0x00000030
6285 +#define PM_RSTC_WRCFG_FULL_RESET       0x00000020
6286 +#define PM_RSTC_RESET                  0x00000102
6287 +
6288 +#define PM_RSTS_HADPOR_SET                                 0x00001000
6289 +#define PM_RSTS_HADSRH_SET                                 0x00000400
6290 +#define PM_RSTS_HADSRF_SET                                 0x00000200
6291 +#define PM_RSTS_HADSRQ_SET                                 0x00000100
6292 +#define PM_RSTS_HADWRH_SET                                 0x00000040
6293 +#define PM_RSTS_HADWRF_SET                                 0x00000020
6294 +#define PM_RSTS_HADWRQ_SET                                 0x00000010
6295 +#define PM_RSTS_HADDRH_SET                                 0x00000004
6296 +#define PM_RSTS_HADDRF_SET                                 0x00000002
6297 +#define PM_RSTS_HADDRQ_SET                                 0x00000001
6298 +
6299 +#define UART0_CLOCK      3000000
6300 +
6301 +#endif
6302 +
6303 +/* END */
6304 --- /dev/null
6305 +++ b/arch/arm/mach-bcm2708/include/mach/power.h
6306 @@ -0,0 +1,26 @@
6307 +/*
6308 + *  linux/arch/arm/mach-bcm2708/power.h
6309 + *
6310 + *  Copyright (C) 2010 Broadcom
6311 + *
6312 + * This program is free software; you can redistribute it and/or modify
6313 + * it under the terms of the GNU General Public License version 2 as
6314 + * published by the Free Software Foundation.
6315 + *
6316 + * This device provides a shared mechanism for controlling the power to
6317 + * VideoCore subsystems.
6318 + */
6319 +
6320 +#ifndef _MACH_BCM2708_POWER_H
6321 +#define _MACH_BCM2708_POWER_H
6322 +
6323 +#include <linux/types.h>
6324 +#include <mach/arm_power.h>
6325 +
6326 +typedef unsigned int BCM_POWER_HANDLE_T;
6327 +
6328 +extern int bcm_power_open(BCM_POWER_HANDLE_T *handle);
6329 +extern int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request);
6330 +extern int bcm_power_close(BCM_POWER_HANDLE_T handle);
6331 +
6332 +#endif
6333 --- /dev/null
6334 +++ b/arch/arm/mach-bcm2708/include/mach/system.h
6335 @@ -0,0 +1,38 @@
6336 +/*
6337 + *  arch/arm/mach-bcm2708/include/mach/system.h
6338 + *
6339 + *  Copyright (C) 2010 Broadcom
6340 + *  Copyright (C) 2003 ARM Limited
6341 + *  Copyright (C) 2000 Deep Blue Solutions Ltd
6342 + *
6343 + * This program is free software; you can redistribute it and/or modify
6344 + * it under the terms of the GNU General Public License as published by
6345 + * the Free Software Foundation; either version 2 of the License, or
6346 + * (at your option) any later version.
6347 + *
6348 + * This program is distributed in the hope that it will be useful,
6349 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6350 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6351 + * GNU General Public License for more details.
6352 + *
6353 + * You should have received a copy of the GNU General Public License
6354 + * along with this program; if not, write to the Free Software
6355 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6356 + */
6357 +#ifndef __ASM_ARCH_SYSTEM_H
6358 +#define __ASM_ARCH_SYSTEM_H
6359 +
6360 +#include <linux/io.h>
6361 +#include <mach/hardware.h>
6362 +#include <mach/platform.h>
6363 +
6364 +static inline void arch_idle(void)
6365 +{
6366 +       /*
6367 +        * This should do all the clock switching
6368 +        * and wait for interrupt tricks
6369 +        */
6370 +       cpu_do_idle();
6371 +}
6372 +
6373 +#endif
6374 --- /dev/null
6375 +++ b/arch/arm/mach-bcm2708/include/mach/timex.h
6376 @@ -0,0 +1,23 @@
6377 +/*
6378 + *  arch/arm/mach-bcm2708/include/mach/timex.h
6379 + *
6380 + *  BCM2708 sysem clock frequency
6381 + *
6382 + *  Copyright (C) 2010 Broadcom
6383 + *
6384 + * This program is free software; you can redistribute it and/or modify
6385 + * it under the terms of the GNU General Public License as published by
6386 + * the Free Software Foundation; either version 2 of the License, or
6387 + * (at your option) any later version.
6388 + *
6389 + * This program is distributed in the hope that it will be useful,
6390 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6391 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6392 + * GNU General Public License for more details.
6393 + *
6394 + * You should have received a copy of the GNU General Public License
6395 + * along with this program; if not, write to the Free Software
6396 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6397 + */
6398 +
6399 +#define CLOCK_TICK_RATE                (1000000)
6400 --- /dev/null
6401 +++ b/arch/arm/mach-bcm2708/include/mach/uncompress.h
6402 @@ -0,0 +1,85 @@
6403 +/*
6404 + *  arch/arm/mach-bcn2708/include/mach/uncompress.h
6405 + *
6406 + *  Copyright (C) 2010 Broadcom
6407 + *  Copyright (C) 2003 ARM Limited
6408 + *
6409 + * This program is free software; you can redistribute it and/or modify
6410 + * it under the terms of the GNU General Public License as published by
6411 + * the Free Software Foundation; either version 2 of the License, or
6412 + * (at your option) any later version.
6413 + *
6414 + * This program is distributed in the hope that it will be useful,
6415 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6416 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6417 + * GNU General Public License for more details.
6418 + *
6419 + * You should have received a copy of the GNU General Public License
6420 + * along with this program; if not, write to the Free Software
6421 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6422 + */
6423 +
6424 +#include <linux/io.h>
6425 +#include <linux/amba/serial.h>
6426 +#include <mach/hardware.h>
6427 +
6428 +#define UART_BAUD 115200
6429 +
6430 +#define BCM2708_UART_DR   __io(UART0_BASE + UART01x_DR)
6431 +#define BCM2708_UART_FR   __io(UART0_BASE + UART01x_FR)
6432 +#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
6433 +#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
6434 +#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
6435 +#define BCM2708_UART_CR   __io(UART0_BASE + UART011_CR)
6436 +
6437 +/*
6438 + * This does not append a newline
6439 + */
6440 +static inline void putc(int c)
6441 +{
6442 +       while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
6443 +               barrier();
6444 +
6445 +       __raw_writel(c, BCM2708_UART_DR);
6446 +}
6447 +
6448 +static inline void flush(void)
6449 +{
6450 +       int fr;
6451 +
6452 +       do {
6453 +               fr = __raw_readl(BCM2708_UART_FR);
6454 +               barrier();
6455 +       } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
6456 +}
6457 +
6458 +static inline void arch_decomp_setup(void)
6459 +{
6460 +       int temp, div, rem, frac;
6461 +
6462 +       temp = 16 * UART_BAUD;
6463 +       div = UART0_CLOCK / temp;
6464 +       rem = UART0_CLOCK % temp;
6465 +       temp = (8 * rem) / UART_BAUD;
6466 +       frac = (temp >> 1) + (temp & 1);
6467 +
6468 +       /* Make sure the UART is disabled before we start */
6469 +       __raw_writel(0, BCM2708_UART_CR);
6470 +
6471 +       /* Set the baud rate */
6472 +       __raw_writel(div, BCM2708_UART_IBRD);
6473 +       __raw_writel(frac, BCM2708_UART_FBRD);
6474 +
6475 +       /* Set the UART to 8n1, FIFO enabled */
6476 +       __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
6477 +
6478 +       /* Enable the UART */
6479 +       __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
6480 +                       BCM2708_UART_CR);
6481 +}
6482 +
6483 +/*
6484 + * nothing to do
6485 + */
6486 +#define arch_decomp_wdog()
6487 +
6488 --- /dev/null
6489 +++ b/arch/arm/mach-bcm2708/include/mach/vcio.h
6490 @@ -0,0 +1,141 @@
6491 +/*
6492 + *  arch/arm/mach-bcm2708/include/mach/vcio.h
6493 + *
6494 + *  Copyright (C) 2010 Broadcom
6495 + *
6496 + * This program is free software; you can redistribute it and/or modify
6497 + * it under the terms of the GNU General Public License as published by
6498 + * the Free Software Foundation; either version 2 of the License, or
6499 + * (at your option) any later version.
6500 + *
6501 + * This program is distributed in the hope that it will be useful,
6502 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6503 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6504 + * GNU General Public License for more details.
6505 + *
6506 + * You should have received a copy of the GNU General Public License
6507 + * along with this program; if not, write to the Free Software
6508 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6509 + */
6510 +#ifndef _MACH_BCM2708_VCIO_H
6511 +#define _MACH_BCM2708_VCIO_H
6512 +
6513 +/* Routines to handle I/O via the VideoCore "ARM control" registers
6514 + * (semaphores, doorbells, mailboxes)
6515 + */
6516 +
6517 +#define BCM_VCIO_DRIVER_NAME "bcm2708_vcio"
6518 +
6519 +/* Constants shared with the ARM identifying separate mailbox channels */
6520 +#define MBOX_CHAN_POWER    0 /* for use by the power management interface */
6521 +#define MBOX_CHAN_FB       1 /* for use by the frame buffer */
6522 +#define MBOX_CHAN_VCHIQ    3 /* for use by the VCHIQ interface */
6523 +#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */
6524 +#define MBOX_CHAN_COUNT    9
6525 +
6526 +/* Mailbox property tags */
6527 +enum {
6528 +       VCMSG_PROPERTY_END               = 0x00000000,
6529 +       VCMSG_GET_FIRMWARE_REVISION      = 0x00000001,
6530 +       VCMSG_GET_BOARD_MODEL            = 0x00010001,
6531 +       VCMSG_GET_BOARD_REVISION         = 0x00020002,
6532 +       VCMSG_GET_BOARD_MAC_ADDRESS      = 0x00020003,
6533 +       VCMSG_GET_BOARD_SERIAL           = 0x00020004,
6534 +       VCMSG_GET_ARM_MEMORY             = 0x00020005,
6535 +       VCMSG_GET_VC_MEMORY              = 0x00020006,
6536 +       VCMSG_GET_CLOCKS                 = 0x00020007,
6537 +       VCMSG_GET_COMMAND_LINE           = 0x00050001,
6538 +       VCMSG_GET_DMA_CHANNELS           = 0x00060001,
6539 +       VCMSG_GET_POWER_STATE            = 0x00020001,
6540 +       VCMSG_GET_TIMING                 = 0x00020002,
6541 +       VCMSG_SET_POWER_STATE            = 0x00028001,
6542 +       VCMSG_GET_CLOCK_STATE            = 0x00030001,
6543 +       VCMSG_SET_CLOCK_STATE            = 0x00038001,
6544 +       VCMSG_GET_CLOCK_RATE             = 0x00030002,
6545 +       VCMSG_SET_CLOCK_RATE             = 0x00038002,
6546 +       VCMSG_GET_VOLTAGE                = 0x00030003,
6547 +       VCMSG_SET_VOLTAGE                = 0x00038003,
6548 +       VCMSG_GET_MAX_CLOCK              = 0x00030004,
6549 +       VCMSG_GET_MAX_VOLTAGE            = 0x00030005,
6550 +       VCMSG_GET_TEMPERATURE            = 0x00030006,
6551 +       VCMSG_GET_MIN_CLOCK              = 0x00030007,
6552 +       VCMSG_GET_MIN_VOLTAGE            = 0x00030008,
6553 +       VCMSG_GET_TURBO                  = 0x00030009,
6554 +       VCMSG_SET_TURBO                  = 0x00038009,
6555 +       VCMSG_SET_ALLOCATE_BUFFER        = 0x00040001,
6556 +       VCMSG_SET_RELEASE_BUFFER         = 0x00048001,
6557 +       VCMSG_SET_BLANK_SCREEN           = 0x00040002,
6558 +       VCMSG_TST_BLANK_SCREEN           = 0x00044002,
6559 +       VCMSG_GET_PHYSICAL_WIDTH_HEIGHT  = 0x00040003,
6560 +       VCMSG_TST_PHYSICAL_WIDTH_HEIGHT  = 0x00044003,
6561 +       VCMSG_SET_PHYSICAL_WIDTH_HEIGHT  = 0x00048003,
6562 +       VCMSG_GET_VIRTUAL_WIDTH_HEIGHT   = 0x00040004,
6563 +       VCMSG_TST_VIRTUAL_WIDTH_HEIGHT   = 0x00044004,
6564 +       VCMSG_SET_VIRTUAL_WIDTH_HEIGHT   = 0x00048004,
6565 +       VCMSG_GET_DEPTH                  = 0x00040005,
6566 +       VCMSG_TST_DEPTH                  = 0x00044005,
6567 +       VCMSG_SET_DEPTH                  = 0x00048005,
6568 +       VCMSG_GET_PIXEL_ORDER            = 0x00040006,
6569 +       VCMSG_TST_PIXEL_ORDER            = 0x00044006,
6570 +       VCMSG_SET_PIXEL_ORDER            = 0x00048006,
6571 +       VCMSG_GET_ALPHA_MODE             = 0x00040007,
6572 +       VCMSG_TST_ALPHA_MODE             = 0x00044007,
6573 +       VCMSG_SET_ALPHA_MODE             = 0x00048007,
6574 +       VCMSG_GET_PITCH                  = 0x00040008,
6575 +       VCMSG_TST_PITCH                  = 0x00044008,
6576 +       VCMSG_SET_PITCH                  = 0x00048008,
6577 +       VCMSG_GET_VIRTUAL_OFFSET         = 0x00040009,
6578 +       VCMSG_TST_VIRTUAL_OFFSET         = 0x00044009,
6579 +       VCMSG_SET_VIRTUAL_OFFSET         = 0x00048009,
6580 +       VCMSG_GET_OVERSCAN               = 0x0004000a,
6581 +       VCMSG_TST_OVERSCAN               = 0x0004400a,
6582 +       VCMSG_SET_OVERSCAN               = 0x0004800a,
6583 +       VCMSG_GET_PALETTE                = 0x0004000b,
6584 +       VCMSG_TST_PALETTE                = 0x0004400b,
6585 +       VCMSG_SET_PALETTE                = 0x0004800b,
6586 +       VCMSG_GET_LAYER                  = 0x0004000c,
6587 +       VCMSG_TST_LAYER                  = 0x0004400c,
6588 +       VCMSG_SET_LAYER                  = 0x0004800c,
6589 +       VCMSG_GET_TRANSFORM              = 0x0004000d,
6590 +       VCMSG_TST_TRANSFORM              = 0x0004400d,
6591 +       VCMSG_SET_TRANSFORM              = 0x0004800d,
6592 +};
6593 +
6594 +extern int /*rc*/ bcm_mailbox_read(unsigned chan, uint32_t *data28);
6595 +extern int /*rc*/ bcm_mailbox_write(unsigned chan, uint32_t data28);
6596 +extern int /*rc*/ bcm_mailbox_property(void *data, int size);
6597 +
6598 +#include <linux/ioctl.h>
6599 +
6600 +/*
6601 + * The major device number. We can't rely on dynamic
6602 + * registration any more, because ioctls need to know
6603 + * it.
6604 + */
6605 +#define MAJOR_NUM 100
6606 +
6607 +/*
6608 + * Set the message of the device driver
6609 + */
6610 +#define IOCTL_MBOX_PROPERTY _IOWR(MAJOR_NUM, 0, char *)
6611 +/*
6612 + * _IOWR means that we're creating an ioctl command
6613 + * number for passing information from a user process
6614 + * to the kernel module and from the kernel module to user process
6615 + *
6616 + * The first arguments, MAJOR_NUM, is the major device
6617 + * number we're using.
6618 + *
6619 + * The second argument is the number of the command
6620 + * (there could be several with different meanings).
6621 + *
6622 + * The third argument is the type we want to get from
6623 + * the process to the kernel.
6624 + */
6625 +
6626 +/*
6627 + * The name of the device file
6628 + */
6629 +#define DEVICE_FILE_NAME "char_dev"
6630 +
6631 +#endif
6632 --- /dev/null
6633 +++ b/arch/arm/mach-bcm2708/include/mach/vc_mem.h
6634 @@ -0,0 +1,36 @@
6635 +/*****************************************************************************
6636 +* Copyright 2010 - 2011 Broadcom Corporation.  All rights reserved.
6637 +*
6638 +* Unless you and Broadcom execute a separate written software license
6639 +* agreement governing use of this software, this software is licensed to you
6640 +* under the terms of the GNU General Public License version 2, available at
6641 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
6642 +*
6643 +* Notwithstanding the above, under no circumstances may you combine this
6644 +* software in any way with any other Broadcom software provided under a
6645 +* license other than the GPL, without Broadcom's express prior written
6646 +* consent.
6647 +*****************************************************************************/
6648 +
6649 +#if !defined( VC_MEM_H )
6650 +#define VC_MEM_H
6651 +
6652 +#include <linux/ioctl.h>
6653 +
6654 +#define VC_MEM_IOC_MAGIC  'v'
6655 +
6656 +#define VC_MEM_IOC_MEM_PHYS_ADDR    _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
6657 +#define VC_MEM_IOC_MEM_SIZE         _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
6658 +#define VC_MEM_IOC_MEM_BASE         _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
6659 +#define VC_MEM_IOC_MEM_LOAD         _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
6660 +
6661 +#if defined( __KERNEL__ )
6662 +#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
6663 +
6664 +extern unsigned long mm_vc_mem_phys_addr;
6665 +extern unsigned int  mm_vc_mem_size;
6666 +extern int vc_mem_get_current_size( void );
6667 +#endif
6668 +
6669 +#endif  /* VC_MEM_H */
6670 +
6671 --- /dev/null
6672 +++ b/arch/arm/mach-bcm2708/include/mach/vc_support.h
6673 @@ -0,0 +1,69 @@
6674 +#ifndef _VC_SUPPORT_H_
6675 +#define _VC_SUPPORT_H_
6676 +
6677 +/*
6678 + * vc_support.h
6679 + *
6680 + *  Created on: 25 Nov 2012
6681 + *      Author: Simon
6682 + */
6683 +
6684 +enum {
6685 +/*
6686 +      If a MEM_HANDLE_T is discardable, the memory manager may resize it to size
6687 +      0 at any time when it is not locked or retained.
6688 +   */
6689 +   MEM_FLAG_DISCARDABLE = 1 << 0,
6690 +
6691 +   /*
6692 +      If a MEM_HANDLE_T is allocating (or normal), its block of memory will be
6693 +      accessed in an allocating fashion through the cache.
6694 +   */
6695 +   MEM_FLAG_NORMAL = 0 << 2,
6696 +   MEM_FLAG_ALLOCATING = MEM_FLAG_NORMAL,
6697 +
6698 +   /*
6699 +      If a MEM_HANDLE_T is direct, its block of memory will be accessed
6700 +      directly, bypassing the cache.
6701 +   */
6702 +   MEM_FLAG_DIRECT = 1 << 2,
6703 +
6704 +   /*
6705 +      If a MEM_HANDLE_T is coherent, its block of memory will be accessed in a
6706 +      non-allocating fashion through the cache.
6707 +   */
6708 +   MEM_FLAG_COHERENT = 2 << 2,
6709 +
6710 +   /*
6711 +      If a MEM_HANDLE_T is L1-nonallocating, its block of memory will be accessed by
6712 +      the VPU in a fashion which is allocating in L2, but only coherent in L1.
6713 +   */
6714 +   MEM_FLAG_L1_NONALLOCATING = (MEM_FLAG_DIRECT | MEM_FLAG_COHERENT),
6715 +
6716 +   /*
6717 +      If a MEM_HANDLE_T is zero'd, its contents are set to 0 rather than
6718 +      MEM_HANDLE_INVALID on allocation and resize up.
6719 +   */
6720 +   MEM_FLAG_ZERO = 1 << 4,
6721 +
6722 +   /*
6723 +      If a MEM_HANDLE_T is uninitialised, it will not be reset to a defined value
6724 +      (either zero, or all 1's) on allocation.
6725 +    */
6726 +   MEM_FLAG_NO_INIT = 1 << 5,
6727 +
6728 +   /*
6729 +      Hints.
6730 +   */
6731 +   MEM_FLAG_HINT_PERMALOCK = 1 << 6, /* Likely to be locked for long periods of time. */
6732 +};
6733 +
6734 +unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags);
6735 +unsigned int ReleaseVcMemory(unsigned int handle);
6736 +unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle);
6737 +unsigned int UnlockVcMemory(unsigned int handle);
6738 +
6739 +unsigned int ExecuteVcCode(unsigned int code,
6740 +               unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5);
6741 +
6742 +#endif
6743 --- /dev/null
6744 +++ b/arch/arm/mach-bcm2708/include/mach/vmalloc.h
6745 @@ -0,0 +1,20 @@
6746 +/*
6747 + *  arch/arm/mach-bcm2708/include/mach/vmalloc.h
6748 + *
6749 + *  Copyright (C) 2010 Broadcom
6750 + *
6751 + * This program is free software; you can redistribute it and/or modify
6752 + * it under the terms of the GNU General Public License as published by
6753 + * the Free Software Foundation; either version 2 of the License, or
6754 + * (at your option) any later version.
6755 + *
6756 + * This program is distributed in the hope that it will be useful,
6757 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6758 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6759 + * GNU General Public License for more details.
6760 + *
6761 + * You should have received a copy of the GNU General Public License
6762 + * along with this program; if not, write to the Free Software
6763 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6764 + */
6765 +#define VMALLOC_END            (0xe8000000)
6766 --- /dev/null
6767 +++ b/arch/arm/mach-bcm2708/Kconfig
6768 @@ -0,0 +1,48 @@
6769 +menu "Broadcom BCM2708 Implementations"
6770 +       depends on ARCH_BCM2708
6771 +
6772 +config MACH_BCM2708
6773 +       bool "Broadcom BCM2708 Development Platform"
6774 +       select NEED_MACH_MEMORY_H
6775 +       select NEED_MACH_IO_H
6776 +       select CPU_V6
6777 +       help
6778 +         Include support for the Broadcom(R) BCM2708 platform.
6779 +
6780 +config BCM2708_GPIO
6781 +       bool "BCM2708 gpio support"
6782 +       depends on MACH_BCM2708
6783 +       select ARCH_REQUIRE_GPIOLIB
6784 +        default y
6785 +       help
6786 +         Include support for the Broadcom(R) BCM2708 gpio.
6787 +
6788 +config BCM2708_VCMEM
6789 +       bool "Videocore Memory"
6790 +       depends on MACH_BCM2708
6791 +        default y
6792 +        help
6793 +          Helper for videocore memory access and total size allocation.
6794 +
6795 +config BCM2708_NOL2CACHE
6796 +       bool "Videocore L2 cache disable"
6797 +       depends on MACH_BCM2708
6798 +        default n
6799 +        help
6800 +          Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
6801 +
6802 +config BCM2708_DMAER
6803 +       tristate "BCM2708 DMA helper"
6804 +       depends on MACH_BCM2708
6805 +        default n
6806 +        help
6807 +          Enable DMA helper for accelerating X composition
6808 +
6809 +config BCM2708_SPIDEV
6810 +       bool "Bind spidev to SPI0 master"
6811 +       depends on MACH_BCM2708
6812 +       depends on SPI
6813 +        default y
6814 +               help
6815 +                       Binds spidev driver to the SPI0 master
6816 +endmenu
6817 --- /dev/null
6818 +++ b/arch/arm/mach-bcm2708/Makefile
6819 @@ -0,0 +1,11 @@
6820 +#
6821 +# Makefile for the linux kernel.
6822 +#
6823 +
6824 +obj-$(CONFIG_MACH_BCM2708)     += clock.o bcm2708.o armctrl.o vcio.o power.o dma.o
6825 +obj-$(CONFIG_BCM2708_GPIO)     += bcm2708_gpio.o
6826 +obj-$(CONFIG_BCM2708_VCMEM)    += vc_mem.o
6827 +
6828 +obj-$(CONFIG_BCM2708_DMAER)    += dmaer_master.o
6829 +dmaer_master-objs              := dmaer.o vc_support.o
6830 +
6831 --- /dev/null
6832 +++ b/arch/arm/mach-bcm2708/Makefile.boot
6833 @@ -0,0 +1,3 @@
6834 +   zreladdr-y  := 0x00008000
6835 +params_phys-y  := 0x00000100
6836 +initrd_phys-y  := 0x00800000
6837 --- /dev/null
6838 +++ b/arch/arm/mach-bcm2708/power.c
6839 @@ -0,0 +1,194 @@
6840 +/*
6841 + *      linux/arch/arm/mach-bcm2708/power.c
6842 + *
6843 + *      Copyright (C) 2010 Broadcom
6844 + *
6845 + * This program is free software; you can redistribute it and/or modify
6846 + * it under the terms of the GNU General Public License version 2 as
6847 + * published by the Free Software Foundation.
6848 + *
6849 + * This device provides a shared mechanism for controlling the power to
6850 + * VideoCore subsystems.
6851 + */
6852 +
6853 +#include <linux/module.h>
6854 +#include <linux/semaphore.h>
6855 +#include <linux/bug.h>
6856 +#include <mach/power.h>
6857 +#include <mach/vcio.h>
6858 +#include <mach/arm_power.h>
6859 +
6860 +#define DRIVER_NAME "bcm2708_power"
6861 +
6862 +#define BCM_POWER_MAXCLIENTS 4
6863 +#define BCM_POWER_NOCLIENT (1<<31)
6864 +
6865 +/* Some drivers expect there devices to be permanently powered */
6866 +#define BCM_POWER_ALWAYS_ON (BCM_POWER_USB)
6867 +
6868 +#if 1
6869 +#define DPRINTK printk
6870 +#else
6871 +#define DPRINTK if (0) printk
6872 +#endif
6873 +
6874 +struct state_struct {
6875 +       uint32_t global_request;
6876 +       uint32_t client_request[BCM_POWER_MAXCLIENTS];
6877 +       struct semaphore client_mutex;
6878 +       struct semaphore mutex;
6879 +} g_state;
6880 +
6881 +int bcm_power_open(BCM_POWER_HANDLE_T *handle)
6882 +{
6883 +       BCM_POWER_HANDLE_T i;
6884 +       int ret = -EBUSY;
6885 +
6886 +       down(&g_state.client_mutex);
6887 +
6888 +       for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
6889 +               if (g_state.client_request[i] == BCM_POWER_NOCLIENT) {
6890 +                       g_state.client_request[i] = BCM_POWER_NONE;
6891 +                       *handle = i;
6892 +                       ret = 0;
6893 +                       break;
6894 +               }
6895 +       }
6896 +
6897 +       up(&g_state.client_mutex);
6898 +
6899 +       DPRINTK("bcm_power_open() -> %d\n", *handle);
6900 +
6901 +       return ret;
6902 +}
6903 +EXPORT_SYMBOL_GPL(bcm_power_open);
6904 +
6905 +int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request)
6906 +{
6907 +       int rc = 0;
6908 +
6909 +       DPRINTK("bcm_power_request(%d, %x)\n", handle, request);
6910 +
6911 +       if ((handle < BCM_POWER_MAXCLIENTS) &&
6912 +           (g_state.client_request[handle] != BCM_POWER_NOCLIENT)) {
6913 +               if (down_interruptible(&g_state.mutex) != 0) {
6914 +                       DPRINTK("bcm_power_request -> interrupted\n");
6915 +                       return -EINTR;
6916 +               }
6917 +
6918 +               if (request != g_state.client_request[handle]) {
6919 +                       uint32_t others_request = 0;
6920 +                       uint32_t global_request;
6921 +                       BCM_POWER_HANDLE_T i;
6922 +
6923 +                       for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
6924 +                               if (i != handle)
6925 +                                       others_request |=
6926 +                                           g_state.client_request[i];
6927 +                       }
6928 +                       others_request &= ~BCM_POWER_NOCLIENT;
6929 +
6930 +                       global_request = request | others_request;
6931 +                       if (global_request != g_state.global_request) {
6932 +                               uint32_t actual;
6933 +
6934 +                               /* Send a request to VideoCore */
6935 +                               bcm_mailbox_write(MBOX_CHAN_POWER,
6936 +                                                 global_request << 4);
6937 +
6938 +                               /* Wait for a response during power-up */
6939 +                               if (global_request & ~g_state.global_request) {
6940 +                                       rc = bcm_mailbox_read(MBOX_CHAN_POWER,
6941 +                                                             &actual);
6942 +                                       DPRINTK
6943 +                                           ("bcm_mailbox_read -> %08x, %d\n",
6944 +                                            actual, rc);
6945 +                                       actual >>= 4;
6946 +                               } else {
6947 +                                       rc = 0;
6948 +                                       actual = global_request;
6949 +                               }
6950 +
6951 +                               if (rc == 0) {
6952 +                                       if (actual != global_request) {
6953 +                                               printk(KERN_ERR
6954 +                                                    "%s: prev global %x, new global %x, actual %x, request %x, others_request %x\n",
6955 +                                                    __func__,
6956 +                                                    g_state.global_request,
6957 +                                                    global_request, actual, request, others_request);
6958 +                                               /* A failure */
6959 +                                               BUG_ON((others_request & actual)
6960 +                                                      != others_request);
6961 +                                               request &= actual;
6962 +                                               rc = -EIO;
6963 +                                       }
6964 +
6965 +                                       g_state.global_request = actual;
6966 +                                       g_state.client_request[handle] =
6967 +                                           request;
6968 +                               }
6969 +                       }
6970 +               }
6971 +               up(&g_state.mutex);
6972 +       } else {
6973 +               rc = -EINVAL;
6974 +       }
6975 +       DPRINTK("bcm_power_request -> %d\n", rc);
6976 +       return rc;
6977 +}
6978 +EXPORT_SYMBOL_GPL(bcm_power_request);
6979 +
6980 +int bcm_power_close(BCM_POWER_HANDLE_T handle)
6981 +{
6982 +       int rc;
6983 +
6984 +       DPRINTK("bcm_power_close(%d)\n", handle);
6985 +
6986 +       rc = bcm_power_request(handle, BCM_POWER_NONE);
6987 +       if (rc == 0)
6988 +               g_state.client_request[handle] = BCM_POWER_NOCLIENT;
6989 +
6990 +       return rc;
6991 +}
6992 +EXPORT_SYMBOL_GPL(bcm_power_close);
6993 +
6994 +static int __init bcm_power_init(void)
6995 +{
6996 +#if defined(BCM_POWER_ALWAYS_ON)
6997 +       BCM_POWER_HANDLE_T always_on_handle;
6998 +#endif
6999 +       int rc = 0;
7000 +       int i;
7001 +
7002 +       printk(KERN_INFO "bcm_power: Broadcom power driver\n");
7003 +       bcm_mailbox_write(MBOX_CHAN_POWER, 0);
7004 +
7005 +       for (i = 0; i < BCM_POWER_MAXCLIENTS; i++)
7006 +               g_state.client_request[i] = BCM_POWER_NOCLIENT;
7007 +
7008 +       sema_init(&g_state.client_mutex, 1);
7009 +       sema_init(&g_state.mutex, 1);
7010 +
7011 +       g_state.global_request = 0;
7012 +
7013 +#if defined(BCM_POWER_ALWAYS_ON)
7014 +       if (BCM_POWER_ALWAYS_ON) {
7015 +               bcm_power_open(&always_on_handle);
7016 +               bcm_power_request(always_on_handle, BCM_POWER_ALWAYS_ON);
7017 +       }
7018 +#endif
7019 +
7020 +       return rc;
7021 +}
7022 +
7023 +static void __exit bcm_power_exit(void)
7024 +{
7025 +       bcm_mailbox_write(MBOX_CHAN_POWER, 0);
7026 +}
7027 +
7028 +arch_initcall(bcm_power_init); /* Initialize early */
7029 +module_exit(bcm_power_exit);
7030 +
7031 +MODULE_AUTHOR("Phil Elwell");
7032 +MODULE_DESCRIPTION("Interface to BCM2708 power management");
7033 +MODULE_LICENSE("GPL");
7034 --- /dev/null
7035 +++ b/arch/arm/mach-bcm2708/vcio.c
7036 @@ -0,0 +1,474 @@
7037 +/*
7038 + *  linux/arch/arm/mach-bcm2708/vcio.c
7039 + *
7040 + *  Copyright (C) 2010 Broadcom
7041 + *
7042 + * This program is free software; you can redistribute it and/or modify
7043 + * it under the terms of the GNU General Public License version 2 as
7044 + * published by the Free Software Foundation.
7045 + *
7046 + * This device provides a shared mechanism for writing to the mailboxes,
7047 + * semaphores, doorbells etc. that are shared between the ARM and the
7048 + * VideoCore processor
7049 + */
7050 +
7051 +#if defined(CONFIG_SERIAL_BCM_MBOX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
7052 +#define SUPPORT_SYSRQ
7053 +#endif
7054 +
7055 +#include <linux/module.h>
7056 +#include <linux/console.h>
7057 +#include <linux/serial_core.h>
7058 +#include <linux/serial.h>
7059 +#include <linux/errno.h>
7060 +#include <linux/device.h>
7061 +#include <linux/init.h>
7062 +#include <linux/mm.h>
7063 +#include <linux/dma-mapping.h>
7064 +#include <linux/platform_device.h>
7065 +#include <linux/sysrq.h>
7066 +#include <linux/delay.h>
7067 +#include <linux/slab.h>
7068 +#include <linux/interrupt.h>
7069 +#include <linux/irq.h>
7070 +
7071 +#include <linux/io.h>
7072 +
7073 +#include <mach/vcio.h>
7074 +#include <mach/platform.h>
7075 +
7076 +#include <asm/uaccess.h>
7077 +
7078 +
7079 +#define DRIVER_NAME BCM_VCIO_DRIVER_NAME
7080 +
7081 +/* ----------------------------------------------------------------------
7082 + *     Mailbox
7083 + * -------------------------------------------------------------------- */
7084 +
7085 +/* offsets from a mail box base address */
7086 +#define MAIL_WRT       0x00    /* write - and next 4 words */
7087 +#define MAIL_RD                0x00    /* read - and next 4 words */
7088 +#define MAIL_POL       0x10    /* read without popping the fifo */
7089 +#define MAIL_SND       0x14    /* sender ID (bottom two bits) */
7090 +#define MAIL_STA       0x18    /* status */
7091 +#define MAIL_CNF       0x1C    /* configuration */
7092 +
7093 +#define MBOX_MSG(chan, data28)         (((data28) & ~0xf) | ((chan) & 0xf))
7094 +#define MBOX_MSG_LSB(chan, data28) (((data28) << 4) | ((chan) & 0xf))
7095 +#define MBOX_CHAN(msg)                 ((msg) & 0xf)
7096 +#define MBOX_DATA28(msg)               ((msg) & ~0xf)
7097 +#define MBOX_DATA28_LSB(msg)           (((uint32_t)msg) >> 4)
7098 +
7099 +#define MBOX_MAGIC 0xd0d0c0de
7100 +
7101 +struct vc_mailbox {
7102 +       struct device *dev;     /* parent device */
7103 +       void __iomem *status;
7104 +       void __iomem *config;
7105 +       void __iomem *read;
7106 +       void __iomem *write;
7107 +       uint32_t msg[MBOX_CHAN_COUNT];
7108 +       struct semaphore sema[MBOX_CHAN_COUNT];
7109 +       uint32_t magic;
7110 +};
7111 +
7112 +static void mbox_init(struct vc_mailbox *mbox_out, struct device *dev,
7113 +                     uint32_t addr_mbox)
7114 +{
7115 +       int i;
7116 +
7117 +       mbox_out->dev = dev;
7118 +       mbox_out->status = __io_address(addr_mbox + MAIL_STA);
7119 +       mbox_out->config = __io_address(addr_mbox + MAIL_CNF);
7120 +       mbox_out->read = __io_address(addr_mbox + MAIL_RD);
7121 +       /* Write to the other mailbox */
7122 +       mbox_out->write =
7123 +           __io_address((addr_mbox ^ ARM_0_MAIL0_WRT ^ ARM_0_MAIL1_WRT) +
7124 +                        MAIL_WRT);
7125 +
7126 +       for (i = 0; i < MBOX_CHAN_COUNT; i++) {
7127 +               mbox_out->msg[i] = 0;
7128 +               sema_init(&mbox_out->sema[i], 0);
7129 +       }
7130 +
7131 +       /* Enable the interrupt on data reception */
7132 +       writel(ARM_MC_IHAVEDATAIRQEN, mbox_out->config);
7133 +
7134 +       mbox_out->magic = MBOX_MAGIC;
7135 +}
7136 +
7137 +static int mbox_write(struct vc_mailbox *mbox, unsigned chan, uint32_t data28)
7138 +{
7139 +       int rc;
7140 +
7141 +       if (mbox->magic != MBOX_MAGIC)
7142 +               rc = -EINVAL;
7143 +       else {
7144 +               /* wait for the mailbox FIFO to have some space in it */
7145 +               while (0 != (readl(mbox->status) & ARM_MS_FULL))
7146 +                       cpu_relax();
7147 +
7148 +               writel(MBOX_MSG(chan, data28), mbox->write);
7149 +               rc = 0;
7150 +       }
7151 +       return rc;
7152 +}
7153 +
7154 +static int mbox_read(struct vc_mailbox *mbox, unsigned chan, uint32_t *data28)
7155 +{
7156 +       int rc;
7157 +
7158 +       if (mbox->magic != MBOX_MAGIC)
7159 +               rc = -EINVAL;
7160 +       else {
7161 +               down(&mbox->sema[chan]);
7162 +               *data28 = MBOX_DATA28(mbox->msg[chan]);
7163 +               mbox->msg[chan] = 0;
7164 +               rc = 0;
7165 +       }
7166 +       return rc;
7167 +}
7168 +
7169 +static irqreturn_t mbox_irq(int irq, void *dev_id)
7170 +{
7171 +       /* wait for the mailbox FIFO to have some data in it */
7172 +       struct vc_mailbox *mbox = (struct vc_mailbox *) dev_id;
7173 +       int status = readl(mbox->status);
7174 +       int ret = IRQ_NONE;
7175 +
7176 +       while (!(status & ARM_MS_EMPTY)) {
7177 +               uint32_t msg = readl(mbox->read);
7178 +               int chan = MBOX_CHAN(msg);
7179 +               if (chan < MBOX_CHAN_COUNT) {
7180 +                       if (mbox->msg[chan]) {
7181 +                               /* Overflow */
7182 +                               printk(KERN_ERR DRIVER_NAME
7183 +                                      ": mbox chan %d overflow - drop %08x\n",
7184 +                                      chan, msg);
7185 +                       } else {
7186 +                               mbox->msg[chan] = (msg | 0xf);
7187 +                               up(&mbox->sema[chan]);
7188 +                       }
7189 +               } else {
7190 +                       printk(KERN_ERR DRIVER_NAME
7191 +                              ": invalid channel selector (msg %08x)\n", msg);
7192 +               }
7193 +               ret = IRQ_HANDLED;
7194 +               status = readl(mbox->status);
7195 +       }
7196 +       return ret;
7197 +}
7198 +
7199 +static struct irqaction mbox_irqaction = {
7200 +       .name = "ARM Mailbox IRQ",
7201 +       .flags = IRQF_DISABLED | IRQF_IRQPOLL,
7202 +       .handler = mbox_irq,
7203 +};
7204 +
7205 +/* ----------------------------------------------------------------------
7206 + *     Mailbox Methods
7207 + * -------------------------------------------------------------------- */
7208 +
7209 +static struct device *mbox_dev;        /* we assume there's only one! */
7210 +
7211 +static int dev_mbox_write(struct device *dev, unsigned chan, uint32_t data28)
7212 +{
7213 +       int rc;
7214 +
7215 +       struct vc_mailbox *mailbox = dev_get_drvdata(dev);
7216 +       device_lock(dev);
7217 +       rc = mbox_write(mailbox, chan, data28);
7218 +       device_unlock(dev);
7219 +
7220 +       return rc;
7221 +}
7222 +
7223 +static int dev_mbox_read(struct device *dev, unsigned chan, uint32_t *data28)
7224 +{
7225 +       int rc;
7226 +
7227 +       struct vc_mailbox *mailbox = dev_get_drvdata(dev);
7228 +       device_lock(dev);
7229 +       rc = mbox_read(mailbox, chan, data28);
7230 +       device_unlock(dev);
7231 +
7232 +       return rc;
7233 +}
7234 +
7235 +extern int bcm_mailbox_write(unsigned chan, uint32_t data28)
7236 +{
7237 +       if (mbox_dev)
7238 +               return dev_mbox_write(mbox_dev, chan, data28);
7239 +       else
7240 +               return -ENODEV;
7241 +}
7242 +EXPORT_SYMBOL_GPL(bcm_mailbox_write);
7243 +
7244 +extern int bcm_mailbox_read(unsigned chan, uint32_t *data28)
7245 +{
7246 +       if (mbox_dev)
7247 +               return dev_mbox_read(mbox_dev, chan, data28);
7248 +       else
7249 +               return -ENODEV;
7250 +}
7251 +EXPORT_SYMBOL_GPL(bcm_mailbox_read);
7252 +
7253 +static void dev_mbox_register(const char *dev_name, struct device *dev)
7254 +{
7255 +       mbox_dev = dev;
7256 +}
7257 +
7258 +static int mbox_copy_from_user(void *dst, const void *src, int size)
7259 +{
7260 +       if ( (uint32_t)src < TASK_SIZE)
7261 +       {
7262 +               return copy_from_user(dst, src, size);
7263 +       }
7264 +       else
7265 +       {
7266 +               memcpy( dst, src, size );
7267 +               return 0;
7268 +       }
7269 +}
7270 +
7271 +static int mbox_copy_to_user(void *dst, const void *src, int size)
7272 +{
7273 +       if ( (uint32_t)dst < TASK_SIZE)
7274 +       {
7275 +               return copy_to_user(dst, src, size);
7276 +       }
7277 +       else
7278 +       {
7279 +               memcpy( dst, src, size );
7280 +               return 0;
7281 +       }
7282 +}
7283 +
7284 +static DEFINE_MUTEX(mailbox_lock);
7285 +extern int bcm_mailbox_property(void *data, int size)
7286 +{
7287 +       uint32_t success;
7288 +       dma_addr_t mem_bus;                             /* the memory address accessed from videocore */
7289 +       void *mem_kern;                                 /* the memory address accessed from driver */
7290 +       int s = 0;
7291 +
7292 +        mutex_lock(&mailbox_lock);
7293 +       /* allocate some memory for the messages communicating with GPU */
7294 +       mem_kern = dma_alloc_coherent(NULL, PAGE_ALIGN(size), &mem_bus, GFP_ATOMIC);
7295 +       if (mem_kern) {
7296 +               /* create the message */
7297 +               mbox_copy_from_user(mem_kern, data, size);
7298 +
7299 +               /* send the message */
7300 +               wmb();
7301 +               s = bcm_mailbox_write(MBOX_CHAN_PROPERTY, (uint32_t)mem_bus);
7302 +               if (s == 0) {
7303 +                       s = bcm_mailbox_read(MBOX_CHAN_PROPERTY, &success);
7304 +               }
7305 +               if (s == 0) {
7306 +                       /* copy the response */
7307 +                       rmb();
7308 +                       mbox_copy_to_user(data, mem_kern, size);
7309 +               }
7310 +               dma_free_coherent(NULL, PAGE_ALIGN(size), mem_kern, mem_bus);
7311 +       } else {
7312 +               s = -ENOMEM;
7313 +       }
7314 +       if (s != 0)
7315 +               printk(KERN_ERR DRIVER_NAME ": %s failed (%d)\n", __func__, s);
7316 +
7317 +        mutex_unlock(&mailbox_lock);
7318 +       return s;
7319 +}
7320 +EXPORT_SYMBOL_GPL(bcm_mailbox_property);
7321 +
7322 +/* ----------------------------------------------------------------------
7323 + *     Platform Device for Mailbox
7324 + * -------------------------------------------------------------------- */
7325 +
7326 +/*
7327 + * Is the device open right now? Used to prevent
7328 + * concurent access into the same device
7329 + */
7330 +static int Device_Open = 0;
7331 +
7332 +/*
7333 + * This is called whenever a process attempts to open the device file
7334 + */
7335 +static int device_open(struct inode *inode, struct file *file)
7336 +{
7337 +       /*
7338 +        * We don't want to talk to two processes at the same time
7339 +        */
7340 +       if (Device_Open)
7341 +               return -EBUSY;
7342 +
7343 +       Device_Open++;
7344 +       /*
7345 +        * Initialize the message
7346 +        */
7347 +       try_module_get(THIS_MODULE);
7348 +       return 0;
7349 +}
7350 +
7351 +static int device_release(struct inode *inode, struct file *file)
7352 +{
7353 +       /*
7354 +        * We're now ready for our next caller
7355 +        */
7356 +       Device_Open--;
7357 +
7358 +       module_put(THIS_MODULE);
7359 +       return 0;
7360 +}
7361 +
7362 +/*
7363 + * This function is called whenever a process tries to do an ioctl on our
7364 + * device file. We get two extra parameters (additional to the inode and file
7365 + * structures, which all device functions get): the number of the ioctl called
7366 + * and the parameter given to the ioctl function.
7367 + *
7368 + * If the ioctl is write or read/write (meaning output is returned to the
7369 + * calling process), the ioctl call returns the output of this function.
7370 + *
7371 + */
7372 +static long device_ioctl(struct file *file,    /* see include/linux/fs.h */
7373 +                unsigned int ioctl_num,        /* number and param for ioctl */
7374 +                unsigned long ioctl_param)
7375 +{
7376 +       unsigned size;
7377 +       /*
7378 +        * Switch according to the ioctl called
7379 +        */
7380 +       switch (ioctl_num) {
7381 +       case IOCTL_MBOX_PROPERTY:
7382 +               /*
7383 +                * Receive a pointer to a message (in user space) and set that
7384 +                * to be the device's message.  Get the parameter given to
7385 +                * ioctl by the process.
7386 +                */
7387 +               mbox_copy_from_user(&size, (void *)ioctl_param, sizeof size);
7388 +               return bcm_mailbox_property((void *)ioctl_param, size);
7389 +               break;
7390 +       default:
7391 +               printk(KERN_ERR DRIVER_NAME "unknown ioctl: %d\n", ioctl_num);
7392 +               return -EINVAL;
7393 +       }
7394 +
7395 +       return 0;
7396 +}
7397 +
7398 +/* Module Declarations */
7399 +
7400 +/*
7401 + * This structure will hold the functions to be called
7402 + * when a process does something to the device we
7403 + * created. Since a pointer to this structure is kept in
7404 + * the devices table, it can't be local to
7405 + * init_module. NULL is for unimplemented functios.
7406 + */
7407 +struct file_operations fops = {
7408 +       .unlocked_ioctl = device_ioctl,
7409 +       .open = device_open,
7410 +       .release = device_release,      /* a.k.a. close */
7411 +};
7412 +
7413 +static int bcm_vcio_probe(struct platform_device *pdev)
7414 +{
7415 +       int ret = 0;
7416 +       struct vc_mailbox *mailbox;
7417 +
7418 +       mailbox = kzalloc(sizeof(*mailbox), GFP_KERNEL);
7419 +       if (NULL == mailbox) {
7420 +               printk(KERN_ERR DRIVER_NAME ": failed to allocate "
7421 +                      "mailbox memory\n");
7422 +               ret = -ENOMEM;
7423 +       } else {
7424 +               struct resource *res;
7425 +
7426 +               res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7427 +               if (res == NULL) {
7428 +                       printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
7429 +                              "resource\n");
7430 +                       ret = -ENODEV;
7431 +                       kfree(mailbox);
7432 +               } else {
7433 +                       /* should be based on the registers from res really */
7434 +                       mbox_init(mailbox, &pdev->dev, ARM_0_MAIL0_RD);
7435 +
7436 +                       platform_set_drvdata(pdev, mailbox);
7437 +                       dev_mbox_register(DRIVER_NAME, &pdev->dev);
7438 +
7439 +                       mbox_irqaction.dev_id = mailbox;
7440 +                       setup_irq(IRQ_ARM_MAILBOX, &mbox_irqaction);
7441 +                       printk(KERN_INFO DRIVER_NAME ": mailbox at %p\n",
7442 +                              __io_address(ARM_0_MAIL0_RD));
7443 +               }
7444 +       }
7445 +
7446 +       if (ret == 0) {
7447 +               /*
7448 +                * Register the character device
7449 +                */
7450 +               ret = register_chrdev(MAJOR_NUM, DEVICE_FILE_NAME, &fops);
7451 +
7452 +               /*
7453 +                * Negative values signify an error
7454 +                */
7455 +               if (ret < 0) {
7456 +                       printk(KERN_ERR DRIVER_NAME
7457 +                              "Failed registering the character device %d\n", ret);
7458 +                       return ret;
7459 +               }
7460 +       }
7461 +       return ret;
7462 +}
7463 +
7464 +static int bcm_vcio_remove(struct platform_device *pdev)
7465 +{
7466 +       struct vc_mailbox *mailbox = platform_get_drvdata(pdev);
7467 +
7468 +       platform_set_drvdata(pdev, NULL);
7469 +       kfree(mailbox);
7470 +
7471 +       return 0;
7472 +}
7473 +
7474 +static struct platform_driver bcm_mbox_driver = {
7475 +       .probe = bcm_vcio_probe,
7476 +       .remove = bcm_vcio_remove,
7477 +
7478 +       .driver = {
7479 +                  .name = DRIVER_NAME,
7480 +                  .owner = THIS_MODULE,
7481 +                  },
7482 +};
7483 +
7484 +static int __init bcm_mbox_init(void)
7485 +{
7486 +       int ret;
7487 +
7488 +       printk(KERN_INFO "mailbox: Broadcom VideoCore Mailbox driver\n");
7489 +
7490 +       ret = platform_driver_register(&bcm_mbox_driver);
7491 +       if (ret != 0) {
7492 +               printk(KERN_ERR DRIVER_NAME ": failed to register "
7493 +                      "on platform\n");
7494 +       }
7495 +
7496 +       return ret;
7497 +}
7498 +
7499 +static void __exit bcm_mbox_exit(void)
7500 +{
7501 +       platform_driver_unregister(&bcm_mbox_driver);
7502 +}
7503 +
7504 +arch_initcall(bcm_mbox_init);  /* Initialize early */
7505 +module_exit(bcm_mbox_exit);
7506 +
7507 +MODULE_AUTHOR("Gray Girling");
7508 +MODULE_DESCRIPTION("ARM I/O to VideoCore processor");
7509 +MODULE_LICENSE("GPL");
7510 +MODULE_ALIAS("platform:bcm-mbox");
7511 --- /dev/null
7512 +++ b/arch/arm/mach-bcm2708/vc_mem.c
7513 @@ -0,0 +1,462 @@
7514 +/*****************************************************************************
7515 +* Copyright 2010 - 2011 Broadcom Corporation.  All rights reserved.
7516 +*
7517 +* Unless you and Broadcom execute a separate written software license
7518 +* agreement governing use of this software, this software is licensed to you
7519 +* under the terms of the GNU General Public License version 2, available at
7520 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
7521 +*
7522 +* Notwithstanding the above, under no circumstances may you combine this
7523 +* software in any way with any other Broadcom software provided under a
7524 +* license other than the GPL, without Broadcom's express prior written
7525 +* consent.
7526 +*****************************************************************************/
7527 +
7528 +#include <linux/kernel.h>
7529 +#include <linux/module.h>
7530 +#include <linux/fs.h>
7531 +#include <linux/device.h>
7532 +#include <linux/cdev.h>
7533 +#include <linux/mm.h>
7534 +#include <linux/slab.h>
7535 +#include <linux/proc_fs.h>
7536 +#include <asm/uaccess.h>
7537 +#include <linux/dma-mapping.h>
7538 +
7539 +#ifdef CONFIG_ARCH_KONA
7540 +#include <chal/chal_ipc.h>
7541 +#elif CONFIG_ARCH_BCM2708
7542 +#else
7543 +#include <csp/chal_ipc.h>
7544 +#endif
7545 +
7546 +#include "mach/vc_mem.h"
7547 +#include <mach/vcio.h>
7548 +
7549 +#define DRIVER_NAME  "vc-mem"
7550 +
7551 +// Uncomment to enable debug logging
7552 +// #define ENABLE_DBG
7553 +
7554 +#if defined(ENABLE_DBG)
7555 +#define LOG_DBG( fmt, ... )  printk( KERN_INFO fmt "\n", ##__VA_ARGS__ )
7556 +#else
7557 +#define LOG_DBG( fmt, ... )
7558 +#endif
7559 +#define LOG_ERR( fmt, ... )  printk( KERN_ERR fmt "\n", ##__VA_ARGS__ )
7560 +
7561 +// Device (/dev) related variables
7562 +static dev_t vc_mem_devnum = 0;
7563 +static struct class *vc_mem_class = NULL;
7564 +static struct cdev vc_mem_cdev;
7565 +static int vc_mem_inited = 0;
7566 +
7567 +// Proc entry
7568 +static struct proc_dir_entry *vc_mem_proc_entry;
7569 +
7570 +/*
7571 + * Videocore memory addresses and size
7572 + *
7573 + * Drivers that wish to know the videocore memory addresses and sizes should
7574 + * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
7575 + * headers. This allows the other drivers to not be tied down to a a certain
7576 + * address/size at compile time.
7577 + *
7578 + * In the future, the goal is to have the videocore memory virtual address and
7579 + * size be calculated at boot time rather than at compile time. The decision of
7580 + * where the videocore memory resides and its size would be in the hands of the
7581 + * bootloader (and/or kernel). When that happens, the values of these variables
7582 + * would be calculated and assigned in the init function.
7583 + */
7584 +// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
7585 +unsigned long mm_vc_mem_phys_addr = 0x00000000;
7586 +unsigned int mm_vc_mem_size = 0;
7587 +unsigned int mm_vc_mem_base = 0;
7588 +
7589 +EXPORT_SYMBOL(mm_vc_mem_phys_addr);
7590 +EXPORT_SYMBOL(mm_vc_mem_size);
7591 +EXPORT_SYMBOL(mm_vc_mem_base);
7592 +
7593 +static uint phys_addr = 0;
7594 +static uint mem_size = 0;
7595 +static uint mem_base = 0;
7596 +
7597 +
7598 +/****************************************************************************
7599 +*
7600 +*   vc_mem_open
7601 +*
7602 +***************************************************************************/
7603 +
7604 +static int
7605 +vc_mem_open(struct inode *inode, struct file *file)
7606 +{
7607 +       (void) inode;
7608 +       (void) file;
7609 +
7610 +       LOG_DBG("%s: called file = 0x%p", __func__, file);
7611 +
7612 +       return 0;
7613 +}
7614 +
7615 +/****************************************************************************
7616 +*
7617 +*   vc_mem_release
7618 +*
7619 +***************************************************************************/
7620 +
7621 +static int
7622 +vc_mem_release(struct inode *inode, struct file *file)
7623 +{
7624 +       (void) inode;
7625 +       (void) file;
7626 +
7627 +       LOG_DBG("%s: called file = 0x%p", __func__, file);
7628 +
7629 +       return 0;
7630 +}
7631 +
7632 +/****************************************************************************
7633 +*
7634 +*   vc_mem_get_size
7635 +*
7636 +***************************************************************************/
7637 +
7638 +static void
7639 +vc_mem_get_size(void)
7640 +{
7641 +}
7642 +
7643 +/****************************************************************************
7644 +*
7645 +*   vc_mem_get_base
7646 +*
7647 +***************************************************************************/
7648 +
7649 +static void
7650 +vc_mem_get_base(void)
7651 +{
7652 +}
7653 +
7654 +/****************************************************************************
7655 +*
7656 +*   vc_mem_get_current_size
7657 +*
7658 +***************************************************************************/
7659 +
7660 +int
7661 +vc_mem_get_current_size(void)
7662 +{
7663 +       return mm_vc_mem_size;
7664 +}
7665 +
7666 +EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
7667 +
7668 +/****************************************************************************
7669 +*
7670 +*   vc_mem_ioctl
7671 +*
7672 +***************************************************************************/
7673 +
7674 +static long
7675 +vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
7676 +{
7677 +       int rc = 0;
7678 +
7679 +       (void) cmd;
7680 +       (void) arg;
7681 +
7682 +       LOG_DBG("%s: called file = 0x%p", __func__, file);
7683 +
7684 +       switch (cmd) {
7685 +       case VC_MEM_IOC_MEM_PHYS_ADDR:
7686 +               {
7687 +                       LOG_DBG("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p",
7688 +                               __func__, (void *) mm_vc_mem_phys_addr);
7689 +
7690 +                       if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
7691 +                                        sizeof (mm_vc_mem_phys_addr)) != 0) {
7692 +                               rc = -EFAULT;
7693 +                       }
7694 +                       break;
7695 +               }
7696 +       case VC_MEM_IOC_MEM_SIZE:
7697 +               {
7698 +                       // Get the videocore memory size first
7699 +                       vc_mem_get_size();
7700 +
7701 +                       LOG_DBG("%s: VC_MEM_IOC_MEM_SIZE=%u", __func__,
7702 +                               mm_vc_mem_size);
7703 +
7704 +                       if (copy_to_user((void *) arg, &mm_vc_mem_size,
7705 +                                        sizeof (mm_vc_mem_size)) != 0) {
7706 +                               rc = -EFAULT;
7707 +                       }
7708 +                       break;
7709 +               }
7710 +       case VC_MEM_IOC_MEM_BASE:
7711 +               {
7712 +                       // Get the videocore memory base
7713 +                       vc_mem_get_base();
7714 +
7715 +                       LOG_DBG("%s: VC_MEM_IOC_MEM_BASE=%u", __func__,
7716 +                               mm_vc_mem_base);
7717 +
7718 +                       if (copy_to_user((void *) arg, &mm_vc_mem_base,
7719 +                                        sizeof (mm_vc_mem_base)) != 0) {
7720 +                               rc = -EFAULT;
7721 +                       }
7722 +                       break;
7723 +               }
7724 +       case VC_MEM_IOC_MEM_LOAD:
7725 +               {
7726 +                       // Get the videocore memory base
7727 +                       vc_mem_get_base();
7728 +
7729 +                       LOG_DBG("%s: VC_MEM_IOC_MEM_LOAD=%u", __func__,
7730 +                               mm_vc_mem_base);
7731 +
7732 +                       if (copy_to_user((void *) arg, &mm_vc_mem_base,
7733 +                                        sizeof (mm_vc_mem_base)) != 0) {
7734 +                               rc = -EFAULT;
7735 +                       }
7736 +                       break;
7737 +               }
7738 +       default:
7739 +               {
7740 +                       return -ENOTTY;
7741 +               }
7742 +       }
7743 +       LOG_DBG("%s: file = 0x%p returning %d", __func__, file, rc);
7744 +
7745 +       return rc;
7746 +}
7747 +
7748 +/****************************************************************************
7749 +*
7750 +*   vc_mem_mmap
7751 +*
7752 +***************************************************************************/
7753 +
7754 +static int
7755 +vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
7756 +{
7757 +       int rc = 0;
7758 +       unsigned long length = vma->vm_end - vma->vm_start;
7759 +       unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
7760 +
7761 +       LOG_DBG("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx",
7762 +               __func__, (long) vma->vm_start, (long) vma->vm_end,
7763 +               (long) vma->vm_pgoff);
7764 +
7765 +       if (offset + length > mm_vc_mem_size) {
7766 +               LOG_ERR("%s: length %ld is too big", __func__, length);
7767 +               return -EINVAL;
7768 +       }
7769 +       // Do not cache the memory map
7770 +       vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
7771 +
7772 +       rc = remap_pfn_range(vma, vma->vm_start,
7773 +                            (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
7774 +                            vma->vm_pgoff, length, vma->vm_page_prot);
7775 +       if (rc != 0) {
7776 +               LOG_ERR("%s: remap_pfn_range failed (rc=%d)", __func__, rc);
7777 +       }
7778 +
7779 +       return rc;
7780 +}
7781 +
7782 +/****************************************************************************
7783 +*
7784 +*   File Operations for the driver.
7785 +*
7786 +***************************************************************************/
7787 +
7788 +static const struct file_operations vc_mem_fops = {
7789 +       .owner = THIS_MODULE,
7790 +       .open = vc_mem_open,
7791 +       .release = vc_mem_release,
7792 +       .unlocked_ioctl = vc_mem_ioctl,
7793 +       .mmap = vc_mem_mmap,
7794 +};
7795 +
7796 +/****************************************************************************
7797 +*
7798 +*   vc_mem_proc_read
7799 +*
7800 +***************************************************************************/
7801 +
7802 +static int
7803 +vc_mem_proc_read(char *buf, char **start, off_t offset, int count, int *eof,
7804 +                void *data)
7805 +{
7806 +       char *p = buf;
7807 +
7808 +       (void) start;
7809 +       (void) count;
7810 +       (void) data;
7811 +
7812 +       if (offset > 0) {
7813 +               *eof = 1;
7814 +               return 0;
7815 +       }
7816 +       // Get the videocore memory size first
7817 +       vc_mem_get_size();
7818 +
7819 +       p += sprintf(p, "Videocore memory:\n");
7820 +       if (mm_vc_mem_phys_addr != 0)
7821 +               p += sprintf(p, "   Physical address: 0x%p\n",
7822 +                            (void *) mm_vc_mem_phys_addr);
7823 +       else
7824 +               p += sprintf(p, "   Physical address: 0x00000000\n");
7825 +       p += sprintf(p, "   Length (bytes):   %u\n", mm_vc_mem_size);
7826 +
7827 +       *eof = 1;
7828 +       return p - buf;
7829 +}
7830 +
7831 +/****************************************************************************
7832 +*
7833 +*   vc_mem_proc_write
7834 +*
7835 +***************************************************************************/
7836 +
7837 +static int
7838 +vc_mem_proc_write(struct file *file, const char __user * buffer,
7839 +                 unsigned long count, void *data)
7840 +{
7841 +       int rc = -EFAULT;
7842 +       char input_str[10];
7843 +
7844 +       memset(input_str, 0, sizeof (input_str));
7845 +
7846 +       if (count > sizeof (input_str)) {
7847 +               LOG_ERR("%s: input string length too long", __func__);
7848 +               goto out;
7849 +       }
7850 +
7851 +       if (copy_from_user(input_str, buffer, count - 1)) {
7852 +               LOG_ERR("%s: failed to get input string", __func__);
7853 +               goto out;
7854 +       }
7855 +
7856 +       if (strncmp(input_str, "connect", strlen("connect")) == 0) {
7857 +               // Get the videocore memory size from the videocore
7858 +               vc_mem_get_size();
7859 +       }
7860 +
7861 +      out:
7862 +       return rc;
7863 +}
7864 +
7865 +/****************************************************************************
7866 +*
7867 +*   vc_mem_init
7868 +*
7869 +***************************************************************************/
7870 +
7871 +static int __init
7872 +vc_mem_init(void)
7873 +{
7874 +       int rc = -EFAULT;
7875 +       struct device *dev;
7876 +
7877 +       LOG_DBG("%s: called", __func__);
7878 +
7879 +       mm_vc_mem_phys_addr = phys_addr;
7880 +       mm_vc_mem_size = mem_size;
7881 +       mm_vc_mem_base = mem_base;
7882 +
7883 +       vc_mem_get_size();
7884 +
7885 +       printk("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
7886 +               mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
7887 +
7888 +       if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
7889 +               LOG_ERR("%s: alloc_chrdev_region failed (rc=%d)", __func__, rc);
7890 +               goto out_err;
7891 +       }
7892 +
7893 +       cdev_init(&vc_mem_cdev, &vc_mem_fops);
7894 +       if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
7895 +               LOG_ERR("%s: cdev_add failed (rc=%d)", __func__, rc);
7896 +               goto out_unregister;
7897 +       }
7898 +
7899 +       vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
7900 +       if (IS_ERR(vc_mem_class)) {
7901 +               rc = PTR_ERR(vc_mem_class);
7902 +               LOG_ERR("%s: class_create failed (rc=%d)", __func__, rc);
7903 +               goto out_cdev_del;
7904 +       }
7905 +
7906 +       dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
7907 +                           DRIVER_NAME);
7908 +       if (IS_ERR(dev)) {
7909 +               rc = PTR_ERR(dev);
7910 +               LOG_ERR("%s: device_create failed (rc=%d)", __func__, rc);
7911 +               goto out_class_destroy;
7912 +       }
7913 +
7914 +#if 0
7915 +       vc_mem_proc_entry = create_proc_entry(DRIVER_NAME, 0444, NULL);
7916 +       if (vc_mem_proc_entry == NULL) {
7917 +               rc = -EFAULT;
7918 +               LOG_ERR("%s: create_proc_entry failed", __func__);
7919 +               goto out_device_destroy;
7920 +       }
7921 +       vc_mem_proc_entry->read_proc = vc_mem_proc_read;
7922 +       vc_mem_proc_entry->write_proc = vc_mem_proc_write;
7923 +#endif
7924 +
7925 +       vc_mem_inited = 1;
7926 +       return 0;
7927 +
7928 +      out_device_destroy:
7929 +       device_destroy(vc_mem_class, vc_mem_devnum);
7930 +
7931 +      out_class_destroy:
7932 +       class_destroy(vc_mem_class);
7933 +       vc_mem_class = NULL;
7934 +
7935 +      out_cdev_del:
7936 +       cdev_del(&vc_mem_cdev);
7937 +
7938 +      out_unregister:
7939 +       unregister_chrdev_region(vc_mem_devnum, 1);
7940 +
7941 +      out_err:
7942 +       return -1;
7943 +}
7944 +
7945 +/****************************************************************************
7946 +*
7947 +*   vc_mem_exit
7948 +*
7949 +***************************************************************************/
7950 +
7951 +static void __exit
7952 +vc_mem_exit(void)
7953 +{
7954 +       LOG_DBG("%s: called", __func__);
7955 +
7956 +       if (vc_mem_inited) {
7957 +#if 0
7958 +               remove_proc_entry(vc_mem_proc_entry->name, NULL);
7959 +#endif
7960 +               device_destroy(vc_mem_class, vc_mem_devnum);
7961 +               class_destroy(vc_mem_class);
7962 +               cdev_del(&vc_mem_cdev);
7963 +               unregister_chrdev_region(vc_mem_devnum, 1);
7964 +       }
7965 +}
7966 +
7967 +module_init(vc_mem_init);
7968 +module_exit(vc_mem_exit);
7969 +MODULE_LICENSE("GPL");
7970 +MODULE_AUTHOR("Broadcom Corporation");
7971 +
7972 +module_param(phys_addr, uint, 0644);
7973 +module_param(mem_size, uint, 0644);
7974 +module_param(mem_base, uint, 0644);
7975 +
7976 --- /dev/null
7977 +++ b/arch/arm/mach-bcm2708/vc_support.c
7978 @@ -0,0 +1,319 @@
7979 +/*
7980 + * vc_support.c
7981 + *
7982 + *  Created on: 25 Nov 2012
7983 + *      Author: Simon
7984 + */
7985 +
7986 +#include <linux/module.h>
7987 +#include <mach/vcio.h>
7988 +
7989 +#ifdef ECLIPSE_IGNORE
7990 +
7991 +#define __user
7992 +#define __init
7993 +#define __exit
7994 +#define __iomem
7995 +#define KERN_DEBUG
7996 +#define KERN_ERR
7997 +#define KERN_WARNING
7998 +#define KERN_INFO
7999 +#define _IOWR(a, b, c) b
8000 +#define _IOW(a, b, c) b
8001 +#define _IO(a, b) b
8002 +
8003 +#endif
8004 +
8005 +/****** VC MAILBOX FUNCTIONALITY ******/
8006 +unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags)
8007 +{
8008 +       struct vc_msg
8009 +       {
8010 +               unsigned int m_msgSize;
8011 +               unsigned int m_response;
8012 +
8013 +               struct vc_tag
8014 +               {
8015 +                       unsigned int m_tagId;
8016 +                       unsigned int m_sendBufferSize;
8017 +                       union {
8018 +                               unsigned int m_sendDataSize;
8019 +                               unsigned int m_recvDataSize;
8020 +                       };
8021 +
8022 +                       struct args
8023 +                       {
8024 +                               union {
8025 +                                       unsigned int m_size;
8026 +                                       unsigned int m_handle;
8027 +                               };
8028 +                               unsigned int m_alignment;
8029 +                               unsigned int m_flags;
8030 +                       } m_args;
8031 +               } m_tag;
8032 +
8033 +               unsigned int m_endTag;
8034 +       } msg;
8035 +       int s;
8036 +
8037 +       msg.m_msgSize = sizeof(msg);
8038 +       msg.m_response = 0;
8039 +       msg.m_endTag = 0;
8040 +
8041 +       //fill in the tag for the allocation command
8042 +       msg.m_tag.m_tagId = 0x3000c;
8043 +       msg.m_tag.m_sendBufferSize = 12;
8044 +       msg.m_tag.m_sendDataSize = 12;
8045 +
8046 +       //fill in our args
8047 +       msg.m_tag.m_args.m_size = size;
8048 +       msg.m_tag.m_args.m_alignment = alignment;
8049 +       msg.m_tag.m_args.m_flags = flags;
8050 +
8051 +       //run the command
8052 +       s = bcm_mailbox_property(&msg, sizeof(msg));
8053 +
8054 +       if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
8055 +       {
8056 +               *pHandle = msg.m_tag.m_args.m_handle;
8057 +               return 0;
8058 +       }
8059 +       else
8060 +       {
8061 +               printk(KERN_ERR "failed to allocate vc memory: s=%d response=%08x recv data size=%08x\n",
8062 +                               s, msg.m_response, msg.m_tag.m_recvDataSize);
8063 +               return 1;
8064 +       }
8065 +}
8066 +
8067 +unsigned int ReleaseVcMemory(unsigned int handle)
8068 +{
8069 +       struct vc_msg
8070 +       {
8071 +               unsigned int m_msgSize;
8072 +               unsigned int m_response;
8073 +
8074 +               struct vc_tag
8075 +               {
8076 +                       unsigned int m_tagId;
8077 +                       unsigned int m_sendBufferSize;
8078 +                       union {
8079 +                               unsigned int m_sendDataSize;
8080 +                               unsigned int m_recvDataSize;
8081 +                       };
8082 +
8083 +                       struct args
8084 +                       {
8085 +                               union {
8086 +                                       unsigned int m_handle;
8087 +                                       unsigned int m_error;
8088 +                               };
8089 +                       } m_args;
8090 +               } m_tag;
8091 +
8092 +               unsigned int m_endTag;
8093 +       } msg;
8094 +       int s;
8095 +
8096 +       msg.m_msgSize = sizeof(msg);
8097 +       msg.m_response = 0;
8098 +       msg.m_endTag = 0;
8099 +
8100 +       //fill in the tag for the release command
8101 +       msg.m_tag.m_tagId = 0x3000f;
8102 +       msg.m_tag.m_sendBufferSize = 4;
8103 +       msg.m_tag.m_sendDataSize = 4;
8104 +
8105 +       //pass across the handle
8106 +       msg.m_tag.m_args.m_handle = handle;
8107 +
8108 +       s = bcm_mailbox_property(&msg, sizeof(msg));
8109 +
8110 +       if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0)
8111 +               return 0;
8112 +       else
8113 +       {
8114 +               printk(KERN_ERR "failed to release vc memory: s=%d response=%08x recv data size=%08x error=%08x\n",
8115 +                               s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error);
8116 +               return 1;
8117 +       }
8118 +}
8119 +
8120 +unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle)
8121 +{
8122 +       struct vc_msg
8123 +       {
8124 +               unsigned int m_msgSize;
8125 +               unsigned int m_response;
8126 +
8127 +               struct vc_tag
8128 +               {
8129 +                       unsigned int m_tagId;
8130 +                       unsigned int m_sendBufferSize;
8131 +                       union {
8132 +                               unsigned int m_sendDataSize;
8133 +                               unsigned int m_recvDataSize;
8134 +                       };
8135 +
8136 +                       struct args
8137 +                       {
8138 +                               union {
8139 +                                       unsigned int m_handle;
8140 +                                       unsigned int m_busAddress;
8141 +                               };
8142 +                       } m_args;
8143 +               } m_tag;
8144 +
8145 +               unsigned int m_endTag;
8146 +       } msg;
8147 +       int s;
8148 +
8149 +       msg.m_msgSize = sizeof(msg);
8150 +       msg.m_response = 0;
8151 +       msg.m_endTag = 0;
8152 +
8153 +       //fill in the tag for the lock command
8154 +       msg.m_tag.m_tagId = 0x3000d;
8155 +       msg.m_tag.m_sendBufferSize = 4;
8156 +       msg.m_tag.m_sendDataSize = 4;
8157 +
8158 +       //pass across the handle
8159 +       msg.m_tag.m_args.m_handle = handle;
8160 +
8161 +       s = bcm_mailbox_property(&msg, sizeof(msg));
8162 +
8163 +       if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
8164 +       {
8165 +               //pick out the bus address
8166 +               *pBusAddress = msg.m_tag.m_args.m_busAddress;
8167 +               return 0;
8168 +       }
8169 +       else
8170 +       {
8171 +               printk(KERN_ERR "failed to lock vc memory: s=%d response=%08x recv data size=%08x\n",
8172 +                               s, msg.m_response, msg.m_tag.m_recvDataSize);
8173 +               return 1;
8174 +       }
8175 +}
8176 +
8177 +unsigned int UnlockVcMemory(unsigned int handle)
8178 +{
8179 +       struct vc_msg
8180 +       {
8181 +               unsigned int m_msgSize;
8182 +               unsigned int m_response;
8183 +
8184 +               struct vc_tag
8185 +               {
8186 +                       unsigned int m_tagId;
8187 +                       unsigned int m_sendBufferSize;
8188 +                       union {
8189 +                               unsigned int m_sendDataSize;
8190 +                               unsigned int m_recvDataSize;
8191 +                       };
8192 +
8193 +                       struct args
8194 +                       {
8195 +                               union {
8196 +                                       unsigned int m_handle;
8197 +                                       unsigned int m_error;
8198 +                               };
8199 +                       } m_args;
8200 +               } m_tag;
8201 +
8202 +               unsigned int m_endTag;
8203 +       } msg;
8204 +       int s;
8205 +
8206 +       msg.m_msgSize = sizeof(msg);
8207 +       msg.m_response = 0;
8208 +       msg.m_endTag = 0;
8209 +
8210 +       //fill in the tag for the unlock command
8211 +       msg.m_tag.m_tagId = 0x3000e;
8212 +       msg.m_tag.m_sendBufferSize = 4;
8213 +       msg.m_tag.m_sendDataSize = 4;
8214 +
8215 +       //pass across the handle
8216 +       msg.m_tag.m_args.m_handle = handle;
8217 +
8218 +       s = bcm_mailbox_property(&msg, sizeof(msg));
8219 +
8220 +       //check the error code too
8221 +       if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0)
8222 +               return 0;
8223 +       else
8224 +       {
8225 +               printk(KERN_ERR "failed to unlock vc memory: s=%d response=%08x recv data size=%08x error%08x\n",
8226 +                               s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error);
8227 +               return 1;
8228 +       }
8229 +}
8230 +
8231 +unsigned int ExecuteVcCode(unsigned int code,
8232 +               unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5)
8233 +{
8234 +       struct vc_msg
8235 +       {
8236 +               unsigned int m_msgSize;
8237 +               unsigned int m_response;
8238 +
8239 +               struct vc_tag
8240 +               {
8241 +                       unsigned int m_tagId;
8242 +                       unsigned int m_sendBufferSize;
8243 +                       union {
8244 +                               unsigned int m_sendDataSize;
8245 +                               unsigned int m_recvDataSize;
8246 +                       };
8247 +
8248 +                       struct args
8249 +                       {
8250 +                               union {
8251 +                                       unsigned int m_pCode;
8252 +                                       unsigned int m_return;
8253 +                               };
8254 +                               unsigned int m_r0;
8255 +                               unsigned int m_r1;
8256 +                               unsigned int m_r2;
8257 +                               unsigned int m_r3;
8258 +                               unsigned int m_r4;
8259 +                               unsigned int m_r5;
8260 +                       } m_args;
8261 +               } m_tag;
8262 +
8263 +               unsigned int m_endTag;
8264 +       } msg;
8265 +       int s;
8266 +
8267 +       msg.m_msgSize = sizeof(msg);
8268 +       msg.m_response = 0;
8269 +       msg.m_endTag = 0;
8270 +
8271 +       //fill in the tag for the unlock command
8272 +       msg.m_tag.m_tagId = 0x30010;
8273 +       msg.m_tag.m_sendBufferSize = 28;
8274 +       msg.m_tag.m_sendDataSize = 28;
8275 +
8276 +       //pass across the handle
8277 +       msg.m_tag.m_args.m_pCode = code;
8278 +       msg.m_tag.m_args.m_r0 = r0;
8279 +       msg.m_tag.m_args.m_r1 = r1;
8280 +       msg.m_tag.m_args.m_r2 = r2;
8281 +       msg.m_tag.m_args.m_r3 = r3;
8282 +       msg.m_tag.m_args.m_r4 = r4;
8283 +       msg.m_tag.m_args.m_r5 = r5;
8284 +
8285 +       s = bcm_mailbox_property(&msg, sizeof(msg));
8286 +
8287 +       //check the error code too
8288 +       if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
8289 +               return msg.m_tag.m_args.m_return;
8290 +       else
8291 +       {
8292 +               printk(KERN_ERR "failed to execute: s=%d response=%08x recv data size=%08x\n",
8293 +                               s, msg.m_response, msg.m_tag.m_recvDataSize);
8294 +               return 1;
8295 +       }
8296 +}
8297 +
8298 --- a/arch/arm/Makefile
8299 +++ b/arch/arm/Makefile
8300 @@ -144,6 +144,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x0020
8301  # by CONFIG_* macro name.
8302  machine-$(CONFIG_ARCH_AT91)            += at91
8303  machine-$(CONFIG_ARCH_BCM)             += bcm
8304 +machine-$(CONFIG_ARCH_BCM2708)         += bcm2708
8305  machine-$(CONFIG_ARCH_BCM2835)         += bcm2835
8306  machine-$(CONFIG_ARCH_CLPS711X)                += clps711x
8307  machine-$(CONFIG_ARCH_CNS3XXX)         += cns3xxx
8308 --- a/arch/arm/mm/Kconfig
8309 +++ b/arch/arm/mm/Kconfig
8310 @@ -358,7 +358,7 @@ config CPU_PJ4B
8311
8312  # ARMv6
8313  config CPU_V6
8314 -       bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
8315 +       bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708
8316         select CPU_32v6
8317         select CPU_ABRT_EV6
8318         select CPU_CACHE_V6
8319 --- a/arch/arm/mm/proc-v6.S
8320 +++ b/arch/arm/mm/proc-v6.S
8321 @@ -73,10 +73,19 @@ ENDPROC(cpu_v6_reset)
8322   *
8323   *     IRQs are already disabled.
8324   */
8325 +
8326 +/* See jira SW-5991 for details of this workaround */
8327  ENTRY(cpu_v6_do_idle)
8328 -       mov     r1, #0
8329 -       mcr     p15, 0, r1, c7, c10, 4          @ DWB - WFI may enter a low-power mode
8330 -       mcr     p15, 0, r1, c7, c0, 4           @ wait for interrupt
8331 +       .align 5
8332 +       mov     r1, #2
8333 +1:     subs    r1, #1
8334 +       nop
8335 +       mcreq   p15, 0, r1, c7, c10, 4          @ DWB - WFI may enter a low-power mode
8336 +       mcreq   p15, 0, r1, c7, c0, 4           @ wait for interrupt
8337 +       nop
8338 +       nop
8339 +       nop
8340 +       bne 1b
8341         mov     pc, lr
8342
8343  ENTRY(cpu_v6_dcache_clean_area)
8344 --- a/arch/arm/tools/mach-types
8345 +++ b/arch/arm/tools/mach-types
8346 @@ -522,6 +522,7 @@ torbreck            MACH_TORBRECK           TORBRECK                3090
8347  prima2_evb             MACH_PRIMA2_EVB         PRIMA2_EVB              3103
8348  paz00                  MACH_PAZ00              PAZ00                   3128
8349  acmenetusfoxg20                MACH_ACMENETUSFOXG20    ACMENETUSFOXG20         3129
8350 +bcm2708                        MACH_BCM2708            BCM2708                 3138
8351  ag5evm                 MACH_AG5EVM             AG5EVM                  3189
8352  ics_if_voip            MACH_ICS_IF_VOIP        ICS_IF_VOIP             3206
8353  wlf_cragg_6410         MACH_WLF_CRAGG_6410     WLF_CRAGG_6410          3207