5bdcdabdfcf3c5c296c9e000b89166b46e5ba865
[openwrt/staging/wigyori.git] / target / linux / brcm2708 / patches-4.19 / 950-0085-ASoC-wm8804-MCLK-configuration-options-32-bit.patch
1 From b6bdfa9b91311644ca2acaef35bdc6593b83e6e3 Mon Sep 17 00:00:00 2001
2 From: Daniel Matuschek <info@crazy-audio.com>
3 Date: Wed, 15 Jan 2014 21:41:23 +0100
4 Subject: [PATCH 085/782] ASoC: wm8804: MCLK configuration options, 32-bit
5
6 WM8804 can run with PLL frequencies of 256xfs and 128xfs for most sample
7 rates. At 192kHz only 128xfs is supported. The existing driver selects
8 128xfs automatically for some lower samples rates. By using an
9 additional mclk_div divider, it is now possible to control the
10 behaviour. This allows using 256xfs PLL frequency on all sample rates up
11 to 96kHz. It should allow lower jitter and better signal quality. The
12 behavior has to be controlled by the sound card driver, because some
13 sample frequency share the same setting. e.g. 192kHz and 96kHz use
14 24.576MHz master clock. The only difference is the MCLK divider.
15
16 This also added support for 32bit data.
17
18 Signed-off-by: Daniel Matuschek <daniel@matuschek.net>
19 ---
20 sound/soc/codecs/wm8804.c | 1 +
21 1 file changed, 1 insertion(+)
22
23 --- a/sound/soc/codecs/wm8804.c
24 +++ b/sound/soc/codecs/wm8804.c
25 @@ -550,6 +550,7 @@ static const struct snd_soc_component_dr
26 .use_pmdown_time = 1,
27 .endianness = 1,
28 .non_legacy_dai_naming = 1,
29 + .idle_bias_on = true,
30 };
31
32 const struct regmap_config wm8804_regmap_config = {