target/linux/brcm2708/patches-4.19/950-0633-ARM-dts-Add-bcm2711-rpi-4-b.dts-and-components.patch

   1 From c71ece7992a28b9b58f4b5fffc688b91985bc841 Mon Sep 17 00:00:00 2001
   2 From: Phil Elwell <phil@raspberrypi.org>
   3 Date: Wed, 29 May 2019 13:54:21 +0100
   4 Subject: [PATCH 633/773] ARM: dts: Add bcm2711-rpi-4-b.dts and components
   5
   6 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
   7 ---
   8  arch/arm/boot/dts/Makefile            |   1 +
   9  arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 320 ++++++++++++
  10  arch/arm/boot/dts/bcm2711.dtsi        |  50 ++
  11  arch/arm/boot/dts/bcm2838.dtsi        | 724 ++++++++++++++++++++++++++
  12  4 files changed, 1095 insertions(+)
  13  create mode 100644 arch/arm/boot/dts/bcm2711-rpi-4-b.dts
  14  create mode 100644 arch/arm/boot/dts/bcm2711.dtsi
  15  create mode 100644 arch/arm/boot/dts/bcm2838.dtsi
  16
  17 --- a/arch/arm/boot/dts/Makefile
  18 +++ b/arch/arm/boot/dts/Makefile
  19 @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
  20         bcm2708-rpi-zero-w.dtb \
  21         bcm2709-rpi-2-b.dtb \
  22         bcm2710-rpi-3-b.dtb \
  23 +       bcm2711-rpi-4-b.dtb \
  24         bcm2710-rpi-3-b-plus.dtb \
  25         bcm2710-rpi-cm3.dtb
  26
  27 --- /dev/null
  28 +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
  29 @@ -0,0 +1,320 @@
  30 +/dts-v1/;
  31 +
  32 +#include "bcm2711.dtsi"
  33 +
  34 +/ {
  35 +       compatible = "raspberrypi,4-model-b", "brcm,bcm2838", "brcm,bcm2837";
  36 +       model = "Raspberry Pi 4 Model B";
  37 +       #address-cells = <2>;
  38 +       #size-cells = <1>;
  39 +
  40 +       memory {
  41 +               device_type = "memory";
  42 +               reg = <0x0 0x0 0x0>;
  43 +       };
  44 +
  45 +       chosen {
  46 +               bootargs = "8250.nr_uarts=1 cma=64M";
  47 +       };
  48 +
  49 +       aliases {
  50 +               serial0 = &uart1;
  51 +               serial1 = &uart0;
  52 +               mmc0 = &emmc2;
  53 +               mmc1 = &mmcnr;
  54 +               mmc2 = &sdhost;
  55 +               /delete-property/ ethernet;
  56 +               /delete-property/ intc;
  57 +               ethernet0 = &genet;
  58 +       };
  59 +};
  60 +
  61 +&soc {
  62 +       virtgpio: virtgpio {
  63 +               compatible = "brcm,bcm2835-virtgpio";
  64 +               gpio-controller;
  65 +               #gpio-cells = <2>;
  66 +               firmware = <&firmware>;
  67 +               status = "okay";
  68 +       };
  69 +};
  70 +
  71 +&mmcnr {
  72 +       pinctrl-names = "default";
  73 +       pinctrl-0 = <&sdio_pins>;
  74 +       bus-width = <4>;
  75 +       status = "okay";
  76 +};
  77 +
  78 +&firmware {
  79 +       expgpio: expgpio {
  80 +               compatible = "raspberrypi,firmware-gpio";
  81 +               gpio-controller;
  82 +               #gpio-cells = <2>;
  83 +               status = "okay";
  84 +       };
  85 +};
  86 +
  87 +&uart0 {
  88 +       pinctrl-names = "default";
  89 +       pinctrl-0 = <&uart0_pins &bt_pins>;
  90 +       status = "okay";
  91 +};
  92 +
  93 +&uart1 {
  94 +       pinctrl-names = "default";
  95 +       pinctrl-0 = <&uart1_pins>;
  96 +       status = "okay";
  97 +};
  98 +
  99 +&spi0 {
 100 +       pinctrl-names = "default";
 101 +       pinctrl-0 = <&spi0_pins &spi0_cs_pins>;
 102 +       cs-gpios = <&gpio 8 1>, <&gpio 7 1>;
 103 +
 104 +       spidev0: spidev@0{
 105 +               compatible = "spidev";
 106 +               reg = <0>;      /* CE0 */
 107 +               #address-cells = <1>;
 108 +               #size-cells = <0>;
 109 +               spi-max-frequency = <125000000>;
 110 +       };
 111 +
 112 +       spidev1: spidev@1{
 113 +               compatible = "spidev";
 114 +               reg = <1>;      /* CE1 */
 115 +               #address-cells = <1>;
 116 +               #size-cells = <0>;
 117 +               spi-max-frequency = <125000000>;
 118 +       };
 119 +};
 120 +
 121 +// =============================================
 122 +// Board specific stuff here
 123 +
 124 +/ {
 125 +
 126 +       sd_io_1v8_reg: sd_io_1v8_reg {
 127 +               status = "okay";
 128 +               compatible = "regulator-gpio";
 129 +               vin-supply = <&vdd_5v0_reg>;
 130 +               regulator-name = "vdd-sd-io";
 131 +               regulator-min-microvolt = <1800000>;
 132 +               regulator-max-microvolt = <3300000>;
 133 +               regulator-boot-on;
 134 +               regulator-always-on;
 135 +               regulator-settling-time-us = <5000>;
 136 +
 137 +               gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;
 138 +               states = <1800000 0x1
 139 +                         3300000 0x0>;
 140 +       };
 141 +};
 142 +
 143 +&sdhost {
 144 +       status = "disabled";
 145 +};
 146 +
 147 +&emmc2 {
 148 +       status = "okay";
 149 +       broken-cd;
 150 +       vqmmc-supply = <&sd_io_1v8_reg>;
 151 +};
 152 +
 153 +&leds {
 154 +       act_led: act {
 155 +               label = "led0";
 156 +               linux,default-trigger = "mmc0";
 157 +               gpios = <&gpio 42 0>;
 158 +       };
 159 +
 160 +       pwr_led: pwr {
 161 +               label = "led1";
 162 +               linux,default-trigger = "input";
 163 +               gpios = <&expgpio 2 0>;
 164 +       };
 165 +};
 166 +
 167 +&audio {
 168 +       pinctrl-names = "default";
 169 +       pinctrl-0 = <&audio_pins>;
 170 +};
 171 +
 172 +&sdhost_gpio48 {
 173 +       brcm,pins = <22 23 24 25 26 27>;
 174 +       brcm,function = <BCM2835_FSEL_ALT0>;
 175 +};
 176 +
 177 +&gpio {
 178 +       spi0_pins: spi0_pins {
 179 +               brcm,pins = <9 10 11>;
 180 +               brcm,function = <BCM2835_FSEL_ALT0>;
 181 +       };
 182 +
 183 +       spi0_cs_pins: spi0_cs_pins {
 184 +               brcm,pins = <8 7>;
 185 +               brcm,function = <BCM2835_FSEL_GPIO_OUT>;
 186 +       };
 187 +
 188 +       spi3_pins: spi3_pins {
 189 +               brcm,pins = <1 2 3>;
 190 +               brcm,function = <BCM2835_FSEL_ALT3>;
 191 +       };
 192 +
 193 +       spi3_cs_pins: spi3_cs_pins {
 194 +               brcm,pins = <0 24>;
 195 +               brcm,function = <BCM2835_FSEL_GPIO_OUT>;
 196 +       };
 197 +
 198 +       spi4_pins: spi4_pins {
 199 +               brcm,pins = <5 6 7>;
 200 +               brcm,function = <BCM2835_FSEL_ALT3>;
 201 +       };
 202 +
 203 +       spi4_cs_pins: spi4_cs_pins {
 204 +               brcm,pins = <4 25>;
 205 +               brcm,function = <BCM2835_FSEL_GPIO_OUT>;
 206 +       };
 207 +
 208 +       spi5_pins: spi5_pins {
 209 +               brcm,pins = <13 14 15>;
 210 +               brcm,function = <BCM2835_FSEL_ALT3>;
 211 +       };
 212 +
 213 +       spi5_cs_pins: spi5_cs_pins {
 214 +               brcm,pins = <12 26>;
 215 +               brcm,function = <BCM2835_FSEL_GPIO_OUT>;
 216 +       };
 217 +
 218 +       spi6_pins: spi6_pins {
 219 +               brcm,pins = <19 20 21>;
 220 +               brcm,function = <BCM2835_FSEL_ALT3>;
 221 +       };
 222 +
 223 +       spi6_cs_pins: spi6_cs_pins {
 224 +               brcm,pins = <18 27>;
 225 +               brcm,function = <BCM2835_FSEL_GPIO_OUT>;
 226 +       };
 227 +
 228 +       i2c0_pins: i2c0 {
 229 +               brcm,pins = <0 1>;
 230 +               brcm,function = <BCM2835_FSEL_ALT0>;
 231 +       };
 232 +
 233 +       i2c1_pins: i2c1 {
 234 +               brcm,pins = <2 3>;
 235 +               brcm,function = <BCM2835_FSEL_ALT0>;
 236 +       };
 237 +
 238 +       i2c3_pins: i2c3 {
 239 +               brcm,pins = <4 5>;
 240 +               brcm,function = <BCM2835_FSEL_ALT5>;
 241 +       };
 242 +
 243 +       i2c4_pins: i2c4 {
 244 +               brcm,pins = <8 9>;
 245 +               brcm,function = <BCM2835_FSEL_ALT5>;
 246 +       };
 247 +
 248 +       i2c5_pins: i2c5 {
 249 +               brcm,pins = <12 13>;
 250 +               brcm,function = <BCM2835_FSEL_ALT5>;
 251 +       };
 252 +
 253 +       i2c6_pins: i2c6 {
 254 +               brcm,pins = <22 23>;
 255 +               brcm,function = <BCM2835_FSEL_ALT5>;
 256 +       };
 257 +
 258 +       i2s_pins: i2s {
 259 +               brcm,pins = <18 19 20 21>;
 260 +               brcm,function = <BCM2835_FSEL_ALT0>;
 261 +       };
 262 +
 263 +       sdio_pins: sdio_pins {
 264 +               brcm,pins =     <34 35 36 37 38 39>;
 265 +               brcm,function = <BCM2835_FSEL_ALT3>; // alt3 = SD1
 266 +               brcm,pull =     <0 2 2 2 2 2>;
 267 +       };
 268 +
 269 +       bt_pins: bt_pins {
 270 +               brcm,pins = "-"; // non-empty to keep btuart happy, //4 = 0
 271 +                                // to fool pinctrl
 272 +               brcm,function = <0>;
 273 +               brcm,pull = <2>;
 274 +       };
 275 +
 276 +       uart0_pins: uart0_pins {
 277 +               brcm,pins = <32 33>;
 278 +               brcm,function = <BCM2835_FSEL_ALT3>;
 279 +               brcm,pull = <0 2>;
 280 +       };
 281 +
 282 +       uart1_pins: uart1_pins {
 283 +               brcm,pins;
 284 +               brcm,function;
 285 +               brcm,pull;
 286 +       };
 287 +
 288 +       uart2_pins: uart2_pins {
 289 +               brcm,pins = <0 1>;
 290 +               brcm,function = <BCM2835_FSEL_ALT4>;
 291 +               brcm,pull = <0 2>;
 292 +       };
 293 +
 294 +       uart3_pins: uart3_pins {
 295 +               brcm,pins = <4 5>;
 296 +               brcm,function = <BCM2835_FSEL_ALT4>;
 297 +               brcm,pull = <0 2>;
 298 +       };
 299 +
 300 +       uart4_pins: uart4_pins {
 301 +               brcm,pins = <8 9>;
 302 +               brcm,function = <BCM2835_FSEL_ALT4>;
 303 +               brcm,pull = <0 2>;
 304 +       };
 305 +
 306 +       uart5_pins: uart5_pins {
 307 +               brcm,pins = <12 13>;
 308 +               brcm,function = <BCM2835_FSEL_ALT4>;
 309 +               brcm,pull = <0 2>;
 310 +       };
 311 +
 312 +       audio_pins: audio_pins {
 313 +               brcm,pins = <40 41>;
 314 +               brcm,function = <4>;
 315 +       };
 316 +};
 317 +
 318 +&i2c0 {
 319 +       pinctrl-names = "default";
 320 +       pinctrl-0 = <&i2c0_pins>;
 321 +       clock-frequency = <100000>;
 322 +};
 323 +
 324 +&i2c1 {
 325 +       pinctrl-names = "default";
 326 +       pinctrl-0 = <&i2c1_pins>;
 327 +       clock-frequency = <100000>;
 328 +};
 329 +
 330 +&i2c2 {
 331 +       clock-frequency = <100000>;
 332 +};
 333 +
 334 +&i2s {
 335 +       pinctrl-names = "default";
 336 +       pinctrl-0 = <&i2s_pins>;
 337 +};
 338 +
 339 +/ {
 340 +       __overrides__ {
 341 +               act_led_gpio = <&act_led>,"gpios:4";
 342 +               act_led_activelow = <&act_led>,"gpios:8";
 343 +               act_led_trigger = <&act_led>,"linux,default-trigger";
 344 +
 345 +               pwr_led_gpio = <&pwr_led>,"gpios:4";
 346 +               pwr_led_activelow = <&pwr_led>,"gpios:8";
 347 +               pwr_led_trigger = <&pwr_led>,"linux,default-trigger";
 348 +       };
 349 +};
 350 --- /dev/null
 351 +++ b/arch/arm/boot/dts/bcm2711.dtsi
 352 @@ -0,0 +1,50 @@
 353 +#include "bcm2838.dtsi"
 354 +#include "bcm270x.dtsi"
 355 +#include "bcm2708-rpi.dtsi"
 356 +
 357 +/ {
 358 +       soc {
 359 +               /delete-node/ mailbox@7e00b840;
 360 +               /delete-node/ v3d@7ec00000;
 361 +       };
 362 +
 363 +       __overrides__ {
 364 +               arm_freq;
 365 +       };
 366 +};
 367 +
 368 +&dma {
 369 +       brcm,dma-channel-mask = <0x7ef5>;
 370 +};
 371 +
 372 +&txp {
 373 +       interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 374 +};
 375 +
 376 +&firmwarekms {
 377 +       interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 378 +};
 379 +
 380 +&smi {
 381 +       interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 382 +};
 383 +
 384 +&mmc {
 385 +       interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 386 +};
 387 +
 388 +&mmcnr {
 389 +       interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 390 +};
 391 +
 392 +&usb {
 393 +       reg = <0x7e980000 0x10000>,
 394 +             <0x7e00b200 0x200>;
 395 +       interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 396 +                    <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 397 +};
 398 +
 399 +&gpio {
 400 +       interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 401 +                    <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 402 +};
 403 --- /dev/null
 404 +++ b/arch/arm/boot/dts/bcm2838.dtsi
 405 @@ -0,0 +1,724 @@
 406 +// SPDX-License-Identifier: GPL-2.0
 407 +#include "bcm283x.dtsi"
 408 +
 409 +#include <dt-bindings/interrupt-controller/arm-gic.h>
 410 +#include <dt-bindings/soc/bcm2835-pm.h>
 411 +
 412 +/ {
 413 +       compatible = "brcm,bcm2838", "brcm,bcm2837";
 414 +
 415 +       interrupt-parent = <&gicv2>;
 416 +
 417 +       soc {
 418 +               ranges = <0x7e000000  0x0 0xfe000000  0x01800000>,
 419 +                        <0x7c000000  0x0 0xfc000000  0x02000000>,
 420 +                        <0x40000000  0x0 0xff800000  0x00800000>;
 421 +               /* Emulate a contiguous 30-bit address range for DMA */
 422 +               dma-ranges = <0xc0000000  0x0 0x00000000  0x3c000000>;
 423 +
 424 +               /delete-node/ mailbox@7e00b840;
 425 +               /delete-node/ interrupt-controller@7e00f300;
 426 +
 427 +               local_intc: local_intc@40000000 {
 428 +                       compatible = "brcm,bcm2836-l1-intc";
 429 +                       reg = <0x40000000 0x100>;
 430 +               };
 431 +
 432 +               gicv2: gic400@40041000 {
 433 +                       interrupt-controller;
 434 +                       #interrupt-cells = <3>;
 435 +                       compatible = "arm,gic-400";
 436 +                       reg =   <0x40041000 0x1000>,
 437 +                               <0x40042000 0x2000>,
 438 +                               <0x40046000 0x2000>,
 439 +                               <0x40048000 0x2000>;
 440 +               };
 441 +
 442 +               thermal: thermal@7d5d2200 {
 443 +                       compatible = "brcm,avs-tmon-bcm2838";
 444 +                       reg = <0x7d5d2200 0x2c>;
 445 +                       interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 446 +                       interrupt-names = "tmon";
 447 +                       clocks = <&clocks BCM2835_CLOCK_TSENS>;
 448 +                       #thermal-sensor-cells = <0>;
 449 +                       status = "okay";
 450 +               };
 451 +
 452 +               pm: watchdog@7e100000 {
 453 +                       reg = <0x7e100000 0x114>,
 454 +                             <0x7e00a000 0x24>,
 455 +                             <0x7ec11000 0x20>;
 456 +               };
 457 +
 458 +               rng@7e104000 {
 459 +                       interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 460 +               };
 461 +
 462 +               uart2: serial@7e201400 {
 463 +                       compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
 464 +                       reg = <0x7e201400 0x200>;
 465 +                       interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 466 +                       clocks = <&clocks BCM2835_CLOCK_UART>,
 467 +                                <&clocks BCM2835_CLOCK_VPU>;
 468 +                       clock-names = "uartclk", "apb_pclk";
 469 +                       arm,primecell-periphid = <0x00241011>;
 470 +                       status = "disabled";
 471 +               };
 472 +
 473 +               uart3: serial@7e201600 {
 474 +                       compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
 475 +                       reg = <0x7e201600 0x200>;
 476 +                       interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 477 +                       clocks = <&clocks BCM2835_CLOCK_UART>,
 478 +                                <&clocks BCM2835_CLOCK_VPU>;
 479 +                       clock-names = "uartclk", "apb_pclk";
 480 +                       arm,primecell-periphid = <0x00241011>;
 481 +                       status = "disabled";
 482 +               };
 483 +
 484 +               uart4: serial@7e201800 {
 485 +                       compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
 486 +                       reg = <0x7e201800 0x200>;
 487 +                       interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 488 +                       clocks = <&clocks BCM2835_CLOCK_UART>,
 489 +                                <&clocks BCM2835_CLOCK_VPU>;
 490 +                       clock-names = "uartclk", "apb_pclk";
 491 +                       arm,primecell-periphid = <0x00241011>;
 492 +                       status = "disabled";
 493 +               };
 494 +
 495 +               uart5: serial@7e201a00 {
 496 +                       compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
 497 +                       reg = <0x7e201a00 0x200>;
 498 +                       interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 499 +                       clocks = <&clocks BCM2835_CLOCK_UART>,
 500 +                                <&clocks BCM2835_CLOCK_VPU>;
 501 +                       clock-names = "uartclk", "apb_pclk";
 502 +                       arm,primecell-periphid = <0x00241011>;
 503 +                       status = "disabled";
 504 +               };
 505 +
 506 +               spi@7e204000 {
 507 +                       reg = <0x7e204000 0x0200>;
 508 +                       interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 509 +               };
 510 +
 511 +               spi3: spi@7e204600 {
 512 +                       compatible = "brcm,bcm2835-spi";
 513 +                       reg = <0x7e204600 0x0200>;
 514 +                       interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 515 +                       clocks = <&clocks BCM2835_CLOCK_VPU>;
 516 +                       #address-cells = <1>;
 517 +                       #size-cells = <0>;
 518 +                       status = "disabled";
 519 +               };
 520 +
 521 +               spi4: spi@7e204800 {
 522 +                       compatible = "brcm,bcm2835-spi";
 523 +                       reg = <0x7e204800 0x0200>;
 524 +                       interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 525 +                       clocks = <&clocks BCM2835_CLOCK_VPU>;
 526 +                       #address-cells = <1>;
 527 +                       #size-cells = <0>;
 528 +                       status = "disabled";
 529 +               };
 530 +
 531 +               spi5: spi@7e204a00 {
 532 +                       compatible = "brcm,bcm2835-spi";
 533 +                       reg = <0x7e204a00 0x0200>;
 534 +                       interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 535 +                       clocks = <&clocks BCM2835_CLOCK_VPU>;
 536 +                       #address-cells = <1>;
 537 +                       #size-cells = <0>;
 538 +                       status = "disabled";
 539 +               };
 540 +
 541 +               spi6: spi@7e204c00 {
 542 +                       compatible = "brcm,bcm2835-spi";
 543 +                       reg = <0x7e204c00 0x0200>;
 544 +                       interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 545 +                       clocks = <&clocks BCM2835_CLOCK_VPU>;
 546 +                       #address-cells = <1>;
 547 +                       #size-cells = <0>;
 548 +                       status = "disabled";
 549 +               };
 550 +
 551 +               i2c3: i2c@7e205600 {
 552 +                       compatible = "brcm,bcm2835-i2c";
 553 +                       reg = <0x7e205600 0x200>;
 554 +                       interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 555 +                       clocks = <&clocks BCM2835_CLOCK_VPU>;
 556 +                       #address-cells = <1>;
 557 +                       #size-cells = <0>;
 558 +                       status = "disabled";
 559 +               };
 560 +
 561 +               i2c4: i2c@7e205800 {
 562 +                       compatible = "brcm,bcm2835-i2c";
 563 +                       reg = <0x7e205800 0x200>;
 564 +                       interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 565 +                       clocks = <&clocks BCM2835_CLOCK_VPU>;
 566 +                       #address-cells = <1>;
 567 +                       #size-cells = <0>;
 568 +                       status = "disabled";
 569 +               };
 570 +
 571 +               i2c5: i2c@7e205a00 {
 572 +                       compatible = "brcm,bcm2835-i2c";
 573 +                       reg = <0x7e205a00 0x200>;
 574 +                       interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 575 +                       clocks = <&clocks BCM2835_CLOCK_VPU>;
 576 +                       #address-cells = <1>;
 577 +                       #size-cells = <0>;
 578 +                       status = "disabled";
 579 +               };
 580 +
 581 +               i2c6: i2c@7e205c00 {
 582 +                       compatible = "brcm,bcm2835-i2c";
 583 +                       reg = <0x7e205c00 0x200>;
 584 +                       interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 585 +                       clocks = <&clocks BCM2835_CLOCK_VPU>;
 586 +                       #address-cells = <1>;
 587 +                       #size-cells = <0>;
 588 +                       status = "disabled";
 589 +               };
 590 +
 591 +               pixelvalve@7e206000 {
 592 +                       interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 593 +               };
 594 +
 595 +               pixelvalve@7e207000 {
 596 +                       interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 597 +               };
 598 +
 599 +               emmc2: emmc2@7e340000 {
 600 +                       compatible = "brcm,bcm2711-emmc2";
 601 +                       status = "okay";
 602 +                       interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 603 +                       clocks = <&clocks BCM2838_CLOCK_EMMC2>;
 604 +                       reg = <0x7e340000 0x100>;
 605 +               };
 606 +
 607 +               hvs@7e400000 {
 608 +                       interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 609 +               };
 610 +
 611 +               pixelvalve@7e807000 {
 612 +                       interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 613 +               };
 614 +       };
 615 +
 616 +       arm-pmu {
 617 +               /*
 618 +                * N.B. the A72 PMU support only exists in arch/arm64, hence
 619 +                * the fallback to the A53 version.
 620 +                */
 621 +               compatible = "arm,cortex-a72-pmu", "arm,cortex-a53-pmu";
 622 +               interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 623 +                       <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 624 +                       <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 625 +                       <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 626 +       };
 627 +
 628 +       timer {
 629 +               compatible = "arm,armv7-timer";
 630 +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
 631 +                                         IRQ_TYPE_LEVEL_LOW)>,
 632 +                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
 633 +                                         IRQ_TYPE_LEVEL_LOW)>,
 634 +                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
 635 +                                         IRQ_TYPE_LEVEL_LOW)>,
 636 +                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
 637 +                                         IRQ_TYPE_LEVEL_LOW)>;
 638 +               arm,cpu-registers-not-fw-configured;
 639 +               always-on;
 640 +       };
 641 +
 642 +       cpus: cpus {
 643 +               #address-cells = <1>;
 644 +               #size-cells = <0>;
 645 +               enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
 646 +
 647 +               cpu0: cpu@0 {
 648 +                       device_type = "cpu";
 649 +                       compatible = "arm,cortex-a72";
 650 +                       reg = <0>;
 651 +                       enable-method = "spin-table";
 652 +                       cpu-release-addr = <0x0 0x000000d8>;
 653 +               };
 654 +
 655 +               cpu1: cpu@1 {
 656 +                       device_type = "cpu";
 657 +                       compatible = "arm,cortex-a72";
 658 +                       reg = <1>;
 659 +                       enable-method = "spin-table";
 660 +                       cpu-release-addr = <0x0 0x000000e0>;
 661 +               };
 662 +
 663 +               cpu2: cpu@2 {
 664 +                       device_type = "cpu";
 665 +                       compatible = "arm,cortex-a72";
 666 +                       reg = <2>;
 667 +                       enable-method = "spin-table";
 668 +                       cpu-release-addr = <0x0 0x000000e8>;
 669 +               };
 670 +
 671 +               cpu3: cpu@3 {
 672 +                       device_type = "cpu";
 673 +                       compatible = "arm,cortex-a72";
 674 +                       reg = <3>;
 675 +                       enable-method = "spin-table";
 676 +                       cpu-release-addr = <0x0 0x000000f0>;
 677 +               };
 678 +       };
 679 +
 680 +       v3dbus {
 681 +               compatible = "simple-bus";
 682 +               #address-cells = <1>;
 683 +               #size-cells = <1>;
 684 +               ranges = <0x7c500000  0x0 0xfc500000  0x03300000>,
 685 +                        <0x40000000  0x0 0xff800000  0x00800000>;
 686 +               dma-ranges = <0x00000000  0x0 0x00000000  0x3c000000>;
 687 +
 688 +               v3d: v3d@7ec04000 {
 689 +                       compatible = "brcm,2711-v3d";
 690 +                       reg =
 691 +                           <0x7ec00000 0x4000>,
 692 +                           <0x7ec04000 0x4000>;
 693 +                       reg-names = "hub", "core0";
 694 +
 695 +                       power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
 696 +                       resets = <&pm BCM2835_RESET_V3D>;
 697 +                       clocks = <&clocks BCM2835_CLOCK_V3D>;
 698 +                       interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 699 +                       status = "okay";
 700 +               };
 701 +       };
 702 +
 703 +       scb: scb {
 704 +               compatible = "simple-bus";
 705 +               #address-cells = <2>;
 706 +               #size-cells = <1>;
 707 +
 708 +               ranges = <0x0 0x7c000000  0x0 0xfc000000  0x03800000>,
 709 +                        <0x0 0x40000000  0x0 0xff800000  0x00800000>,
 710 +                        <0x6 0x00000000  0x6 0x00000000  0x40000000>,
 711 +                        <0x0 0x00000000  0x0 0x00000000  0xfc000000>;
 712 +               dma-ranges = <0x0 0x00000000  0x0 0x00000000  0xfc000000>;
 713 +
 714 +               pcie_0: pcie@7d500000 {
 715 +                       reg = <0x0 0x7d500000 0x9310>,
 716 +                             <0x0 0x7e00f300 0x20>;
 717 +                       msi-controller;
 718 +                       msi-parent = <&pcie_0>;
 719 +                       #address-cells = <3>;
 720 +                       #interrupt-cells = <1>;
 721 +                       #size-cells = <2>;
 722 +                       bus-range = <0x0 0x01>;
 723 +                       compatible = "brcm,bcm7211-pcie", "brcm,bcm7445-pcie",
 724 +                                    "brcm,pci-plat-dev";
 725 +                       max-link-speed = <2>;
 726 +                       tot-num-pcie = <1>;
 727 +                       linux,pci-domain = <0>;
 728 +                       interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 729 +                                    <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 730 +                       interrupt-names = "pcie", "msi";
 731 +                       interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 732 +                       interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
 733 +                                               IRQ_TYPE_LEVEL_HIGH
 734 +                                        0 0 0 2 &gicv2 GIC_SPI 144
 735 +                                               IRQ_TYPE_LEVEL_HIGH
 736 +                                        0 0 0 3 &gicv2 GIC_SPI 145
 737 +                                               IRQ_TYPE_LEVEL_HIGH
 738 +                                        0 0 0 4 &gicv2 GIC_SPI 146
 739 +                                               IRQ_TYPE_LEVEL_HIGH>;
 740 +
 741 +                       /* Map outbound accesses from scb:0x6_00000000-03ffffff
 742 +                        * to pci:0x0_f8000000-fbffffff
 743 +                        */
 744 +                       ranges = <0x02000000 0x0 0xf8000000  0x6 0x00000000
 745 +                                 0x0 0x04000000>;
 746 +                       /* Map inbound accesses from pci:0x0_00000000..ffffffff
 747 +                        * to scb:0x0_00000000-ffffffff
 748 +                        */
 749 +                       dma-ranges = <0x02000000 0x0 0x00000000  0x0 0x00000000
 750 +                                     0x1 0x00000000>;
 751 +                       status = "okay";
 752 +               };
 753 +
 754 +               genet: genet@7d580000 {
 755 +                       compatible = "brcm,genet-v5";
 756 +                       reg = <0x0 0x7d580000 0x10000>;
 757 +                       status = "okay";
 758 +                       #address-cells = <0x1>;
 759 +                       #size-cells = <0x1>;
 760 +                       interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 761 +                                    <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 762 +                       phy-handle = <&phy1>;
 763 +                       phy-mode = "rgmii";
 764 +                       mdio@e14 {
 765 +                               #address-cells = <0x0>;
 766 +                               #size-cells = <0x1>;
 767 +                               compatible = "brcm,genet-mdio-v5";
 768 +                               reg = <0xe14 0x8>;
 769 +                               reg-names = "mdio";
 770 +                               phy1: genet-phy@0 {
 771 +                                       compatible =
 772 +                                               "ethernet-phy-ieee802.3-c22";
 773 +                                       /* No interrupts - use PHY_POLL */
 774 +                                       max-speed = <1000>;
 775 +                                       reg = <0x1>;
 776 +                               };
 777 +                       };
 778 +               };
 779 +
 780 +               xhci: xhci@7e9c0000 {
 781 +                       compatible = "generic-xhci";
 782 +                       status = "disabled";
 783 +                       reg = <0x0 0x7e9c0000 0x100000>;
 784 +                       interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 785 +               };
 786 +
 787 +               vchiq: mailbox@7e00b840 {
 788 +                       compatible = "brcm,bcm2838-vchiq";
 789 +                       reg = <0 0x7e00b840 0x3c>;
 790 +                       interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 791 +               };
 792 +
 793 +               hevc-decoder@7eb00000 {
 794 +                       compatible = "raspberrypi,argon-hevc-decoder";
 795 +                       reg = <0x0 0x7eb00000 0x10000>;
 796 +                       status = "okay";
 797 +               };
 798 +
 799 +               argon-local-intc@7eb10000 {
 800 +                       compatible = "raspberrypi,argon-local-intc";
 801 +                       reg = <0x0 0x7eb10000 0x1000>;
 802 +                       status = "okay";
 803 +                       interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 804 +               };
 805 +
 806 +               h264-decoder@7eb20000 {
 807 +                       compatible = "raspberrypi,argon-h264-decoder";
 808 +                       reg = <0x0 0x7eb20000 0x10000>;
 809 +                       status = "okay";
 810 +               };
 811 +
 812 +               vp9-decoder@7eb30000 {
 813 +                       compatible = "raspberrypi,argon-vp9-decoder";
 814 +                       reg = <0x0 0x7eb30000 0x10000>;
 815 +                       status = "okay";
 816 +               };
 817 +       };
 818 +};
 819 +
 820 +&clk_osc {
 821 +       clock-frequency = <54000000>;
 822 +};
 823 +
 824 +&clocks {
 825 +       compatible = "brcm,bcm2838-cprman";
 826 +};
 827 +
 828 +&cpu_thermal {
 829 +       coefficients = <(-487)  410040>;
 830 +};
 831 +
 832 +&dsi0 {
 833 +       interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 834 +};
 835 +
 836 +&dsi1 {
 837 +       interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 838 +};
 839 +
 840 +&gpio {
 841 +       gpclk0_gpio49: gpclk0_gpio49 {
 842 +               brcm,pins = <49>;
 843 +               brcm,function = <BCM2835_FSEL_ALT1>;
 844 +               brcm,pull = <BCM2835_PUD_OFF>;
 845 +       };
 846 +       gpclk1_gpio50: gpclk1_gpio50 {
 847 +               brcm,pins = <50>;
 848 +               brcm,function = <BCM2835_FSEL_ALT1>;
 849 +               brcm,pull = <BCM2835_PUD_OFF>;
 850 +       };
 851 +       gpclk2_gpio51: gpclk2_gpio51 {
 852 +               brcm,pins = <51>;
 853 +               brcm,function = <BCM2835_FSEL_ALT1>;
 854 +               brcm,pull = <BCM2835_PUD_OFF>;
 855 +       };
 856 +
 857 +       i2c0_gpio46: i2c0_gpio46 {
 858 +               brcm,pins = <46 47>;
 859 +               brcm,function = <BCM2835_FSEL_ALT0>;
 860 +       };
 861 +       i2c1_gpio46: i2c1_gpio46 {
 862 +               brcm,pins = <46 47>;
 863 +               brcm,function = <BCM2835_FSEL_ALT1>;
 864 +       };
 865 +       i2c3_gpio2: i2c3_gpio2 {
 866 +               brcm,pins = <2 3>;
 867 +               brcm,function = <BCM2835_FSEL_ALT5>;
 868 +       };
 869 +       i2c3_gpio4: i2c3_gpio4 {
 870 +               brcm,pins = <4 5>;
 871 +               brcm,function = <BCM2835_FSEL_ALT5>;
 872 +       };
 873 +       i2c4_gpio6: i2c4_gpio6 {
 874 +               brcm,pins = <6 7>;
 875 +               brcm,function = <BCM2835_FSEL_ALT5>;
 876 +       };
 877 +       i2c4_gpio8: i2c4_gpio8 {
 878 +               brcm,pins = <8 9>;
 879 +               brcm,function = <BCM2835_FSEL_ALT5>;
 880 +       };
 881 +       i2c5_gpio10: i2c5_gpio10 {
 882 +               brcm,pins = <10 11>;
 883 +               brcm,function = <BCM2835_FSEL_ALT5>;
 884 +       };
 885 +       i2c5_gpio12: i2c5_gpio12 {
 886 +               brcm,pins = <12 13>;
 887 +               brcm,function = <BCM2835_FSEL_ALT5>;
 888 +       };
 889 +       i2c6_gpio0: i2c6_gpio0 {
 890 +               brcm,pins = <0 1>;
 891 +               brcm,function = <BCM2835_FSEL_ALT5>;
 892 +       };
 893 +       i2c6_gpio22: i2c6_gpio22 {
 894 +               brcm,pins = <22 23>;
 895 +               brcm,function = <BCM2835_FSEL_ALT5>;
 896 +       };
 897 +       i2c_slave_gpio8: i2c_slave_gpio8 {
 898 +               brcm,pins = <8 9 10 11>;
 899 +               brcm,function = <BCM2835_FSEL_ALT3>;
 900 +       };
 901 +
 902 +       jtag_gpio48: jtag_gpio48 {
 903 +               brcm,pins = <48 49 50 51 52 53>;
 904 +               brcm,function = <BCM2835_FSEL_ALT4>;
 905 +       };
 906 +
 907 +       mii_gpio28: mii_gpio28 {
 908 +               brcm,pins = <28 29 30 31>;
 909 +               brcm,function = <BCM2835_FSEL_ALT4>;
 910 +       };
 911 +       mii_gpio36: mii_gpio36 {
 912 +               brcm,pins = <36 37 38 39>;
 913 +               brcm,function = <BCM2835_FSEL_ALT5>;
 914 +       };
 915 +
 916 +       pcm_gpio50: pcm_gpio50 {
 917 +               brcm,pins = <50 51 52 53>;
 918 +               brcm,function = <BCM2835_FSEL_ALT2>;
 919 +       };
 920 +
 921 +       pwm0_gpio52: pwm0_gpio52 {
 922 +               brcm,pins = <52>;
 923 +               brcm,function = <BCM2835_FSEL_ALT1>;
 924 +               brcm,pull = <BCM2835_PUD_OFF>;
 925 +       };
 926 +       pwm1_gpio53: pwm1_gpio53 {
 927 +               brcm,pins = <53>;
 928 +               brcm,function = <BCM2835_FSEL_ALT1>;
 929 +               brcm,pull = <BCM2835_PUD_OFF>;
 930 +       };
 931 +
 932 +       /* The following group consists of:
 933 +         *  RGMII_START_STOP
 934 +         *  RGMII_RX_OK
 935 +         */
 936 +       rgmii_gpio35: rgmii_gpio35 {
 937 +               brcm,pins = <35 36>;
 938 +               brcm,function = <BCM2835_FSEL_ALT4>;
 939 +       };
 940 +       rgmii_irq_gpio34: rgmii_irq_gpio34 {
 941 +               brcm,pins = <34>;
 942 +               brcm,function = <BCM2835_FSEL_ALT5>;
 943 +       };
 944 +       rgmii_irq_gpio39: rgmii_irq_gpio39 {
 945 +               brcm,pins = <39>;
 946 +               brcm,function = <BCM2835_FSEL_ALT4>;
 947 +       };
 948 +       rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
 949 +               brcm,pins = <28 29>;
 950 +               brcm,function = <BCM2835_FSEL_ALT5>;
 951 +       };
 952 +       rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
 953 +               brcm,pins = <37 38>;
 954 +               brcm,function = <BCM2835_FSEL_ALT4>;
 955 +       };
 956 +
 957 +       spi0_gpio46: spi0_gpio46 {
 958 +               brcm,pins = <46 47 48 49>;
 959 +               brcm,function = <BCM2835_FSEL_ALT2>;
 960 +       };
 961 +       spi2_gpio46: spi2_gpio46 {
 962 +               brcm,pins = <46 47 48 49 50>;
 963 +               brcm,function = <BCM2835_FSEL_ALT5>;
 964 +       };
 965 +       spi3_gpio0: spi3_gpio0 {
 966 +               brcm,pins = <0 1 2 3>;
 967 +               brcm,function = <BCM2835_FSEL_ALT3>;
 968 +       };
 969 +       spi4_gpio4: spi4_gpio4 {
 970 +               brcm,pins = <4 5 6 7>;
 971 +               brcm,function = <BCM2835_FSEL_ALT3>;
 972 +       };
 973 +       spi5_gpio12: spi5_gpio12 {
 974 +               brcm,pins = <12 13 14 15>;
 975 +               brcm,function = <BCM2835_FSEL_ALT3>;
 976 +       };
 977 +       spi6_gpio18: spi6_gpio18 {
 978 +               brcm,pins = <18 19 20 21>;
 979 +               brcm,function = <BCM2835_FSEL_ALT3>;
 980 +       };
 981 +
 982 +       uart2_gpio0: uart2_gpio0 {
 983 +               brcm,pins = <0 1>;
 984 +               brcm,function = <BCM2835_FSEL_ALT4>;
 985 +               brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
 986 +       };
 987 +       uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
 988 +               brcm,pins = <2 3>;
 989 +               brcm,function = <BCM2835_FSEL_ALT4>;
 990 +               brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
 991 +       };
 992 +       uart3_gpio4: uart3_gpio4 {
 993 +               brcm,pins = <4 5>;
 994 +               brcm,function = <BCM2835_FSEL_ALT4>;
 995 +               brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
 996 +       };
 997 +       uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
 998 +               brcm,pins = <6 7>;
 999 +               brcm,function = <BCM2835_FSEL_ALT4>;
1000 +               brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
1001 +       };
1002 +       uart4_gpio8: uart4_gpio8 {
1003 +               brcm,pins = <8 9>;
1004 +               brcm,function = <BCM2835_FSEL_ALT4>;
1005 +               brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
1006 +       };
1007 +       uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
1008 +               brcm,pins = <10 11>;
1009 +               brcm,function = <BCM2835_FSEL_ALT4>;
1010 +               brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
1011 +       };
1012 +       uart5_gpio12: uart5_gpio12 {
1013 +               brcm,pins = <12 13>;
1014 +               brcm,function = <BCM2835_FSEL_ALT4>;
1015 +               brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
1016 +       };
1017 +       uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
1018 +               brcm,pins = <14 15>;
1019 +               brcm,function = <BCM2835_FSEL_ALT4>;
1020 +               brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
1021 +       };
1022 +};
1023 +
1024 +&vec {
1025 +       interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1026 +};
1027 +
1028 +&usb {
1029 +       interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1030 +};
1031 +
1032 +&hdmi {
1033 +       interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1034 +                    <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1035 +};
1036 +
1037 +&uart1 {
1038 +       interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1039 +};
1040 +
1041 +&spi1 {
1042 +       interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1043 +};
1044 +
1045 +&spi2 {
1046 +       interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1047 +};
1048 +
1049 +&csi0 {
1050 +       interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1051 +};
1052 +
1053 +&csi1 {
1054 +       interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1055 +};
1056 +
1057 +&sdhci {
1058 +       interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1059 +};
1060 +
1061 +&i2c0 {
1062 +       interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1063 +};
1064 +
1065 +&i2c1 {
1066 +       interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1067 +};
1068 +
1069 +&i2c2 {
1070 +       interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1071 +};
1072 +
1073 +&gpio {
1074 +       interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1075 +                    <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1076 +                    <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1077 +                    <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1078 +};
1079 +
1080 +&mailbox {
1081 +       interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1082 +};
1083 +
1084 +&rng {
1085 +       compatible = "brcm,bcm2838-rng200";
1086 +};
1087 +
1088 +&sdhost {
1089 +       interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1090 +};
1091 +
1092 +&uart0 {
1093 +       interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1094 +};
1095 +
1096 +&dma {
1097 +       interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
1098 +               <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1099 +               <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1100 +               <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1101 +               <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
1102 +               <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
1103 +               <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
1104 +               <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dmalite  7 */
1105 +               <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dmalite  8 */
1106 +               <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* dmalite  9 */
1107 +               <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 10 */
1108 +               /* DMA4 - 40 bit DMA engines */
1109 +               <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, /* dma4    11 */
1110 +               <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, /* dma4    12 */
1111 +               <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, /* dma4    13 */
1112 +               <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; /* dma4    14 */
1113 +       interrupt-names = "dma0",
1114 +                         "dma1",
1115 +                         "dma2",
1116 +                         "dma3",
1117 +                         "dma4",
1118 +                         "dma5",
1119 +                         "dma6",
1120 +                         "dma7",
1121 +                         "dma8",
1122 +                         "dma9",
1123 +                         "dma10",
1124 +                         "dma11",
1125 +                         "dma12",
1126 +                         "dma13",
1127 +                         "dma14";
1128 +       brcm,dma-channel-mask = <0x7ef5>;
1129 +};