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[openwrt/staging/wigyori.git] / target / linux / brcm47xx-2.6 / patches-2.6.22 / 150-cpu_fixes.patch
1 Index: linux-2.6.22-rc6/arch/mips/kernel/genex.S
2 ===================================================================
3 --- linux-2.6.22-rc6.orig/arch/mips/kernel/genex.S 2007-07-04 01:52:47.812492000 +0200
4 +++ linux-2.6.22-rc6/arch/mips/kernel/genex.S 2007-07-04 01:53:01.585352750 +0200
5 @@ -51,6 +51,10 @@
6 NESTED(except_vec3_generic, 0, sp)
7 .set push
8 .set noat
9 +#ifdef CONFIG_BCM947XX
10 + nop
11 + nop
12 +#endif
13 #if R5432_CP0_INTERRUPT_WAR
14 mfc0 k0, CP0_INDEX
15 #endif
16 Index: linux-2.6.22-rc6/arch/mips/mm/c-r4k.c
17 ===================================================================
18 --- linux-2.6.22-rc6.orig/arch/mips/mm/c-r4k.c 2007-07-04 01:53:01.545350250 +0200
19 +++ linux-2.6.22-rc6/arch/mips/mm/c-r4k.c 2007-07-04 02:17:11.435962750 +0200
20 @@ -29,6 +29,9 @@
21 #include <asm/cacheflush.h> /* for run_uncached() */
22
23
24 +/* For enabling BCM4710 cache workarounds */
25 +int bcm4710 = 0;
26 +
27 /*
28 * Special Variant of smp_call_function for use by cache functions:
29 *
30 @@ -93,6 +96,9 @@
31 {
32 unsigned long dc_lsize = cpu_dcache_line_size();
33
34 + if (bcm4710)
35 + r4k_blast_dcache_page = blast_dcache_page;
36 + else
37 if (dc_lsize == 0)
38 r4k_blast_dcache_page = (void *)cache_noop;
39 else if (dc_lsize == 16)
40 @@ -107,6 +113,9 @@
41 {
42 unsigned long dc_lsize = cpu_dcache_line_size();
43
44 + if (bcm4710)
45 + r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
46 + else
47 if (dc_lsize == 0)
48 r4k_blast_dcache_page_indexed = (void *)cache_noop;
49 else if (dc_lsize == 16)
50 @@ -121,6 +130,9 @@
51 {
52 unsigned long dc_lsize = cpu_dcache_line_size();
53
54 + if (bcm4710)
55 + r4k_blast_dcache = blast_dcache;
56 + else
57 if (dc_lsize == 0)
58 r4k_blast_dcache = (void *)cache_noop;
59 else if (dc_lsize == 16)
60 @@ -538,6 +550,9 @@
61 r4k_blast_icache();
62 else
63 protected_blast_icache_range(start, end);
64 +
65 + if (bcm4710)
66 + r4k_flush_cache_all();
67 }
68
69 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
70 @@ -618,6 +633,8 @@
71 unsigned long addr = (unsigned long) arg;
72
73 R4600_HIT_CACHEOP_WAR_IMPL;
74 + BCM4710_PROTECTED_FILL_TLB(addr);
75 + BCM4710_PROTECTED_FILL_TLB(addr + 4);
76 if (dc_lsize)
77 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
78 if (!cpu_icache_snoops_remote_store && scache_size)
79 @@ -1144,6 +1161,17 @@
80 * silly idea of putting something else there ...
81 */
82 switch (current_cpu_data.cputype) {
83 + case CPU_BCM3302:
84 + {
85 + u32 cm;
86 + cm = read_c0_diag();
87 + /* Enable icache */
88 + cm |= (1 << 31);
89 + /* Enable dcache */
90 + cm |= (1 << 30);
91 + write_c0_diag(cm);
92 + }
93 + break;
94 case CPU_R4000PC:
95 case CPU_R4000SC:
96 case CPU_R4000MC:
97 @@ -1174,6 +1202,15 @@
98 /* Default cache error handler for R4000 and R5000 family */
99 set_uncached_handler (0x100, &except_vec2_generic, 0x80);
100
101 + /* Check if special workarounds are required */
102 +#ifdef CONFIG_BCM947XX
103 + if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
104 + printk("Enabling BCM4710A0 cache workarounds.\n");
105 + bcm4710 = 1;
106 + } else
107 +#endif
108 + bcm4710 = 0;
109 +
110 probe_pcache();
111 setup_scache();
112
113 @@ -1219,5 +1256,13 @@
114 build_clear_page();
115 build_copy_page();
116 local_r4k___flush_cache_all(NULL);
117 +#ifdef CONFIG_BCM947XX
118 + {
119 + static void (*_coherency_setup)(void);
120 + _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
121 + _coherency_setup();
122 + }
123 +#else
124 coherency_setup();
125 +#endif
126 }
127 Index: linux-2.6.22-rc6/arch/mips/mm/tlbex.c
128 ===================================================================
129 --- linux-2.6.22-rc6.orig/arch/mips/mm/tlbex.c 2007-07-04 01:53:01.193328250 +0200
130 +++ linux-2.6.22-rc6/arch/mips/mm/tlbex.c 2007-07-04 02:17:26.112880000 +0200
131 @@ -1229,6 +1229,10 @@
132 #endif
133 }
134
135 +#ifdef CONFIG_BCM947XX
136 +extern int bcm4710;
137 +#endif
138 +
139 static void __init build_r4000_tlb_refill_handler(void)
140 {
141 u32 *p = tlb_handler;
142 @@ -1243,6 +1247,11 @@
143 memset(relocs, 0, sizeof(relocs));
144 memset(final_handler, 0, sizeof(final_handler));
145
146 +#ifdef CONFIG_BCM947XX
147 + if (current_cpu_data.cputype == CPU_BCM3302)
148 + i_nop(&p);
149 +#endif
150 +
151 /*
152 * create the plain linear handler
153 */
154 Index: linux-2.6.22-rc6/include/asm-mips/r4kcache.h
155 ===================================================================
156 --- linux-2.6.22-rc6.orig/include/asm-mips/r4kcache.h 2007-07-04 01:52:47.840493750 +0200
157 +++ linux-2.6.22-rc6/include/asm-mips/r4kcache.h 2007-07-04 01:53:01.673358250 +0200
158 @@ -17,6 +17,20 @@
159 #include <asm/cpu-features.h>
160 #include <asm/mipsmtregs.h>
161
162 +#ifdef CONFIG_BCM947XX
163 +#include <asm/paccess.h>
164 +#include <linux/ssb/ssb.h>
165 +#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE + SSB_IMSTATE)))
166 +
167 +#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
168 +#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
169 +#else
170 +#define BCM4710_DUMMY_RREG()
171 +
172 +#define BCM4710_FILL_TLB(addr)
173 +#define BCM4710_PROTECTED_FILL_TLB(addr)
174 +#endif
175 +
176 /*
177 * This macro return a properly sign-extended address suitable as base address
178 * for indexed cache operations. Two issues here:
179 @@ -150,6 +164,7 @@
180 static inline void flush_dcache_line_indexed(unsigned long addr)
181 {
182 __dflush_prologue
183 + BCM4710_DUMMY_RREG();
184 cache_op(Index_Writeback_Inv_D, addr);
185 __dflush_epilogue
186 }
187 @@ -169,6 +184,7 @@
188 static inline void flush_dcache_line(unsigned long addr)
189 {
190 __dflush_prologue
191 + BCM4710_DUMMY_RREG();
192 cache_op(Hit_Writeback_Inv_D, addr);
193 __dflush_epilogue
194 }
195 @@ -176,6 +192,7 @@
196 static inline void invalidate_dcache_line(unsigned long addr)
197 {
198 __dflush_prologue
199 + BCM4710_DUMMY_RREG();
200 cache_op(Hit_Invalidate_D, addr);
201 __dflush_epilogue
202 }
203 @@ -208,6 +225,7 @@
204 */
205 static inline void protected_flush_icache_line(unsigned long addr)
206 {
207 + BCM4710_DUMMY_RREG();
208 protected_cache_op(Hit_Invalidate_I, addr);
209 }
210
211 @@ -219,6 +237,7 @@
212 */
213 static inline void protected_writeback_dcache_line(unsigned long addr)
214 {
215 + BCM4710_DUMMY_RREG();
216 protected_cache_op(Hit_Writeback_Inv_D, addr);
217 }
218
219 @@ -339,8 +358,52 @@
220 : "r" (base), \
221 "i" (op));
222
223 +static inline void blast_dcache(void)
224 +{
225 + unsigned long start = KSEG0;
226 + unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
227 + unsigned long end = (start + dcache_size);
228 +
229 + do {
230 + BCM4710_DUMMY_RREG();
231 + cache_op(Index_Writeback_Inv_D, start);
232 + start += current_cpu_data.dcache.linesz;
233 + } while(start < end);
234 +}
235 +
236 +static inline void blast_dcache_page(unsigned long page)
237 +{
238 + unsigned long start = page;
239 + unsigned long end = start + PAGE_SIZE;
240 +
241 + BCM4710_FILL_TLB(start);
242 + do {
243 + BCM4710_DUMMY_RREG();
244 + cache_op(Hit_Writeback_Inv_D, start);
245 + start += current_cpu_data.dcache.linesz;
246 + } while(start < end);
247 +}
248 +
249 +static inline void blast_dcache_page_indexed(unsigned long page)
250 +{
251 + unsigned long start = page;
252 + unsigned long end = start + PAGE_SIZE;
253 + unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
254 + unsigned long ws_end = current_cpu_data.dcache.ways <<
255 + current_cpu_data.dcache.waybit;
256 + unsigned long ws, addr;
257 + for (ws = 0; ws < ws_end; ws += ws_inc) {
258 + start = page + ws;
259 + for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
260 + BCM4710_DUMMY_RREG();
261 + cache_op(Index_Writeback_Inv_D, addr);
262 + }
263 + }
264 +}
265 +
266 +
267 /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
268 -#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
269 +#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
270 static inline void blast_##pfx##cache##lsize(void) \
271 { \
272 unsigned long start = INDEX_BASE; \
273 @@ -352,6 +415,7 @@
274 \
275 __##pfx##flush_prologue \
276 \
277 + war \
278 for (ws = 0; ws < ws_end; ws += ws_inc) \
279 for (addr = start; addr < end; addr += lsize * 32) \
280 cache##lsize##_unroll32(addr|ws,indexop); \
281 @@ -366,6 +430,7 @@
282 \
283 __##pfx##flush_prologue \
284 \
285 + war \
286 do { \
287 cache##lsize##_unroll32(start,hitop); \
288 start += lsize * 32; \
289 @@ -384,6 +449,8 @@
290 current_cpu_data.desc.waybit; \
291 unsigned long ws, addr; \
292 \
293 + war \
294 + \
295 __##pfx##flush_prologue \
296 \
297 for (ws = 0; ws < ws_end; ws += ws_inc) \
298 @@ -393,28 +460,30 @@
299 __##pfx##flush_epilogue \
300 }
301
302 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
303 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
304 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
305 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
306 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
307 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
308 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
309 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
310 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
311 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
312 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
313 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
314 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
315 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
316 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
317 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
318 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
319 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
320
321 /* build blast_xxx_range, protected_blast_xxx_range */
322 -#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
323 +#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
324 static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
325 unsigned long end) \
326 { \
327 unsigned long lsize = cpu_##desc##_line_size(); \
328 unsigned long addr = start & ~(lsize - 1); \
329 unsigned long aend = (end - 1) & ~(lsize - 1); \
330 + war \
331 \
332 __##pfx##flush_prologue \
333 \
334 while (1) { \
335 + war2 \
336 prot##cache_op(hitop, addr); \
337 if (addr == aend) \
338 break; \
339 @@ -424,13 +493,13 @@
340 __##pfx##flush_epilogue \
341 }
342
343 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
344 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
345 -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
346 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
347 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
348 +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
349 +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
350 +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
351 +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
352 +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
353 /* blast_inv_dcache_range */
354 -__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
355 -__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
356 +__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
357 +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
358
359 #endif /* _ASM_R4KCACHE_H */
360 Index: linux-2.6.22-rc6/include/asm-mips/stackframe.h
361 ===================================================================
362 --- linux-2.6.22-rc6.orig/include/asm-mips/stackframe.h 2007-07-04 01:52:47.852494500 +0200
363 +++ linux-2.6.22-rc6/include/asm-mips/stackframe.h 2007-07-04 01:53:01.697359750 +0200
364 @@ -350,6 +350,10 @@
365 .macro RESTORE_SP_AND_RET
366 LONG_L sp, PT_R29(sp)
367 .set mips3
368 +#ifdef CONFIG_BCM947XX
369 + nop
370 + nop
371 +#endif
372 eret
373 .set mips0
374 .endm
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