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strip the kernel version suffix from target directories, except for brcm-2.4 (the...
[openwrt/staging/wigyori.git] / target / linux / brcm47xx / patches-2.6.22 / 120-b44_ssb_support.patch
1 Index: linux-2.6.22-rc4/drivers/net/b44.c
2 ===================================================================
3 --- linux-2.6.22-rc4.orig/drivers/net/b44.c 2007-06-10 21:32:13.000000000 +0100
4 +++ linux-2.6.22-rc4/drivers/net/b44.c 2007-06-10 21:33:15.000000000 +0100
5 @@ -1,7 +1,9 @@
6 -/* b44.c: Broadcom 4400 device driver.
7 +/* b44.c: Broadcom 4400/47xx device driver.
8 *
9 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
10 - * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
11 + * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
12 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
13 + * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
14 * Copyright (C) 2006 Broadcom Corporation.
15 *
16 * Distribute under GPL.
17 @@ -20,11 +22,13 @@
18 #include <linux/delay.h>
19 #include <linux/init.h>
20 #include <linux/dma-mapping.h>
21 +#include <linux/ssb/ssb.h>
22
23 #include <asm/uaccess.h>
24 #include <asm/io.h>
25 #include <asm/irq.h>
26
27 +
28 #include "b44.h"
29
30 #define DRV_MODULE_NAME "b44"
31 @@ -86,8 +90,8 @@
32 static char version[] __devinitdata =
33 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
34
35 -MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
36 -MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
37 +MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
38 +MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
39 MODULE_LICENSE("GPL");
40 MODULE_VERSION(DRV_MODULE_VERSION);
41
42 @@ -95,18 +99,11 @@
43 module_param(b44_debug, int, 0);
44 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
45
46 -static struct pci_device_id b44_pci_tbl[] = {
47 - { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
48 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
49 - { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0,
50 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
51 - { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
52 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
53 - { } /* terminate list with empty entry */
54 +static struct ssb_device_id b44_ssb_tbl[] = {
55 + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
56 + SSB_DEVTABLE_END
57 };
58
59 -MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
60 -
61 static void b44_halt(struct b44 *);
62 static void b44_init_rings(struct b44 *);
63
64 @@ -118,6 +115,7 @@
65
66 static int dma_desc_align_mask;
67 static int dma_desc_sync_size;
68 +static int instance;
69
70 static const char b44_gstrings[][ETH_GSTRING_LEN] = {
71 #define _B44(x...) # x,
72 @@ -125,35 +123,24 @@
73 #undef _B44
74 };
75
76 -static inline void b44_sync_dma_desc_for_device(struct pci_dev *pdev,
77 - dma_addr_t dma_base,
78 - unsigned long offset,
79 - enum dma_data_direction dir)
80 -{
81 - dma_sync_single_range_for_device(&pdev->dev, dma_base,
82 - offset & dma_desc_align_mask,
83 - dma_desc_sync_size, dir);
84 -}
85 -
86 -static inline void b44_sync_dma_desc_for_cpu(struct pci_dev *pdev,
87 - dma_addr_t dma_base,
88 - unsigned long offset,
89 - enum dma_data_direction dir)
90 -{
91 - dma_sync_single_range_for_cpu(&pdev->dev, dma_base,
92 - offset & dma_desc_align_mask,
93 - dma_desc_sync_size, dir);
94 -}
95 -
96 -static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
97 -{
98 - return readl(bp->regs + reg);
99 -}
100 -
101 -static inline void bw32(const struct b44 *bp,
102 - unsigned long reg, unsigned long val)
103 -{
104 - writel(val, bp->regs + reg);
105 +static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
106 + dma_addr_t dma_base,
107 + unsigned long offset,
108 + enum dma_data_direction dir)
109 +{
110 + dma_sync_single_range_for_device(&sdev->dev, dma_base,
111 + offset & dma_desc_align_mask,
112 + dma_desc_sync_size, dir);
113 +}
114 +
115 +static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
116 + dma_addr_t dma_base,
117 + unsigned long offset,
118 + enum dma_data_direction dir)
119 +{
120 + dma_sync_single_range_for_cpu(&sdev->dev, dma_base,
121 + offset & dma_desc_align_mask,
122 + dma_desc_sync_size, dir);
123 }
124
125 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
126 @@ -181,117 +168,29 @@
127 return 0;
128 }
129
130 -/* Sonics SiliconBackplane support routines. ROFL, you should see all the
131 - * buzz words used on this company's website :-)
132 - *
133 - * All of these routines must be invoked with bp->lock held and
134 - * interrupts disabled.
135 - */
136 -
137 -#define SB_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
138 -#define BCM4400_PCI_CORE_ADDR 0x18002000 /* Address of PCI core on BCM4400 cards */
139 -
140 -static u32 ssb_get_core_rev(struct b44 *bp)
141 -{
142 - return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
143 -}
144 -
145 -static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
146 -{
147 - u32 bar_orig, pci_rev, val;
148 -
149 - pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
150 - pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
151 - pci_rev = ssb_get_core_rev(bp);
152 -
153 - val = br32(bp, B44_SBINTVEC);
154 - val |= cores;
155 - bw32(bp, B44_SBINTVEC, val);
156 -
157 - val = br32(bp, SSB_PCI_TRANS_2);
158 - val |= SSB_PCI_PREF | SSB_PCI_BURST;
159 - bw32(bp, SSB_PCI_TRANS_2, val);
160 -
161 - pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
162 -
163 - return pci_rev;
164 -}
165 -
166 -static void ssb_core_disable(struct b44 *bp)
167 -{
168 - if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
169 - return;
170 -
171 - bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
172 - b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
173 - b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
174 - bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
175 - SBTMSLOW_REJECT | SBTMSLOW_RESET));
176 - br32(bp, B44_SBTMSLOW);
177 - udelay(1);
178 - bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
179 - br32(bp, B44_SBTMSLOW);
180 - udelay(1);
181 -}
182 -
183 -static void ssb_core_reset(struct b44 *bp)
184 +static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
185 {
186 u32 val;
187
188 - ssb_core_disable(bp);
189 - bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
190 - br32(bp, B44_SBTMSLOW);
191 - udelay(1);
192 -
193 - /* Clear SERR if set, this is a hw bug workaround. */
194 - if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
195 - bw32(bp, B44_SBTMSHIGH, 0);
196 -
197 - val = br32(bp, B44_SBIMSTATE);
198 - if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
199 - bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
200 -
201 - bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
202 - br32(bp, B44_SBTMSLOW);
203 - udelay(1);
204 + bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
205 + (index << CAM_CTRL_INDEX_SHIFT)));
206
207 - bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
208 - br32(bp, B44_SBTMSLOW);
209 - udelay(1);
210 -}
211 + b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
212
213 -static int ssb_core_unit(struct b44 *bp)
214 -{
215 -#if 0
216 - u32 val = br32(bp, B44_SBADMATCH0);
217 - u32 base;
218 + val = br32(bp, B44_CAM_DATA_LO);
219
220 - type = val & SBADMATCH0_TYPE_MASK;
221 - switch (type) {
222 - case 0:
223 - base = val & SBADMATCH0_BS0_MASK;
224 - break;
225 + data[2] = (val >> 24) & 0xFF;
226 + data[3] = (val >> 16) & 0xFF;
227 + data[4] = (val >> 8) & 0xFF;
228 + data[5] = (val >> 0) & 0xFF;
229
230 - case 1:
231 - base = val & SBADMATCH0_BS1_MASK;
232 - break;
233 + val = br32(bp, B44_CAM_DATA_HI);
234
235 - case 2:
236 - default:
237 - base = val & SBADMATCH0_BS2_MASK;
238 - break;
239 - };
240 -#endif
241 - return 0;
242 -}
243 -
244 -static int ssb_is_core_up(struct b44 *bp)
245 -{
246 - return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
247 - == SBTMSLOW_CLOCK);
248 + data[0] = (val >> 8) & 0xFF;
249 + data[1] = (val >> 0) & 0xFF;
250 }
251
252 -static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
253 +static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
254 {
255 u32 val;
256
257 @@ -327,14 +226,14 @@
258 bw32(bp, B44_IMASK, bp->imask);
259 }
260
261 -static int b44_readphy(struct b44 *bp, int reg, u32 *val)
262 +static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
263 {
264 int err;
265
266 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
267 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
268 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
269 - (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
270 + (phy_addr << MDIO_DATA_PMD_SHIFT) |
271 (reg << MDIO_DATA_RA_SHIFT) |
272 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
273 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
274 @@ -343,18 +242,34 @@
275 return err;
276 }
277
278 -static int b44_writephy(struct b44 *bp, int reg, u32 val)
279 +static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
280 {
281 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
282 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
283 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
284 - (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
285 + (phy_addr << MDIO_DATA_PMD_SHIFT) |
286 (reg << MDIO_DATA_RA_SHIFT) |
287 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
288 (val & MDIO_DATA_DATA)));
289 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
290 }
291
292 +static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
293 +{
294 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
295 + return 0;
296 +
297 + return __b44_readphy(bp, bp->phy_addr, reg, val);
298 +}
299 +
300 +static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
301 +{
302 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
303 + return 0;
304 +
305 + return __b44_writephy(bp, bp->phy_addr, reg, val);
306 +}
307 +
308 /* miilib interface */
309 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
310 * due to code existing before miilib use was added to this driver.
311 @@ -383,6 +298,8 @@
312 u32 val;
313 int err;
314
315 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
316 + return 0;
317 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
318 if (err)
319 return err;
320 @@ -441,11 +358,27 @@
321 __b44_set_flow_ctrl(bp, pause_enab);
322 }
323
324 +
325 +extern char *nvram_get(char *name); //FIXME: move elsewhere
326 static int b44_setup_phy(struct b44 *bp)
327 {
328 u32 val;
329 int err;
330
331 + /*
332 + * workaround for bad hardware design in Linksys WAP54G v1.0
333 + * see https://dev.openwrt.org/ticket/146
334 + * check and reset bit "isolate"
335 + */
336 + if ((atoi(nvram_get("boardnum")) == 2) &&
337 + (__b44_readphy(bp, 0, MII_BMCR, &val) == 0) &&
338 + (val & BMCR_ISOLATE) &&
339 + (__b44_writephy(bp, 0, MII_BMCR, val & ~BMCR_ISOLATE) != 0)) {
340 + printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
341 + }
342 +
343 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
344 + return 0;
345 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
346 goto out;
347 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
348 @@ -541,6 +474,19 @@
349 {
350 u32 bmsr, aux;
351
352 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
353 + bp->flags |= B44_FLAG_100_BASE_T;
354 + bp->flags |= B44_FLAG_FULL_DUPLEX;
355 + if (!netif_carrier_ok(bp->dev)) {
356 + u32 val = br32(bp, B44_TX_CTRL);
357 + val |= TX_CTRL_DUPLEX;
358 + bw32(bp, B44_TX_CTRL, val);
359 + netif_carrier_on(bp->dev);
360 + b44_link_report(bp);
361 + }
362 + return;
363 + }
364 +
365 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
366 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
367 (bmsr != 0xffff)) {
368 @@ -617,10 +563,10 @@
369
370 BUG_ON(skb == NULL);
371
372 - pci_unmap_single(bp->pdev,
373 + dma_unmap_single(&bp->sdev->dev,
374 pci_unmap_addr(rp, mapping),
375 skb->len,
376 - PCI_DMA_TODEVICE);
377 + DMA_TO_DEVICE);
378 rp->skb = NULL;
379 dev_kfree_skb_irq(skb);
380 }
381 @@ -656,10 +602,10 @@
382 skb = dev_alloc_skb(RX_PKT_BUF_SZ);
383 if (skb == NULL)
384 return -ENOMEM;
385 -
386 - mapping = pci_map_single(bp->pdev, skb->data,
387 +
388 + mapping = dma_map_single(&bp->sdev->dev, skb->data,
389 RX_PKT_BUF_SZ,
390 - PCI_DMA_FROMDEVICE);
391 + DMA_FROM_DEVICE);
392
393 /* Hardware bug work-around, the chip is unable to do PCI DMA
394 to/from anything above 1GB :-( */
395 @@ -667,18 +613,18 @@
396 mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
397 /* Sigh... */
398 if (!dma_mapping_error(mapping))
399 - pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
400 + dma_unmap_single(&bp->sdev->dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
401 dev_kfree_skb_any(skb);
402 skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA);
403 if (skb == NULL)
404 return -ENOMEM;
405 - mapping = pci_map_single(bp->pdev, skb->data,
406 + mapping = dma_map_single(&bp->sdev->dev, skb->data,
407 RX_PKT_BUF_SZ,
408 - PCI_DMA_FROMDEVICE);
409 + DMA_FROM_DEVICE);
410 if (dma_mapping_error(mapping) ||
411 mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
412 if (!dma_mapping_error(mapping))
413 - pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
414 + dma_unmap_single(&bp->sdev->dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
415 dev_kfree_skb_any(skb);
416 return -ENOMEM;
417 }
418 @@ -707,9 +653,9 @@
419 dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
420
421 if (bp->flags & B44_FLAG_RX_RING_HACK)
422 - b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
423 - dest_idx * sizeof(dp),
424 - DMA_BIDIRECTIONAL);
425 + b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
426 + dest_idx * sizeof(dp),
427 + DMA_BIDIRECTIONAL);
428
429 return RX_PKT_BUF_SZ;
430 }
431 @@ -736,9 +682,9 @@
432 pci_unmap_addr(src_map, mapping));
433
434 if (bp->flags & B44_FLAG_RX_RING_HACK)
435 - b44_sync_dma_desc_for_cpu(bp->pdev, bp->rx_ring_dma,
436 - src_idx * sizeof(src_desc),
437 - DMA_BIDIRECTIONAL);
438 + b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
439 + src_idx * sizeof(src_desc),
440 + DMA_BIDIRECTIONAL);
441
442 ctrl = src_desc->ctrl;
443 if (dest_idx == (B44_RX_RING_SIZE - 1))
444 @@ -752,13 +698,13 @@
445 src_map->skb = NULL;
446
447 if (bp->flags & B44_FLAG_RX_RING_HACK)
448 - b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
449 - dest_idx * sizeof(dest_desc),
450 - DMA_BIDIRECTIONAL);
451 + b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
452 + dest_idx * sizeof(dest_desc),
453 + DMA_BIDIRECTIONAL);
454
455 - pci_dma_sync_single_for_device(bp->pdev, le32_to_cpu(src_desc->addr),
456 + dma_sync_single_for_device(&bp->sdev->dev, le32_to_cpu(src_desc->addr),
457 RX_PKT_BUF_SZ,
458 - PCI_DMA_FROMDEVICE);
459 + DMA_FROM_DEVICE);
460 }
461
462 static int b44_rx(struct b44 *bp, int budget)
463 @@ -778,9 +724,9 @@
464 struct rx_header *rh;
465 u16 len;
466
467 - pci_dma_sync_single_for_cpu(bp->pdev, map,
468 + dma_sync_single_for_cpu(&bp->sdev->dev, map,
469 RX_PKT_BUF_SZ,
470 - PCI_DMA_FROMDEVICE);
471 + DMA_FROM_DEVICE);
472 rh = (struct rx_header *) skb->data;
473 len = le16_to_cpu(rh->len);
474 if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
475 @@ -812,11 +758,11 @@
476 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
477 if (skb_size < 0)
478 goto drop_it;
479 - pci_unmap_single(bp->pdev, map,
480 - skb_size, PCI_DMA_FROMDEVICE);
481 + dma_unmap_single(&bp->sdev->dev, map,
482 + skb_size, DMA_FROM_DEVICE);
483 /* Leave out rx_header */
484 - skb_put(skb, len+bp->rx_offset);
485 - skb_pull(skb,bp->rx_offset);
486 + skb_put(skb, len+bp->rx_offset);
487 + skb_pull(skb,bp->rx_offset);
488 } else {
489 struct sk_buff *copy_skb;
490
491 @@ -985,23 +931,23 @@
492 goto err_out;
493 }
494
495 - mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
496 + mapping = dma_map_single(&bp->sdev->dev, skb->data, len, DMA_TO_DEVICE);
497 if (dma_mapping_error(mapping) || mapping + len > DMA_30BIT_MASK) {
498 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
499 if (!dma_mapping_error(mapping))
500 - pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE);
501 + dma_unmap_single(&bp->sdev->dev, mapping, len, DMA_TO_DEVICE);
502
503 bounce_skb = __dev_alloc_skb(TX_PKT_BUF_SZ,
504 GFP_ATOMIC|GFP_DMA);
505 if (!bounce_skb)
506 goto err_out;
507
508 - mapping = pci_map_single(bp->pdev, bounce_skb->data,
509 - len, PCI_DMA_TODEVICE);
510 + mapping = dma_map_single(&bp->sdev->dev, bounce_skb->data,
511 + len, DMA_TO_DEVICE);
512 if (dma_mapping_error(mapping) || mapping + len > DMA_30BIT_MASK) {
513 if (!dma_mapping_error(mapping))
514 - pci_unmap_single(bp->pdev, mapping,
515 - len, PCI_DMA_TODEVICE);
516 + dma_unmap_single(&bp->sdev->dev, mapping,
517 + len, DMA_TO_DEVICE);
518 dev_kfree_skb_any(bounce_skb);
519 goto err_out;
520 }
521 @@ -1025,9 +971,9 @@
522 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
523
524 if (bp->flags & B44_FLAG_TX_RING_HACK)
525 - b44_sync_dma_desc_for_device(bp->pdev, bp->tx_ring_dma,
526 - entry * sizeof(bp->tx_ring[0]),
527 - DMA_TO_DEVICE);
528 + b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
529 + entry * sizeof(bp->tx_ring[0]),
530 + DMA_TO_DEVICE);
531
532 entry = NEXT_TX(entry);
533
534 @@ -1100,10 +1046,10 @@
535
536 if (rp->skb == NULL)
537 continue;
538 - pci_unmap_single(bp->pdev,
539 + dma_unmap_single(&bp->sdev->dev,
540 pci_unmap_addr(rp, mapping),
541 RX_PKT_BUF_SZ,
542 - PCI_DMA_FROMDEVICE);
543 + DMA_FROM_DEVICE);
544 dev_kfree_skb_any(rp->skb);
545 rp->skb = NULL;
546 }
547 @@ -1114,10 +1060,10 @@
548
549 if (rp->skb == NULL)
550 continue;
551 - pci_unmap_single(bp->pdev,
552 + dma_unmap_single(&bp->sdev->dev,
553 pci_unmap_addr(rp, mapping),
554 rp->skb->len,
555 - PCI_DMA_TODEVICE);
556 + DMA_TO_DEVICE);
557 dev_kfree_skb_any(rp->skb);
558 rp->skb = NULL;
559 }
560 @@ -1139,14 +1085,14 @@
561 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
562
563 if (bp->flags & B44_FLAG_RX_RING_HACK)
564 - dma_sync_single_for_device(&bp->pdev->dev, bp->rx_ring_dma,
565 - DMA_TABLE_BYTES,
566 - PCI_DMA_BIDIRECTIONAL);
567 + dma_sync_single_for_device(&bp->sdev->dev, bp->rx_ring_dma,
568 + DMA_TABLE_BYTES,
569 + DMA_BIDIRECTIONAL);
570
571 if (bp->flags & B44_FLAG_TX_RING_HACK)
572 - dma_sync_single_for_device(&bp->pdev->dev, bp->tx_ring_dma,
573 - DMA_TABLE_BYTES,
574 - PCI_DMA_TODEVICE);
575 + dma_sync_single_for_device(&bp->sdev->dev, bp->tx_ring_dma,
576 + DMA_TABLE_BYTES,
577 + DMA_TO_DEVICE);
578
579 for (i = 0; i < bp->rx_pending; i++) {
580 if (b44_alloc_rx_skb(bp, -1, i) < 0)
581 @@ -1166,24 +1112,24 @@
582 bp->tx_buffers = NULL;
583 if (bp->rx_ring) {
584 if (bp->flags & B44_FLAG_RX_RING_HACK) {
585 - dma_unmap_single(&bp->pdev->dev, bp->rx_ring_dma,
586 - DMA_TABLE_BYTES,
587 - DMA_BIDIRECTIONAL);
588 + dma_unmap_single(&bp->sdev->dev, bp->rx_ring_dma,
589 + DMA_TABLE_BYTES,
590 + DMA_BIDIRECTIONAL);
591 kfree(bp->rx_ring);
592 } else
593 - pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
594 + dma_free_coherent(&bp->sdev->dev, DMA_TABLE_BYTES,
595 bp->rx_ring, bp->rx_ring_dma);
596 bp->rx_ring = NULL;
597 bp->flags &= ~B44_FLAG_RX_RING_HACK;
598 }
599 if (bp->tx_ring) {
600 if (bp->flags & B44_FLAG_TX_RING_HACK) {
601 - dma_unmap_single(&bp->pdev->dev, bp->tx_ring_dma,
602 - DMA_TABLE_BYTES,
603 - DMA_TO_DEVICE);
604 + dma_unmap_single(&bp->sdev->dev, bp->tx_ring_dma,
605 + DMA_TABLE_BYTES,
606 + DMA_TO_DEVICE);
607 kfree(bp->tx_ring);
608 } else
609 - pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
610 + dma_free_coherent(&bp->sdev->dev, DMA_TABLE_BYTES,
611 bp->tx_ring, bp->tx_ring_dma);
612 bp->tx_ring = NULL;
613 bp->flags &= ~B44_FLAG_TX_RING_HACK;
614 @@ -1209,7 +1155,7 @@
615 goto out_err;
616
617 size = DMA_TABLE_BYTES;
618 - bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
619 + bp->rx_ring = dma_alloc_coherent(&bp->sdev->dev, size, &bp->rx_ring_dma, GFP_ATOMIC);
620 if (!bp->rx_ring) {
621 /* Allocation may have failed due to pci_alloc_consistent
622 insisting on use of GFP_DMA, which is more restrictive
623 @@ -1221,9 +1167,9 @@
624 if (!rx_ring)
625 goto out_err;
626
627 - rx_ring_dma = dma_map_single(&bp->pdev->dev, rx_ring,
628 - DMA_TABLE_BYTES,
629 - DMA_BIDIRECTIONAL);
630 + rx_ring_dma = dma_map_single(&bp->sdev->dev, rx_ring,
631 + DMA_TABLE_BYTES,
632 + DMA_BIDIRECTIONAL);
633
634 if (dma_mapping_error(rx_ring_dma) ||
635 rx_ring_dma + size > DMA_30BIT_MASK) {
636 @@ -1236,9 +1182,9 @@
637 bp->flags |= B44_FLAG_RX_RING_HACK;
638 }
639
640 - bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
641 + bp->tx_ring = dma_alloc_coherent(&bp->sdev->dev, size, &bp->tx_ring_dma, GFP_ATOMIC);
642 if (!bp->tx_ring) {
643 - /* Allocation may have failed due to pci_alloc_consistent
644 + /* Allocation may have failed due to dma_alloc_coherent
645 insisting on use of GFP_DMA, which is more restrictive
646 than necessary... */
647 struct dma_desc *tx_ring;
648 @@ -1248,9 +1194,9 @@
649 if (!tx_ring)
650 goto out_err;
651
652 - tx_ring_dma = dma_map_single(&bp->pdev->dev, tx_ring,
653 - DMA_TABLE_BYTES,
654 - DMA_TO_DEVICE);
655 + tx_ring_dma = dma_map_single(&bp->sdev->dev, tx_ring,
656 + DMA_TABLE_BYTES,
657 + DMA_TO_DEVICE);
658
659 if (dma_mapping_error(tx_ring_dma) ||
660 tx_ring_dma + size > DMA_30BIT_MASK) {
661 @@ -1285,7 +1231,9 @@
662 /* bp->lock is held. */
663 static void b44_chip_reset(struct b44 *bp)
664 {
665 - if (ssb_is_core_up(bp)) {
666 + struct ssb_device *sdev = bp->sdev;
667 +
668 + if (ssb_device_is_enabled(bp->sdev)) {
669 bw32(bp, B44_RCV_LAZY, 0);
670 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
671 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
672 @@ -1297,19 +1245,23 @@
673 }
674 bw32(bp, B44_DMARX_CTRL, 0);
675 bp->rx_prod = bp->rx_cons = 0;
676 - } else {
677 - ssb_pci_setup(bp, (bp->core_unit == 0 ?
678 - SBINTVEC_ENET0 :
679 - SBINTVEC_ENET1));
680 }
681
682 - ssb_core_reset(bp);
683 -
684 + ssb_device_enable(bp->sdev, 0);
685 b44_clear_stats(bp);
686
687 - /* Make PHY accessible. */
688 - bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
689 + switch (sdev->bus->bustype) {
690 + case SSB_BUSTYPE_SSB:
691 + bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
692 + (((ssb_clockspeed(sdev->bus) + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
693 + & MDIO_CTRL_MAXF_MASK)));
694 + break;
695 + case SSB_BUSTYPE_PCI:
696 + bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
697 (0x0d & MDIO_CTRL_MAXF_MASK)));
698 + break;
699 + }
700 +
701 br32(bp, B44_MDIO_CTRL);
702
703 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
704 @@ -1352,6 +1304,7 @@
705 {
706 struct b44 *bp = netdev_priv(dev);
707 struct sockaddr *addr = p;
708 + u32 val;
709
710 if (netif_running(dev))
711 return -EBUSY;
712 @@ -1362,7 +1315,11 @@
713 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
714
715 spin_lock_irq(&bp->lock);
716 - __b44_set_mac_addr(bp);
717 +
718 + val = br32(bp, B44_RXCONFIG);
719 + if (!(val & RXCONFIG_CAM_ABSENT))
720 + __b44_set_mac_addr(bp);
721 +
722 spin_unlock_irq(&bp->lock);
723
724 return 0;
725 @@ -1448,18 +1405,6 @@
726 return err;
727 }
728
729 -#if 0
730 -/*static*/ void b44_dump_state(struct b44 *bp)
731 -{
732 - u32 val32, val32_2, val32_3, val32_4, val32_5;
733 - u16 val16;
734 -
735 - pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
736 - printk("DEBUG: PCI status [%04x] \n", val16);
737 -
738 -}
739 -#endif
740 -
741 #ifdef CONFIG_NET_POLL_CONTROLLER
742 /*
743 * Polling receive - used by netconsole and other diagnostic tools
744 @@ -1574,7 +1519,6 @@
745 static void b44_setup_wol(struct b44 *bp)
746 {
747 u32 val;
748 - u16 pmval;
749
750 bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
751
752 @@ -1598,13 +1542,6 @@
753 } else {
754 b44_setup_pseudo_magicp(bp);
755 }
756 -
757 - val = br32(bp, B44_SBTMSLOW);
758 - bw32(bp, B44_SBTMSLOW, val | SBTMSLOW_PE);
759 -
760 - pci_read_config_word(bp->pdev, SSB_PMCSR, &pmval);
761 - pci_write_config_word(bp->pdev, SSB_PMCSR, pmval | SSB_PE);
762 -
763 }
764
765 static int b44_close(struct net_device *dev)
766 @@ -1704,7 +1641,7 @@
767
768 val = br32(bp, B44_RXCONFIG);
769 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
770 - if (dev->flags & IFF_PROMISC) {
771 + if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
772 val |= RXCONFIG_PROMISC;
773 bw32(bp, B44_RXCONFIG, val);
774 } else {
775 @@ -1751,12 +1688,8 @@
776
777 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
778 {
779 - struct b44 *bp = netdev_priv(dev);
780 - struct pci_dev *pci_dev = bp->pdev;
781 -
782 strcpy (info->driver, DRV_MODULE_NAME);
783 strcpy (info->version, DRV_MODULE_VERSION);
784 - strcpy (info->bus_info, pci_name(pci_dev));
785 }
786
787 static int b44_nway_reset(struct net_device *dev)
788 @@ -2040,6 +1973,245 @@
789 .get_perm_addr = ethtool_op_get_perm_addr,
790 };
791
792 +static int b44_ethtool_ioctl (struct net_device *dev, void __user *useraddr)
793 +{
794 + struct b44 *bp = dev->priv;
795 + u32 ethcmd;
796 +
797 + if (copy_from_user (&ethcmd, useraddr, sizeof (ethcmd)))
798 + return -EFAULT;
799 +
800 + switch (ethcmd) {
801 + case ETHTOOL_GDRVINFO: {
802 + struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
803 + strcpy (info.driver, DRV_MODULE_NAME);
804 + strcpy (info.version, DRV_MODULE_VERSION);
805 + memset(&info.fw_version, 0, sizeof(info.fw_version));
806 + info.eedump_len = 0;
807 + info.regdump_len = 0;
808 + if (copy_to_user (useraddr, &info, sizeof (info)))
809 + return -EFAULT;
810 + return 0;
811 + }
812 +
813 + case ETHTOOL_GSET: {
814 + struct ethtool_cmd cmd = { ETHTOOL_GSET };
815 +
816 + if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
817 + return -EAGAIN;
818 + cmd.supported = (SUPPORTED_Autoneg);
819 + cmd.supported |= (SUPPORTED_100baseT_Half |
820 + SUPPORTED_100baseT_Full |
821 + SUPPORTED_10baseT_Half |
822 + SUPPORTED_10baseT_Full |
823 + SUPPORTED_MII);
824 +
825 + cmd.advertising = 0;
826 + if (bp->flags & B44_FLAG_ADV_10HALF)
827 + cmd.advertising |= ADVERTISE_10HALF;
828 + if (bp->flags & B44_FLAG_ADV_10FULL)
829 + cmd.advertising |= ADVERTISE_10FULL;
830 + if (bp->flags & B44_FLAG_ADV_100HALF)
831 + cmd.advertising |= ADVERTISE_100HALF;
832 + if (bp->flags & B44_FLAG_ADV_100FULL)
833 + cmd.advertising |= ADVERTISE_100FULL;
834 + cmd.advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
835 + cmd.speed = (bp->flags & B44_FLAG_100_BASE_T) ?
836 + SPEED_100 : SPEED_10;
837 + cmd.duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
838 + DUPLEX_FULL : DUPLEX_HALF;
839 + cmd.port = 0;
840 + cmd.phy_address = bp->phy_addr;
841 + cmd.transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
842 + XCVR_INTERNAL : XCVR_EXTERNAL;
843 + cmd.autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
844 + AUTONEG_DISABLE : AUTONEG_ENABLE;
845 + cmd.maxtxpkt = 0;
846 + cmd.maxrxpkt = 0;
847 + if (copy_to_user(useraddr, &cmd, sizeof(cmd)))
848 + return -EFAULT;
849 + return 0;
850 + }
851 + case ETHTOOL_SSET: {
852 + struct ethtool_cmd cmd;
853 +
854 + if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
855 + return -EAGAIN;
856 +
857 + if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
858 + return -EFAULT;
859 +
860 + /* We do not support gigabit. */
861 + if (cmd.autoneg == AUTONEG_ENABLE) {
862 + if (cmd.advertising &
863 + (ADVERTISED_1000baseT_Half |
864 + ADVERTISED_1000baseT_Full))
865 + return -EINVAL;
866 + } else if ((cmd.speed != SPEED_100 &&
867 + cmd.speed != SPEED_10) ||
868 + (cmd.duplex != DUPLEX_HALF &&
869 + cmd.duplex != DUPLEX_FULL)) {
870 + return -EINVAL;
871 + }
872 +
873 + spin_lock_irq(&bp->lock);
874 +
875 + if (cmd.autoneg == AUTONEG_ENABLE) {
876 + bp->flags &= ~B44_FLAG_FORCE_LINK;
877 + bp->flags &= ~(B44_FLAG_ADV_10HALF |
878 + B44_FLAG_ADV_10FULL |
879 + B44_FLAG_ADV_100HALF |
880 + B44_FLAG_ADV_100FULL);
881 + if (cmd.advertising & ADVERTISE_10HALF)
882 + bp->flags |= B44_FLAG_ADV_10HALF;
883 + if (cmd.advertising & ADVERTISE_10FULL)
884 + bp->flags |= B44_FLAG_ADV_10FULL;
885 + if (cmd.advertising & ADVERTISE_100HALF)
886 + bp->flags |= B44_FLAG_ADV_100HALF;
887 + if (cmd.advertising & ADVERTISE_100FULL)
888 + bp->flags |= B44_FLAG_ADV_100FULL;
889 + } else {
890 + bp->flags |= B44_FLAG_FORCE_LINK;
891 + if (cmd.speed == SPEED_100)
892 + bp->flags |= B44_FLAG_100_BASE_T;
893 + if (cmd.duplex == DUPLEX_FULL)
894 + bp->flags |= B44_FLAG_FULL_DUPLEX;
895 + }
896 +
897 + b44_setup_phy(bp);
898 +
899 + spin_unlock_irq(&bp->lock);
900 +
901 + return 0;
902 + }
903 +
904 + case ETHTOOL_GMSGLVL: {
905 + struct ethtool_value edata = { ETHTOOL_GMSGLVL };
906 + edata.data = bp->msg_enable;
907 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
908 + return -EFAULT;
909 + return 0;
910 + }
911 + case ETHTOOL_SMSGLVL: {
912 + struct ethtool_value edata;
913 + if (copy_from_user(&edata, useraddr, sizeof(edata)))
914 + return -EFAULT;
915 + bp->msg_enable = edata.data;
916 + return 0;
917 + }
918 + case ETHTOOL_NWAY_RST: {
919 + u32 bmcr;
920 + int r;
921 +
922 + spin_lock_irq(&bp->lock);
923 + b44_readphy(bp, MII_BMCR, &bmcr);
924 + b44_readphy(bp, MII_BMCR, &bmcr);
925 + r = -EINVAL;
926 + if (bmcr & BMCR_ANENABLE) {
927 + b44_writephy(bp, MII_BMCR,
928 + bmcr | BMCR_ANRESTART);
929 + r = 0;
930 + }
931 + spin_unlock_irq(&bp->lock);
932 +
933 + return r;
934 + }
935 + case ETHTOOL_GLINK: {
936 + struct ethtool_value edata = { ETHTOOL_GLINK };
937 + edata.data = netif_carrier_ok(bp->dev) ? 1 : 0;
938 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
939 + return -EFAULT;
940 + return 0;
941 + }
942 + case ETHTOOL_GRINGPARAM: {
943 + struct ethtool_ringparam ering = { ETHTOOL_GRINGPARAM };
944 +
945 + ering.rx_max_pending = B44_RX_RING_SIZE - 1;
946 + ering.rx_pending = bp->rx_pending;
947 +
948 + /* XXX ethtool lacks a tx_max_pending, oops... */
949 +
950 + if (copy_to_user(useraddr, &ering, sizeof(ering)))
951 + return -EFAULT;
952 + return 0;
953 + }
954 + case ETHTOOL_SRINGPARAM: {
955 + struct ethtool_ringparam ering;
956 +
957 + if (copy_from_user(&ering, useraddr, sizeof(ering)))
958 + return -EFAULT;
959 +
960 + if ((ering.rx_pending > B44_RX_RING_SIZE - 1) ||
961 + (ering.rx_mini_pending != 0) ||
962 + (ering.rx_jumbo_pending != 0) ||
963 + (ering.tx_pending > B44_TX_RING_SIZE - 1))
964 + return -EINVAL;
965 +
966 + spin_lock_irq(&bp->lock);
967 +
968 + bp->rx_pending = ering.rx_pending;
969 + bp->tx_pending = ering.tx_pending;
970 +
971 + b44_halt(bp);
972 + b44_init_rings(bp);
973 + b44_init_hw(bp, 1);
974 + netif_wake_queue(bp->dev);
975 + spin_unlock_irq(&bp->lock);
976 +
977 + b44_enable_ints(bp);
978 +
979 + return 0;
980 + }
981 + case ETHTOOL_GPAUSEPARAM: {
982 + struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
983 +
984 + epause.autoneg =
985 + (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
986 + epause.rx_pause =
987 + (bp->flags & B44_FLAG_RX_PAUSE) != 0;
988 + epause.tx_pause =
989 + (bp->flags & B44_FLAG_TX_PAUSE) != 0;
990 + if (copy_to_user(useraddr, &epause, sizeof(epause)))
991 + return -EFAULT;
992 + return 0;
993 + }
994 + case ETHTOOL_SPAUSEPARAM: {
995 + struct ethtool_pauseparam epause;
996 +
997 + if (copy_from_user(&epause, useraddr, sizeof(epause)))
998 + return -EFAULT;
999 +
1000 + spin_lock_irq(&bp->lock);
1001 + if (epause.autoneg)
1002 + bp->flags |= B44_FLAG_PAUSE_AUTO;
1003 + else
1004 + bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1005 + if (epause.rx_pause)
1006 + bp->flags |= B44_FLAG_RX_PAUSE;
1007 + else
1008 + bp->flags &= ~B44_FLAG_RX_PAUSE;
1009 + if (epause.tx_pause)
1010 + bp->flags |= B44_FLAG_TX_PAUSE;
1011 + else
1012 + bp->flags &= ~B44_FLAG_TX_PAUSE;
1013 + if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1014 + b44_halt(bp);
1015 + b44_init_rings(bp);
1016 + b44_init_hw(bp, 1);
1017 + } else {
1018 + __b44_set_flow_ctrl(bp, bp->flags);
1019 + }
1020 + spin_unlock_irq(&bp->lock);
1021 +
1022 + b44_enable_ints(bp);
1023 +
1024 + return 0;
1025 + }
1026 + };
1027 +
1028 + return -EOPNOTSUPP;
1029 +}
1030 +
1031 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1032 {
1033 struct mii_ioctl_data *data = if_mii(ifr);
1034 @@ -2049,40 +2221,64 @@
1035 if (!netif_running(dev))
1036 goto out;
1037
1038 - spin_lock_irq(&bp->lock);
1039 - err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
1040 - spin_unlock_irq(&bp->lock);
1041 -out:
1042 - return err;
1043 -}
1044 + switch (cmd) {
1045 + case SIOCETHTOOL:
1046 + return b44_ethtool_ioctl(dev, (void __user*) ifr->ifr_data);
1047
1048 -/* Read 128-bytes of EEPROM. */
1049 -static int b44_read_eeprom(struct b44 *bp, u8 *data)
1050 -{
1051 - long i;
1052 - __le16 *ptr = (__le16 *) data;
1053 + case SIOCGMIIPHY:
1054 + data->phy_id = bp->phy_addr;
1055
1056 - for (i = 0; i < 128; i += 2)
1057 - ptr[i / 2] = cpu_to_le16(readw(bp->regs + 4096 + i));
1058 + /* fallthru */
1059 + case SIOCGMIIREG: {
1060 + u32 mii_regval;
1061 + spin_lock_irq(&bp->lock);
1062 + err = __b44_readphy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
1063 + spin_unlock_irq(&bp->lock);
1064
1065 - return 0;
1066 + data->val_out = mii_regval;
1067 +
1068 + return err;
1069 + }
1070 +
1071 + case SIOCSMIIREG:
1072 + if (!capable(CAP_NET_ADMIN))
1073 + return -EPERM;
1074 +
1075 + spin_lock_irq(&bp->lock);
1076 + err = __b44_writephy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1077 + spin_unlock_irq(&bp->lock);
1078 +
1079 + return err;
1080 +
1081 + default:
1082 + break;
1083 + };
1084 + return -EOPNOTSUPP;
1085 +
1086 +out:
1087 + return err;
1088 }
1089
1090 static int __devinit b44_get_invariants(struct b44 *bp)
1091 {
1092 - u8 eeprom[128];
1093 - int err;
1094 + struct ssb_device *sdev = bp->sdev;
1095 + int err = 0;
1096 + u8 *addr;
1097
1098 - err = b44_read_eeprom(bp, &eeprom[0]);
1099 - if (err)
1100 - goto out;
1101 + bp->dma_offset = ssb_dma_translation(sdev);
1102 +
1103 + switch (instance) {
1104 + case 1:
1105 + addr = sdev->bus->sprom.r1.et0mac;
1106 + bp->phy_addr = sdev->bus->sprom.r1.et0phyaddr;
1107 + break;
1108 + default:
1109 + addr = sdev->bus->sprom.r1.et1mac;
1110 + bp->phy_addr = sdev->bus->sprom.r1.et1phyaddr;
1111 + break;
1112 + }
1113
1114 - bp->dev->dev_addr[0] = eeprom[79];
1115 - bp->dev->dev_addr[1] = eeprom[78];
1116 - bp->dev->dev_addr[2] = eeprom[81];
1117 - bp->dev->dev_addr[3] = eeprom[80];
1118 - bp->dev->dev_addr[4] = eeprom[83];
1119 - bp->dev->dev_addr[5] = eeprom[82];
1120 + memcpy(bp->dev->dev_addr, addr, 6);
1121
1122 if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
1123 printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
1124 @@ -2091,108 +2287,52 @@
1125
1126 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
1127
1128 - bp->phy_addr = eeprom[90] & 0x1f;
1129 -
1130 /* With this, plus the rx_header prepended to the data by the
1131 * hardware, we'll land the ethernet header on a 2-byte boundary.
1132 */
1133 bp->rx_offset = 30;
1134 -
1135 bp->imask = IMASK_DEF;
1136 -
1137 - bp->core_unit = ssb_core_unit(bp);
1138 - bp->dma_offset = SB_PCI_DMA;
1139 -
1140 /* XXX - really required?
1141 bp->flags |= B44_FLAG_BUGGY_TXPTR;
1142 - */
1143 -
1144 - if (ssb_get_core_rev(bp) >= 7)
1145 - bp->flags |= B44_FLAG_B0_ANDLATER;
1146 + */
1147
1148 -out:
1149 return err;
1150 }
1151
1152 -static int __devinit b44_init_one(struct pci_dev *pdev,
1153 - const struct pci_device_id *ent)
1154 +static int __devinit b44_init_one(struct ssb_device *sdev,
1155 + const struct ssb_device_id *ent)
1156 {
1157 static int b44_version_printed = 0;
1158 - unsigned long b44reg_base, b44reg_len;
1159 struct net_device *dev;
1160 struct b44 *bp;
1161 int err, i;
1162
1163 + instance++;
1164 +
1165 if (b44_version_printed++ == 0)
1166 printk(KERN_INFO "%s", version);
1167
1168 - err = pci_enable_device(pdev);
1169 - if (err) {
1170 - dev_err(&pdev->dev, "Cannot enable PCI device, "
1171 - "aborting.\n");
1172 - return err;
1173 - }
1174 -
1175 - if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1176 - dev_err(&pdev->dev,
1177 - "Cannot find proper PCI device "
1178 - "base address, aborting.\n");
1179 - err = -ENODEV;
1180 - goto err_out_disable_pdev;
1181 - }
1182 -
1183 - err = pci_request_regions(pdev, DRV_MODULE_NAME);
1184 - if (err) {
1185 - dev_err(&pdev->dev,
1186 - "Cannot obtain PCI resources, aborting.\n");
1187 - goto err_out_disable_pdev;
1188 - }
1189 -
1190 - pci_set_master(pdev);
1191 -
1192 - err = pci_set_dma_mask(pdev, (u64) DMA_30BIT_MASK);
1193 - if (err) {
1194 - dev_err(&pdev->dev, "No usable DMA configuration, aborting.\n");
1195 - goto err_out_free_res;
1196 - }
1197 -
1198 - err = pci_set_consistent_dma_mask(pdev, (u64) DMA_30BIT_MASK);
1199 - if (err) {
1200 - dev_err(&pdev->dev, "No usable DMA configuration, aborting.\n");
1201 - goto err_out_free_res;
1202 - }
1203 -
1204 - b44reg_base = pci_resource_start(pdev, 0);
1205 - b44reg_len = pci_resource_len(pdev, 0);
1206 -
1207 dev = alloc_etherdev(sizeof(*bp));
1208 if (!dev) {
1209 - dev_err(&pdev->dev, "Etherdev alloc failed, aborting.\n");
1210 + dev_err(&sdev->dev, "Etherdev alloc failed, aborting.\n");
1211 err = -ENOMEM;
1212 - goto err_out_free_res;
1213 + goto out;
1214 }
1215
1216 SET_MODULE_OWNER(dev);
1217 - SET_NETDEV_DEV(dev,&pdev->dev);
1218 + SET_NETDEV_DEV(dev,&sdev->dev);
1219
1220 /* No interesting netdevice features in this card... */
1221 dev->features |= 0;
1222
1223 bp = netdev_priv(dev);
1224 - bp->pdev = pdev;
1225 + bp->sdev = sdev;
1226 bp->dev = dev;
1227
1228 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
1229
1230 spin_lock_init(&bp->lock);
1231
1232 - bp->regs = ioremap(b44reg_base, b44reg_len);
1233 - if (bp->regs == 0UL) {
1234 - dev_err(&pdev->dev, "Cannot map device registers, aborting.\n");
1235 - err = -ENOMEM;
1236 - goto err_out_free_dev;
1237 - }
1238 -
1239 bp->rx_pending = B44_DEF_RX_RING_PENDING;
1240 bp->tx_pending = B44_DEF_TX_RING_PENDING;
1241
1242 @@ -2211,16 +2351,16 @@
1243 dev->poll_controller = b44_poll_controller;
1244 #endif
1245 dev->change_mtu = b44_change_mtu;
1246 - dev->irq = pdev->irq;
1247 + dev->irq = sdev->irq;
1248 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
1249
1250 netif_carrier_off(dev);
1251
1252 err = b44_get_invariants(bp);
1253 if (err) {
1254 - dev_err(&pdev->dev,
1255 + dev_err(&sdev->dev,
1256 "Problem fetching invariants of chip, aborting.\n");
1257 - goto err_out_iounmap;
1258 + goto err_out_free_dev;
1259 }
1260
1261 bp->mii_if.dev = dev;
1262 @@ -2239,61 +2379,52 @@
1263
1264 err = register_netdev(dev);
1265 if (err) {
1266 - dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1267 - goto err_out_iounmap;
1268 + dev_err(&sdev->dev, "Cannot register net device, aborting.\n");
1269 + goto out;
1270 }
1271
1272 - pci_set_drvdata(pdev, dev);
1273 -
1274 - pci_save_state(bp->pdev);
1275 + ssb_set_drvdata(sdev, dev);
1276
1277 /* Chip reset provides power to the b44 MAC & PCI cores, which
1278 * is necessary for MAC register access.
1279 */
1280 b44_chip_reset(bp);
1281
1282 - printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
1283 + printk(KERN_INFO "%s: Broadcom 10/100BaseT Ethernet ", dev->name);
1284 for (i = 0; i < 6; i++)
1285 printk("%2.2x%c", dev->dev_addr[i],
1286 i == 5 ? '\n' : ':');
1287
1288 - return 0;
1289 + /* Initialize phy */
1290 + spin_lock_irq(&bp->lock);
1291 + b44_chip_reset(bp);
1292 + spin_unlock_irq(&bp->lock);
1293
1294 -err_out_iounmap:
1295 - iounmap(bp->regs);
1296 + return 0;
1297
1298 err_out_free_dev:
1299 free_netdev(dev);
1300
1301 -err_out_free_res:
1302 - pci_release_regions(pdev);
1303 -
1304 -err_out_disable_pdev:
1305 - pci_disable_device(pdev);
1306 - pci_set_drvdata(pdev, NULL);
1307 +out:
1308 return err;
1309 }
1310
1311 -static void __devexit b44_remove_one(struct pci_dev *pdev)
1312 +static void __devexit b44_remove_one(struct ssb_device *pdev)
1313 {
1314 - struct net_device *dev = pci_get_drvdata(pdev);
1315 - struct b44 *bp = netdev_priv(dev);
1316 + struct net_device *dev = ssb_get_drvdata(pdev);
1317
1318 unregister_netdev(dev);
1319 - iounmap(bp->regs);
1320 free_netdev(dev);
1321 - pci_release_regions(pdev);
1322 - pci_disable_device(pdev);
1323 - pci_set_drvdata(pdev, NULL);
1324 + ssb_set_drvdata(pdev, NULL);
1325 }
1326
1327 -static int b44_suspend(struct pci_dev *pdev, pm_message_t state)
1328 +static int b44_suspend(struct ssb_device *pdev, pm_message_t state)
1329 {
1330 - struct net_device *dev = pci_get_drvdata(pdev);
1331 + struct net_device *dev = ssb_get_drvdata(pdev);
1332 struct b44 *bp = netdev_priv(dev);
1333
1334 if (!netif_running(dev))
1335 - return 0;
1336 + return 0;
1337
1338 del_timer_sync(&bp->timer);
1339
1340 @@ -2311,26 +2442,16 @@
1341 b44_init_hw(bp, B44_PARTIAL_RESET);
1342 b44_setup_wol(bp);
1343 }
1344 - pci_disable_device(pdev);
1345 +
1346 return 0;
1347 }
1348
1349 -static int b44_resume(struct pci_dev *pdev)
1350 +static int b44_resume(struct ssb_device *pdev)
1351 {
1352 - struct net_device *dev = pci_get_drvdata(pdev);
1353 + struct net_device *dev = ssb_get_drvdata(pdev);
1354 struct b44 *bp = netdev_priv(dev);
1355 int rc = 0;
1356
1357 - pci_restore_state(pdev);
1358 - rc = pci_enable_device(pdev);
1359 - if (rc) {
1360 - printk(KERN_ERR PFX "%s: pci_enable_device failed\n",
1361 - dev->name);
1362 - return rc;
1363 - }
1364 -
1365 - pci_set_master(pdev);
1366 -
1367 if (!netif_running(dev))
1368 return 0;
1369
1370 @@ -2356,29 +2477,31 @@
1371 return 0;
1372 }
1373
1374 -static struct pci_driver b44_driver = {
1375 +static struct ssb_driver b44_driver = {
1376 .name = DRV_MODULE_NAME,
1377 - .id_table = b44_pci_tbl,
1378 + .id_table = b44_ssb_tbl,
1379 .probe = b44_init_one,
1380 .remove = __devexit_p(b44_remove_one),
1381 - .suspend = b44_suspend,
1382 - .resume = b44_resume,
1383 + .suspend = b44_suspend,
1384 + .resume = b44_resume,
1385 };
1386
1387 static int __init b44_init(void)
1388 {
1389 unsigned int dma_desc_align_size = dma_get_cache_alignment();
1390
1391 + instance = 0;
1392 +
1393 /* Setup paramaters for syncing RX/TX DMA descriptors */
1394 dma_desc_align_mask = ~(dma_desc_align_size - 1);
1395 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
1396
1397 - return pci_register_driver(&b44_driver);
1398 + return ssb_driver_register(&b44_driver);
1399 }
1400
1401 static void __exit b44_cleanup(void)
1402 {
1403 - pci_unregister_driver(&b44_driver);
1404 + ssb_driver_unregister(&b44_driver);
1405 }
1406
1407 module_init(b44_init);
1408 Index: linux-2.6.22-rc4/drivers/net/b44.h
1409 ===================================================================
1410 --- linux-2.6.22-rc4.orig/drivers/net/b44.h 2007-06-10 21:32:13.000000000 +0100
1411 +++ linux-2.6.22-rc4/drivers/net/b44.h 2007-06-10 21:33:15.000000000 +0100
1412 @@ -129,6 +129,7 @@
1413 #define RXCONFIG_FLOW 0x00000020 /* Flow Control Enable */
1414 #define RXCONFIG_FLOW_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */
1415 #define RXCONFIG_RFILT 0x00000080 /* Reject Filter */
1416 +#define RXCONFIG_CAM_ABSENT 0x00000100 /* CAM Absent */
1417 #define B44_RXMAXLEN 0x0404UL /* EMAC RX Max Packet Length */
1418 #define B44_TXMAXLEN 0x0408UL /* EMAC TX Max Packet Length */
1419 #define B44_MDIO_CTRL 0x0410UL /* EMAC MDIO Control */
1420 @@ -227,75 +228,9 @@
1421 #define B44_RX_PAUSE 0x05D4UL /* MIB RX Pause Packets */
1422 #define B44_RX_NPAUSE 0x05D8UL /* MIB RX Non-Pause Packets */
1423
1424 -/* Silicon backplane register definitions */
1425 -#define B44_SBIMSTATE 0x0F90UL /* SB Initiator Agent State */
1426 -#define SBIMSTATE_PC 0x0000000f /* Pipe Count */
1427 -#define SBIMSTATE_AP_MASK 0x00000030 /* Arbitration Priority */
1428 -#define SBIMSTATE_AP_BOTH 0x00000000 /* Use both timeslices and token */
1429 -#define SBIMSTATE_AP_TS 0x00000010 /* Use timeslices only */
1430 -#define SBIMSTATE_AP_TK 0x00000020 /* Use token only */
1431 -#define SBIMSTATE_AP_RSV 0x00000030 /* Reserved */
1432 -#define SBIMSTATE_IBE 0x00020000 /* In Band Error */
1433 -#define SBIMSTATE_TO 0x00040000 /* Timeout */
1434 -#define B44_SBINTVEC 0x0F94UL /* SB Interrupt Mask */
1435 -#define SBINTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
1436 -#define SBINTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
1437 -#define SBINTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */
1438 -#define SBINTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */
1439 -#define SBINTVEC_USB 0x00000010 /* Enable interrupts for usb */
1440 -#define SBINTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */
1441 -#define SBINTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
1442 -#define B44_SBTMSLOW 0x0F98UL /* SB Target State Low */
1443 -#define SBTMSLOW_RESET 0x00000001 /* Reset */
1444 -#define SBTMSLOW_REJECT 0x00000002 /* Reject */
1445 -#define SBTMSLOW_CLOCK 0x00010000 /* Clock Enable */
1446 -#define SBTMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
1447 -#define SBTMSLOW_PE 0x40000000 /* Power Management Enable */
1448 -#define SBTMSLOW_BE 0x80000000 /* BIST Enable */
1449 -#define B44_SBTMSHIGH 0x0F9CUL /* SB Target State High */
1450 -#define SBTMSHIGH_SERR 0x00000001 /* S-error */
1451 -#define SBTMSHIGH_INT 0x00000002 /* Interrupt */
1452 -#define SBTMSHIGH_BUSY 0x00000004 /* Busy */
1453 -#define SBTMSHIGH_GCR 0x20000000 /* Gated Clock Request */
1454 -#define SBTMSHIGH_BISTF 0x40000000 /* BIST Failed */
1455 -#define SBTMSHIGH_BISTD 0x80000000 /* BIST Done */
1456 -#define B44_SBIDHIGH 0x0FFCUL /* SB Identification High */
1457 -#define SBIDHIGH_RC_MASK 0x0000000f /* Revision Code */
1458 -#define SBIDHIGH_CC_MASK 0x0000fff0 /* Core Code */
1459 -#define SBIDHIGH_CC_SHIFT 4
1460 -#define SBIDHIGH_VC_MASK 0xffff0000 /* Vendor Code */
1461 -#define SBIDHIGH_VC_SHIFT 16
1462 -
1463 -/* SSB PCI config space registers. */
1464 -#define SSB_PMCSR 0x44
1465 -#define SSB_PE 0x100
1466 -#define SSB_BAR0_WIN 0x80
1467 -#define SSB_BAR1_WIN 0x84
1468 -#define SSB_SPROM_CONTROL 0x88
1469 -#define SSB_BAR1_CONTROL 0x8c
1470 -
1471 -/* SSB core and host control registers. */
1472 -#define SSB_CONTROL 0x0000UL
1473 -#define SSB_ARBCONTROL 0x0010UL
1474 -#define SSB_ISTAT 0x0020UL
1475 -#define SSB_IMASK 0x0024UL
1476 -#define SSB_MBOX 0x0028UL
1477 -#define SSB_BCAST_ADDR 0x0050UL
1478 -#define SSB_BCAST_DATA 0x0054UL
1479 -#define SSB_PCI_TRANS_0 0x0100UL
1480 -#define SSB_PCI_TRANS_1 0x0104UL
1481 -#define SSB_PCI_TRANS_2 0x0108UL
1482 -#define SSB_SPROM 0x0800UL
1483 -
1484 -#define SSB_PCI_MEM 0x00000000
1485 -#define SSB_PCI_IO 0x00000001
1486 -#define SSB_PCI_CFG0 0x00000002
1487 -#define SSB_PCI_CFG1 0x00000003
1488 -#define SSB_PCI_PREF 0x00000004
1489 -#define SSB_PCI_BURST 0x00000008
1490 -#define SSB_PCI_MASK0 0xfc000000
1491 -#define SSB_PCI_MASK1 0xfc000000
1492 -#define SSB_PCI_MASK2 0xc0000000
1493 +#define br32(bp, REG) ssb_read32((bp)->sdev, (REG))
1494 +#define bw32(bp, REG, VAL) ssb_write32((bp)->sdev, (REG), (VAL))
1495 +#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
1496
1497 /* 4400 PHY registers */
1498 #define B44_MII_AUXCTRL 24 /* Auxiliary Control */
1499 @@ -346,10 +281,12 @@
1500
1501 struct ring_info {
1502 struct sk_buff *skb;
1503 - DECLARE_PCI_UNMAP_ADDR(mapping);
1504 + dma_addr_t mapping;
1505 };
1506
1507 #define B44_MCAST_TABLE_SIZE 32
1508 +#define B44_PHY_ADDR_NO_PHY 30
1509 +#define B44_MDC_RATIO 5000000
1510
1511 #define B44_STAT_REG_DECLARE \
1512 _B44(tx_good_octets) \
1513 @@ -425,9 +362,10 @@
1514
1515 u32 dma_offset;
1516 u32 flags;
1517 -#define B44_FLAG_B0_ANDLATER 0x00000001
1518 +#define B44_FLAG_INIT_COMPLETE 0x00000001
1519 #define B44_FLAG_BUGGY_TXPTR 0x00000002
1520 #define B44_FLAG_REORDER_BUG 0x00000004
1521 +#define B44_FLAG_B0_ANDLATER 0x00000008
1522 #define B44_FLAG_PAUSE_AUTO 0x00008000
1523 #define B44_FLAG_FULL_DUPLEX 0x00010000
1524 #define B44_FLAG_100_BASE_T 0x00020000
1525 @@ -452,8 +390,7 @@
1526 struct net_device_stats stats;
1527 struct b44_hw_stats hw_stats;
1528
1529 - void __iomem *regs;
1530 - struct pci_dev *pdev;
1531 + struct ssb_device *sdev;
1532 struct net_device *dev;
1533
1534 dma_addr_t rx_ring_dma, tx_ring_dma;
1535 Index: linux-2.6.22-rc4/drivers/net/Kconfig
1536 ===================================================================
1537 --- linux-2.6.22-rc4.orig/drivers/net/Kconfig 2007-06-10 21:32:48.000000000 +0100
1538 +++ linux-2.6.22-rc4/drivers/net/Kconfig 2007-06-10 21:33:15.000000000 +0100
1539 @@ -1511,7 +1511,7 @@
1540
1541 config B44
1542 tristate "Broadcom 4400 ethernet support"
1543 - depends on NET_PCI && PCI
1544 + depends on SSB && EXPERIMENTAL
1545 select MII
1546 help
1547 If you have a network (Ethernet) controller of this type, say Y and
Staging tree of Zoltan Herpai