target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c

   1 /*
   2  * Copyright 2012 Gateworks Corporation
   3  *     Chris Lang <clang@gateworks.com>
   4  *     Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * This file is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License, Version 2, as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irqchip/chained_irq.h>
  15 #include <linux/io.h>
  16 #include <linux/gpio.h>
  17 #include <linux/irq.h>
  18
  19 #include <asm/mach/irq.h>
  20
  21 /*
  22  * Registers
  23  */
  24 #define GPIO_INPUT                          0x04
  25 #define GPIO_DIR                            0x08
  26 #define GPIO_SET                            0x10
  27 #define GPIO_CLEAR                          0x14
  28 #define GPIO_INTERRUPT_ENABLE               0x20
  29 #define GPIO_INTERRUPT_RAW_STATUS           0x24
  30 #define GPIO_INTERRUPT_MASKED_STATUS        0x28
  31 #define GPIO_INTERRUPT_MASK                 0x2C
  32 #define GPIO_INTERRUPT_CLEAR                0x30
  33 #define GPIO_INTERRUPT_TRIGGER_METHOD       0x34
  34 #define GPIO_INTERRUPT_TRIGGER_BOTH_EDGES   0x38
  35 #define GPIO_INTERRUPT_TRIGGER_TYPE         0x3C
  36
  37 #define GPIO_INTERRUPT_TRIGGER_METHOD_EDGE  0
  38 #define GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL 1
  39 #define GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE  0
  40 #define GPIO_INTERRUPT_TRIGGER_EDGE_BOTH    1
  41 #define GPIO_INTERRUPT_TRIGGER_TYPE_RISING  0
  42 #define GPIO_INTERRUPT_TRIGGER_TYPE_FALLING 1
  43 #define GPIO_INTERRUPT_TRIGGER_TYPE_HIGH    0
  44 #define GPIO_INTERRUPT_TRIGGER_TYPE_LOW     1
  45
  46 struct cns3xxx_gpio_chip {
  47         struct gpio_chip    chip;
  48         spinlock_t          lock;
  49         void __iomem        *base;
  50         int                 secondary_irq_base;
  51 };
  52
  53 static struct cns3xxx_gpio_chip cns3xxx_gpio_chips[2];
  54 static int cns3xxx_gpio_chip_count;
  55
  56 static inline void
  57 __set_direction(struct cns3xxx_gpio_chip *cchip, unsigned pin, int input)
  58 {
  59         u32 reg;
  60
  61         reg = __raw_readl(cchip->base + GPIO_DIR);
  62         if (input)
  63                 reg &= ~(1 << pin);
  64         else
  65                 reg |= (1 << pin);
  66         __raw_writel(reg, cchip->base + GPIO_DIR);
  67 }
  68
  69 /*
  70  * GENERIC_GPIO primatives
  71  */
  72 static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
  73 {
  74         struct cns3xxx_gpio_chip *cchip =
  75                 container_of(chip, struct cns3xxx_gpio_chip, chip);
  76         unsigned long flags;
  77
  78         spin_lock_irqsave(&cchip->lock, flags);
  79         __set_direction(cchip, pin, 1);
  80         spin_unlock_irqrestore(&cchip->lock, flags);
  81
  82         return 0;
  83 }
  84
  85 static int cns3xxx_gpio_get(struct gpio_chip *chip, unsigned pin)
  86 {
  87         struct cns3xxx_gpio_chip *cchip =
  88                 container_of(chip, struct cns3xxx_gpio_chip, chip);
  89         int val;
  90
  91         val = ((__raw_readl(cchip->base + GPIO_INPUT) >> pin) & 0x1);
  92
  93         return val;
  94 }
  95
  96 static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int level)
  97 {
  98         struct cns3xxx_gpio_chip *cchip =
  99                 container_of(chip, struct cns3xxx_gpio_chip, chip);
 100         unsigned long flags;
 101
 102         spin_lock_irqsave(&cchip->lock, flags);
 103         if (level)
 104                 __raw_writel(1 << pin, cchip->base + GPIO_SET);
 105         else
 106                 __raw_writel(1 << pin, cchip->base + GPIO_CLEAR);
 107         __set_direction(cchip, pin, 0);
 108         spin_unlock_irqrestore(&cchip->lock, flags);
 109
 110         return 0;
 111 }
 112
 113 static void cns3xxx_gpio_set(struct gpio_chip *chip, unsigned pin,
 114         int level)
 115 {
 116         struct cns3xxx_gpio_chip *cchip =
 117                 container_of(chip, struct cns3xxx_gpio_chip, chip);
 118
 119         if (level)
 120                 __raw_writel(1 << pin, cchip->base + GPIO_SET);
 121         else
 122                 __raw_writel(1 << pin, cchip->base + GPIO_CLEAR);
 123 }
 124
 125 static int cns3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
 126 {
 127         struct cns3xxx_gpio_chip *cchip =
 128                 container_of(chip, struct cns3xxx_gpio_chip, chip);
 129
 130         return cchip->secondary_irq_base + pin;
 131 }
 132
 133
 134 /*
 135  * IRQ support
 136  */
 137
 138 /* one interrupt per GPIO controller (GPIOA/GPIOB)
 139  * this is called in task context, with IRQs enabled
 140  */
 141 static void cns3xxx_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 142 {
 143         struct cns3xxx_gpio_chip *cchip = irq_get_handler_data(irq);
 144         struct irq_chip *chip = irq_get_chip(irq);
 145         u16 i;
 146         u32 reg;
 147
 148         chained_irq_enter(chip, desc); /* mask and ack the base interrupt */
 149
 150         /* see which pin(s) triggered the interrupt */
 151         reg = __raw_readl(cchip->base + GPIO_INTERRUPT_RAW_STATUS);
 152         for (i = 0; i < 32; i++) {
 153                 if (reg & (1 << i)) {
 154                         /* let the generic IRQ layer handle an interrupt */
 155                         generic_handle_irq(cchip->secondary_irq_base + i);
 156                 }
 157         }
 158
 159         chained_irq_exit(chip, desc); /* unmask the base interrupt */
 160 }
 161
 162 static int cns3xxx_gpio_irq_set_type(struct irq_data *d, u32 irqtype)
 163 {
 164         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 165         struct cns3xxx_gpio_chip *cchip = gc->private;
 166         u32 gpio = d->irq - cchip->secondary_irq_base;
 167         unsigned long flags;
 168         u32 method, edges, type;
 169
 170         spin_lock_irqsave(&cchip->lock, flags);
 171         method = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD);
 172         edges  = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES);
 173         type   = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE);
 174         method &= ~(1 << gpio);
 175         edges  &= ~(1 << gpio);
 176         type   &= ~(1 << gpio);
 177
 178         switch(irqtype) {
 179         case IRQ_TYPE_EDGE_RISING:
 180                 method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
 181                 edges  |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio);
 182                 type   |= (GPIO_INTERRUPT_TRIGGER_TYPE_RISING << gpio);
 183                 break;
 184         case IRQ_TYPE_EDGE_FALLING:
 185                 method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
 186                 edges  |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio);
 187                 type   |= (GPIO_INTERRUPT_TRIGGER_TYPE_FALLING << gpio);
 188                 break;
 189         case IRQ_TYPE_EDGE_BOTH:
 190                 method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
 191                 edges  |= (GPIO_INTERRUPT_TRIGGER_EDGE_BOTH << gpio);
 192                 break;
 193         case IRQ_TYPE_LEVEL_LOW:
 194                 method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio);
 195                 type   |= (GPIO_INTERRUPT_TRIGGER_TYPE_LOW << gpio);
 196                 break;
 197         case IRQ_TYPE_LEVEL_HIGH:
 198                 method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio);
 199                 type   |= (GPIO_INTERRUPT_TRIGGER_TYPE_HIGH << gpio);
 200                 break;
 201         default:
 202                 printk(KERN_WARNING "No irq type\n");
 203                 spin_unlock_irqrestore(&cchip->lock, flags);
 204                 return -EINVAL;
 205         }
 206
 207         __raw_writel(method, cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD);
 208         __raw_writel(edges,  cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES);
 209         __raw_writel(type,   cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE);
 210         spin_unlock_irqrestore(&cchip->lock, flags);
 211
 212         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 213                 __irq_set_handler_locked(d->irq, handle_level_irq);
 214         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 215                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 216
 217         return 0;
 218 }
 219
 220 void __init cns3xxx_gpio_init(int gpio_base, int ngpio,
 221         u32 base, int irq, int secondary_irq_base)
 222 {
 223         struct cns3xxx_gpio_chip *cchip;
 224         struct irq_chip_generic *gc;
 225         struct irq_chip_type *ct;
 226         char gc_label[16];
 227
 228         if (cns3xxx_gpio_chip_count == ARRAY_SIZE(cns3xxx_gpio_chips))
 229                 return;
 230
 231         snprintf(gc_label, sizeof(gc_label), "cns3xxx_gpio%d",
 232                 cns3xxx_gpio_chip_count);
 233
 234         cchip = cns3xxx_gpio_chips + cns3xxx_gpio_chip_count;
 235         cchip->chip.label = kstrdup(gc_label, GFP_KERNEL);
 236         cchip->chip.direction_input = cns3xxx_gpio_direction_input;
 237         cchip->chip.get = cns3xxx_gpio_get;
 238         cchip->chip.direction_output = cns3xxx_gpio_direction_output;
 239         cchip->chip.set = cns3xxx_gpio_set;
 240         cchip->chip.to_irq = cns3xxx_gpio_to_irq;
 241         cchip->chip.base = gpio_base;
 242         cchip->chip.ngpio = ngpio;
 243         cchip->chip.can_sleep = 0;
 244         spin_lock_init(&cchip->lock);
 245         cchip->base = (void __iomem *)base;
 246         cchip->secondary_irq_base = secondary_irq_base;
 247
 248         BUG_ON(gpiochip_add(&cchip->chip) < 0);
 249         cns3xxx_gpio_chip_count++;
 250
 251         /* clear GPIO interrupts */
 252         __raw_writel(0xffff, cchip->base + GPIO_INTERRUPT_CLEAR);
 253
 254         /*
 255          * IRQ chip init
 256          */
 257         gc = irq_alloc_generic_chip("cns3xxx_gpio_irq", 1, secondary_irq_base,
 258                 cchip->base, handle_edge_irq);
 259         gc->private = cchip;
 260
 261         ct = gc->chip_types;
 262         ct->type = IRQ_TYPE_EDGE_FALLING;
 263         ct->regs.ack = GPIO_INTERRUPT_CLEAR;
 264         ct->regs.enable = GPIO_INTERRUPT_ENABLE;
 265         ct->chip.irq_ack = irq_gc_ack_set_bit;
 266         ct->chip.irq_enable = irq_gc_unmask_enable_reg;
 267         ct->chip.irq_disable = irq_gc_mask_disable_reg;
 268         ct->chip.irq_set_type = cns3xxx_gpio_irq_set_type;
 269         ct->handler = handle_edge_irq;
 270
 271         irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
 272                 IRQ_NOREQUEST, 0);
 273
 274         irq_set_chained_handler(irq, cns3xxx_gpio_irq_handler);
 275         irq_set_handler_data(irq, cchip);
 276 }