target/linux/cns3xxx/patches-2.6.31/301-dma_cache_ownership_maint.patch

   1 --- a/arch/arm/mm/cache-v6.S
   2 +++ b/arch/arm/mm/cache-v6.S
   3 @@ -179,6 +179,10 @@ ENTRY(v6_flush_kern_dcache_page)
   4   *     - end     - virtual end address of region
   5   */
   6  ENTRY(v6_dma_inv_range)
   7 +#ifdef CONFIG_SMP
   8 +       ldrb    r2, [r0]
   9 +       strb    r2, [r0]
  10 +#endif
  11         tst     r0, #D_CACHE_LINE_SIZE - 1
  12         bic     r0, r0, #D_CACHE_LINE_SIZE - 1
  13  #ifdef HARVARD_CACHE
  14 @@ -187,6 +191,10 @@ ENTRY(v6_dma_inv_range)
  15         mcrne   p15, 0, r0, c7, c11, 1          @ clean unified line
  16  #endif
  17         tst     r1, #D_CACHE_LINE_SIZE - 1
  18 +#ifdef CONFIG_SMP
  19 +       ldrneb  r2, [r1, #-1]
  20 +       strneb  r2, [r1, #-1]
  21 +#endif
  22         bic     r1, r1, #D_CACHE_LINE_SIZE - 1
  23  #ifdef HARVARD_CACHE
  24         mcrne   p15, 0, r1, c7, c14, 1          @ clean & invalidate D line
  25 @@ -201,6 +209,10 @@ ENTRY(v6_dma_inv_range)
  26  #endif
  27         add     r0, r0, #D_CACHE_LINE_SIZE
  28         cmp     r0, r1
  29 +#ifdef CONFIG_SMP
  30 +       ldrlo   r2, [r0]
  31 +       strlo   r2, [r0]
  32 +#endif
  33         blo     1b
  34         mov     r0, #0
  35         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
  36 @@ -214,6 +226,9 @@ ENTRY(v6_dma_inv_range)
  37  ENTRY(v6_dma_clean_range)
  38         bic     r0, r0, #D_CACHE_LINE_SIZE - 1
  39  1:
  40 +#ifdef CONFIG_SMP
  41 +       ldr r2, [r0]
  42 +#endif
  43  #ifdef HARVARD_CACHE
  44         mcr     p15, 0, r0, c7, c10, 1          @ clean D line
  45  #else
  46 @@ -232,6 +247,10 @@ ENTRY(v6_dma_clean_range)
  47   *     - end     - virtual end address of region
  48   */
  49  ENTRY(v6_dma_flush_range)
  50 +#ifdef CONFIG_SMP
  51 +       ldrb    r2, [r0]
  52 +       strb    r2, [r0]
  53 +#endif
  54         bic     r0, r0, #D_CACHE_LINE_SIZE - 1
  55  1:
  56  #ifdef HARVARD_CACHE
  57 @@ -241,6 +260,10 @@ ENTRY(v6_dma_flush_range)
  58  #endif
  59         add     r0, r0, #D_CACHE_LINE_SIZE
  60         cmp     r0, r1
  61 +#ifdef CONFIG_SMP
  62 +       ldrlob   r2, [r0]
  63 +       strlob   r2, [r0]
  64 +#endif
  65         blo     1b
  66         mov     r0, #0
  67         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer