target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h

   1 /*******************************************************************************
   2 Copyright (C) Marvell International Ltd. and its affiliates
   3
   4 This software file (the "File") is owned and distributed by Marvell
   5 International Ltd. and/or its affiliates ("Marvell") under the following
   6 alternative licensing terms.  Once you have made an election to distribute the
   7 File under one of the following license alternatives, please (i) delete this
   8 introductory statement regarding license alternatives, (ii) delete the two
   9 license alternatives that you have not elected to use and (iii) preserve the
  10 Marvell copyright notice above.
  11
  12 ********************************************************************************
  13 Marvell Commercial License Option
  14
  15 If you received this File from Marvell and you have entered into a commercial
  16 license agreement (a "Commercial License") with Marvell, the File is licensed
  17 to you under the terms of the applicable Commercial License.
  18
  19 ********************************************************************************
  20 Marvell GPL License Option
  21
  22 If you received this File from Marvell, you may opt to use, redistribute and/or
  23 modify this File in accordance with the terms and conditions of the General
  24 Public License Version 2, June 1991 (the "GPL License"), a copy of which is
  25 available along with the File in the license.txt file or by writing to the Free
  26 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
  27 on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
  28
  29 THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
  30 WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
  31 DISCLAIMED.  The GPL License provides additional details about this warranty
  32 disclaimer.
  33 ********************************************************************************
  34 Marvell BSD License Option
  35
  36 If you received this File from Marvell, you may opt to use, redistribute and/or
  37 modify this File under the following licensing terms.
  38 Redistribution and use in source and binary forms, with or without modification,
  39 are permitted provided that the following conditions are met:
  40
  41     *   Redistributions of source code must retain the above copyright notice,
  42             this list of conditions and the following disclaimer.
  43
  44     *   Redistributions in binary form must reproduce the above copyright
  45         notice, this list of conditions and the following disclaimer in the
  46         documentation and/or other materials provided with the distribution.
  47
  48     *   Neither the name of Marvell nor the names of its contributors may be
  49         used to endorse or promote products derived from this software without
  50         specific prior written permission.
  51
  52 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  53 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  54 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  55 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
  56 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  57 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  58 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  59 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  60 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  61 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  62
  63 *******************************************************************************/
  64
  65 #ifndef __INCmvDramIfRegsh
  66 #define __INCmvDramIfRegsh
  67
  68
  69 /* DDR SDRAM Controller Address Decode Registers */
  70 /* SDRAM CSn Base Address Register (SCBAR) */
  71 #define SDRAM_BASE_ADDR_REG(csNum)      (0x1500 + (csNum * 8))
  72 #define SCBAR_BASE_OFFS                         16
  73 #define SCBAR_BASE_MASK                         (0xffff << SCBAR_BASE_OFFS)
  74 #define SCBAR_BASE_ALIGNMENT            0x10000
  75
  76 /* SDRAM CSn Size Register (SCSR) */
  77 #define SDRAM_SIZE_REG(csNum)   (0x1504 + (csNum * 8))
  78 #define SCSR_WIN_EN                                     BIT0
  79 #define SCSR_SIZE_OFFS                          16
  80 #define SCSR_SIZE_MASK                          (0xffff << SCSR_SIZE_OFFS)
  81 #define SCSR_SIZE_ALIGNMENT                     0x10000
  82
  83 /* configuration register */
  84 #define SDRAM_CONFIG_REG                0x1400
  85 #define SDRAM_REFRESH_OFFS              0
  86 #define SDRAM_REFRESH_MAX               0x3000
  87 #define SDRAM_REFRESH_MASK              (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS)
  88 #define SDRAM_DWIDTH_OFFS       14
  89 #define SDRAM_DWIDTH_MASK       (3 << SDRAM_DWIDTH_OFFS)
  90 #define SDRAM_DWIDTH_16BIT      (1 << SDRAM_DWIDTH_OFFS)
  91 #define SDRAM_DWIDTH_32BIT      (2 << SDRAM_DWIDTH_OFFS)
  92 #define SDRAM_DTYPE_OFFS        16
  93 #define SDRAM_DTYPE_MASK        (1 << SDRAM_DTYPE_OFFS)
  94 #define SDRAM_DTYPE_DDR1        (0 << SDRAM_DTYPE_OFFS)
  95 #define SDRAM_DTYPE_DDR2        (1 << SDRAM_DTYPE_OFFS)
  96 #define SDRAM_REGISTERED                (1 << 17)
  97 #define SDRAM_PERR_OFFS                 18
  98 #define SDRAM_PERR_MASK                 (1 << SDRAM_PERR_OFFS)
  99 #define SDRAM_PERR_NO_WRITE     (0 << SDRAM_PERR_OFFS)
 100 #define SDRAM_PERR_WRITE        (1 << SDRAM_PERR_OFFS)
 101 #define SDRAM_DCFG_OFFS         20
 102 #define SDRAM_DCFG_MASK         (0x3 << SDRAM_DCFG_OFFS)
 103 #define SDRAM_DCFG_X16_DEV      (1 << SDRAM_DCFG_OFFS)
 104 #define SDRAM_DCFG_X8_DEV       (2 << SDRAM_DCFG_OFFS)
 105 #define SDRAM_SRMODE                    (1 << 24)
 106 #define SDRAM_SRCLK_OFFS                25
 107 #define SDRAM_SRCLK_MASK                (1 << SDRAM_SRCLK_OFFS)
 108 #define SDRAM_SRCLK_KEPT                (0 << SDRAM_SRCLK_OFFS)
 109 #define SDRAM_SRCLK_GATED               (1 << SDRAM_SRCLK_OFFS)
 110 #define SDRAM_CATTH_OFFS                26
 111 #define SDRAM_CATTHR_EN                 (1 << SDRAM_CATTH_OFFS)
 112
 113
 114 /* dunit control register */
 115 #define SDRAM_DUNIT_CTRL_REG    0x1404
 116 #define SDRAM_CTRL_POS_OFFS             6
 117 #define SDRAM_CTRL_POS_FALL             (0 << SDRAM_CTRL_POS_OFFS)
 118 #define SDRAM_CTRL_POS_RISE             (1 << SDRAM_CTRL_POS_OFFS)
 119 #define SDRAM_CLK1DRV_OFFS      12
 120 #define SDRAM_CLK1DRV_MASK      (1 << SDRAM_CLK1DRV_OFFS)
 121 #define SDRAM_CLK1DRV_HIGH_Z    (0 << SDRAM_CLK1DRV_OFFS)
 122 #define SDRAM_CLK1DRV_NORMAL    (1 << SDRAM_CLK1DRV_OFFS)
 123 #define SDRAM_LOCKEN_OFFS       18
 124 #define SDRAM_LOCKEN_MASK       (1 << SDRAM_LOCKEN_OFFS)
 125 #define SDRAM_LOCKEN_DISABLE    (0 << SDRAM_LOCKEN_OFFS)
 126 #define SDRAM_LOCKEN_ENABLE     (1 << SDRAM_LOCKEN_OFFS)
 127 #define SDRAM_ST_BURST_DEL_OFFS         24
 128 #define SDRAM_ST_BURST_DEL_MAX  0xf
 129 #define SDRAM_ST_BURST_DEL_MASK (SDRAM_ST_BURST_DEL_MAX<<SDRAM_ST_BURST_DEL_OFFS)
 130
 131 /* sdram timing control low register */
 132 #define SDRAM_TIMING_CTRL_LOW_REG       0x1408
 133 #define SDRAM_TRCD_OFFS                 4
 134 #define SDRAM_TRCD_MASK                 (0xF << SDRAM_TRCD_OFFS)
 135 #define SDRAM_TRP_OFFS                  8
 136 #define SDRAM_TRP_MASK                  (0xF << SDRAM_TRP_OFFS)
 137 #define SDRAM_TWR_OFFS                  12
 138 #define SDRAM_TWR_MASK                  (0xF << SDRAM_TWR_OFFS)
 139 #define SDRAM_TWTR_OFFS                 16
 140 #define SDRAM_TWTR_MASK                 (0xF << SDRAM_TWTR_OFFS)
 141 #define SDRAM_TRAS_OFFS                 20
 142 #define SDRAM_TRAS_MASK                 (0xF << SDRAM_TRAS_OFFS)
 143 #define SDRAM_TRRD_OFFS                 24
 144 #define SDRAM_TRRD_MASK                 (0xF << SDRAM_TRRD_OFFS)
 145 #define SDRAM_TRTP_OFFS                 28
 146 #define SDRAM_TRTP_MASK                 (0xF << SDRAM_TRTP_OFFS)
 147
 148 /* sdram timing control high register */
 149 #define SDRAM_TIMING_CTRL_HIGH_REG      0x140c
 150 #define SDRAM_TRFC_OFFS                 0
 151 #define SDRAM_TRFC_MASK                 (0xF << SDRAM_TRFC_OFFS)
 152 #define SDRAM_TR2R_OFFS                 4
 153 #define SDRAM_TR2R_MASK                 (0x3 << SDRAM_TR2R_OFFS)
 154 #define SDRAM_TR2W_W2R_OFFS             6
 155 #define SDRAM_TR2W_W2R_MASK             (0x3 << SDRAM_TR2W_W2R_OFFS)
 156 #define SDRAM_TRFC_EXT_OFFS             8
 157 #define SDRAM_TRFC_EXT_MASK             (0x1 << SDRAM_TRFC_EXT_OFFS)
 158 #define SDRAM_TW2W_OFFS             10
 159 #define SDRAM_TW2W_MASK             (0x1 << SDRAM_TW2W_OFFS)
 160
 161 /* address control register */
 162 #define SDRAM_ADDR_CTRL_REG             0x1410
 163 #define SDRAM_DSIZE_OFFS            4
 164 #define SDRAM_DSIZE_MASK            (0x3 << SDRAM_DSIZE_OFFS)
 165 #define SDRAM_DSIZE_128Mb           (0x0 << SDRAM_DSIZE_OFFS)
 166 #define SDRAM_DSIZE_256Mb           (0x1 << SDRAM_DSIZE_OFFS)
 167 #define SDRAM_DSIZE_512Mb           (0x2 << SDRAM_DSIZE_OFFS)
 168
 169 /* SDRAM Open Pages Control registers */
 170 #define SDRAM_OPEN_PAGE_CTRL_REG        0x1414
 171 #define SDRAM_OPEN_PAGE_EN                  (0 << 0)
 172 #define SDRAM_OPEN_PAGE_DIS                 (1 << 0)
 173
 174 /* sdram opertion register */
 175 #define SDRAM_OPERATION_REG     0x1418
 176 #define SDRAM_CMD_OFFS                  0
 177 #define SDRAM_CMD_MASK                  (0x7 << SDRAM_CMD_OFFS)
 178 #define SDRAM_CMD_NORMAL                (0x0 << SDRAM_CMD_OFFS)
 179 #define SDRAM_CMD_PRECHARGE_ALL (0x1 << SDRAM_CMD_OFFS)
 180 #define SDRAM_CMD_REFRESH_ALL   (0x2 << SDRAM_CMD_OFFS)
 181 #define SDRAM_CMD_REG_SET_CMD   (0x3 << SDRAM_CMD_OFFS)
 182 #define SDRAM_CMD_EXT_MODE_SET  (0x4 << SDRAM_CMD_OFFS)
 183 #define SDRAM_CMD_NOP                   (0x5 << SDRAM_CMD_OFFS)
 184 #define SDRAM_CMD_SLF_RFRSH     (0x7 << SDRAM_CMD_OFFS)
 185 #define SDRAM_CMD_EMRS2_CMD     (0x8 << SDRAM_CMD_OFFS)
 186 #define SDRAM_CMD_EMRS3_CMD     (0x9 << SDRAM_CMD_OFFS)
 187
 188 /* sdram mode register */
 189 #define SDRAM_MODE_REG                  0x141c
 190 #define SDRAM_BURST_LEN_OFFS    0
 191 #define SDRAM_BURST_LEN_MASK    (0x7 << SDRAM_BURST_LEN_OFFS)
 192 #define SDRAM_BURST_LEN_4       (0x2 << SDRAM_BURST_LEN_OFFS)
 193 #define SDRAM_CL_OFFS                   4
 194 #define SDRAM_CL_MASK                   (0x7 << SDRAM_CL_OFFS)
 195 #define SDRAM_DDR1_CL_2         (0x2 << SDRAM_CL_OFFS)
 196 #define SDRAM_DDR1_CL_3         (0x3 << SDRAM_CL_OFFS)
 197 #define SDRAM_DDR1_CL_4         (0x4 << SDRAM_CL_OFFS)
 198 #define SDRAM_DDR1_CL_1_5       (0x5 << SDRAM_CL_OFFS)
 199 #define SDRAM_DDR1_CL_2_5       (0x6 << SDRAM_CL_OFFS)
 200 #define SDRAM_DDR2_CL_3         (0x3 << SDRAM_CL_OFFS)
 201 #define SDRAM_DDR2_CL_4         (0x4 << SDRAM_CL_OFFS)
 202 #define SDRAM_DDR2_CL_5                 (0x5 << SDRAM_CL_OFFS)
 203 #define SDRAM_TM_OFFS           7
 204 #define SDRAM_TM_MASK           (1 << SDRAM_TM_OFFS)
 205 #define SDRAM_TM_NORMAL         (0 << SDRAM_TM_OFFS)
 206 #define SDRAM_TM_TEST_MODE      (1 << SDRAM_TM_OFFS)
 207 #define SDRAM_DLL_OFFS          8
 208 #define SDRAM_DLL_MASK          (1 << SDRAM_DLL_OFFS)
 209 #define SDRAM_DLL_NORMAL        (0 << SDRAM_DLL_OFFS)
 210 #define SDRAM_DLL_RESET         (1 << SDRAM_DLL_OFFS)
 211 #define SDRAM_WR_OFFS           11
 212 #define SDRAM_WR_MAX            7
 213 #define SDRAM_WR_MASK           (SDRAM_WR_MAX << SDRAM_WR_OFFS)
 214 #define SDRAM_PD_OFFS           12
 215 #define SDRAM_PD_MASK           (1 << SDRAM_PD_OFFS)
 216 #define SDRAM_PD_FAST_EXIT      (0 << SDRAM_PD_OFFS)
 217 #define SDRAM_PD_SLOW_EXIT      (1 << SDRAM_PD_OFFS)
 218
 219 /* DDR SDRAM Extended Mode register (DSEMR) */
 220 #define SDRAM_EXTENDED_MODE_REG 0x1420
 221 #define DSEMR_DLL_ENABLE                (1 << 0)
 222 #define DSEMR_DS_OFFS                   1
 223 #define DSEMR_DS_MASK                   (1 << DSEMR_DS_OFFS)
 224 #define DSEMR_DS_NORMAL                 (0 << DSEMR_DS_OFFS)
 225 #define DSEMR_DS_REDUCED                (1 << DSEMR_DS_OFFS)
 226 #define DSEMR_RTT0_OFFS                 2
 227 #define DSEMR_RTT1_OFFS                 6
 228 #define DSEMR_RTT_ODT_DISABLE   ((0 << DSEMR_RTT0_OFFS)||(0 << DSEMR_RTT1_OFFS))
 229 #define DSEMR_RTT_ODT_75_OHM    ((1 << DSEMR_RTT0_OFFS)||(0 << DSEMR_RTT1_OFFS))
 230 #define DSEMR_RTT_ODT_150_OHM   ((0 << DSEMR_RTT0_OFFS)||(1 << DSEMR_RTT1_OFFS))
 231 #define DSEMR_OCD_OFFS                  7
 232 #define DSEMR_OCD_MASK                  (0x7 << DSEMR_OCD_OFFS)
 233 #define DSEMR_OCD_EXIT_CALIB    (0 << DSEMR_OCD_OFFS)
 234 #define DSEMR_OCD_DRIVE1                (1 << DSEMR_OCD_OFFS)
 235 #define DSEMR_OCD_DRIVE0                (2 << DSEMR_OCD_OFFS)
 236 #define DSEMR_OCD_ADJUST_MODE   (4 << DSEMR_OCD_OFFS)
 237 #define DSEMR_OCD_CALIB_DEFAULT (7 << DSEMR_OCD_OFFS)
 238 #define DSEMR_DQS_OFFS                  10
 239 #define DSEMR_DQS_MASK                  (1 << DSEMR_DQS_OFFS)
 240 #define DSEMR_DQS_DIFFERENTIAL  (0 << DSEMR_DQS_OFFS)
 241 #define DSEMR_DQS_SINGLE_ENDED  (0 << DSEMR_DQS_OFFS)
 242 #define DSEMR_RDQS_ENABLE               (1 << 11)
 243 #define DSEMR_QOFF_OUTPUT_BUFF_EN       (1 << 12)
 244
 245 /* DDR SDRAM Operation Control Register */
 246 #define SDRAM_OPERATION_CTRL_REG        0x142c
 247
 248 /* Dunit FTDLL Configuration Register */
 249 #define SDRAM_FTDLL_CONFIG_REG                  0x1484
 250
 251 /* Pads Calibration register */
 252 #define SDRAM_ADDR_CTRL_PADS_CAL_REG    0x14c0
 253 #define SDRAM_DATA_PADS_CAL_REG         0x14c4
 254 #define SDRAM_DRVN_OFFS                                 0
 255 #define SDRAM_DRVN_MASK                                 (0x3F << SDRAM_DRVN_OFFS)
 256 #define SDRAM_DRVP_OFFS                                 6
 257 #define SDRAM_DRVP_MASK                                 (0x3F << SDRAM_DRVP_OFFS)
 258 #define SDRAM_PRE_DRIVER_STRENGTH_OFFS  12
 259 #define SDRAM_PRE_DRIVER_STRENGTH_MASK  (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
 260 #define SDRAM_TUNE_EN                   BIT16
 261 #define SDRAM_LOCK_OFFS                 17
 262 #define SDRAM_LOCK_MAKS                 (0x1F << SDRAM_LOCK_OFFS)
 263 #define SDRAM_LOCKN_OFFS                17
 264 #define SDRAM_LOCKN_MAKS                (0x3F << SDRAM_LOCKN_OFFS)
 265 #define SDRAM_LOCKP_OFFS                23
 266 #define SDRAM_LOCKP_MAKS                (0x3F << SDRAM_LOCKP_OFFS)
 267 #define SDRAM_WR_EN                     (1 << 31)
 268
 269 /* DDR2 SDRAM ODT Control (Low) Register (DSOCLR) */
 270 #define DDR2_SDRAM_ODT_CTRL_LOW_REG  0x1494
 271 #define DSOCLR_ODT_RD_OFFS(odtNum)   (odtNum * 4)
 272 #define DSOCLR_ODT_RD_MASK(odtNum)   (0xf << DSOCLR_ODT_RD_OFFS(odtNum))
 273 #define DSOCLR_ODT_RD(odtNum, bank)  ((1 << bank) << DSOCLR_ODT_RD_OFFS(odtNum))
 274 #define DSOCLR_ODT_WR_OFFS(odtNum)   (16 + (odtNum * 4))
 275 #define DSOCLR_ODT_WR_MASK(odtNum)   (0xf << DSOCLR_ODT_WR_OFFS(odtNum))
 276 #define DSOCLR_ODT_WD(odtNum, bank)  ((1 << bank) << DSOCLR_ODT_WR_OFFS(odtNum))
 277
 278 /* DDR2 SDRAM ODT Control (High) Register (DSOCHR) */
 279 #define DDR2_SDRAM_ODT_CTRL_HIGH_REG    0x1498
 280 /* Optional control values to DSOCHR_ODT_EN macro */
 281 #define DDR2_ODT_CTRL_DUNIT         0
 282 #define DDR2_ODT_CTRL_NEVER         1
 283 #define DDR2_ODT_CTRL_ALWAYS        3
 284 #define DSOCHR_ODT_EN_OFFS(odtNum)  (odtNum * 2)
 285 #define DSOCHR_ODT_EN_MASK(odtNum)  (0x3 << DSOCHR_ODT_EN_OFFS(odtNum))
 286 #define DSOCHR_ODT_EN(odtNum, ctrl) ((1 << ctrl) << DSOCHR_ODT_RD_OFFS(odtNum))
 287
 288 /* DDR2 Dunit ODT Control Register (DDOCR)*/
 289 #define DDR2_DUNIT_ODT_CONTROL_REG  0x149c
 290 #define DDOCR_ODT_RD_OFFS           0
 291 #define DDOCR_ODT_RD_MASK           (0xf << DDOCR_ODT_RD_OFFS)
 292 #define DDOCR_ODT_RD(bank)          ((1 << bank) << DDOCR_ODT_RD_OFFS)
 293 #define DDOCR_ODT_WR_OFFS           4
 294 #define DDOCR_ODT_WR_MASK           (0xf << DDOCR_ODT_WR_OFFS)
 295 #define DDOCR_ODT_WR(bank)          ((1 << bank) << DDOCR_ODT_WR_OFFS)
 296 #define DSOCR_ODT_EN_OFFS           8
 297 #define DSOCR_ODT_EN_MASK           (0x3 << DSOCR_ODT_EN_OFFS)
 298 #define DSOCR_ODT_EN(ctrl)          ((1 << ctrl) << DSOCR_ODT_EN_OFFS)
 299 #define DSOCR_ODT_SEL_OFFS          10
 300 #define DSOCR_ODT_SEL_MASK          (0x3 << DSOCR_ODT_SEL_OFFS)
 301
 302 /* DDR SDRAM Initialization Control Register (DSICR) */
 303 #define DDR_SDRAM_INIT_CTRL_REG         0x1480
 304 #define DSICR_INIT_EN                           (1 << 0)
 305
 306 #endif /* __INCmvDramIfRegsh */