target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h

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  64
  65
  66 #ifndef __INCmvEthRegsh
  67 #define __INCmvEthRegsh
  68
  69 #ifdef __cplusplus
  70 extern "C" {
  71 #endif /* __cplusplus */
  72
  73 #include "ctrlEnv/mvCtrlEnvSpec.h"
  74
  75 /****************************************/
  76 /*        Ethernet Unit Registers       */
  77 /****************************************/
  78 #define ETH_REG_BASE                                    MV_ETH_REG_BASE
  79
  80 #define ETH_PHY_ADDR_REG(port)              (ETH_REG_BASE(port) + 0x000)
  81 #define ETH_SMI_REG(port)                   (ETH_REG_BASE(port) + 0x004)
  82 #define ETH_UNIT_DEF_ADDR_REG(port)         (ETH_REG_BASE(port) + 0x008)
  83 #define ETH_UNIT_DEF_ID_REG(port)           (ETH_REG_BASE(port) + 0x00c)
  84 #define ETH_UNIT_RESERVED(port)             (ETH_REG_BASE(port) + 0x014)
  85 #define ETH_UNIT_INTR_CAUSE_REG(port)       (ETH_REG_BASE(port) + 0x080)
  86 #define ETH_UNIT_INTR_MASK_REG(port)        (ETH_REG_BASE(port) + 0x084)
  87
  88
  89 #define ETH_UNIT_ERROR_ADDR_REG(port)       (ETH_REG_BASE(port) + 0x094)
  90 #define ETH_UNIT_INT_ADDR_ERROR_REG(port)   (ETH_REG_BASE(port) + 0x098)
  91 #define ETH_UNIT_CONTROL_REG(port)          (ETH_REG_BASE(port) + 0x0B0)
  92
  93 #define ETH_PORT_CONFIG_REG(port)           (ETH_REG_BASE(port) + 0x400)
  94 #define ETH_PORT_CONFIG_EXTEND_REG(port)    (ETH_REG_BASE(port) + 0x404)
  95 #define ETH_MII_SERIAL_PARAM_REG(port)      (ETH_REG_BASE(port) + 0x408)
  96 #define ETH_GMII_SERIAL_PARAM_REG(port)     (ETH_REG_BASE(port) + 0x40c)
  97 #define ETH_VLAN_ETHER_TYPE_REG(port)       (ETH_REG_BASE(port) + 0x410)
  98 #define ETH_MAC_ADDR_LOW_REG(port)          (ETH_REG_BASE(port) + 0x414)
  99 #define ETH_MAC_ADDR_HIGH_REG(port)         (ETH_REG_BASE(port) + 0x418)
 100 #define ETH_SDMA_CONFIG_REG(port)           (ETH_REG_BASE(port) + 0x41c)
 101 #define ETH_DIFF_SERV_PRIO_REG(port, code)  (ETH_REG_BASE(port) + 0x420  + ((code)<<2))
 102 #define ETH_PORT_SERIAL_CTRL_REG(port)      (ETH_REG_BASE(port) + 0x43c)
 103 #define ETH_VLAN_TAG_TO_PRIO_REG(port)      (ETH_REG_BASE(port) + 0x440)
 104 #define ETH_PORT_STATUS_REG(port)           (ETH_REG_BASE(port) + 0x444)
 105
 106 #define ETH_RX_QUEUE_COMMAND_REG(port)      (ETH_REG_BASE(port) + 0x680)
 107 #define ETH_TX_QUEUE_COMMAND_REG(port)      (ETH_REG_BASE(port) + 0x448)
 108
 109 #define ETH_PORT_SERIAL_CTRL_1_REG(port)    (ETH_REG_BASE(port) + 0x44c)
 110 #define ETH_PORT_STATUS_1_REG(port)         (ETH_REG_BASE(port) + 0x450)
 111 #define ETH_PORT_MARVELL_HEADER_REG(port)   (ETH_REG_BASE(port) + 0x454)
 112 #define ETH_PORT_FIFO_PARAMS_REG(port)      (ETH_REG_BASE(port) + 0x458)
 113 #define ETH_MAX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x45c)
 114 #define ETH_INTR_CAUSE_REG(port)            (ETH_REG_BASE(port) + 0x460)
 115 #define ETH_INTR_CAUSE_EXT_REG(port)        (ETH_REG_BASE(port) + 0x464)
 116 #define ETH_INTR_MASK_REG(port)             (ETH_REG_BASE(port) + 0x468)
 117 #define ETH_INTR_MASK_EXT_REG(port)         (ETH_REG_BASE(port) + 0x46c)
 118 #define ETH_TX_FIFO_URGENT_THRESH_REG(port) (ETH_REG_BASE(port) + 0x474)
 119 #define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (ETH_REG_BASE(port) + 0x47c)
 120 #define ETH_RX_DISCARD_PKTS_CNTR_REG(port)  (ETH_REG_BASE(port) + 0x484)
 121 #define ETH_RX_OVERRUN_PKTS_CNTR_REG(port)  (ETH_REG_BASE(port) + 0x488)
 122 #define ETH_INTERNAL_ADDR_ERROR_REG(port)   (ETH_REG_BASE(port) + 0x494)
 123 #define ETH_TX_FIXED_PRIO_CFG_REG(port)     (ETH_REG_BASE(port) + 0x4dc)
 124 #define ETH_TX_TOKEN_RATE_CFG_REG(port)     (ETH_REG_BASE(port) + 0x4e0)
 125 #define ETH_TX_QUEUE_COMMAND1_REG(port)     (ETH_REG_BASE(port) + 0x4e4)
 126 #define ETH_MAX_TRANSMIT_UNIT_REG(port)     (ETH_REG_BASE(port) + 0x4e8)
 127 #define ETH_TX_TOKEN_BUCKET_SIZE_REG(port)  (ETH_REG_BASE(port) + 0x4ec)
 128 #define ETH_TX_TOKEN_BUCKET_COUNT_REG(port) (ETH_REG_BASE(port) + 0x780)
 129 #define ETH_RX_DESCR_STAT_CMD_REG(port, q)  (ETH_REG_BASE(port) + 0x600 + ((q)<<4))
 130 #define ETH_RX_BYTE_COUNT_REG(port, q)      (ETH_REG_BASE(port) + 0x604 + ((q)<<4))
 131 #define ETH_RX_BUF_PTR_REG(port, q)         (ETH_REG_BASE(port) + 0x608 + ((q)<<4))
 132 #define ETH_RX_CUR_DESC_PTR_REG(port, q)    (ETH_REG_BASE(port) + 0x60c + ((q)<<4))
 133 #define ETH_TX_CUR_DESC_PTR_REG(port, q)    (ETH_REG_BASE(port) + 0x6c0 + ((q)<<2))
 134
 135 #define ETH_TXQ_TOKEN_COUNT_REG(port, q)    (ETH_REG_BASE(port) + 0x700 + ((q)<<4))
 136 #define ETH_TXQ_TOKEN_CFG_REG(port, q)      (ETH_REG_BASE(port) + 0x704 + ((q)<<4))
 137 #define ETH_TXQ_ARBITER_CFG_REG(port, q)    (ETH_REG_BASE(port) + 0x708 + ((q)<<4))
 138
 139 #if (MV_ETH_VERSION >= 4)
 140 #define ETH_TXQ_CMD_1_REG(port)             (ETH_REG_BASE(port) + 0x4E4)
 141 #define ETH_EJP_TX_HI_IPG_REG(port)         (ETH_REG_BASE(port) + 0x7A8)
 142 #define ETH_EJP_TX_LO_IPG_REG(port)         (ETH_REG_BASE(port) + 0x7B8)
 143 #define ETH_EJP_HI_TKN_LO_PKT_REG(port)     (ETH_REG_BASE(port) + 0x7C0)
 144 #define ETH_EJP_HI_TKN_ASYNC_PKT_REG(port)  (ETH_REG_BASE(port) + 0x7C4)
 145 #define ETH_EJP_LO_TKN_ASYNC_PKT_REG(port)  (ETH_REG_BASE(port) + 0x7C8)
 146 #define ETH_EJP_TX_SPEED_REG(port)          (ETH_REG_BASE(port) + 0x7D0)
 147 #endif /* MV_ETH_VERSION >= 4 */
 148
 149 #define ETH_MIB_COUNTERS_BASE(port)         (ETH_REG_BASE(port) + 0x1000)
 150 #define ETH_DA_FILTER_SPEC_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1400)
 151 #define ETH_DA_FILTER_OTH_MCAST_BASE(port)  (ETH_REG_BASE(port) + 0x1500)
 152 #define ETH_DA_FILTER_UCAST_BASE(port)      (ETH_REG_BASE(port) + 0x1600)
 153
 154 /* Phy address register definitions */
 155 #define ETH_PHY_ADDR_OFFS          0
 156 #define ETH_PHY_ADDR_MASK          (0x1f <<ETH_PHY_ADDR_OFFS)
 157
 158 /* MIB Counters register definitions */
 159 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW    0x0
 160 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH   0x4
 161 #define ETH_MIB_BAD_OCTETS_RECEIVED         0x8
 162 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR   0xc
 163 #define ETH_MIB_GOOD_FRAMES_RECEIVED        0x10
 164 #define ETH_MIB_BAD_FRAMES_RECEIVED         0x14
 165 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED   0x18
 166 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED   0x1c
 167 #define ETH_MIB_FRAMES_64_OCTETS            0x20
 168 #define ETH_MIB_FRAMES_65_TO_127_OCTETS     0x24
 169 #define ETH_MIB_FRAMES_128_TO_255_OCTETS    0x28
 170 #define ETH_MIB_FRAMES_256_TO_511_OCTETS    0x2c
 171 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS   0x30
 172 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS   0x34
 173 #define ETH_MIB_GOOD_OCTETS_SENT_LOW        0x38
 174 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH       0x3c
 175 #define ETH_MIB_GOOD_FRAMES_SENT            0x40
 176 #define ETH_MIB_EXCESSIVE_COLLISION         0x44
 177 #define ETH_MIB_MULTICAST_FRAMES_SENT       0x48
 178 #define ETH_MIB_BROADCAST_FRAMES_SENT       0x4c
 179 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED  0x50
 180 #define ETH_MIB_FC_SENT                     0x54
 181 #define ETH_MIB_GOOD_FC_RECEIVED            0x58
 182 #define ETH_MIB_BAD_FC_RECEIVED             0x5c
 183 #define ETH_MIB_UNDERSIZE_RECEIVED          0x60
 184 #define ETH_MIB_FRAGMENTS_RECEIVED          0x64
 185 #define ETH_MIB_OVERSIZE_RECEIVED           0x68
 186 #define ETH_MIB_JABBER_RECEIVED             0x6c
 187 #define ETH_MIB_MAC_RECEIVE_ERROR           0x70
 188 #define ETH_MIB_BAD_CRC_EVENT               0x74
 189 #define ETH_MIB_COLLISION                   0x78
 190 #define ETH_MIB_LATE_COLLISION              0x7c
 191
 192
 193 /****************************************/
 194 /*        Ethernet Unit Register BITs   */
 195 /****************************************/
 196
 197 #define ETH_RXQ_ENABLE_OFFSET               0
 198 #define ETH_RXQ_ENABLE_MASK                 (0x000000FF << ETH_RXQ_ENABLE_OFFSET)
 199
 200 #define ETH_RXQ_DISABLE_OFFSET              8
 201 #define ETH_RXQ_DISABLE_MASK                (0x000000FF << ETH_RXQ_DISABLE_OFFSET)
 202
 203 /***** BITs of Transmit Queue Command (TQC) register *****/
 204 #define ETH_TXQ_ENABLE_OFFSET               0
 205 #define ETH_TXQ_ENABLE_MASK                 (0x000000FF << ETH_TXQ_ENABLE_OFFSET)
 206
 207 #define ETH_TXQ_DISABLE_OFFSET              8
 208 #define ETH_TXQ_DISABLE_MASK                (0x000000FF << ETH_TXQ_DISABLE_OFFSET)
 209
 210 #if (MV_ETH_VERSION >= 4)
 211 #define ETH_TX_EJP_RESET_BIT                0
 212 #define ETH_TX_EJP_RESET_MASK               (1 << ETH_TX_EJP_RESET_BIT)
 213
 214 #define ETH_TX_EJP_ENABLE_BIT               2
 215 #define ETH_TX_EJP_ENABLE_MASK              (1 << ETH_TX_EJP_ENABLE_BIT)
 216
 217 #define ETH_TX_LEGACY_WRR_BIT               3
 218 #define ETH_TX_LEGACY_WRR_MASK              (1 << ETH_TX_LEGACY_WRR_BIT)
 219 #endif /* (MV_ETH_VERSION >= 4) */
 220
 221 /***** BITs of Ethernet Port Status reg (PSR) *****/
 222 #define ETH_LINK_UP_BIT                     1
 223 #define ETH_LINK_UP_MASK                    (1<<ETH_LINK_UP_BIT)
 224
 225 #define ETH_FULL_DUPLEX_BIT                 2
 226 #define ETH_FULL_DUPLEX_MASK                (1<<ETH_FULL_DUPLEX_BIT)
 227
 228 #define ETH_ENABLE_RCV_FLOW_CTRL_BIT        3
 229 #define ETH_ENABLE_RCV_FLOW_CTRL_MASK       (1<<ETH_ENABLE_RCV_FLOW_CTRL_BIT)
 230
 231 #define ETH_GMII_SPEED_1000_BIT             4
 232 #define ETH_GMII_SPEED_1000_MASK            (1<<ETH_GMII_SPEED_1000_BIT)
 233
 234 #define ETH_MII_SPEED_100_BIT               5
 235 #define ETH_MII_SPEED_100_MASK              (1<<ETH_MII_SPEED_100_BIT)
 236
 237 #define ETH_TX_IN_PROGRESS_BIT              7
 238 #define ETH_TX_IN_PROGRESS_MASK             (1<<ETH_TX_IN_PROGRESS_BIT)
 239
 240 #define ETH_TX_FIFO_EMPTY_BIT               10
 241 #define ETH_TX_FIFO_EMPTY_MASK              (1<<ETH_TX_FIFO_EMPTY_BIT)
 242
 243 /***** BITs of Ethernet Port Status 1 reg (PS1R) *****/
 244 #define ETH_AUTO_NEG_DONE_BIT               4
 245 #define ETH_AUTO_NEG_DONE_MASK              (1<<ETH_AUTO_NEG_DONE_BIT)
 246
 247 #define ETH_SERDES_PLL_LOCKED_BIT           6
 248 #define ETH_SERDES_PLL_LOCKED_MASK          (1<<ETH_SERDES_PLL_LOCKED_BIT)
 249
 250 /***** BITs of Port Configuration reg (PxCR) *****/
 251 #define ETH_UNICAST_PROMISCUOUS_MODE_BIT    0
 252 #define ETH_UNICAST_PROMISCUOUS_MODE_MASK   (1<<ETH_UNICAST_PROMISCUOUS_MODE_BIT)
 253
 254 #define ETH_DEF_RX_QUEUE_OFFSET             1
 255 #define ETH_DEF_RX_QUEUE_ALL_MASK           (0x7<<ETH_DEF_RX_QUEUE_OFFSET)
 256 #define ETH_DEF_RX_QUEUE_MASK(queue)        ((queue)<<ETH_DEF_RX_QUEUE_OFFSET)
 257
 258 #define ETH_DEF_RX_ARP_QUEUE_OFFSET         4
 259 #define ETH_DEF_RX_ARP_QUEUE_ALL_MASK       (0x7<<ETH_DEF_RX_ARP_QUEUE_OFFSET)
 260 #define ETH_DEF_RX_ARP_QUEUE_MASK(queue)    ((queue)<<ETH_DEF_RX_ARP_QUEUE_OFFSET)
 261
 262 #define ETH_REJECT_NOT_IP_ARP_BCAST_BIT     7
 263 #define ETH_REJECT_NOT_IP_ARP_BCAST_MASK    (1<<ETH_REJECT_NOT_IP_ARP_BCAST_BIT)
 264
 265 #define ETH_REJECT_IP_BCAST_BIT             8
 266 #define ETH_REJECT_IP_BCAST_MASK            (1<<ETH_REJECT_IP_BCAST_BIT)
 267
 268 #define ETH_REJECT_ARP_BCAST_BIT            9
 269 #define ETH_REJECT_ARP_BCAST_MASK           (1<<ETH_REJECT_ARP_BCAST_BIT)
 270
 271 #define ETH_TX_NO_SET_ERROR_SUMMARY_BIT     12
 272 #define ETH_TX_NO_SET_ERROR_SUMMARY_MASK    (1<<ETH_TX_NO_SET_ERROR_SUMMARY_BIT)
 273
 274 #define ETH_CAPTURE_TCP_FRAMES_ENABLE_BIT   14
 275 #define ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK  (1<<ETH_CAPTURE_TCP_FRAMES_ENABLE_BIT)
 276
 277 #define ETH_CAPTURE_UDP_FRAMES_ENABLE_BIT   15
 278 #define ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK  (1<<ETH_CAPTURE_UDP_FRAMES_ENABLE_BIT)
 279
 280 #define ETH_DEF_RX_TCP_QUEUE_OFFSET         16
 281 #define ETH_DEF_RX_TCP_QUEUE_ALL_MASK       (0x7<<ETH_DEF_RX_TCP_QUEUE_OFFSET)
 282 #define ETH_DEF_RX_TCP_QUEUE_MASK(queue)    ((queue)<<ETH_DEF_RX_TCP_QUEUE_OFFSET)
 283
 284 #define ETH_DEF_RX_UDP_QUEUE_OFFSET         19
 285 #define ETH_DEF_RX_UDP_QUEUE_ALL_MASK       (0x7<<ETH_DEF_RX_UDP_QUEUE_OFFSET)
 286 #define ETH_DEF_RX_UDP_QUEUE_MASK(queue)    ((queue)<<ETH_DEF_RX_UDP_QUEUE_OFFSET)
 287
 288 #define ETH_DEF_RX_BPDU_QUEUE_OFFSET        22
 289 #define ETH_DEF_RX_BPDU_QUEUE_ALL_MASK      (0x7<<ETH_DEF_RX_BPDU_QUEUE_OFFSET)
 290 #define ETH_DEF_RX_BPDU_QUEUE_MASK(queue)   ((queue)<<ETH_DEF_RX_BPDU_QUEUE_OFFSET)
 291
 292 #define ETH_RX_CHECKSUM_MODE_OFFSET         25
 293 #define ETH_RX_CHECKSUM_NO_PSEUDO_HDR       (0<<ETH_RX_CHECKSUM_MODE_OFFSET)
 294 #define ETH_RX_CHECKSUM_WITH_PSEUDO_HDR     (1<<ETH_RX_CHECKSUM_MODE_OFFSET)
 295
 296 /***** BITs of Port Configuration Extend reg (PxCXR) *****/
 297 #define ETH_CAPTURE_SPAN_BPDU_ENABLE_BIT    1
 298 #define ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK   (1<<ETH_CAPTURE_SPAN_BPDU_ENABLE_BIT)
 299
 300 #define ETH_TX_DISABLE_GEN_CRC_BIT          3
 301 #define ETH_TX_DISABLE_GEN_CRC_MASK         (1<<ETH_TX_DISABLE_GEN_CRC_BIT)
 302
 303 /***** BITs of Tx/Rx queue command reg (RQCR/TQCR) *****/
 304 #define ETH_QUEUE_ENABLE_OFFSET             0
 305 #define ETH_QUEUE_ENABLE_ALL_MASK           (0xFF<<ETH_QUEUE_ENABLE_OFFSET)
 306 #define ETH_QUEUE_ENABLE_MASK(queue)        (1<<((queue)+ETH_QUEUE_ENABLE_OFFSET))
 307
 308 #define ETH_QUEUE_DISABLE_OFFSET            8
 309 #define ETH_QUEUE_DISABLE_ALL_MASK          (0xFF<<ETH_QUEUE_DISABLE_OFFSET)
 310 #define ETH_QUEUE_DISABLE_MASK(queue)       (1<<((queue)+ETH_QUEUE_DISABLE_OFFSET))
 311
 312
 313 /***** BITs of Port Sdma Configuration reg (SDCR) *****/
 314 #define ETH_RX_FRAME_INTERRUPT_BIT          0
 315 #define ETH_RX_FRAME_INTERRUPT_MASK         (1<<ETH_RX_FRAME_INTERRUPT_BIT)
 316
 317 #define ETH_BURST_SIZE_1_64BIT_VALUE        0
 318 #define ETH_BURST_SIZE_2_64BIT_VALUE        1
 319 #define ETH_BURST_SIZE_4_64BIT_VALUE        2
 320 #define ETH_BURST_SIZE_8_64BIT_VALUE        3
 321 #define ETH_BURST_SIZE_16_64BIT_VALUE       4
 322
 323 #define ETH_RX_BURST_SIZE_OFFSET            1
 324 #define ETH_RX_BURST_SIZE_ALL_MASK          (0x7<<ETH_RX_BURST_SIZE_OFFSET)
 325 #define ETH_RX_BURST_SIZE_MASK(burst)       ((burst)<<ETH_RX_BURST_SIZE_OFFSET)
 326
 327 #define ETH_RX_NO_DATA_SWAP_BIT             4
 328 #define ETH_RX_NO_DATA_SWAP_MASK            (1<<ETH_RX_NO_DATA_SWAP_BIT)
 329 #define ETH_RX_DATA_SWAP_MASK               (0<<ETH_RX_NO_DATA_SWAP_BIT)
 330
 331 #define ETH_TX_NO_DATA_SWAP_BIT             5
 332 #define ETH_TX_NO_DATA_SWAP_MASK            (1<<ETH_TX_NO_DATA_SWAP_BIT)
 333 #define ETH_TX_DATA_SWAP_MASK               (0<<ETH_TX_NO_DATA_SWAP_BIT)
 334
 335 #define ETH_DESC_SWAP_BIT                   6
 336 #define ETH_DESC_SWAP_MASK                  (1<<ETH_DESC_SWAP_BIT)
 337 #define ETH_NO_DESC_SWAP_MASK               (0<<ETH_DESC_SWAP_BIT)
 338
 339 #define ETH_RX_INTR_COAL_OFFSET             7
 340 #define ETH_RX_INTR_COAL_ALL_MASK           (0x3fff<<ETH_RX_INTR_COAL_OFFSET)
 341 #define ETH_RX_INTR_COAL_MASK(value)        (((value)<<ETH_RX_INTR_COAL_OFFSET)  \
 342                                              & ETH_RX_INTR_COAL_ALL_MASK)
 343
 344 #define ETH_TX_BURST_SIZE_OFFSET            22
 345 #define ETH_TX_BURST_SIZE_ALL_MASK          (0x7<<ETH_TX_BURST_SIZE_OFFSET)
 346 #define ETH_TX_BURST_SIZE_MASK(burst)       ((burst)<<ETH_TX_BURST_SIZE_OFFSET)
 347
 348 #define ETH_RX_INTR_COAL_MSB_BIT            25
 349 #define ETH_RX_INTR_COAL_MSB_MASK           (1<<ETH_RX_INTR_COAL_MSB_BIT)
 350
 351 /* BITs Port #x Tx FIFO Urgent Threshold (PxTFUT) */
 352 #define ETH_TX_INTR_COAL_OFFSET             4
 353 #define ETH_TX_INTR_COAL_ALL_MASK           (0x3fff << ETH_TX_INTR_COAL_OFFSET)
 354 #define ETH_TX_INTR_COAL_MASK(value)        (((value) << ETH_TX_INTR_COAL_OFFSET)  \
 355                                              & ETH_TX_INTR_COAL_ALL_MASK)
 356
 357 /* BITs of Port Serial Control reg (PSCR) */
 358 #define ETH_PORT_ENABLE_BIT                 0
 359 #define ETH_PORT_ENABLE_MASK                (1<<ETH_PORT_ENABLE_BIT)
 360
 361 #define ETH_FORCE_LINK_PASS_BIT             1
 362 #define ETH_FORCE_LINK_PASS_MASK            (1<<ETH_FORCE_LINK_PASS_BIT)
 363
 364 #define ETH_DISABLE_DUPLEX_AUTO_NEG_BIT     2
 365 #define ETH_DISABLE_DUPLEX_AUTO_NEG_MASK    (1<<ETH_DISABLE_DUPLEX_AUTO_NEG_BIT)
 366
 367 #define ETH_DISABLE_FC_AUTO_NEG_BIT         3
 368 #define ETH_DISABLE_FC_AUTO_NEG_MASK        (1<<ETH_DISABLE_FC_AUTO_NEG_BIT)
 369
 370 #define ETH_ADVERTISE_SYM_FC_BIT            4
 371 #define ETH_ADVERTISE_SYM_FC_MASK           (1<<ETH_ADVERTISE_SYM_FC_BIT)
 372
 373 #define ETH_TX_FC_MODE_OFFSET               5
 374 #define ETH_TX_FC_MODE_MASK                 (3<<ETH_TX_FC_MODE_OFFSET)
 375 #define ETH_TX_FC_NO_PAUSE                  (0<<ETH_TX_FC_MODE_OFFSET)
 376 #define ETH_TX_FC_SEND_PAUSE                (1<<ETH_TX_FC_MODE_OFFSET)
 377
 378 #define ETH_TX_BP_MODE_OFFSET               7
 379 #define ETH_TX_BP_MODE_MASK                 (3<<ETH_TX_BP_MODE_OFFSET)
 380 #define ETH_TX_BP_NO_JAM                    (0<<ETH_TX_BP_MODE_OFFSET)
 381 #define ETH_TX_BP_SEND_JAM                  (1<<ETH_TX_BP_MODE_OFFSET)
 382
 383 #define ETH_DO_NOT_FORCE_LINK_FAIL_BIT      10
 384 #define ETH_DO_NOT_FORCE_LINK_FAIL_MASK     (1<<ETH_DO_NOT_FORCE_LINK_FAIL_BIT)
 385
 386 #define ETH_RETRANSMIT_FOREVER_BIT          11
 387 #define ETH_RETRANSMIT_FOREVER_MASK         (1<<ETH_RETRANSMIT_FOREVER_BIT)
 388
 389 #define ETH_DISABLE_SPEED_AUTO_NEG_BIT      13
 390 #define ETH_DISABLE_SPEED_AUTO_NEG_MASK     (1<<ETH_DISABLE_SPEED_AUTO_NEG_BIT)
 391
 392 #define ETH_DTE_ADVERT_BIT                  14
 393 #define ETH_DTE_ADVERT_MASK                 (1<<ETH_DTE_ADVERT_BIT)
 394
 395 #define ETH_MII_PHY_MODE_BIT                15
 396 #define ETH_MII_PHY_MODE_MAC                (0<<ETH_MII_PHY_MODE_BIT)
 397 #define ETH_MII_PHY_MODE_PHY                (1<<ETH_MII_PHY_MODE_BIT)
 398
 399 #define ETH_MII_SOURCE_SYNCH_BIT            16
 400 #define ETH_MII_STANDARD_SYNCH              (0<<ETH_MII_SOURCE_SYNCH_BIT)
 401 #define ETH_MII_400Mbps_SYNCH               (1<<ETH_MII_SOURCE_CLK_BIT)
 402
 403 #define ETH_MAX_RX_PACKET_SIZE_OFFSET       17
 404 #define ETH_MAX_RX_PACKET_SIZE_MASK         (7<<ETH_MAX_RX_PACKET_SIZE_OFFSET)
 405 #define ETH_MAX_RX_PACKET_1518BYTE          (0<<ETH_MAX_RX_PACKET_SIZE_OFFSET)
 406 #define ETH_MAX_RX_PACKET_1522BYTE          (1<<ETH_MAX_RX_PACKET_SIZE_OFFSET)
 407 #define ETH_MAX_RX_PACKET_1552BYTE          (2<<ETH_MAX_RX_PACKET_SIZE_OFFSET)
 408 #define ETH_MAX_RX_PACKET_9022BYTE          (3<<ETH_MAX_RX_PACKET_SIZE_OFFSET)
 409 #define ETH_MAX_RX_PACKET_9192BYTE          (4<<ETH_MAX_RX_PACKET_SIZE_OFFSET)
 410 #define ETH_MAX_RX_PACKET_9700BYTE          (5<<ETH_MAX_RX_PACKET_SIZE_OFFSET)
 411
 412 #define ETH_SET_FULL_DUPLEX_BIT             21
 413 #define ETH_SET_FULL_DUPLEX_MASK            (1<<ETH_SET_FULL_DUPLEX_BIT)
 414
 415 #define ETH_SET_FLOW_CTRL_BIT               22
 416 #define ETH_SET_FLOW_CTRL_MASK              (1<<ETH_SET_FLOW_CTRL_BIT)
 417
 418 #define ETH_SET_GMII_SPEED_1000_BIT         23
 419 #define ETH_SET_GMII_SPEED_1000_MASK        (1<<ETH_SET_GMII_SPEED_1000_BIT)
 420
 421 #define ETH_SET_MII_SPEED_100_BIT           24
 422 #define ETH_SET_MII_SPEED_100_MASK          (1<<ETH_SET_MII_SPEED_100_BIT)
 423
 424 /* BITs of Port Serial Control 1 reg (PSC1R) */
 425 #define ETH_PSC_ENABLE_BIT                  2
 426 #define ETH_PSC_ENABLE_MASK                 (1<<ETH_PSC_ENABLE_BIT)
 427
 428 #define ETH_RGMII_ENABLE_BIT                3
 429 #define ETH_RGMII_ENABLE_MASK               (1<<ETH_RGMII_ENABLE_BIT)
 430
 431 #define ETH_PORT_RESET_BIT                  4
 432 #define ETH_PORT_RESET_MASK                 (1<<ETH_PORT_RESET_BIT)
 433
 434 #define ETH_INBAND_AUTO_NEG_ENABLE_BIT      6
 435 #define ETH_INBAND_AUTO_NEG_ENABLE_MASK     (1<<ETH_INBAND_AUTO_NEG_ENABLE_BIT)
 436
 437 #define ETH_INBAND_AUTO_NEG_BYPASS_BIT      7
 438 #define ETH_INBAND_AUTO_NEG_BYPASS_MASK     (1<<ETH_INBAND_AUTO_NEG_BYPASS_BIT)
 439
 440 #define ETH_INBAND_AUTO_NEG_START_BIT       8
 441 #define ETH_INBAND_AUTO_NEG_START_MASK      (1<<ETH_INBAND_AUTO_NEG_START_BIT)
 442
 443 #define ETH_PORT_TYPE_BIT                   11
 444 #define ETH_PORT_TYPE_1000BasedX_MASK       (1<<ETH_PORT_TYPE_BIT)
 445
 446 #define ETH_SGMII_MODE_BIT                  12
 447 #define ETH_1000BaseX_MODE_MASK             (0<<ETH_SGMII_MODE_BIT)
 448 #define ETH_SGMII_MODE_MASK                 (1<<ETH_SGMII_MODE_BIT)
 449
 450 #define ETH_MGMII_MODE_BIT                  13
 451
 452 #define ETH_EN_MII_ODD_PRE_BIT              22
 453 #define ETH_EN_MII_ODD_PRE_MASK             (1<<ETH_EN_MII_ODD_PRE_BIT)
 454
 455 /* BITs of SDMA Descriptor Command/Status field */
 456 #if defined(MV_CPU_BE)
 457 typedef struct _ethRxDesc
 458 {
 459     MV_U16      byteCnt    ;    /* Descriptor buffer byte count     */
 460     MV_U16      bufSize    ;    /* Buffer size                      */
 461     MV_U32      cmdSts     ;    /* Descriptor command status        */
 462     MV_U32      nextDescPtr;    /* Next descriptor pointer          */
 463     MV_U32      bufPtr     ;    /* Descriptor buffer pointer        */
 464     MV_ULONG    returnInfo ;    /* User resource return information */
 465 } ETH_RX_DESC;
 466
 467 typedef struct _ethTxDesc
 468 {
 469     MV_U16      byteCnt    ;    /* Descriptor buffer byte count     */
 470     MV_U16      L4iChk     ;    /* CPU provided TCP Checksum        */
 471     MV_U32      cmdSts     ;    /* Descriptor command status        */
 472     MV_U32      nextDescPtr;    /* Next descriptor pointer          */
 473     MV_U32      bufPtr     ;    /* Descriptor buffer pointer        */
 474     MV_ULONG    returnInfo ;    /* User resource return information */
 475     MV_U8*      alignBufPtr;    /* Pointer to 8 byte aligned buffer */
 476 } ETH_TX_DESC;
 477
 478 #elif defined(MV_CPU_LE)
 479
 480 typedef struct _ethRxDesc
 481 {
 482     MV_U32      cmdSts     ;    /* Descriptor command status        */
 483     MV_U16      bufSize    ;    /* Buffer size                      */
 484     MV_U16      byteCnt    ;    /* Descriptor buffer byte count     */
 485     MV_U32      bufPtr     ;    /* Descriptor buffer pointer        */
 486     MV_U32      nextDescPtr;    /* Next descriptor pointer          */
 487     MV_ULONG    returnInfo ;    /* User resource return information */
 488 } ETH_RX_DESC;
 489
 490 typedef struct _ethTxDesc
 491 {
 492     MV_U32      cmdSts     ;    /* Descriptor command status        */
 493     MV_U16      L4iChk     ;    /* CPU provided TCP Checksum        */
 494     MV_U16      byteCnt    ;    /* Descriptor buffer byte count     */
 495     MV_U32      bufPtr     ;    /* Descriptor buffer pointer        */
 496     MV_U32      nextDescPtr;    /* Next descriptor pointer          */
 497     MV_ULONG    returnInfo ;    /* User resource return information */
 498     MV_U8*      alignBufPtr;    /* Pointer to 32 byte aligned buffer */
 499 } ETH_TX_DESC;
 500
 501 #else
 502 #error "MV_CPU_BE or MV_CPU_LE must be defined"
 503 #endif /* MV_CPU_BE || MV_CPU_LE */
 504
 505 /* Buffer offset from buffer pointer */
 506 #define ETH_RX_BUF_OFFSET               0x2
 507
 508
 509 /* Tx & Rx descriptor bits */
 510 #define ETH_ERROR_SUMMARY_BIT               0
 511 #define ETH_ERROR_SUMMARY_MASK              (1<<ETH_ERROR_SUMMARY_BIT)
 512
 513 #define ETH_BUFFER_OWNER_BIT                31
 514 #define ETH_BUFFER_OWNED_BY_DMA             (1<<ETH_BUFFER_OWNER_BIT)
 515 #define ETH_BUFFER_OWNED_BY_HOST            (0<<ETH_BUFFER_OWNER_BIT)
 516
 517 /* Tx descriptor bits */
 518 #define ETH_TX_ERROR_CODE_OFFSET            1
 519 #define ETH_TX_ERROR_CODE_MASK              (3<<ETH_TX_ERROR_CODE_OFFSET)
 520 #define ETH_TX_LATE_COLLISION_ERROR         (0<<ETH_TX_ERROR_CODE_OFFSET)
 521 #define ETH_TX_UNDERRUN_ERROR               (1<<ETH_TX_ERROR_CODE_OFFSET)
 522 #define ETH_TX_EXCESSIVE_COLLISION_ERROR    (2<<ETH_TX_ERROR_CODE_OFFSET)
 523
 524 #define ETH_TX_LLC_SNAP_FORMAT_BIT          9
 525 #define ETH_TX_LLC_SNAP_FORMAT_MASK         (1<<ETH_TX_LLC_SNAP_FORMAT_BIT)
 526
 527 #define ETH_TX_IP_FRAG_BIT                  10
 528 #define ETH_TX_IP_FRAG_MASK                 (1<<ETH_TX_IP_FRAG_BIT)
 529 #define ETH_TX_IP_FRAG                      (0<<ETH_TX_IP_FRAG_BIT)
 530 #define ETH_TX_IP_NO_FRAG                   (1<<ETH_TX_IP_FRAG_BIT)
 531
 532 #define ETH_TX_IP_HEADER_LEN_OFFSET         11
 533 #define ETH_TX_IP_HEADER_LEN_ALL_MASK       (0xF<<ETH_TX_IP_HEADER_LEN_OFFSET)
 534 #define ETH_TX_IP_HEADER_LEN_MASK(len)      ((len)<<ETH_TX_IP_HEADER_LEN_OFFSET)
 535
 536 #define ETH_TX_VLAN_TAGGED_FRAME_BIT        15
 537 #define ETH_TX_VLAN_TAGGED_FRAME_MASK       (1<<ETH_TX_VLAN_TAGGED_FRAME_BIT)
 538
 539 #define ETH_TX_L4_TYPE_BIT                  16
 540 #define ETH_TX_L4_TCP_TYPE                  (0<<ETH_TX_L4_TYPE_BIT)
 541 #define ETH_TX_L4_UDP_TYPE                  (1<<ETH_TX_L4_TYPE_BIT)
 542
 543 #define ETH_TX_GENERATE_L4_CHKSUM_BIT       17
 544 #define ETH_TX_GENERATE_L4_CHKSUM_MASK      (1<<ETH_TX_GENERATE_L4_CHKSUM_BIT)
 545
 546 #define ETH_TX_GENERATE_IP_CHKSUM_BIT       18
 547 #define ETH_TX_GENERATE_IP_CHKSUM_MASK      (1<<ETH_TX_GENERATE_IP_CHKSUM_BIT)
 548
 549 #define ETH_TX_ZERO_PADDING_BIT             19
 550 #define ETH_TX_ZERO_PADDING_MASK            (1<<ETH_TX_ZERO_PADDING_BIT)
 551
 552 #define ETH_TX_LAST_DESC_BIT                20
 553 #define ETH_TX_LAST_DESC_MASK               (1<<ETH_TX_LAST_DESC_BIT)
 554
 555 #define ETH_TX_FIRST_DESC_BIT               21
 556 #define ETH_TX_FIRST_DESC_MASK              (1<<ETH_TX_FIRST_DESC_BIT)
 557
 558 #define ETH_TX_GENERATE_CRC_BIT             22
 559 #define ETH_TX_GENERATE_CRC_MASK            (1<<ETH_TX_GENERATE_CRC_BIT)
 560
 561 #define ETH_TX_ENABLE_INTERRUPT_BIT         23
 562 #define ETH_TX_ENABLE_INTERRUPT_MASK        (1<<ETH_TX_ENABLE_INTERRUPT_BIT)
 563
 564 #define ETH_TX_AUTO_MODE_BIT                30
 565 #define ETH_TX_AUTO_MODE_MASK               (1<<ETH_TX_AUTO_MODE_BIT)
 566
 567
 568 /* Rx descriptor bits */
 569 #define ETH_RX_ERROR_CODE_OFFSET            1
 570 #define ETH_RX_ERROR_CODE_MASK              (3<<ETH_RX_ERROR_CODE_OFFSET)
 571 #define ETH_RX_CRC_ERROR                    (0<<ETH_RX_ERROR_CODE_OFFSET)
 572 #define ETH_RX_OVERRUN_ERROR                (1<<ETH_RX_ERROR_CODE_OFFSET)
 573 #define ETH_RX_MAX_FRAME_LEN_ERROR          (2<<ETH_RX_ERROR_CODE_OFFSET)
 574 #define ETH_RX_RESOURCE_ERROR               (3<<ETH_RX_ERROR_CODE_OFFSET)
 575
 576 #define ETH_RX_L4_CHECKSUM_OFFSET           3
 577 #define ETH_RX_L4_CHECKSUM_MASK             (0xffff<<ETH_RX_L4_CHECKSUM_OFFSET)
 578
 579 #define ETH_RX_VLAN_TAGGED_FRAME_BIT        19
 580 #define ETH_RX_VLAN_TAGGED_FRAME_MASK       (1<<ETH_RX_VLAN_TAGGED_FRAME_BIT)
 581
 582 #define ETH_RX_BPDU_FRAME_BIT               20
 583 #define ETH_RX_BPDU_FRAME_MASK              (1<<ETH_RX_BPDU_FRAME_BIT)
 584
 585 #define ETH_RX_L4_TYPE_OFFSET               21
 586 #define ETH_RX_L4_TYPE_MASK                 (3<<ETH_RX_L4_TYPE_OFFSET)
 587 #define ETH_RX_L4_TCP_TYPE                  (0<<ETH_RX_L4_TYPE_OFFSET)
 588 #define ETH_RX_L4_UDP_TYPE                  (1<<ETH_RX_L4_TYPE_OFFSET)
 589 #define ETH_RX_L4_OTHER_TYPE                (2<<ETH_RX_L4_TYPE_OFFSET)
 590
 591 #define ETH_RX_NOT_LLC_SNAP_FORMAT_BIT      23
 592 #define ETH_RX_NOT_LLC_SNAP_FORMAT_MASK     (1<<ETH_RX_NOT_LLC_SNAP_FORMAT_BIT)
 593
 594 #define ETH_RX_IP_FRAME_TYPE_BIT            24
 595 #define ETH_RX_IP_FRAME_TYPE_MASK           (1<<ETH_RX_IP_FRAME_TYPE_BIT)
 596
 597 #define ETH_RX_IP_HEADER_OK_BIT             25
 598 #define ETH_RX_IP_HEADER_OK_MASK            (1<<ETH_RX_IP_HEADER_OK_BIT)
 599
 600 #define ETH_RX_LAST_DESC_BIT                26
 601 #define ETH_RX_LAST_DESC_MASK               (1<<ETH_RX_LAST_DESC_BIT)
 602
 603 #define ETH_RX_FIRST_DESC_BIT               27
 604 #define ETH_RX_FIRST_DESC_MASK              (1<<ETH_RX_FIRST_DESC_BIT)
 605
 606 #define ETH_RX_UNKNOWN_DA_BIT               28
 607 #define ETH_RX_UNKNOWN_DA_MASK              (1<<ETH_RX_UNKNOWN_DA_BIT)
 608
 609 #define ETH_RX_ENABLE_INTERRUPT_BIT         29
 610 #define ETH_RX_ENABLE_INTERRUPT_MASK        (1<<ETH_RX_ENABLE_INTERRUPT_BIT)
 611
 612 #define ETH_RX_L4_CHECKSUM_OK_BIT           30
 613 #define ETH_RX_L4_CHECKSUM_OK_MASK          (1<<ETH_RX_L4_CHECKSUM_OK_BIT)
 614
 615 /* Rx descriptor bufSize field */
 616 #define ETH_RX_IP_FRAGMENTED_FRAME_BIT      2
 617 #define ETH_RX_IP_FRAGMENTED_FRAME_MASK     (1<<ETH_RX_IP_FRAGMENTED_FRAME_BIT)
 618
 619 #define ETH_RX_BUFFER_MASK                  0xFFF8
 620
 621
 622 /* Ethernet Cause Register BITs */
 623 #define ETH_CAUSE_RX_READY_SUM_BIT          0
 624 #define ETH_CAUSE_EXTEND_BIT                1
 625
 626 #define ETH_CAUSE_RX_READY_OFFSET           2
 627 #define ETH_CAUSE_RX_READY_BIT(queue)       (ETH_CAUSE_RX_READY_OFFSET + (queue))
 628 #define ETH_CAUSE_RX_READY_MASK(queue)      (1 << (ETH_CAUSE_RX_READY_BIT(queue)))
 629
 630 #define ETH_CAUSE_RX_ERROR_SUM_BIT          10
 631 #define ETH_CAUSE_RX_ERROR_OFFSET           11
 632 #define ETH_CAUSE_RX_ERROR_BIT(queue)       (ETH_CAUSE_RX_ERROR_OFFSET + (queue))
 633 #define ETH_CAUSE_RX_ERROR_MASK(queue)      (1 << (ETH_CAUSE_RX_ERROR_BIT(queue)))
 634
 635 #define ETH_CAUSE_TX_END_BIT                19
 636 #define ETH_CAUSE_SUM_BIT                   31
 637
 638 /* Ethernet Cause Extended Register BITs */
 639 #define ETH_CAUSE_TX_BUF_OFFSET             0
 640 #define ETH_CAUSE_TX_BUF_BIT(queue)         (ETH_CAUSE_TX_BUF_OFFSET + (queue))
 641 #define ETH_CAUSE_TX_BUF_MASK(queue)        (1 << (ETH_CAUSE_TX_BUF_BIT(queue)))
 642
 643 #define ETH_CAUSE_TX_ERROR_OFFSET           8
 644 #define ETH_CAUSE_TX_ERROR_BIT(queue)       (ETH_CAUSE_TX_ERROR_OFFSET + (queue))
 645 #define ETH_CAUSE_TX_ERROR_MASK(queue)      (1 << (ETH_CAUSE_TX_ERROR_BIT(queue)))
 646
 647 #define ETH_CAUSE_PHY_STATUS_CHANGE_BIT     16
 648 #define ETH_CAUSE_RX_OVERRUN_BIT            18
 649 #define ETH_CAUSE_TX_UNDERRUN_BIT           19
 650 #define ETH_CAUSE_LINK_STATE_CHANGE_BIT     20
 651 #define ETH_CAUSE_INTERNAL_ADDR_ERR_BIT     23
 652 #define ETH_CAUSE_EXTEND_SUM_BIT            31
 653
 654 /* Marvell Header Register */
 655 /* Marvell Header register bits */
 656 #define ETH_MVHDR_EN_BIT                    0
 657 #define ETH_MVHDR_EN_MASK                   (1 << ETH_MVHDR_EN_BIT)
 658
 659 #define ETH_MVHDR_DAPREFIX_BIT              1
 660 #define ETH_MVHDR_DAPREFIX_MASK             (0x3 << ETH_MVHDR_DAPREFIX_BIT)
 661 #define ETH_MVHDR_DAPREFIX_PRI_1_2          (0x1 << ETH_MVHDR_DAPREFIX_BIT)
 662 #define ETH_MVHDR_DAPREFIX_DBNUM_PRI        (0x2 << ETH_MVHDR_DAPREFIX_BIT)
 663 #define ETH_MVHDR_DAPREFIX_SPID_PRI         (0x3 << ETH_MVHDR_DAPREFIX_BIT)
 664
 665 #define ETH_MVHDR_MHMASK_BIT                8
 666 #define ETH_MVHDR_MHMASK_MASK               (0x3 << ETH_MVHDR_MHMASK_BIT)
 667 #define ETH_MVHDR_MHMASK_8_QUEUE            (0x0 << ETH_MVHDR_MHMASK_BIT)
 668 #define ETH_MVHDR_MHMASK_4_QUEUE            (0x1 << ETH_MVHDR_MHMASK_BIT)
 669 #define ETH_MVHDR_MHMASK_2_QUEUE            (0x3 << ETH_MVHDR_MHMASK_BIT)
 670
 671
 672 /* Relevant for 6183 ONLY */
 673 #define ETH_UNIT_PORTS_PADS_CALIB_0_REG     (MV_ETH_REG_BASE(0) + 0x0A0)
 674 #define ETH_UNIT_PORTS_PADS_CALIB_1_REG     (MV_ETH_REG_BASE(0) + 0x0A4)
 675 #define ETH_UNIT_PORTS_PADS_CALIB_2_REG     (MV_ETH_REG_BASE(0) + 0x0A8)
 676 /* Ethernet Unit Ports Pads Calibration_REG (ETH_UNIT_PORTS_PADS_CALIB_x_REG)  */
 677 #define ETH_ETHERNET_PAD_CLIB_DRVN_OFFS         0
 678 #define ETH_ETHERNET_PAD_CLIB_DRVN_MASK         (0x1F << ETH_ETHERNET_PAD_CLIB_DRVN_OFFS)
 679
 680 #define ETH_ETHERNET_PAD_CLIB_DRVP_OFFS         5
 681 #define ETH_ETHERNET_PAD_CLIB_DRVP_MASK         (0x1F << ETH_ETHERNET_PAD_CLIB_DRVP_OFFS)
 682
 683 #define ETH_ETHERNET_PAD_CLIB_TUNEEN_OFFS       16
 684 #define ETH_ETHERNET_PAD_CLIB_TUNEEN_MASK       (0x1 << ETH_ETHERNET_PAD_CLIB_TUNEEN_OFFS)
 685
 686 #define ETH_ETHERNET_PAD_CLIB_LOCKN_OFFS        17
 687 #define ETH_ETHERNET_PAD_CLIB_LOCKN_MASK        (0x1F << ETH_ETHERNET_PAD_CLIB_LOCKN_OFFS)
 688
 689 #define ETH_ETHERNET_PAD_CLIB_OFFST_OFFS        24
 690 #define ETH_ETHERNET_PAD_CLIB_OFFST_MASK        (0x1F << ETH_ETHERNET_PAD_CLIB_OFFST_OFFS)
 691
 692 #define ETH_ETHERNET_PAD_CLIB_WR_EN_OFFS        31
 693 #define ETH_ETHERNET_PAD_CLIB_WR_EN_MASK        (0x1  << ETH_ETHERNET_PAD_CLIB_WR_EN_OFFS)
 694
 695
 696 #ifdef __cplusplus
 697 }
 698 #endif /* __cplusplus */
 699
 700 #endif /* __INCmvEthRegsh */