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kernel: generic: Add kernel 4.14 support
[openwrt/staging/wigyori.git] / target / linux / generic / files / drivers / net / phy / b53 / b53_common.c
1 /*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/gpio.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/switch.h>
27 #include <linux/phy.h>
28 #include <linux/of.h>
29 #include <linux/of_net.h>
30 #include <linux/platform_data/b53.h>
31
32 #include "b53_regs.h"
33 #include "b53_priv.h"
34
35 /* buffer size needed for displaying all MIBs with max'd values */
36 #define B53_BUF_SIZE 1188
37
38 struct b53_mib_desc {
39 u8 size;
40 u8 offset;
41 const char *name;
42 };
43
44 /* BCM5365 MIB counters */
45 static const struct b53_mib_desc b53_mibs_65[] = {
46 { 8, 0x00, "TxOctets" },
47 { 4, 0x08, "TxDropPkts" },
48 { 4, 0x10, "TxBroadcastPkts" },
49 { 4, 0x14, "TxMulticastPkts" },
50 { 4, 0x18, "TxUnicastPkts" },
51 { 4, 0x1c, "TxCollisions" },
52 { 4, 0x20, "TxSingleCollision" },
53 { 4, 0x24, "TxMultipleCollision" },
54 { 4, 0x28, "TxDeferredTransmit" },
55 { 4, 0x2c, "TxLateCollision" },
56 { 4, 0x30, "TxExcessiveCollision" },
57 { 4, 0x38, "TxPausePkts" },
58 { 8, 0x44, "RxOctets" },
59 { 4, 0x4c, "RxUndersizePkts" },
60 { 4, 0x50, "RxPausePkts" },
61 { 4, 0x54, "Pkts64Octets" },
62 { 4, 0x58, "Pkts65to127Octets" },
63 { 4, 0x5c, "Pkts128to255Octets" },
64 { 4, 0x60, "Pkts256to511Octets" },
65 { 4, 0x64, "Pkts512to1023Octets" },
66 { 4, 0x68, "Pkts1024to1522Octets" },
67 { 4, 0x6c, "RxOversizePkts" },
68 { 4, 0x70, "RxJabbers" },
69 { 4, 0x74, "RxAlignmentErrors" },
70 { 4, 0x78, "RxFCSErrors" },
71 { 8, 0x7c, "RxGoodOctets" },
72 { 4, 0x84, "RxDropPkts" },
73 { 4, 0x88, "RxUnicastPkts" },
74 { 4, 0x8c, "RxMulticastPkts" },
75 { 4, 0x90, "RxBroadcastPkts" },
76 { 4, 0x94, "RxSAChanges" },
77 { 4, 0x98, "RxFragments" },
78 { },
79 };
80
81 #define B63XX_MIB_TXB_ID 0 /* TxOctets */
82 #define B63XX_MIB_RXB_ID 14 /* RxOctets */
83
84 /* BCM63xx MIB counters */
85 static const struct b53_mib_desc b53_mibs_63xx[] = {
86 { 8, 0x00, "TxOctets" },
87 { 4, 0x08, "TxDropPkts" },
88 { 4, 0x0c, "TxQoSPkts" },
89 { 4, 0x10, "TxBroadcastPkts" },
90 { 4, 0x14, "TxMulticastPkts" },
91 { 4, 0x18, "TxUnicastPkts" },
92 { 4, 0x1c, "TxCollisions" },
93 { 4, 0x20, "TxSingleCollision" },
94 { 4, 0x24, "TxMultipleCollision" },
95 { 4, 0x28, "TxDeferredTransmit" },
96 { 4, 0x2c, "TxLateCollision" },
97 { 4, 0x30, "TxExcessiveCollision" },
98 { 4, 0x38, "TxPausePkts" },
99 { 8, 0x3c, "TxQoSOctets" },
100 { 8, 0x44, "RxOctets" },
101 { 4, 0x4c, "RxUndersizePkts" },
102 { 4, 0x50, "RxPausePkts" },
103 { 4, 0x54, "Pkts64Octets" },
104 { 4, 0x58, "Pkts65to127Octets" },
105 { 4, 0x5c, "Pkts128to255Octets" },
106 { 4, 0x60, "Pkts256to511Octets" },
107 { 4, 0x64, "Pkts512to1023Octets" },
108 { 4, 0x68, "Pkts1024to1522Octets" },
109 { 4, 0x6c, "RxOversizePkts" },
110 { 4, 0x70, "RxJabbers" },
111 { 4, 0x74, "RxAlignmentErrors" },
112 { 4, 0x78, "RxFCSErrors" },
113 { 8, 0x7c, "RxGoodOctets" },
114 { 4, 0x84, "RxDropPkts" },
115 { 4, 0x88, "RxUnicastPkts" },
116 { 4, 0x8c, "RxMulticastPkts" },
117 { 4, 0x90, "RxBroadcastPkts" },
118 { 4, 0x94, "RxSAChanges" },
119 { 4, 0x98, "RxFragments" },
120 { 4, 0xa0, "RxSymbolErrors" },
121 { 4, 0xa4, "RxQoSPkts" },
122 { 8, 0xa8, "RxQoSOctets" },
123 { 4, 0xb0, "Pkts1523to2047Octets" },
124 { 4, 0xb4, "Pkts2048to4095Octets" },
125 { 4, 0xb8, "Pkts4096to8191Octets" },
126 { 4, 0xbc, "Pkts8192to9728Octets" },
127 { 4, 0xc0, "RxDiscarded" },
128 { }
129 };
130
131 #define B53XX_MIB_TXB_ID 0 /* TxOctets */
132 #define B53XX_MIB_RXB_ID 12 /* RxOctets */
133
134 /* MIB counters */
135 static const struct b53_mib_desc b53_mibs[] = {
136 { 8, 0x00, "TxOctets" },
137 { 4, 0x08, "TxDropPkts" },
138 { 4, 0x10, "TxBroadcastPkts" },
139 { 4, 0x14, "TxMulticastPkts" },
140 { 4, 0x18, "TxUnicastPkts" },
141 { 4, 0x1c, "TxCollisions" },
142 { 4, 0x20, "TxSingleCollision" },
143 { 4, 0x24, "TxMultipleCollision" },
144 { 4, 0x28, "TxDeferredTransmit" },
145 { 4, 0x2c, "TxLateCollision" },
146 { 4, 0x30, "TxExcessiveCollision" },
147 { 4, 0x38, "TxPausePkts" },
148 { 8, 0x50, "RxOctets" },
149 { 4, 0x58, "RxUndersizePkts" },
150 { 4, 0x5c, "RxPausePkts" },
151 { 4, 0x60, "Pkts64Octets" },
152 { 4, 0x64, "Pkts65to127Octets" },
153 { 4, 0x68, "Pkts128to255Octets" },
154 { 4, 0x6c, "Pkts256to511Octets" },
155 { 4, 0x70, "Pkts512to1023Octets" },
156 { 4, 0x74, "Pkts1024to1522Octets" },
157 { 4, 0x78, "RxOversizePkts" },
158 { 4, 0x7c, "RxJabbers" },
159 { 4, 0x80, "RxAlignmentErrors" },
160 { 4, 0x84, "RxFCSErrors" },
161 { 8, 0x88, "RxGoodOctets" },
162 { 4, 0x90, "RxDropPkts" },
163 { 4, 0x94, "RxUnicastPkts" },
164 { 4, 0x98, "RxMulticastPkts" },
165 { 4, 0x9c, "RxBroadcastPkts" },
166 { 4, 0xa0, "RxSAChanges" },
167 { 4, 0xa4, "RxFragments" },
168 { 4, 0xa8, "RxJumboPkts" },
169 { 4, 0xac, "RxSymbolErrors" },
170 { 4, 0xc0, "RxDiscarded" },
171 { }
172 };
173
174 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
175 {
176 unsigned int i;
177
178 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
179
180 for (i = 0; i < 10; i++) {
181 u8 vta;
182
183 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
184 if (!(vta & VTA_START_CMD))
185 return 0;
186
187 usleep_range(100, 200);
188 }
189
190 return -EIO;
191 }
192
193 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, u16 members,
194 u16 untag)
195 {
196 if (is5325(dev)) {
197 u32 entry = 0;
198
199 if (members) {
200 entry = ((untag & VA_UNTAG_MASK_25) << VA_UNTAG_S_25) |
201 members;
202 if (dev->core_rev >= 3)
203 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
204 else
205 entry |= VA_VALID_25;
206 }
207
208 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
209 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
210 VTA_RW_STATE_WR | VTA_RW_OP_EN);
211 } else if (is5365(dev)) {
212 u16 entry = 0;
213
214 if (members)
215 entry = ((untag & VA_UNTAG_MASK_65) << VA_UNTAG_S_65) |
216 members | VA_VALID_65;
217
218 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
219 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
220 VTA_RW_STATE_WR | VTA_RW_OP_EN);
221 } else {
222 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
223 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
224 (untag << VTE_UNTAG_S) | members);
225
226 b53_do_vlan_op(dev, VTA_CMD_WRITE);
227 }
228 }
229
230 void b53_set_forwarding(struct b53_device *dev, int enable)
231 {
232 u8 mgmt;
233
234 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
235
236 if (enable)
237 mgmt |= SM_SW_FWD_EN;
238 else
239 mgmt &= ~SM_SW_FWD_EN;
240
241 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
242 }
243
244 static void b53_enable_vlan(struct b53_device *dev, int enable)
245 {
246 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
247
248 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
249 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
250 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
251
252 if (is5325(dev) || is5365(dev)) {
253 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
254 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
255 } else if (is63xx(dev)) {
256 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
257 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
258 } else {
259 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
260 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
261 }
262
263 mgmt &= ~SM_SW_FWD_MODE;
264
265 if (enable) {
266 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
267 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
268 vc4 &= ~VC4_ING_VID_CHECK_MASK;
269 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
270 vc5 |= VC5_DROP_VTABLE_MISS;
271
272 if (is5325(dev))
273 vc0 &= ~VC0_RESERVED_1;
274
275 if (is5325(dev) || is5365(dev))
276 vc1 |= VC1_RX_MCST_TAG_EN;
277
278 if (!is5325(dev) && !is5365(dev)) {
279 if (dev->allow_vid_4095)
280 vc5 |= VC5_VID_FFF_EN;
281 else
282 vc5 &= ~VC5_VID_FFF_EN;
283 }
284 } else {
285 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
286 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
287 vc4 &= ~VC4_ING_VID_CHECK_MASK;
288 vc5 &= ~VC5_DROP_VTABLE_MISS;
289
290 if (is5325(dev) || is5365(dev))
291 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
292 else
293 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
294
295 if (is5325(dev) || is5365(dev))
296 vc1 &= ~VC1_RX_MCST_TAG_EN;
297
298 if (!is5325(dev) && !is5365(dev))
299 vc5 &= ~VC5_VID_FFF_EN;
300 }
301
302 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
303 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
304
305 if (is5325(dev) || is5365(dev)) {
306 /* enable the high 8 bit vid check on 5325 */
307 if (is5325(dev) && enable)
308 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
309 VC3_HIGH_8BIT_EN);
310 else
311 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
312
313 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
314 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
315 } else if (is63xx(dev)) {
316 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
317 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
318 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
319 } else {
320 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
321 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
322 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
323 }
324
325 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
326 }
327
328 static int b53_set_jumbo(struct b53_device *dev, int enable, int allow_10_100)
329 {
330 u32 port_mask = 0;
331 u16 max_size = JMS_MIN_SIZE;
332
333 if (is5325(dev) || is5365(dev))
334 return -EINVAL;
335
336 if (enable) {
337 port_mask = dev->enabled_ports;
338 max_size = JMS_MAX_SIZE;
339 if (allow_10_100)
340 port_mask |= JPM_10_100_JUMBO_EN;
341 }
342
343 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
344 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
345 }
346
347 static int b53_flush_arl(struct b53_device *dev)
348 {
349 unsigned int i;
350
351 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
352 FAST_AGE_DONE | FAST_AGE_DYNAMIC | FAST_AGE_STATIC);
353
354 for (i = 0; i < 10; i++) {
355 u8 fast_age_ctrl;
356
357 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
358 &fast_age_ctrl);
359
360 if (!(fast_age_ctrl & FAST_AGE_DONE))
361 return 0;
362
363 mdelay(1);
364 }
365
366 pr_warn("time out while flushing ARL\n");
367
368 return -EINVAL;
369 }
370
371 static void b53_enable_ports(struct b53_device *dev)
372 {
373 unsigned i;
374
375 b53_for_each_port(dev, i) {
376 u8 port_ctrl;
377 u16 pvlan_mask;
378
379 /*
380 * prevent leaking packets between wan and lan in unmanaged
381 * mode through port vlans.
382 */
383 if (dev->enable_vlan || is_cpu_port(dev, i))
384 pvlan_mask = 0x1ff;
385 else if (is531x5(dev) || is5301x(dev))
386 /* BCM53115 may use a different port as cpu port */
387 pvlan_mask = BIT(dev->sw_dev.cpu_port);
388 else
389 pvlan_mask = BIT(B53_CPU_PORT);
390
391 /* BCM5325 CPU port is at 8 */
392 if ((is5325(dev) || is5365(dev)) && i == B53_CPU_PORT_25)
393 i = B53_CPU_PORT;
394
395 if (dev->chip_id == BCM5398_DEVICE_ID && (i == 6 || i == 7))
396 /* disable unused ports 6 & 7 */
397 port_ctrl = PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
398 else if (i == B53_CPU_PORT)
399 port_ctrl = PORT_CTRL_RX_BCST_EN |
400 PORT_CTRL_RX_MCST_EN |
401 PORT_CTRL_RX_UCST_EN;
402 else
403 port_ctrl = 0;
404
405 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i),
406 pvlan_mask);
407
408 /* port state is handled by bcm63xx_enet driver */
409 if (!is63xx(dev) && !(is5301x(dev) && i == 6))
410 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(i),
411 port_ctrl);
412 }
413 }
414
415 static void b53_enable_mib(struct b53_device *dev)
416 {
417 u8 gc;
418
419 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
420
421 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
422
423 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
424 }
425
426 static int b53_apply(struct b53_device *dev)
427 {
428 int i;
429
430 /* clear all vlan entries */
431 if (is5325(dev) || is5365(dev)) {
432 for (i = 1; i < dev->sw_dev.vlans; i++)
433 b53_set_vlan_entry(dev, i, 0, 0);
434 } else {
435 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
436 }
437
438 b53_enable_vlan(dev, dev->enable_vlan);
439
440 /* fill VLAN table */
441 if (dev->enable_vlan) {
442 for (i = 0; i < dev->sw_dev.vlans; i++) {
443 struct b53_vlan *vlan = &dev->vlans[i];
444
445 if (!vlan->members)
446 continue;
447
448 b53_set_vlan_entry(dev, i, vlan->members, vlan->untag);
449 }
450
451 b53_for_each_port(dev, i)
452 b53_write16(dev, B53_VLAN_PAGE,
453 B53_VLAN_PORT_DEF_TAG(i),
454 dev->ports[i].pvid);
455 } else {
456 b53_for_each_port(dev, i)
457 b53_write16(dev, B53_VLAN_PAGE,
458 B53_VLAN_PORT_DEF_TAG(i), 1);
459
460 }
461
462 b53_enable_ports(dev);
463
464 if (!is5325(dev) && !is5365(dev))
465 b53_set_jumbo(dev, dev->enable_jumbo, 1);
466
467 return 0;
468 }
469
470 static void b53_switch_reset_gpio(struct b53_device *dev)
471 {
472 int gpio = dev->reset_gpio;
473
474 if (gpio < 0)
475 return;
476
477 /*
478 * Reset sequence: RESET low(50ms)->high(20ms)
479 */
480 gpio_set_value(gpio, 0);
481 mdelay(50);
482
483 gpio_set_value(gpio, 1);
484 mdelay(20);
485
486 dev->current_page = 0xff;
487 }
488
489 static int b53_configure_ports_of(struct b53_device *dev)
490 {
491 struct device_node *dn, *pn;
492 u32 port_num;
493
494 dn = of_get_child_by_name(dev_of_node(dev->dev), "ports");
495
496 for_each_available_child_of_node(dn, pn) {
497 struct device_node *fixed_link;
498
499 if (of_property_read_u32(pn, "reg", &port_num))
500 continue;
501
502 if (port_num > B53_CPU_PORT)
503 continue;
504
505 fixed_link = of_get_child_by_name(pn, "fixed-link");
506 if (fixed_link) {
507 u32 spd;
508 u8 po = GMII_PO_LINK;
509 int mode = of_get_phy_mode(pn);
510
511 if (!of_property_read_u32(fixed_link, "speed", &spd)) {
512 switch (spd) {
513 case 10:
514 po |= GMII_PO_SPEED_10M;
515 break;
516 case 100:
517 po |= GMII_PO_SPEED_100M;
518 break;
519 case 2000:
520 if (is_imp_port(dev, port_num))
521 po |= PORT_OVERRIDE_SPEED_2000M;
522 else
523 po |= GMII_PO_SPEED_2000M;
524 /* fall through */
525 case 1000:
526 po |= GMII_PO_SPEED_1000M;
527 break;
528 }
529 }
530
531 if (of_property_read_bool(fixed_link, "full-duplex"))
532 po |= PORT_OVERRIDE_FULL_DUPLEX;
533 if (of_property_read_bool(fixed_link, "pause"))
534 po |= GMII_PO_RX_FLOW;
535 if (of_property_read_bool(fixed_link, "asym-pause"))
536 po |= GMII_PO_TX_FLOW;
537
538 if (is_imp_port(dev, port_num)) {
539 po |= PORT_OVERRIDE_EN;
540
541 if (is5325(dev) &&
542 mode == PHY_INTERFACE_MODE_REVMII)
543 po |= PORT_OVERRIDE_RV_MII_25;
544
545 b53_write8(dev, B53_CTRL_PAGE,
546 B53_PORT_OVERRIDE_CTRL, po);
547
548 if (is5325(dev) &&
549 mode == PHY_INTERFACE_MODE_REVMII) {
550 b53_read8(dev, B53_CTRL_PAGE,
551 B53_PORT_OVERRIDE_CTRL, &po);
552 if (!(po & PORT_OVERRIDE_RV_MII_25))
553 pr_err("Failed to enable reverse MII mode\n");
554 return -EINVAL;
555 }
556 } else {
557 po |= GMII_PO_EN;
558 b53_write8(dev, B53_CTRL_PAGE,
559 B53_GMII_PORT_OVERRIDE_CTRL(port_num),
560 po);
561 }
562 }
563 }
564
565 return 0;
566 }
567
568 static int b53_configure_ports(struct b53_device *dev)
569 {
570 u8 cpu_port = dev->sw_dev.cpu_port;
571
572 /* configure MII port if necessary */
573 if (is5325(dev)) {
574 u8 mii_port_override;
575
576 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
577 &mii_port_override);
578 /* reverse mii needs to be enabled */
579 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
580 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
581 mii_port_override | PORT_OVERRIDE_RV_MII_25);
582 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
583 &mii_port_override);
584
585 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
586 pr_err("Failed to enable reverse MII mode\n");
587 return -EINVAL;
588 }
589 }
590 } else if (is531x5(dev) && cpu_port == B53_CPU_PORT) {
591 u8 mii_port_override;
592
593 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
594 &mii_port_override);
595 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
596 mii_port_override | PORT_OVERRIDE_EN |
597 PORT_OVERRIDE_LINK);
598
599 /* BCM47189 has another interface connected to the port 5 */
600 if (dev->enabled_ports & BIT(5)) {
601 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(5);
602 u8 gmii_po;
603
604 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
605 gmii_po |= GMII_PO_LINK |
606 GMII_PO_RX_FLOW |
607 GMII_PO_TX_FLOW |
608 GMII_PO_EN;
609 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
610 }
611 } else if (is5301x(dev)) {
612 if (cpu_port == 8) {
613 u8 mii_port_override;
614
615 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
616 &mii_port_override);
617 mii_port_override |= PORT_OVERRIDE_LINK |
618 PORT_OVERRIDE_RX_FLOW |
619 PORT_OVERRIDE_TX_FLOW |
620 PORT_OVERRIDE_SPEED_2000M |
621 PORT_OVERRIDE_EN;
622 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
623 mii_port_override);
624
625 /* TODO: Ports 5 & 7 require some extra handling */
626 } else {
627 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(cpu_port);
628 u8 gmii_po;
629
630 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
631 gmii_po |= GMII_PO_LINK |
632 GMII_PO_RX_FLOW |
633 GMII_PO_TX_FLOW |
634 GMII_PO_EN |
635 GMII_PO_SPEED_2000M;
636 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
637 }
638 }
639
640 return 0;
641 }
642
643 static int b53_switch_reset(struct b53_device *dev)
644 {
645 int ret = 0;
646 u8 mgmt;
647
648 b53_switch_reset_gpio(dev);
649
650 if (is539x(dev)) {
651 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
652 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
653 }
654
655 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
656
657 if (!(mgmt & SM_SW_FWD_EN)) {
658 mgmt &= ~SM_SW_FWD_MODE;
659 mgmt |= SM_SW_FWD_EN;
660
661 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
662 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
663
664 if (!(mgmt & SM_SW_FWD_EN)) {
665 pr_err("Failed to enable switch!\n");
666 return -EINVAL;
667 }
668 }
669
670 /* enable all ports */
671 b53_enable_ports(dev);
672
673 if (dev->dev->of_node)
674 ret = b53_configure_ports_of(dev);
675 else
676 ret = b53_configure_ports(dev);
677
678 if (ret)
679 return ret;
680
681 b53_enable_mib(dev);
682
683 return b53_flush_arl(dev);
684 }
685
686 /*
687 * Swconfig glue functions
688 */
689
690 static int b53_global_get_vlan_enable(struct switch_dev *dev,
691 const struct switch_attr *attr,
692 struct switch_val *val)
693 {
694 struct b53_device *priv = sw_to_b53(dev);
695
696 val->value.i = priv->enable_vlan;
697
698 return 0;
699 }
700
701 static int b53_global_set_vlan_enable(struct switch_dev *dev,
702 const struct switch_attr *attr,
703 struct switch_val *val)
704 {
705 struct b53_device *priv = sw_to_b53(dev);
706
707 priv->enable_vlan = val->value.i;
708
709 return 0;
710 }
711
712 static int b53_global_get_jumbo_enable(struct switch_dev *dev,
713 const struct switch_attr *attr,
714 struct switch_val *val)
715 {
716 struct b53_device *priv = sw_to_b53(dev);
717
718 val->value.i = priv->enable_jumbo;
719
720 return 0;
721 }
722
723 static int b53_global_set_jumbo_enable(struct switch_dev *dev,
724 const struct switch_attr *attr,
725 struct switch_val *val)
726 {
727 struct b53_device *priv = sw_to_b53(dev);
728
729 priv->enable_jumbo = val->value.i;
730
731 return 0;
732 }
733
734 static int b53_global_get_4095_enable(struct switch_dev *dev,
735 const struct switch_attr *attr,
736 struct switch_val *val)
737 {
738 struct b53_device *priv = sw_to_b53(dev);
739
740 val->value.i = priv->allow_vid_4095;
741
742 return 0;
743 }
744
745 static int b53_global_set_4095_enable(struct switch_dev *dev,
746 const struct switch_attr *attr,
747 struct switch_val *val)
748 {
749 struct b53_device *priv = sw_to_b53(dev);
750
751 priv->allow_vid_4095 = val->value.i;
752
753 return 0;
754 }
755
756 static int b53_global_get_ports(struct switch_dev *dev,
757 const struct switch_attr *attr,
758 struct switch_val *val)
759 {
760 struct b53_device *priv = sw_to_b53(dev);
761
762 val->len = snprintf(priv->buf, B53_BUF_SIZE, "0x%04x",
763 priv->enabled_ports);
764 val->value.s = priv->buf;
765
766 return 0;
767 }
768
769 static int b53_port_get_pvid(struct switch_dev *dev, int port, int *val)
770 {
771 struct b53_device *priv = sw_to_b53(dev);
772
773 *val = priv->ports[port].pvid;
774
775 return 0;
776 }
777
778 static int b53_port_set_pvid(struct switch_dev *dev, int port, int val)
779 {
780 struct b53_device *priv = sw_to_b53(dev);
781
782 if (val > 15 && is5325(priv))
783 return -EINVAL;
784 if (val == 4095 && !priv->allow_vid_4095)
785 return -EINVAL;
786
787 priv->ports[port].pvid = val;
788
789 return 0;
790 }
791
792 static int b53_vlan_get_ports(struct switch_dev *dev, struct switch_val *val)
793 {
794 struct b53_device *priv = sw_to_b53(dev);
795 struct switch_port *port = &val->value.ports[0];
796 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
797 int i;
798
799 val->len = 0;
800
801 if (!vlan->members)
802 return 0;
803
804 for (i = 0; i < dev->ports; i++) {
805 if (!(vlan->members & BIT(i)))
806 continue;
807
808
809 if (!(vlan->untag & BIT(i)))
810 port->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
811 else
812 port->flags = 0;
813
814 port->id = i;
815 val->len++;
816 port++;
817 }
818
819 return 0;
820 }
821
822 static int b53_vlan_set_ports(struct switch_dev *dev, struct switch_val *val)
823 {
824 struct b53_device *priv = sw_to_b53(dev);
825 struct switch_port *port;
826 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
827 int i;
828
829 /* only BCM5325 and BCM5365 supports VID 0 */
830 if (val->port_vlan == 0 && !is5325(priv) && !is5365(priv))
831 return -EINVAL;
832
833 /* VLAN 4095 needs special handling */
834 if (val->port_vlan == 4095 && !priv->allow_vid_4095)
835 return -EINVAL;
836
837 port = &val->value.ports[0];
838 vlan->members = 0;
839 vlan->untag = 0;
840 for (i = 0; i < val->len; i++, port++) {
841 vlan->members |= BIT(port->id);
842
843 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED))) {
844 vlan->untag |= BIT(port->id);
845 priv->ports[port->id].pvid = val->port_vlan;
846 };
847 }
848
849 /* ignore disabled ports */
850 vlan->members &= priv->enabled_ports;
851 vlan->untag &= priv->enabled_ports;
852
853 return 0;
854 }
855
856 static int b53_port_get_link(struct switch_dev *dev, int port,
857 struct switch_port_link *link)
858 {
859 struct b53_device *priv = sw_to_b53(dev);
860
861 if (is_cpu_port(priv, port)) {
862 link->link = 1;
863 link->duplex = 1;
864 link->speed = is5325(priv) || is5365(priv) ?
865 SWITCH_PORT_SPEED_100 : SWITCH_PORT_SPEED_1000;
866 link->aneg = 0;
867 } else if (priv->enabled_ports & BIT(port)) {
868 u32 speed;
869 u16 lnk, duplex;
870
871 b53_read16(priv, B53_STAT_PAGE, B53_LINK_STAT, &lnk);
872 b53_read16(priv, B53_STAT_PAGE, priv->duplex_reg, &duplex);
873
874 lnk = (lnk >> port) & 1;
875 duplex = (duplex >> port) & 1;
876
877 if (is5325(priv) || is5365(priv)) {
878 u16 tmp;
879
880 b53_read16(priv, B53_STAT_PAGE, B53_SPEED_STAT, &tmp);
881 speed = SPEED_PORT_FE(tmp, port);
882 } else {
883 b53_read32(priv, B53_STAT_PAGE, B53_SPEED_STAT, &speed);
884 speed = SPEED_PORT_GE(speed, port);
885 }
886
887 link->link = lnk;
888 if (lnk) {
889 link->duplex = duplex;
890 switch (speed) {
891 case SPEED_STAT_10M:
892 link->speed = SWITCH_PORT_SPEED_10;
893 break;
894 case SPEED_STAT_100M:
895 link->speed = SWITCH_PORT_SPEED_100;
896 break;
897 case SPEED_STAT_1000M:
898 link->speed = SWITCH_PORT_SPEED_1000;
899 break;
900 }
901 }
902
903 link->aneg = 1;
904 } else {
905 link->link = 0;
906 }
907
908 return 0;
909
910 }
911
912 static int b53_port_set_link(struct switch_dev *sw_dev, int port,
913 struct switch_port_link *link)
914 {
915 struct b53_device *dev = sw_to_b53(sw_dev);
916
917 /*
918 * TODO: BCM63XX requires special handling as it can have external phys
919 * and ports might be GE or only FE
920 */
921 if (is63xx(dev))
922 return -ENOTSUPP;
923
924 if (port == sw_dev->cpu_port)
925 return -EINVAL;
926
927 if (!(BIT(port) & dev->enabled_ports))
928 return -EINVAL;
929
930 if (link->speed == SWITCH_PORT_SPEED_1000 &&
931 (is5325(dev) || is5365(dev)))
932 return -EINVAL;
933
934 if (link->speed == SWITCH_PORT_SPEED_1000 && !link->duplex)
935 return -EINVAL;
936
937 return switch_generic_set_link(sw_dev, port, link);
938 }
939
940 static int b53_phy_read16(struct switch_dev *dev, int addr, u8 reg, u16 *value)
941 {
942 struct b53_device *priv = sw_to_b53(dev);
943
944 if (priv->ops->phy_read16)
945 return priv->ops->phy_read16(priv, addr, reg, value);
946
947 return b53_read16(priv, B53_PORT_MII_PAGE(addr), reg, value);
948 }
949
950 static int b53_phy_write16(struct switch_dev *dev, int addr, u8 reg, u16 value)
951 {
952 struct b53_device *priv = sw_to_b53(dev);
953
954 if (priv->ops->phy_write16)
955 return priv->ops->phy_write16(priv, addr, reg, value);
956
957 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg, value);
958 }
959
960 static int b53_global_reset_switch(struct switch_dev *dev)
961 {
962 struct b53_device *priv = sw_to_b53(dev);
963
964 /* reset vlans */
965 priv->enable_vlan = 0;
966 priv->enable_jumbo = 0;
967 priv->allow_vid_4095 = 0;
968
969 memset(priv->vlans, 0, sizeof(*priv->vlans) * dev->vlans);
970 memset(priv->ports, 0, sizeof(*priv->ports) * dev->ports);
971
972 return b53_switch_reset(priv);
973 }
974
975 static int b53_global_apply_config(struct switch_dev *dev)
976 {
977 struct b53_device *priv = sw_to_b53(dev);
978
979 /* disable switching */
980 b53_set_forwarding(priv, 0);
981
982 b53_apply(priv);
983
984 /* enable switching */
985 b53_set_forwarding(priv, 1);
986
987 return 0;
988 }
989
990
991 static int b53_global_reset_mib(struct switch_dev *dev,
992 const struct switch_attr *attr,
993 struct switch_val *val)
994 {
995 struct b53_device *priv = sw_to_b53(dev);
996 u8 gc;
997
998 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
999
1000 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
1001 mdelay(1);
1002 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
1003 mdelay(1);
1004
1005 return 0;
1006 }
1007
1008 static int b53_port_get_mib(struct switch_dev *sw_dev,
1009 const struct switch_attr *attr,
1010 struct switch_val *val)
1011 {
1012 struct b53_device *dev = sw_to_b53(sw_dev);
1013 const struct b53_mib_desc *mibs;
1014 int port = val->port_vlan;
1015 int len = 0;
1016
1017 if (!(BIT(port) & dev->enabled_ports))
1018 return -1;
1019
1020 if (is5365(dev)) {
1021 if (port == 5)
1022 port = 8;
1023
1024 mibs = b53_mibs_65;
1025 } else if (is63xx(dev)) {
1026 mibs = b53_mibs_63xx;
1027 } else {
1028 mibs = b53_mibs;
1029 }
1030
1031 dev->buf[0] = 0;
1032
1033 for (; mibs->size > 0; mibs++) {
1034 u64 val;
1035
1036 if (mibs->size == 8) {
1037 b53_read64(dev, B53_MIB_PAGE(port), mibs->offset, &val);
1038 } else {
1039 u32 val32;
1040
1041 b53_read32(dev, B53_MIB_PAGE(port), mibs->offset,
1042 &val32);
1043 val = val32;
1044 }
1045
1046 len += snprintf(dev->buf + len, B53_BUF_SIZE - len,
1047 "%-20s: %llu\n", mibs->name, val);
1048 }
1049
1050 val->len = len;
1051 val->value.s = dev->buf;
1052
1053 return 0;
1054 }
1055
1056 static int b53_port_get_stats(struct switch_dev *sw_dev, int port,
1057 struct switch_port_stats *stats)
1058 {
1059 struct b53_device *dev = sw_to_b53(sw_dev);
1060 const struct b53_mib_desc *mibs;
1061 int txb_id, rxb_id;
1062 u64 rxb, txb;
1063
1064 if (!(BIT(port) & dev->enabled_ports))
1065 return -EINVAL;
1066
1067 txb_id = B53XX_MIB_TXB_ID;
1068 rxb_id = B53XX_MIB_RXB_ID;
1069
1070 if (is5365(dev)) {
1071 if (port == 5)
1072 port = 8;
1073
1074 mibs = b53_mibs_65;
1075 } else if (is63xx(dev)) {
1076 mibs = b53_mibs_63xx;
1077 txb_id = B63XX_MIB_TXB_ID;
1078 rxb_id = B63XX_MIB_RXB_ID;
1079 } else {
1080 mibs = b53_mibs;
1081 }
1082
1083 dev->buf[0] = 0;
1084
1085 if (mibs->size == 8) {
1086 b53_read64(dev, B53_MIB_PAGE(port), mibs[txb_id].offset, &txb);
1087 b53_read64(dev, B53_MIB_PAGE(port), mibs[rxb_id].offset, &rxb);
1088 } else {
1089 u32 val32;
1090
1091 b53_read32(dev, B53_MIB_PAGE(port), mibs[txb_id].offset, &val32);
1092 txb = val32;
1093
1094 b53_read32(dev, B53_MIB_PAGE(port), mibs[rxb_id].offset, &val32);
1095 rxb = val32;
1096 }
1097
1098 stats->tx_bytes = txb;
1099 stats->rx_bytes = rxb;
1100
1101 return 0;
1102 }
1103
1104 static struct switch_attr b53_global_ops_25[] = {
1105 {
1106 .type = SWITCH_TYPE_INT,
1107 .name = "enable_vlan",
1108 .description = "Enable VLAN mode",
1109 .set = b53_global_set_vlan_enable,
1110 .get = b53_global_get_vlan_enable,
1111 .max = 1,
1112 },
1113 {
1114 .type = SWITCH_TYPE_STRING,
1115 .name = "ports",
1116 .description = "Available ports (as bitmask)",
1117 .get = b53_global_get_ports,
1118 },
1119 };
1120
1121 static struct switch_attr b53_global_ops_65[] = {
1122 {
1123 .type = SWITCH_TYPE_INT,
1124 .name = "enable_vlan",
1125 .description = "Enable VLAN mode",
1126 .set = b53_global_set_vlan_enable,
1127 .get = b53_global_get_vlan_enable,
1128 .max = 1,
1129 },
1130 {
1131 .type = SWITCH_TYPE_STRING,
1132 .name = "ports",
1133 .description = "Available ports (as bitmask)",
1134 .get = b53_global_get_ports,
1135 },
1136 {
1137 .type = SWITCH_TYPE_INT,
1138 .name = "reset_mib",
1139 .description = "Reset MIB counters",
1140 .set = b53_global_reset_mib,
1141 },
1142 };
1143
1144 static struct switch_attr b53_global_ops[] = {
1145 {
1146 .type = SWITCH_TYPE_INT,
1147 .name = "enable_vlan",
1148 .description = "Enable VLAN mode",
1149 .set = b53_global_set_vlan_enable,
1150 .get = b53_global_get_vlan_enable,
1151 .max = 1,
1152 },
1153 {
1154 .type = SWITCH_TYPE_STRING,
1155 .name = "ports",
1156 .description = "Available Ports (as bitmask)",
1157 .get = b53_global_get_ports,
1158 },
1159 {
1160 .type = SWITCH_TYPE_INT,
1161 .name = "reset_mib",
1162 .description = "Reset MIB counters",
1163 .set = b53_global_reset_mib,
1164 },
1165 {
1166 .type = SWITCH_TYPE_INT,
1167 .name = "enable_jumbo",
1168 .description = "Enable Jumbo Frames",
1169 .set = b53_global_set_jumbo_enable,
1170 .get = b53_global_get_jumbo_enable,
1171 .max = 1,
1172 },
1173 {
1174 .type = SWITCH_TYPE_INT,
1175 .name = "allow_vid_4095",
1176 .description = "Allow VID 4095",
1177 .set = b53_global_set_4095_enable,
1178 .get = b53_global_get_4095_enable,
1179 .max = 1,
1180 },
1181 };
1182
1183 static struct switch_attr b53_port_ops[] = {
1184 {
1185 .type = SWITCH_TYPE_STRING,
1186 .name = "mib",
1187 .description = "Get port's MIB counters",
1188 .get = b53_port_get_mib,
1189 },
1190 };
1191
1192 static struct switch_attr b53_no_ops[] = {
1193 };
1194
1195 static const struct switch_dev_ops b53_switch_ops_25 = {
1196 .attr_global = {
1197 .attr = b53_global_ops_25,
1198 .n_attr = ARRAY_SIZE(b53_global_ops_25),
1199 },
1200 .attr_port = {
1201 .attr = b53_no_ops,
1202 .n_attr = ARRAY_SIZE(b53_no_ops),
1203 },
1204 .attr_vlan = {
1205 .attr = b53_no_ops,
1206 .n_attr = ARRAY_SIZE(b53_no_ops),
1207 },
1208
1209 .get_vlan_ports = b53_vlan_get_ports,
1210 .set_vlan_ports = b53_vlan_set_ports,
1211 .get_port_pvid = b53_port_get_pvid,
1212 .set_port_pvid = b53_port_set_pvid,
1213 .apply_config = b53_global_apply_config,
1214 .reset_switch = b53_global_reset_switch,
1215 .get_port_link = b53_port_get_link,
1216 .set_port_link = b53_port_set_link,
1217 .get_port_stats = b53_port_get_stats,
1218 .phy_read16 = b53_phy_read16,
1219 .phy_write16 = b53_phy_write16,
1220 };
1221
1222 static const struct switch_dev_ops b53_switch_ops_65 = {
1223 .attr_global = {
1224 .attr = b53_global_ops_65,
1225 .n_attr = ARRAY_SIZE(b53_global_ops_65),
1226 },
1227 .attr_port = {
1228 .attr = b53_port_ops,
1229 .n_attr = ARRAY_SIZE(b53_port_ops),
1230 },
1231 .attr_vlan = {
1232 .attr = b53_no_ops,
1233 .n_attr = ARRAY_SIZE(b53_no_ops),
1234 },
1235
1236 .get_vlan_ports = b53_vlan_get_ports,
1237 .set_vlan_ports = b53_vlan_set_ports,
1238 .get_port_pvid = b53_port_get_pvid,
1239 .set_port_pvid = b53_port_set_pvid,
1240 .apply_config = b53_global_apply_config,
1241 .reset_switch = b53_global_reset_switch,
1242 .get_port_link = b53_port_get_link,
1243 .set_port_link = b53_port_set_link,
1244 .get_port_stats = b53_port_get_stats,
1245 .phy_read16 = b53_phy_read16,
1246 .phy_write16 = b53_phy_write16,
1247 };
1248
1249 static const struct switch_dev_ops b53_switch_ops = {
1250 .attr_global = {
1251 .attr = b53_global_ops,
1252 .n_attr = ARRAY_SIZE(b53_global_ops),
1253 },
1254 .attr_port = {
1255 .attr = b53_port_ops,
1256 .n_attr = ARRAY_SIZE(b53_port_ops),
1257 },
1258 .attr_vlan = {
1259 .attr = b53_no_ops,
1260 .n_attr = ARRAY_SIZE(b53_no_ops),
1261 },
1262
1263 .get_vlan_ports = b53_vlan_get_ports,
1264 .set_vlan_ports = b53_vlan_set_ports,
1265 .get_port_pvid = b53_port_get_pvid,
1266 .set_port_pvid = b53_port_set_pvid,
1267 .apply_config = b53_global_apply_config,
1268 .reset_switch = b53_global_reset_switch,
1269 .get_port_link = b53_port_get_link,
1270 .set_port_link = b53_port_set_link,
1271 .get_port_stats = b53_port_get_stats,
1272 .phy_read16 = b53_phy_read16,
1273 .phy_write16 = b53_phy_write16,
1274 };
1275
1276 struct b53_chip_data {
1277 u32 chip_id;
1278 const char *dev_name;
1279 const char *alias;
1280 u16 vlans;
1281 u16 enabled_ports;
1282 u8 cpu_port;
1283 u8 vta_regs[3];
1284 u8 duplex_reg;
1285 u8 jumbo_pm_reg;
1286 u8 jumbo_size_reg;
1287 const struct switch_dev_ops *sw_ops;
1288 };
1289
1290 #define B53_VTA_REGS \
1291 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1292 #define B53_VTA_REGS_9798 \
1293 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1294 #define B53_VTA_REGS_63XX \
1295 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1296
1297 static const struct b53_chip_data b53_switch_chips[] = {
1298 {
1299 .chip_id = BCM5325_DEVICE_ID,
1300 .dev_name = "BCM5325",
1301 .alias = "bcm5325",
1302 .vlans = 16,
1303 .enabled_ports = 0x1f,
1304 .cpu_port = B53_CPU_PORT_25,
1305 .duplex_reg = B53_DUPLEX_STAT_FE,
1306 .sw_ops = &b53_switch_ops_25,
1307 },
1308 {
1309 .chip_id = BCM5365_DEVICE_ID,
1310 .dev_name = "BCM5365",
1311 .alias = "bcm5365",
1312 .vlans = 256,
1313 .enabled_ports = 0x1f,
1314 .cpu_port = B53_CPU_PORT_25,
1315 .duplex_reg = B53_DUPLEX_STAT_FE,
1316 .sw_ops = &b53_switch_ops_65,
1317 },
1318 {
1319 .chip_id = BCM5395_DEVICE_ID,
1320 .dev_name = "BCM5395",
1321 .alias = "bcm5395",
1322 .vlans = 4096,
1323 .enabled_ports = 0x1f,
1324 .cpu_port = B53_CPU_PORT,
1325 .vta_regs = B53_VTA_REGS,
1326 .duplex_reg = B53_DUPLEX_STAT_GE,
1327 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1328 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1329 .sw_ops = &b53_switch_ops,
1330 },
1331 {
1332 .chip_id = BCM5397_DEVICE_ID,
1333 .dev_name = "BCM5397",
1334 .alias = "bcm5397",
1335 .vlans = 4096,
1336 .enabled_ports = 0x1f,
1337 .cpu_port = B53_CPU_PORT,
1338 .vta_regs = B53_VTA_REGS_9798,
1339 .duplex_reg = B53_DUPLEX_STAT_GE,
1340 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1341 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1342 .sw_ops = &b53_switch_ops,
1343 },
1344 {
1345 .chip_id = BCM5398_DEVICE_ID,
1346 .dev_name = "BCM5398",
1347 .alias = "bcm5398",
1348 .vlans = 4096,
1349 .enabled_ports = 0x7f,
1350 .cpu_port = B53_CPU_PORT,
1351 .vta_regs = B53_VTA_REGS_9798,
1352 .duplex_reg = B53_DUPLEX_STAT_GE,
1353 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1354 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1355 .sw_ops = &b53_switch_ops,
1356 },
1357 {
1358 .chip_id = BCM53115_DEVICE_ID,
1359 .dev_name = "BCM53115",
1360 .alias = "bcm53115",
1361 .vlans = 4096,
1362 .enabled_ports = 0x1f,
1363 .vta_regs = B53_VTA_REGS,
1364 .cpu_port = B53_CPU_PORT,
1365 .duplex_reg = B53_DUPLEX_STAT_GE,
1366 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1367 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1368 .sw_ops = &b53_switch_ops,
1369 },
1370 {
1371 .chip_id = BCM53125_DEVICE_ID,
1372 .dev_name = "BCM53125",
1373 .alias = "bcm53125",
1374 .vlans = 4096,
1375 .enabled_ports = 0x1f,
1376 .cpu_port = B53_CPU_PORT,
1377 .vta_regs = B53_VTA_REGS,
1378 .duplex_reg = B53_DUPLEX_STAT_GE,
1379 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1380 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1381 .sw_ops = &b53_switch_ops,
1382 },
1383 {
1384 .chip_id = BCM53128_DEVICE_ID,
1385 .dev_name = "BCM53128",
1386 .alias = "bcm53128",
1387 .vlans = 4096,
1388 .enabled_ports = 0x1ff,
1389 .cpu_port = B53_CPU_PORT,
1390 .vta_regs = B53_VTA_REGS,
1391 .duplex_reg = B53_DUPLEX_STAT_GE,
1392 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1393 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1394 .sw_ops = &b53_switch_ops,
1395 },
1396 {
1397 .chip_id = BCM63XX_DEVICE_ID,
1398 .dev_name = "BCM63xx",
1399 .alias = "bcm63xx",
1400 .vlans = 4096,
1401 .enabled_ports = 0, /* pdata must provide them */
1402 .cpu_port = B53_CPU_PORT,
1403 .vta_regs = B53_VTA_REGS_63XX,
1404 .duplex_reg = B53_DUPLEX_STAT_63XX,
1405 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1406 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1407 .sw_ops = &b53_switch_ops,
1408 },
1409 {
1410 .chip_id = BCM53010_DEVICE_ID,
1411 .dev_name = "BCM53010",
1412 .alias = "bcm53011",
1413 .vlans = 4096,
1414 .enabled_ports = 0x1f,
1415 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1416 .vta_regs = B53_VTA_REGS,
1417 .duplex_reg = B53_DUPLEX_STAT_GE,
1418 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1419 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1420 .sw_ops = &b53_switch_ops,
1421 },
1422 {
1423 .chip_id = BCM53011_DEVICE_ID,
1424 .dev_name = "BCM53011",
1425 .alias = "bcm53011",
1426 .vlans = 4096,
1427 .enabled_ports = 0x1bf,
1428 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1429 .vta_regs = B53_VTA_REGS,
1430 .duplex_reg = B53_DUPLEX_STAT_GE,
1431 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1432 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1433 .sw_ops = &b53_switch_ops,
1434 },
1435 {
1436 .chip_id = BCM53012_DEVICE_ID,
1437 .dev_name = "BCM53012",
1438 .alias = "bcm53011",
1439 .vlans = 4096,
1440 .enabled_ports = 0x1bf,
1441 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1442 .vta_regs = B53_VTA_REGS,
1443 .duplex_reg = B53_DUPLEX_STAT_GE,
1444 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1445 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1446 .sw_ops = &b53_switch_ops,
1447 },
1448 {
1449 .chip_id = BCM53018_DEVICE_ID,
1450 .dev_name = "BCM53018",
1451 .alias = "bcm53018",
1452 .vlans = 4096,
1453 .enabled_ports = 0x1f,
1454 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1455 .vta_regs = B53_VTA_REGS,
1456 .duplex_reg = B53_DUPLEX_STAT_GE,
1457 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1458 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1459 .sw_ops = &b53_switch_ops,
1460 },
1461 {
1462 .chip_id = BCM53019_DEVICE_ID,
1463 .dev_name = "BCM53019",
1464 .alias = "bcm53019",
1465 .vlans = 4096,
1466 .enabled_ports = 0x1f,
1467 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1468 .vta_regs = B53_VTA_REGS,
1469 .duplex_reg = B53_DUPLEX_STAT_GE,
1470 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1471 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1472 .sw_ops = &b53_switch_ops,
1473 },
1474 };
1475
1476 static int b53_switch_init_of(struct b53_device *dev)
1477 {
1478 struct device_node *dn, *pn;
1479 const char *alias;
1480 u32 port_num;
1481 u16 ports = 0;
1482
1483 dn = of_get_child_by_name(dev_of_node(dev->dev), "ports");
1484 if (!dn)
1485 return -EINVAL;
1486
1487 for_each_available_child_of_node(dn, pn) {
1488 const char *label;
1489 int len;
1490
1491 if (of_property_read_u32(pn, "reg", &port_num))
1492 continue;
1493
1494 if (port_num > B53_CPU_PORT)
1495 continue;
1496
1497 ports |= BIT(port_num);
1498
1499 label = of_get_property(pn, "label", &len);
1500 if (label && !strcmp(label, "cpu"))
1501 dev->sw_dev.cpu_port = port_num;
1502 }
1503
1504 dev->enabled_ports = ports;
1505
1506 if (!of_property_read_string(dev_of_node(dev->dev), "lede,alias",
1507 &alias))
1508 dev->sw_dev.alias = devm_kstrdup(dev->dev, alias, GFP_KERNEL);
1509
1510 return 0;
1511 }
1512
1513 static int b53_switch_init(struct b53_device *dev)
1514 {
1515 struct switch_dev *sw_dev = &dev->sw_dev;
1516 unsigned i;
1517 int ret;
1518
1519 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1520 const struct b53_chip_data *chip = &b53_switch_chips[i];
1521
1522 if (chip->chip_id == dev->chip_id) {
1523 sw_dev->name = chip->dev_name;
1524 if (!sw_dev->alias)
1525 sw_dev->alias = chip->alias;
1526 if (!dev->enabled_ports)
1527 dev->enabled_ports = chip->enabled_ports;
1528 dev->duplex_reg = chip->duplex_reg;
1529 dev->vta_regs[0] = chip->vta_regs[0];
1530 dev->vta_regs[1] = chip->vta_regs[1];
1531 dev->vta_regs[2] = chip->vta_regs[2];
1532 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1533 sw_dev->ops = chip->sw_ops;
1534 sw_dev->cpu_port = chip->cpu_port;
1535 sw_dev->vlans = chip->vlans;
1536 break;
1537 }
1538 }
1539
1540 if (!sw_dev->name)
1541 return -EINVAL;
1542
1543 /* check which BCM5325x version we have */
1544 if (is5325(dev)) {
1545 u8 vc4;
1546
1547 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1548
1549 /* check reserved bits */
1550 switch (vc4 & 3) {
1551 case 1:
1552 /* BCM5325E */
1553 break;
1554 case 3:
1555 /* BCM5325F - do not use port 4 */
1556 dev->enabled_ports &= ~BIT(4);
1557 break;
1558 default:
1559 /* On the BCM47XX SoCs this is the supported internal switch.*/
1560 #ifndef CONFIG_BCM47XX
1561 /* BCM5325M */
1562 return -EINVAL;
1563 #else
1564 break;
1565 #endif
1566 }
1567 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1568 u64 strap_value;
1569
1570 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1571 /* use second IMP port if GMII is enabled */
1572 if (strap_value & SV_GMII_CTRL_115)
1573 sw_dev->cpu_port = 5;
1574 }
1575
1576 if (dev_of_node(dev->dev)) {
1577 ret = b53_switch_init_of(dev);
1578 if (ret)
1579 return ret;
1580 }
1581
1582 dev->enabled_ports |= BIT(sw_dev->cpu_port);
1583 sw_dev->ports = fls(dev->enabled_ports);
1584
1585 dev->ports = devm_kzalloc(dev->dev,
1586 sizeof(struct b53_port) * sw_dev->ports,
1587 GFP_KERNEL);
1588 if (!dev->ports)
1589 return -ENOMEM;
1590
1591 dev->vlans = devm_kzalloc(dev->dev,
1592 sizeof(struct b53_vlan) * sw_dev->vlans,
1593 GFP_KERNEL);
1594 if (!dev->vlans)
1595 return -ENOMEM;
1596
1597 dev->buf = devm_kzalloc(dev->dev, B53_BUF_SIZE, GFP_KERNEL);
1598 if (!dev->buf)
1599 return -ENOMEM;
1600
1601 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1602 if (dev->reset_gpio >= 0) {
1603 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1604 GPIOF_OUT_INIT_HIGH, "robo_reset");
1605 if (ret)
1606 return ret;
1607 }
1608
1609 return b53_switch_reset(dev);
1610 }
1611
1612 struct b53_device *b53_switch_alloc(struct device *base, struct b53_io_ops *ops,
1613 void *priv)
1614 {
1615 struct b53_device *dev;
1616
1617 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1618 if (!dev)
1619 return NULL;
1620
1621 dev->dev = base;
1622 dev->ops = ops;
1623 dev->priv = priv;
1624 mutex_init(&dev->reg_mutex);
1625
1626 return dev;
1627 }
1628 EXPORT_SYMBOL(b53_switch_alloc);
1629
1630 int b53_switch_detect(struct b53_device *dev)
1631 {
1632 u32 id32;
1633 u16 tmp;
1634 u8 id8;
1635 int ret;
1636
1637 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1638 if (ret)
1639 return ret;
1640
1641 switch (id8) {
1642 case 0:
1643 /*
1644 * BCM5325 and BCM5365 do not have this register so reads
1645 * return 0. But the read operation did succeed, so assume
1646 * this is one of them.
1647 *
1648 * Next check if we can write to the 5325's VTA register; for
1649 * 5365 it is read only.
1650 */
1651
1652 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1653 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1654
1655 if (tmp == 0xf)
1656 dev->chip_id = BCM5325_DEVICE_ID;
1657 else
1658 dev->chip_id = BCM5365_DEVICE_ID;
1659 break;
1660 case BCM5395_DEVICE_ID:
1661 case BCM5397_DEVICE_ID:
1662 case BCM5398_DEVICE_ID:
1663 dev->chip_id = id8;
1664 break;
1665 default:
1666 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1667 if (ret)
1668 return ret;
1669
1670 switch (id32) {
1671 case BCM53115_DEVICE_ID:
1672 case BCM53125_DEVICE_ID:
1673 case BCM53128_DEVICE_ID:
1674 case BCM53010_DEVICE_ID:
1675 case BCM53011_DEVICE_ID:
1676 case BCM53012_DEVICE_ID:
1677 case BCM53018_DEVICE_ID:
1678 case BCM53019_DEVICE_ID:
1679 dev->chip_id = id32;
1680 break;
1681 default:
1682 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1683 id8, id32);
1684 return -ENODEV;
1685 }
1686 }
1687
1688 if (dev->chip_id == BCM5325_DEVICE_ID)
1689 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1690 &dev->core_rev);
1691 else
1692 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1693 &dev->core_rev);
1694 }
1695 EXPORT_SYMBOL(b53_switch_detect);
1696
1697 int b53_switch_register(struct b53_device *dev)
1698 {
1699 int ret;
1700
1701 if (dev->pdata) {
1702 dev->chip_id = dev->pdata->chip_id;
1703 dev->enabled_ports = dev->pdata->enabled_ports;
1704 dev->sw_dev.alias = dev->pdata->alias;
1705 }
1706
1707 if (!dev->chip_id && b53_switch_detect(dev))
1708 return -EINVAL;
1709
1710 ret = b53_switch_init(dev);
1711 if (ret)
1712 return ret;
1713
1714 pr_info("found switch: %s, rev %i\n", dev->sw_dev.name, dev->core_rev);
1715
1716 return register_switch(&dev->sw_dev, NULL);
1717 }
1718 EXPORT_SYMBOL(b53_switch_register);
1719
1720 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1721 MODULE_DESCRIPTION("B53 switch library");
1722 MODULE_LICENSE("Dual BSD/GPL");
Staging tree of Zoltan Herpai