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kernel: rtl8306: fix vlan support on lantiq ar9 p2601hnfx
[openwrt/staging/wigyori.git] / target / linux / generic / files / drivers / net / phy / rtl8306.c
1 /*
2 * rtl8306.c: RTL8306S switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/if.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/list.h>
20 #include <linux/if_ether.h>
21 #include <linux/skbuff.h>
22 #include <linux/netdevice.h>
23 #include <linux/netlink.h>
24 #include <net/genetlink.h>
25 #include <linux/switch.h>
26 #include <linux/delay.h>
27 #include <linux/phy.h>
28
29 //#define DEBUG 1
30
31 /* Global (PHY0) */
32 #define RTL8306_REG_PAGE 16
33 #define RTL8306_REG_PAGE_LO (1 << 15)
34 #define RTL8306_REG_PAGE_HI (1 << 1) /* inverted */
35
36 #define RTL8306_NUM_VLANS 16
37 #define RTL8306_NUM_PORTS 6
38 #define RTL8306_PORT_CPU 5
39 #define RTL8306_NUM_PAGES 4
40 #define RTL8306_NUM_REGS 32
41
42 #define RTL_NAME_S "RTL8306S"
43 #define RTL_NAME_SD "RTL8306SD"
44 #define RTL_NAME_SDM "RTL8306SDM"
45 #define RTL_NAME_UNKNOWN "RTL8306(unknown)"
46
47 #define RTL8306_MAGIC 0x8306
48
49 static LIST_HEAD(phydevs);
50
51 struct rtl_priv {
52 struct list_head list;
53 struct switch_dev dev;
54 int page;
55 int type;
56 int do_cpu;
57 struct mii_bus *bus;
58 char hwname[sizeof(RTL_NAME_UNKNOWN)];
59 bool fixup;
60 };
61
62 struct rtl_phyregs {
63 int nway;
64 int speed;
65 int duplex;
66 };
67
68 #define to_rtl(_dev) container_of(_dev, struct rtl_priv, dev)
69
70 enum {
71 RTL_TYPE_S,
72 RTL_TYPE_SD,
73 RTL_TYPE_SDM,
74 };
75
76 struct rtl_reg {
77 int page;
78 int phy;
79 int reg;
80 int bits;
81 int shift;
82 int inverted;
83 };
84
85 #define RTL_VLAN_REGOFS(name) \
86 (RTL_REG_VLAN1_##name - RTL_REG_VLAN0_##name)
87
88 #define RTL_PORT_REGOFS(name) \
89 (RTL_REG_PORT1_##name - RTL_REG_PORT0_##name)
90
91 #define RTL_PORT_REG(id, reg) \
92 (RTL_REG_PORT0_##reg + (id * RTL_PORT_REGOFS(reg)))
93
94 #define RTL_VLAN_REG(id, reg) \
95 (RTL_REG_VLAN0_##reg + (id * RTL_VLAN_REGOFS(reg)))
96
97 #define RTL_GLOBAL_REGATTR(reg) \
98 .id = RTL_REG_##reg, \
99 .type = SWITCH_TYPE_INT, \
100 .ofs = 0, \
101 .set = rtl_attr_set_int, \
102 .get = rtl_attr_get_int
103
104 #define RTL_PORT_REGATTR(reg) \
105 .id = RTL_REG_PORT0_##reg, \
106 .type = SWITCH_TYPE_INT, \
107 .ofs = RTL_PORT_REGOFS(reg), \
108 .set = rtl_attr_set_port_int, \
109 .get = rtl_attr_get_port_int
110
111 #define RTL_VLAN_REGATTR(reg) \
112 .id = RTL_REG_VLAN0_##reg, \
113 .type = SWITCH_TYPE_INT, \
114 .ofs = RTL_VLAN_REGOFS(reg), \
115 .set = rtl_attr_set_vlan_int, \
116 .get = rtl_attr_get_vlan_int
117
118 enum rtl_regidx {
119 RTL_REG_CHIPID,
120 RTL_REG_CHIPVER,
121 RTL_REG_CHIPTYPE,
122 RTL_REG_CPUPORT,
123
124 RTL_REG_EN_CPUPORT,
125 RTL_REG_EN_TAG_OUT,
126 RTL_REG_EN_TAG_CLR,
127 RTL_REG_EN_TAG_IN,
128 RTL_REG_TRAP_CPU,
129 RTL_REG_CPU_LINKUP,
130 RTL_REG_TRUNK_PORTSEL,
131 RTL_REG_EN_TRUNK,
132 RTL_REG_RESET,
133
134 RTL_REG_VLAN_ENABLE,
135 RTL_REG_VLAN_FILTER,
136 RTL_REG_VLAN_TAG_ONLY,
137 RTL_REG_VLAN_TAG_AWARE,
138 #define RTL_VLAN_ENUM(id) \
139 RTL_REG_VLAN##id##_VID, \
140 RTL_REG_VLAN##id##_PORTMASK
141 RTL_VLAN_ENUM(0),
142 RTL_VLAN_ENUM(1),
143 RTL_VLAN_ENUM(2),
144 RTL_VLAN_ENUM(3),
145 RTL_VLAN_ENUM(4),
146 RTL_VLAN_ENUM(5),
147 RTL_VLAN_ENUM(6),
148 RTL_VLAN_ENUM(7),
149 RTL_VLAN_ENUM(8),
150 RTL_VLAN_ENUM(9),
151 RTL_VLAN_ENUM(10),
152 RTL_VLAN_ENUM(11),
153 RTL_VLAN_ENUM(12),
154 RTL_VLAN_ENUM(13),
155 RTL_VLAN_ENUM(14),
156 RTL_VLAN_ENUM(15),
157 #define RTL_PORT_ENUM(id) \
158 RTL_REG_PORT##id##_PVID, \
159 RTL_REG_PORT##id##_NULL_VID_REPLACE, \
160 RTL_REG_PORT##id##_NON_PVID_DISCARD, \
161 RTL_REG_PORT##id##_VID_INSERT, \
162 RTL_REG_PORT##id##_TAG_INSERT, \
163 RTL_REG_PORT##id##_LINK, \
164 RTL_REG_PORT##id##_SPEED, \
165 RTL_REG_PORT##id##_NWAY, \
166 RTL_REG_PORT##id##_NRESTART, \
167 RTL_REG_PORT##id##_DUPLEX, \
168 RTL_REG_PORT##id##_RXEN, \
169 RTL_REG_PORT##id##_TXEN
170 RTL_PORT_ENUM(0),
171 RTL_PORT_ENUM(1),
172 RTL_PORT_ENUM(2),
173 RTL_PORT_ENUM(3),
174 RTL_PORT_ENUM(4),
175 RTL_PORT_ENUM(5),
176 };
177
178 static const struct rtl_reg rtl_regs[] = {
179 [RTL_REG_CHIPID] = { 0, 4, 30, 16, 0, 0 },
180 [RTL_REG_CHIPVER] = { 0, 4, 31, 8, 0, 0 },
181 [RTL_REG_CHIPTYPE] = { 0, 4, 31, 2, 8, 0 },
182
183 /* CPU port number */
184 [RTL_REG_CPUPORT] = { 2, 4, 21, 3, 0, 0 },
185 /* Enable CPU port function */
186 [RTL_REG_EN_CPUPORT] = { 3, 2, 21, 1, 15, 1 },
187 /* Enable CPU port tag insertion */
188 [RTL_REG_EN_TAG_OUT] = { 3, 2, 21, 1, 12, 0 },
189 /* Enable CPU port tag removal */
190 [RTL_REG_EN_TAG_CLR] = { 3, 2, 21, 1, 11, 0 },
191 /* Enable CPU port tag checking */
192 [RTL_REG_EN_TAG_IN] = { 0, 4, 21, 1, 7, 0 },
193 [RTL_REG_EN_TRUNK] = { 0, 0, 19, 1, 11, 1 },
194 [RTL_REG_TRUNK_PORTSEL] = { 0, 0, 16, 1, 6, 1 },
195 [RTL_REG_RESET] = { 0, 0, 16, 1, 12, 0 },
196
197 [RTL_REG_TRAP_CPU] = { 3, 2, 22, 1, 6, 0 },
198 [RTL_REG_CPU_LINKUP] = { 0, 6, 22, 1, 15, 0 },
199
200 [RTL_REG_VLAN_TAG_ONLY] = { 0, 0, 16, 1, 8, 1 },
201 [RTL_REG_VLAN_FILTER] = { 0, 0, 16, 1, 9, 1 },
202 [RTL_REG_VLAN_TAG_AWARE] = { 0, 0, 16, 1, 10, 1 },
203 [RTL_REG_VLAN_ENABLE] = { 0, 0, 18, 1, 8, 1 },
204
205 #define RTL_VLAN_REGS(id, phy, page, regofs) \
206 [RTL_REG_VLAN##id##_VID] = { page, phy, 25 + regofs, 12, 0, 0 }, \
207 [RTL_REG_VLAN##id##_PORTMASK] = { page, phy, 24 + regofs, 6, 0, 0 }
208 RTL_VLAN_REGS( 0, 0, 0, 0),
209 RTL_VLAN_REGS( 1, 1, 0, 0),
210 RTL_VLAN_REGS( 2, 2, 0, 0),
211 RTL_VLAN_REGS( 3, 3, 0, 0),
212 RTL_VLAN_REGS( 4, 4, 0, 0),
213 RTL_VLAN_REGS( 5, 0, 1, 2),
214 RTL_VLAN_REGS( 6, 1, 1, 2),
215 RTL_VLAN_REGS( 7, 2, 1, 2),
216 RTL_VLAN_REGS( 8, 3, 1, 2),
217 RTL_VLAN_REGS( 9, 4, 1, 2),
218 RTL_VLAN_REGS(10, 0, 1, 4),
219 RTL_VLAN_REGS(11, 1, 1, 4),
220 RTL_VLAN_REGS(12, 2, 1, 4),
221 RTL_VLAN_REGS(13, 3, 1, 4),
222 RTL_VLAN_REGS(14, 4, 1, 4),
223 RTL_VLAN_REGS(15, 0, 1, 6),
224
225 #define REG_PORT_SETTING(port, phy) \
226 [RTL_REG_PORT##port##_SPEED] = { 0, phy, 0, 1, 13, 0 }, \
227 [RTL_REG_PORT##port##_NWAY] = { 0, phy, 0, 1, 12, 0 }, \
228 [RTL_REG_PORT##port##_NRESTART] = { 0, phy, 0, 1, 9, 0 }, \
229 [RTL_REG_PORT##port##_DUPLEX] = { 0, phy, 0, 1, 8, 0 }, \
230 [RTL_REG_PORT##port##_TXEN] = { 0, phy, 24, 1, 11, 0 }, \
231 [RTL_REG_PORT##port##_RXEN] = { 0, phy, 24, 1, 10, 0 }, \
232 [RTL_REG_PORT##port##_LINK] = { 0, phy, 1, 1, 2, 0 }, \
233 [RTL_REG_PORT##port##_NULL_VID_REPLACE] = { 0, phy, 22, 1, 12, 0 }, \
234 [RTL_REG_PORT##port##_NON_PVID_DISCARD] = { 0, phy, 22, 1, 11, 0 }, \
235 [RTL_REG_PORT##port##_VID_INSERT] = { 0, phy, 22, 2, 9, 0 }, \
236 [RTL_REG_PORT##port##_TAG_INSERT] = { 0, phy, 22, 2, 0, 0 }
237
238 REG_PORT_SETTING(0, 0),
239 REG_PORT_SETTING(1, 1),
240 REG_PORT_SETTING(2, 2),
241 REG_PORT_SETTING(3, 3),
242 REG_PORT_SETTING(4, 4),
243 REG_PORT_SETTING(5, 6),
244
245 #define REG_PORT_PVID(phy, page, regofs) \
246 { page, phy, 24 + regofs, 4, 12, 0 }
247 [RTL_REG_PORT0_PVID] = REG_PORT_PVID(0, 0, 0),
248 [RTL_REG_PORT1_PVID] = REG_PORT_PVID(1, 0, 0),
249 [RTL_REG_PORT2_PVID] = REG_PORT_PVID(2, 0, 0),
250 [RTL_REG_PORT3_PVID] = REG_PORT_PVID(3, 0, 0),
251 [RTL_REG_PORT4_PVID] = REG_PORT_PVID(4, 0, 0),
252 [RTL_REG_PORT5_PVID] = REG_PORT_PVID(0, 1, 2),
253 };
254
255
256 static inline void
257 rtl_set_page(struct rtl_priv *priv, unsigned int page)
258 {
259 struct mii_bus *bus = priv->bus;
260 u16 pgsel;
261
262 if (priv->fixup)
263 return;
264
265 if (priv->page == page)
266 return;
267
268 BUG_ON(page > RTL8306_NUM_PAGES);
269 pgsel = bus->read(bus, 0, RTL8306_REG_PAGE);
270 pgsel &= ~(RTL8306_REG_PAGE_LO | RTL8306_REG_PAGE_HI);
271 if (page & (1 << 0))
272 pgsel |= RTL8306_REG_PAGE_LO;
273 if (!(page & (1 << 1))) /* bit is inverted */
274 pgsel |= RTL8306_REG_PAGE_HI;
275 bus->write(bus, 0, RTL8306_REG_PAGE, pgsel);
276 }
277
278 static inline int
279 rtl_w16(struct switch_dev *dev, unsigned int page, unsigned int phy, unsigned int reg, u16 val)
280 {
281 struct rtl_priv *priv = to_rtl(dev);
282 struct mii_bus *bus = priv->bus;
283
284 rtl_set_page(priv, page);
285 bus->write(bus, phy, reg, val);
286 bus->read(bus, phy, reg); /* flush */
287 return 0;
288 }
289
290 static inline int
291 rtl_r16(struct switch_dev *dev, unsigned int page, unsigned int phy, unsigned int reg)
292 {
293 struct rtl_priv *priv = to_rtl(dev);
294 struct mii_bus *bus = priv->bus;
295
296 rtl_set_page(priv, page);
297 return bus->read(bus, phy, reg);
298 }
299
300 static inline u16
301 rtl_rmw(struct switch_dev *dev, unsigned int page, unsigned int phy, unsigned int reg, u16 mask, u16 val)
302 {
303 struct rtl_priv *priv = to_rtl(dev);
304 struct mii_bus *bus = priv->bus;
305 u16 r;
306
307 rtl_set_page(priv, page);
308 r = bus->read(bus, phy, reg);
309 r &= ~mask;
310 r |= val;
311 bus->write(bus, phy, reg, r);
312 return bus->read(bus, phy, reg); /* flush */
313 }
314
315
316 static inline int
317 rtl_get(struct switch_dev *dev, enum rtl_regidx s)
318 {
319 const struct rtl_reg *r = &rtl_regs[s];
320 u16 val;
321
322 BUG_ON(s >= ARRAY_SIZE(rtl_regs));
323 if (r->bits == 0) /* unimplemented */
324 return 0;
325
326 val = rtl_r16(dev, r->page, r->phy, r->reg);
327
328 if (r->shift > 0)
329 val >>= r->shift;
330
331 if (r->inverted)
332 val = ~val;
333
334 val &= (1 << r->bits) - 1;
335
336 return val;
337 }
338
339 static int
340 rtl_set(struct switch_dev *dev, enum rtl_regidx s, unsigned int val)
341 {
342 const struct rtl_reg *r = &rtl_regs[s];
343 u16 mask = 0xffff;
344
345 BUG_ON(s >= ARRAY_SIZE(rtl_regs));
346
347 if (r->bits == 0) /* unimplemented */
348 return 0;
349
350 if (r->shift > 0)
351 val <<= r->shift;
352
353 if (r->inverted)
354 val = ~val;
355
356 if (r->bits != 16) {
357 mask = (1 << r->bits) - 1;
358 mask <<= r->shift;
359 }
360 val &= mask;
361 return rtl_rmw(dev, r->page, r->phy, r->reg, mask, val);
362 }
363
364 static void
365 rtl_fix_pvids(struct switch_dev *dev)
366 {
367 unsigned int port, vlan, mask;
368
369 for (port = 0; port < RTL8306_NUM_PORTS; port++)
370 {
371 /* skip tagged ports */
372 if (rtl_get(dev, RTL_PORT_REG(port, TAG_INSERT)) != 1)
373 continue;
374
375 for (vlan = 0; vlan < RTL8306_NUM_VLANS; vlan++)
376 {
377 mask = rtl_get(dev, RTL_VLAN_REG(vlan, PORTMASK));
378 /* skip non-members */
379 if (!(mask & (1 << port)))
380 continue;
381
382 rtl_set(dev, RTL_PORT_REG(port, PVID), vlan);
383 /* next port */
384 break;
385 }
386 }
387 }
388
389 static void
390 rtl_phy_save(struct switch_dev *dev, int port, struct rtl_phyregs *regs)
391 {
392 regs->nway = rtl_get(dev, RTL_PORT_REG(port, NWAY));
393 regs->speed = rtl_get(dev, RTL_PORT_REG(port, SPEED));
394 regs->duplex = rtl_get(dev, RTL_PORT_REG(port, DUPLEX));
395 }
396
397 static void
398 rtl_phy_restore(struct switch_dev *dev, int port, struct rtl_phyregs *regs)
399 {
400 rtl_set(dev, RTL_PORT_REG(port, NWAY), regs->nway);
401 rtl_set(dev, RTL_PORT_REG(port, SPEED), regs->speed);
402 rtl_set(dev, RTL_PORT_REG(port, DUPLEX), regs->duplex);
403 }
404
405 static void
406 rtl_port_set_enable(struct switch_dev *dev, int port, int enabled)
407 {
408 rtl_set(dev, RTL_PORT_REG(port, RXEN), enabled);
409 rtl_set(dev, RTL_PORT_REG(port, TXEN), enabled);
410
411 if ((port >= 5) || !enabled)
412 return;
413
414 /* restart autonegotiation if enabled */
415 rtl_set(dev, RTL_PORT_REG(port, NRESTART), 1);
416 }
417
418 static int
419 rtl_hw_apply(struct switch_dev *dev)
420 {
421 int i;
422 int trunk_en, trunk_psel;
423 struct rtl_phyregs port5;
424
425 rtl_phy_save(dev, 5, &port5);
426
427 /* disable rx/tx from PHYs */
428 for (i = 0; i < RTL8306_NUM_PORTS - 1; i++) {
429 rtl_port_set_enable(dev, i, 0);
430 }
431
432 /* save trunking status */
433 trunk_en = rtl_get(dev, RTL_REG_EN_TRUNK);
434 trunk_psel = rtl_get(dev, RTL_REG_TRUNK_PORTSEL);
435
436 /* trunk port 3 and 4
437 * XXX: Big WTF, but RealTek seems to do it */
438 rtl_set(dev, RTL_REG_EN_TRUNK, 1);
439 rtl_set(dev, RTL_REG_TRUNK_PORTSEL, 1);
440
441 /* execute the software reset */
442 rtl_set(dev, RTL_REG_RESET, 1);
443
444 /* wait for the reset to complete,
445 * but don't wait for too long */
446 for (i = 0; i < 10; i++) {
447 if (rtl_get(dev, RTL_REG_RESET) == 0)
448 break;
449
450 msleep(1);
451 }
452
453 /* enable rx/tx from PHYs */
454 for (i = 0; i < RTL8306_NUM_PORTS - 1; i++) {
455 rtl_port_set_enable(dev, i, 1);
456 }
457
458 /* restore trunking settings */
459 rtl_set(dev, RTL_REG_EN_TRUNK, trunk_en);
460 rtl_set(dev, RTL_REG_TRUNK_PORTSEL, trunk_psel);
461 rtl_phy_restore(dev, 5, &port5);
462
463 rtl_set(dev, RTL_REG_CPU_LINKUP, 1);
464
465 return 0;
466 }
467
468 static void
469 rtl_hw_init(struct switch_dev *dev)
470 {
471 struct rtl_priv *priv = to_rtl(dev);
472 int i;
473
474 rtl_set(dev, RTL_REG_VLAN_ENABLE, 0);
475 rtl_set(dev, RTL_REG_VLAN_FILTER, 0);
476 rtl_set(dev, RTL_REG_EN_TRUNK, 0);
477 rtl_set(dev, RTL_REG_TRUNK_PORTSEL, 0);
478
479 /* initialize cpu port settings */
480 if (priv->do_cpu) {
481 rtl_set(dev, RTL_REG_CPUPORT, dev->cpu_port);
482 rtl_set(dev, RTL_REG_EN_CPUPORT, 1);
483 } else {
484 rtl_set(dev, RTL_REG_CPUPORT, 7);
485 rtl_set(dev, RTL_REG_EN_CPUPORT, 0);
486 }
487 rtl_set(dev, RTL_REG_EN_TAG_OUT, 0);
488 rtl_set(dev, RTL_REG_EN_TAG_IN, 0);
489 rtl_set(dev, RTL_REG_EN_TAG_CLR, 0);
490
491 /* reset all vlans */
492 for (i = 0; i < RTL8306_NUM_VLANS; i++) {
493 rtl_set(dev, RTL_VLAN_REG(i, VID), i);
494 rtl_set(dev, RTL_VLAN_REG(i, PORTMASK), 0);
495 }
496
497 #ifdef DEBUG
498 /* default to port isolation */
499 for (i = 0; i < RTL8306_NUM_PORTS; i++) {
500 if (i != dev->cpu_port)
501 rtl_set(dev, RTL_VLAN_REG(i, PORTMASK), (1 << dev->cpu_port) | (1 << i));
502 rtl_set(dev, RTL_PORT_REG(i, PVID), i);
503 rtl_set(dev, RTL_PORT_REG(i, NULL_VID_REPLACE), 1);
504 rtl_set(dev, RTL_PORT_REG(i, VID_INSERT), 1);
505 rtl_set(dev, RTL_PORT_REG(i, TAG_INSERT), 3);
506 }
507 #endif
508 rtl_fix_pvids(dev);
509
510 rtl_hw_apply(dev);
511 }
512
513 #ifdef DEBUG
514 static int
515 rtl_set_use_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
516 {
517 struct rtl_priv *priv = to_rtl(dev);
518 priv->do_cpu = val->value.i;
519 rtl_hw_init(dev);
520 return 0;
521 }
522
523 static int
524 rtl_get_use_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
525 {
526 struct rtl_priv *priv = to_rtl(dev);
527 val->value.i = priv->do_cpu;
528 return 0;
529 }
530
531 static int
532 rtl_set_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
533 {
534 dev->cpu_port = val->value.i;
535 rtl_hw_init(dev);
536 return 0;
537 }
538
539 static int
540 rtl_get_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
541 {
542 val->value.i = dev->cpu_port;
543 return 0;
544 }
545 #endif
546
547 static int
548 rtl_reset(struct switch_dev *dev)
549 {
550 rtl_hw_init(dev);
551 return 0;
552 }
553
554 static int
555 rtl_attr_set_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
556 {
557 int idx = attr->id + (val->port_vlan * attr->ofs);
558 struct rtl_phyregs port;
559
560 if (attr->id >= ARRAY_SIZE(rtl_regs))
561 return -EINVAL;
562
563 if ((attr->max > 0) && (val->value.i > attr->max))
564 return -EINVAL;
565
566 /* access to phy register 22 on port 4/5
567 * needs phy status save/restore */
568 if ((val->port_vlan > 3) &&
569 (rtl_regs[idx].reg == 22) &&
570 (rtl_regs[idx].page == 0)) {
571
572 rtl_phy_save(dev, val->port_vlan, &port);
573 rtl_set(dev, idx, val->value.i);
574 rtl_phy_restore(dev, val->port_vlan, &port);
575 } else {
576 rtl_set(dev, idx, val->value.i);
577 }
578
579 return 0;
580 }
581
582 static int
583 rtl_attr_get_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
584 {
585 int idx = attr->id + (val->port_vlan * attr->ofs);
586
587 if (idx >= ARRAY_SIZE(rtl_regs))
588 return -EINVAL;
589
590 val->value.i = rtl_get(dev, idx);
591 return 0;
592 }
593
594 #ifdef DEBUG
595 static int
596 rtl_attr_set_port_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
597 {
598 if (val->port_vlan >= RTL8306_NUM_PORTS)
599 return -EINVAL;
600
601 return rtl_attr_set_int(dev, attr, val);
602 }
603
604 static int
605 rtl_attr_get_port_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
606 {
607 if (val->port_vlan >= RTL8306_NUM_PORTS)
608 return -EINVAL;
609 return rtl_attr_get_int(dev, attr, val);
610 }
611 #endif
612
613 static int
614 rtl_attr_set_port_pvid(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
615 {
616 unsigned int vlan;
617
618 if (val->port_vlan >= RTL8306_NUM_PORTS)
619 return -EINVAL;
620
621 for (vlan = 0; vlan < RTL8306_NUM_VLANS; vlan++) {
622 if (rtl_get(dev, RTL_VLAN_REG(vlan, VID)) == val->value.i) {
623 rtl_set(dev, RTL_PORT_REG(val->port_vlan, PVID), vlan);
624 break;
625 }
626 }
627
628 return 0;
629 }
630
631 static int
632 rtl_attr_get_port_pvid(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
633 {
634 unsigned int vlan;
635
636 if (val->port_vlan >= RTL8306_NUM_PORTS)
637 return -EINVAL;
638
639 vlan = rtl_get(dev, RTL_PORT_REG(val->port_vlan, PVID));
640 val->value.i = rtl_get(dev, RTL_VLAN_REG(vlan, VID));
641
642 return 0;
643 }
644
645 static int
646 rtl_get_port_link(struct switch_dev *dev, int port, struct switch_port_link *link)
647 {
648 if (port >= RTL8306_NUM_PORTS)
649 return -EINVAL;
650
651 link->link = rtl_get(dev, RTL_PORT_REG(port, LINK));
652 if (!link->link)
653 return 0;
654
655 link->duplex = rtl_get(dev, RTL_PORT_REG(port, DUPLEX));
656 link->aneg = rtl_get(dev, RTL_PORT_REG(port, NWAY));
657
658 if (rtl_get(dev, RTL_PORT_REG(port, SPEED)))
659 link->speed = SWITCH_PORT_SPEED_100;
660 else
661 link->speed = SWITCH_PORT_SPEED_10;
662
663 return 0;
664 }
665
666 static int
667 rtl_attr_set_vlan_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
668 {
669 if (val->port_vlan >= dev->vlans)
670 return -EINVAL;
671
672 return rtl_attr_set_int(dev, attr, val);
673 }
674
675 static int
676 rtl_attr_get_vlan_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
677 {
678 if (val->port_vlan >= dev->vlans)
679 return -EINVAL;
680
681 return rtl_attr_get_int(dev, attr, val);
682 }
683
684 static int
685 rtl_get_ports(struct switch_dev *dev, struct switch_val *val)
686 {
687 unsigned int i, mask;
688
689 mask = rtl_get(dev, RTL_VLAN_REG(val->port_vlan, PORTMASK));
690 for (i = 0; i < RTL8306_NUM_PORTS; i++) {
691 struct switch_port *port;
692
693 if (!(mask & (1 << i)))
694 continue;
695
696 port = &val->value.ports[val->len];
697 port->id = i;
698 if (rtl_get(dev, RTL_PORT_REG(i, TAG_INSERT)) == 2)
699 port->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
700 val->len++;
701 }
702
703 return 0;
704 }
705
706 static int
707 rtl_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
708 {
709 struct rtl_priv *priv = to_rtl(dev);
710 struct rtl_phyregs port;
711 int en = val->value.i;
712 int i;
713
714 rtl_set(dev, RTL_REG_EN_TAG_OUT, en && priv->do_cpu);
715 rtl_set(dev, RTL_REG_EN_TAG_IN, en && priv->do_cpu);
716 rtl_set(dev, RTL_REG_EN_TAG_CLR, en && priv->do_cpu);
717 rtl_set(dev, RTL_REG_VLAN_TAG_AWARE, en);
718 if (en)
719 rtl_set(dev, RTL_REG_VLAN_FILTER, en);
720
721 for (i = 0; i < RTL8306_NUM_PORTS; i++) {
722 if (i > 3)
723 rtl_phy_save(dev, val->port_vlan, &port);
724 rtl_set(dev, RTL_PORT_REG(i, NULL_VID_REPLACE), 1);
725 rtl_set(dev, RTL_PORT_REG(i, VID_INSERT), 1);
726 rtl_set(dev, RTL_PORT_REG(i, TAG_INSERT), (en ? 1 : 3));
727 if (i > 3)
728 rtl_phy_restore(dev, val->port_vlan, &port);
729 }
730 rtl_set(dev, RTL_REG_VLAN_ENABLE, en);
731
732 rtl_fix_pvids(dev);
733
734 return 0;
735 }
736
737 static int
738 rtl_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
739 {
740 val->value.i = rtl_get(dev, RTL_REG_VLAN_ENABLE);
741 return 0;
742 }
743
744 static int
745 rtl_set_ports(struct switch_dev *dev, struct switch_val *val)
746 {
747 unsigned int mask = 0;
748 int i;
749
750 for(i = 0; i < val->len; i++)
751 {
752 struct switch_port *port = &val->value.ports[i];
753 bool tagged = false;
754
755 mask |= (1 << port->id);
756
757 if (port->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
758 tagged = true;
759
760 rtl_set(dev, RTL_PORT_REG(port->id, NON_PVID_DISCARD), (tagged ? 0 : 1));
761 rtl_set(dev, RTL_PORT_REG(port->id, VID_INSERT), (tagged ? 0 : 1));
762 rtl_set(dev, RTL_PORT_REG(port->id, TAG_INSERT), (tagged ? 2 : 1));
763 }
764
765 rtl_set(dev, RTL_VLAN_REG(val->port_vlan, PORTMASK), mask);
766
767 rtl_fix_pvids(dev);
768
769 return 0;
770 }
771
772 static struct switch_attr rtl_globals[] = {
773 {
774 .type = SWITCH_TYPE_INT,
775 .name = "enable_vlan",
776 .description = "Enable VLAN mode",
777 .max = 1,
778 .set = rtl_set_vlan,
779 .get = rtl_get_vlan,
780 },
781 {
782 RTL_GLOBAL_REGATTR(EN_TRUNK),
783 .name = "trunk",
784 .description = "Enable port trunking",
785 .max = 1,
786 },
787 {
788 RTL_GLOBAL_REGATTR(TRUNK_PORTSEL),
789 .name = "trunk_sel",
790 .description = "Select ports for trunking (0: 0,1 - 1: 3,4)",
791 .max = 1,
792 },
793 #ifdef DEBUG
794 {
795 RTL_GLOBAL_REGATTR(VLAN_FILTER),
796 .name = "vlan_filter",
797 .description = "Filter incoming packets for allowed VLANS",
798 .max = 1,
799 },
800 {
801 .type = SWITCH_TYPE_INT,
802 .name = "cpuport",
803 .description = "CPU Port",
804 .set = rtl_set_cpuport,
805 .get = rtl_get_cpuport,
806 .max = RTL8306_NUM_PORTS,
807 },
808 {
809 .type = SWITCH_TYPE_INT,
810 .name = "use_cpuport",
811 .description = "CPU Port handling flag",
812 .set = rtl_set_use_cpuport,
813 .get = rtl_get_use_cpuport,
814 .max = RTL8306_NUM_PORTS,
815 },
816 {
817 RTL_GLOBAL_REGATTR(TRAP_CPU),
818 .name = "trap_cpu",
819 .description = "VLAN trap to CPU",
820 .max = 1,
821 },
822 {
823 RTL_GLOBAL_REGATTR(VLAN_TAG_AWARE),
824 .name = "vlan_tag_aware",
825 .description = "Enable VLAN tag awareness",
826 .max = 1,
827 },
828 {
829 RTL_GLOBAL_REGATTR(VLAN_TAG_ONLY),
830 .name = "tag_only",
831 .description = "Only accept tagged packets",
832 .max = 1,
833 },
834 #endif
835 };
836 static struct switch_attr rtl_port[] = {
837 {
838 .type = SWITCH_TYPE_INT,
839 .set = rtl_attr_set_port_pvid,
840 .get = rtl_attr_get_port_pvid,
841 .name = "pvid",
842 .description = "Port VLAN ID",
843 .max = 4095,
844 },
845 #ifdef DEBUG
846 {
847 RTL_PORT_REGATTR(NULL_VID_REPLACE),
848 .name = "null_vid",
849 .description = "NULL VID gets replaced by port default vid",
850 .max = 1,
851 },
852 {
853 RTL_PORT_REGATTR(NON_PVID_DISCARD),
854 .name = "non_pvid_discard",
855 .description = "discard packets with VID != PVID",
856 .max = 1,
857 },
858 {
859 RTL_PORT_REGATTR(VID_INSERT),
860 .name = "vid_insert_remove",
861 .description = "how should the switch insert and remove vids ?",
862 .max = 3,
863 },
864 {
865 RTL_PORT_REGATTR(TAG_INSERT),
866 .name = "tag_insert",
867 .description = "tag insertion handling",
868 .max = 3,
869 },
870 #endif
871 };
872
873 static struct switch_attr rtl_vlan[] = {
874 {
875 RTL_VLAN_REGATTR(VID),
876 .name = "vid",
877 .description = "VLAN ID (1-4095)",
878 .max = 4095,
879 },
880 };
881
882 static const struct switch_dev_ops rtl8306_ops = {
883 .attr_global = {
884 .attr = rtl_globals,
885 .n_attr = ARRAY_SIZE(rtl_globals),
886 },
887 .attr_port = {
888 .attr = rtl_port,
889 .n_attr = ARRAY_SIZE(rtl_port),
890 },
891 .attr_vlan = {
892 .attr = rtl_vlan,
893 .n_attr = ARRAY_SIZE(rtl_vlan),
894 },
895
896 .get_vlan_ports = rtl_get_ports,
897 .set_vlan_ports = rtl_set_ports,
898 .apply_config = rtl_hw_apply,
899 .reset_switch = rtl_reset,
900 .get_port_link = rtl_get_port_link,
901 };
902
903 static int
904 rtl8306_config_init(struct phy_device *pdev)
905 {
906 struct net_device *netdev = pdev->attached_dev;
907 struct rtl_priv *priv = pdev->priv;
908 struct switch_dev *dev = &priv->dev;
909 struct switch_val val;
910 unsigned int chipid, chipver, chiptype;
911 int err;
912
913 /* Only init the switch for the primary PHY */
914 if (pdev->addr != 0)
915 return 0;
916
917 val.value.i = 1;
918 priv->dev.cpu_port = RTL8306_PORT_CPU;
919 priv->dev.ports = RTL8306_NUM_PORTS;
920 priv->dev.vlans = RTL8306_NUM_VLANS;
921 priv->dev.ops = &rtl8306_ops;
922 priv->do_cpu = 0;
923 priv->page = -1;
924 priv->bus = pdev->bus;
925
926 chipid = rtl_get(dev, RTL_REG_CHIPID);
927 chipver = rtl_get(dev, RTL_REG_CHIPVER);
928 chiptype = rtl_get(dev, RTL_REG_CHIPTYPE);
929 switch(chiptype) {
930 case 0:
931 case 2:
932 strncpy(priv->hwname, RTL_NAME_S, sizeof(priv->hwname));
933 priv->type = RTL_TYPE_S;
934 break;
935 case 1:
936 strncpy(priv->hwname, RTL_NAME_SD, sizeof(priv->hwname));
937 priv->type = RTL_TYPE_SD;
938 break;
939 case 3:
940 strncpy(priv->hwname, RTL_NAME_SDM, sizeof(priv->hwname));
941 priv->type = RTL_TYPE_SDM;
942 break;
943 default:
944 strncpy(priv->hwname, RTL_NAME_UNKNOWN, sizeof(priv->hwname));
945 break;
946 }
947
948 dev->name = priv->hwname;
949 rtl_hw_init(dev);
950
951 printk(KERN_INFO "Registering %s switch with Chip ID: 0x%04x, version: 0x%04x\n", priv->hwname, chipid, chipver);
952
953 err = register_switch(dev, netdev);
954 if (err < 0) {
955 kfree(priv);
956 return err;
957 }
958
959 return 0;
960 }
961
962
963 static int
964 rtl8306_fixup(struct phy_device *pdev)
965 {
966 struct rtl_priv priv;
967 u16 chipid;
968
969 /* Attach to primary LAN port and WAN port */
970 if (pdev->addr != 0 && pdev->addr != 4)
971 return 0;
972
973 memset(&priv, 0, sizeof(priv));
974 priv.fixup = true;
975 priv.page = -1;
976 priv.bus = pdev->bus;
977 chipid = rtl_get(&priv.dev, RTL_REG_CHIPID);
978 if (chipid == 0x5988)
979 pdev->phy_id = RTL8306_MAGIC;
980
981 return 0;
982 }
983
984 static int
985 rtl8306_probe(struct phy_device *pdev)
986 {
987 struct rtl_priv *priv;
988
989 list_for_each_entry(priv, &phydevs, list) {
990 /*
991 * share one rtl_priv instance between virtual phy
992 * devices on the same bus
993 */
994 if (priv->bus == pdev->bus)
995 goto found;
996 }
997 priv = kzalloc(sizeof(struct rtl_priv), GFP_KERNEL);
998 if (!priv)
999 return -ENOMEM;
1000
1001 priv->bus = pdev->bus;
1002
1003 found:
1004 pdev->priv = priv;
1005 return 0;
1006 }
1007
1008 static void
1009 rtl8306_remove(struct phy_device *pdev)
1010 {
1011 struct rtl_priv *priv = pdev->priv;
1012 unregister_switch(&priv->dev);
1013 kfree(priv);
1014 }
1015
1016 static int
1017 rtl8306_config_aneg(struct phy_device *pdev)
1018 {
1019 struct rtl_priv *priv = pdev->priv;
1020
1021 /* Only for WAN */
1022 if (pdev->addr == 0)
1023 return 0;
1024
1025 /* Restart autonegotiation */
1026 rtl_set(&priv->dev, RTL_PORT_REG(4, NWAY), 1);
1027 rtl_set(&priv->dev, RTL_PORT_REG(4, NRESTART), 1);
1028
1029 return 0;
1030 }
1031
1032 static int
1033 rtl8306_read_status(struct phy_device *pdev)
1034 {
1035 struct rtl_priv *priv = pdev->priv;
1036 struct switch_dev *dev = &priv->dev;
1037
1038 if (pdev->addr == 4) {
1039 /* WAN */
1040 pdev->speed = rtl_get(dev, RTL_PORT_REG(4, SPEED)) ? SPEED_100 : SPEED_10;
1041 pdev->duplex = rtl_get(dev, RTL_PORT_REG(4, DUPLEX)) ? DUPLEX_FULL : DUPLEX_HALF;
1042 pdev->link = !!rtl_get(dev, RTL_PORT_REG(4, LINK));
1043 } else {
1044 /* LAN */
1045 pdev->speed = SPEED_100;
1046 pdev->duplex = DUPLEX_FULL;
1047 pdev->link = 1;
1048 }
1049
1050 /*
1051 * Bypass generic PHY status read,
1052 * it doesn't work with this switch
1053 */
1054 if (pdev->link) {
1055 pdev->state = PHY_RUNNING;
1056 netif_carrier_on(pdev->attached_dev);
1057 pdev->adjust_link(pdev->attached_dev);
1058 } else {
1059 pdev->state = PHY_NOLINK;
1060 netif_carrier_off(pdev->attached_dev);
1061 pdev->adjust_link(pdev->attached_dev);
1062 }
1063
1064 return 0;
1065 }
1066
1067
1068 static struct phy_driver rtl8306_driver = {
1069 .name = "Realtek RTL8306S",
1070 .flags = PHY_HAS_MAGICANEG,
1071 .phy_id = RTL8306_MAGIC,
1072 .phy_id_mask = 0xffffffff,
1073 .features = PHY_BASIC_FEATURES,
1074 .probe = &rtl8306_probe,
1075 .remove = &rtl8306_remove,
1076 .config_init = &rtl8306_config_init,
1077 .config_aneg = &rtl8306_config_aneg,
1078 .read_status = &rtl8306_read_status,
1079 .driver = { .owner = THIS_MODULE,},
1080 };
1081
1082
1083 static int __init
1084 rtl_init(void)
1085 {
1086 phy_register_fixup_for_id(PHY_ANY_ID, rtl8306_fixup);
1087 return phy_driver_register(&rtl8306_driver);
1088 }
1089
1090 static void __exit
1091 rtl_exit(void)
1092 {
1093 phy_driver_unregister(&rtl8306_driver);
1094 }
1095
1096 module_init(rtl_init);
1097 module_exit(rtl_exit);
1098 MODULE_LICENSE("GPL");
1099
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