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generic: rtl8367b: add definition of debug reg
[openwrt/staging/wigyori.git] / target / linux / generic / files / drivers / net / phy / rtl8367b.c
1 /*
2 * Platform driver for the Realtek RTL8367R-VB ethernet switches
3 *
4 * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/device.h>
15 #include <linux/of.h>
16 #include <linux/of_platform.h>
17 #include <linux/delay.h>
18 #include <linux/skbuff.h>
19 #include <linux/rtl8367.h>
20
21 #include "rtl8366_smi.h"
22
23 #define RTL8367B_RESET_DELAY 1000 /* msecs*/
24
25 #define RTL8367B_PHY_ADDR_MAX 8
26 #define RTL8367B_PHY_REG_MAX 31
27
28 #define RTL8367B_VID_MASK 0x3fff
29 #define RTL8367B_FID_MASK 0xf
30 #define RTL8367B_UNTAG_MASK 0xff
31 #define RTL8367B_MEMBER_MASK 0xff
32
33 #define RTL8367B_PORT_MISC_CFG_REG(_p) (0x000e + 0x20 * (_p))
34 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT 4
35 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_MASK 0x3
36 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_ORIGINAL 0
37 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_KEEP 1
38 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_PRI 2
39 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_REAL 3
40
41 #define RTL8367B_BYPASS_LINE_RATE_REG 0x03f7
42
43 #define RTL8367B_TA_CTRL_REG 0x0500 /*GOOD*/
44 #define RTL8367B_TA_CTRL_SPA_SHIFT 8
45 #define RTL8367B_TA_CTRL_SPA_MASK 0x7
46 #define RTL8367B_TA_CTRL_METHOD BIT(4)/*GOOD*/
47 #define RTL8367B_TA_CTRL_CMD_SHIFT 3
48 #define RTL8367B_TA_CTRL_CMD_READ 0
49 #define RTL8367B_TA_CTRL_CMD_WRITE 1
50 #define RTL8367B_TA_CTRL_TABLE_SHIFT 0 /*GOOD*/
51 #define RTL8367B_TA_CTRL_TABLE_ACLRULE 1
52 #define RTL8367B_TA_CTRL_TABLE_ACLACT 2
53 #define RTL8367B_TA_CTRL_TABLE_CVLAN 3
54 #define RTL8367B_TA_CTRL_TABLE_L2 4
55 #define RTL8367B_TA_CTRL_CVLAN_READ \
56 ((RTL8367B_TA_CTRL_CMD_READ << RTL8367B_TA_CTRL_CMD_SHIFT) | \
57 RTL8367B_TA_CTRL_TABLE_CVLAN)
58 #define RTL8367B_TA_CTRL_CVLAN_WRITE \
59 ((RTL8367B_TA_CTRL_CMD_WRITE << RTL8367B_TA_CTRL_CMD_SHIFT) | \
60 RTL8367B_TA_CTRL_TABLE_CVLAN)
61
62 #define RTL8367B_TA_ADDR_REG 0x0501/*GOOD*/
63 #define RTL8367B_TA_ADDR_MASK 0x3fff/*GOOD*/
64
65 #define RTL8367B_TA_LUT_REG 0x0502/*GOOD*/
66
67 #define RTL8367B_TA_WRDATA_REG(_x) (0x0510 + (_x))/*GOOD*/
68 #define RTL8367B_TA_VLAN_NUM_WORDS 2
69 #define RTL8367B_TA_VLAN_VID_MASK RTL8367B_VID_MASK
70 #define RTL8367B_TA_VLAN0_MEMBER_SHIFT 0
71 #define RTL8367B_TA_VLAN0_MEMBER_MASK RTL8367B_MEMBER_MASK
72 #define RTL8367B_TA_VLAN0_UNTAG_SHIFT 8
73 #define RTL8367B_TA_VLAN0_UNTAG_MASK RTL8367B_MEMBER_MASK
74 #define RTL8367B_TA_VLAN1_FID_SHIFT 0
75 #define RTL8367B_TA_VLAN1_FID_MASK RTL8367B_FID_MASK
76
77 #define RTL8367B_TA_RDDATA_REG(_x) (0x0520 + (_x))/*GOOD*/
78
79 #define RTL8367B_VLAN_PVID_CTRL_REG(_p) (0x0700 + (_p) / 2) /*GOOD*/
80 #define RTL8367B_VLAN_PVID_CTRL_MASK 0x1f /*GOOD*/
81 #define RTL8367B_VLAN_PVID_CTRL_SHIFT(_p) (8 * ((_p) % 2)) /*GOOD*/
82
83 #define RTL8367B_VLAN_MC_BASE(_x) (0x0728 + (_x) * 4) /*GOOD*/
84 #define RTL8367B_VLAN_MC_NUM_WORDS 4 /*GOOD*/
85 #define RTL8367B_VLAN_MC0_MEMBER_SHIFT 0/*GOOD*/
86 #define RTL8367B_VLAN_MC0_MEMBER_MASK RTL8367B_MEMBER_MASK/*GOOD*/
87 #define RTL8367B_VLAN_MC1_FID_SHIFT 0/*GOOD*/
88 #define RTL8367B_VLAN_MC1_FID_MASK RTL8367B_FID_MASK/*GOOD*/
89 #define RTL8367B_VLAN_MC3_EVID_SHIFT 0/*GOOD*/
90 #define RTL8367B_VLAN_MC3_EVID_MASK RTL8367B_VID_MASK/*GOOD*/
91
92 #define RTL8367B_VLAN_CTRL_REG 0x07a8 /*GOOD*/
93 #define RTL8367B_VLAN_CTRL_ENABLE BIT(0)
94
95 #define RTL8367B_VLAN_INGRESS_REG 0x07a9 /*GOOD*/
96
97 #define RTL8367B_PORT_ISOLATION_REG(_p) (0x08a2 + (_p)) /*GOOD*/
98
99 #define RTL8367B_MIB_COUNTER_REG(_x) (0x1000 + (_x)) /*GOOD*/
100 #define RTL8367B_MIB_COUNTER_PORT_OFFSET 0x007c /*GOOD*/
101
102 #define RTL8367B_MIB_ADDRESS_REG 0x1004 /*GOOD*/
103
104 #define RTL8367B_MIB_CTRL0_REG(_x) (0x1005 + (_x)) /*GOOD*/
105 #define RTL8367B_MIB_CTRL0_GLOBAL_RESET_MASK BIT(11) /*GOOD*/
106 #define RTL8367B_MIB_CTRL0_QM_RESET_MASK BIT(10) /*GOOD*/
107 #define RTL8367B_MIB_CTRL0_PORT_RESET_MASK(_p) BIT(2 + (_p)) /*GOOD*/
108 #define RTL8367B_MIB_CTRL0_RESET_MASK BIT(1) /*GOOD*/
109 #define RTL8367B_MIB_CTRL0_BUSY_MASK BIT(0) /*GOOD*/
110
111 #define RTL8367B_SWC0_REG 0x1200/*GOOD*/
112 #define RTL8367B_SWC0_MAX_LENGTH_SHIFT 13/*GOOD*/
113 #define RTL8367B_SWC0_MAX_LENGTH(_x) ((_x) << 13) /*GOOD*/
114 #define RTL8367B_SWC0_MAX_LENGTH_MASK RTL8367B_SWC0_MAX_LENGTH(0x3)
115 #define RTL8367B_SWC0_MAX_LENGTH_1522 RTL8367B_SWC0_MAX_LENGTH(0)
116 #define RTL8367B_SWC0_MAX_LENGTH_1536 RTL8367B_SWC0_MAX_LENGTH(1)
117 #define RTL8367B_SWC0_MAX_LENGTH_1552 RTL8367B_SWC0_MAX_LENGTH(2)
118 #define RTL8367B_SWC0_MAX_LENGTH_16000 RTL8367B_SWC0_MAX_LENGTH(3)
119
120 #define RTL8367B_CHIP_NUMBER_REG 0x1300/*GOOD*/
121
122 #define RTL8367B_CHIP_VER_REG 0x1301/*GOOD*/
123 #define RTL8367B_CHIP_VER_RLVID_SHIFT 12/*GOOD*/
124 #define RTL8367B_CHIP_VER_RLVID_MASK 0xf/*GOOD*/
125 #define RTL8367B_CHIP_VER_MCID_SHIFT 8/*GOOD*/
126 #define RTL8367B_CHIP_VER_MCID_MASK 0xf/*GOOD*/
127 #define RTL8367B_CHIP_VER_BOID_SHIFT 4/*GOOD*/
128 #define RTL8367B_CHIP_VER_BOID_MASK 0xf/*GOOD*/
129 #define RTL8367B_CHIP_VER_AFE_SHIFT 0/*GOOD*/
130 #define RTL8367B_CHIP_VER_AFE_MASK 0x1/*GOOD*/
131
132 #define RTL8367B_CHIP_MODE_REG 0x1302
133 #define RTL8367B_CHIP_MODE_MASK 0x7
134
135 #define RTL8367B_CHIP_DEBUG0_REG 0x1303
136 #define RTL8367B_DEBUG0_SEL33(_x) BIT(8 + (_x))
137 #define RTL8367B_DEBUG0_DRI_OTHER BIT(7)
138 #define RTL8367B_DEBUG0_DRI_RG(_x) BIT(5 + (_x))
139 #define RTL8367B_DEBUG0_DRI(_x) BIT(3 + (_x))
140 #define RTL8367B_DEBUG0_SLR_OTHER BIT(2)
141 #define RTL8367B_DEBUG0_SLR(_x) BIT(_x)
142
143 #define RTL8367B_CHIP_DEBUG1_REG 0x1304
144 #define RTL8367B_DEBUG1_DN_MASK(_x) \
145 GENMASK(6 + (_x)*8, 4 + (_x)*8)
146 #define RTL8367B_DEBUG1_DN_SHIFT(_x) (4 + (_x) * 8)
147 #define RTL8367B_DEBUG1_DP_MASK(_x) \
148 GENMASK(2 + (_x) * 8, (_x) * 8)
149 #define RTL8367B_DEBUG1_DP_SHIFT(_x) ((_x) * 8)
150
151 #define RTL8367B_DIS_REG 0x1305
152 #define RTL8367B_DIS_SKIP_MII_RXER(_x) BIT(12 + (_x))
153 #define RTL8367B_DIS_RGMII_SHIFT(_x) (4 * (_x))
154 #define RTL8367B_DIS_RGMII_MASK 0x7
155
156 #define RTL8367B_EXT_RGMXF_REG(_x) (0x1306 + (_x))
157 #define RTL8367B_EXT_RGMXF_DUMMY0_SHIFT 5
158 #define RTL8367B_EXT_RGMXF_DUMMY0_MASK 0x7ff
159 #define RTL8367B_EXT_RGMXF_TXDELAY_SHIFT 3
160 #define RTL8367B_EXT_RGMXF_TXDELAY_MASK 1
161 #define RTL8367B_EXT_RGMXF_RXDELAY_MASK 0x7
162
163 #define RTL8367B_DI_FORCE_REG(_x) (0x1310 + (_x))
164 #define RTL8367B_DI_FORCE_MODE BIT(12)
165 #define RTL8367B_DI_FORCE_NWAY BIT(7)
166 #define RTL8367B_DI_FORCE_TXPAUSE BIT(6)
167 #define RTL8367B_DI_FORCE_RXPAUSE BIT(5)
168 #define RTL8367B_DI_FORCE_LINK BIT(4)
169 #define RTL8367B_DI_FORCE_DUPLEX BIT(2)
170 #define RTL8367B_DI_FORCE_SPEED_MASK 3
171 #define RTL8367B_DI_FORCE_SPEED_10 0
172 #define RTL8367B_DI_FORCE_SPEED_100 1
173 #define RTL8367B_DI_FORCE_SPEED_1000 2
174
175 #define RTL8367B_MAC_FORCE_REG(_x) (0x1312 + (_x))
176
177 #define RTL8367B_CHIP_RESET_REG 0x1322 /*GOOD*/
178 #define RTL8367B_CHIP_RESET_SW BIT(1) /*GOOD*/
179 #define RTL8367B_CHIP_RESET_HW BIT(0) /*GOOD*/
180
181 #define RTL8367B_PORT_STATUS_REG(_p) (0x1352 + (_p)) /*GOOD*/
182 #define RTL8367B_PORT_STATUS_EN_1000_SPI BIT(11) /*GOOD*/
183 #define RTL8367B_PORT_STATUS_EN_100_SPI BIT(10)/*GOOD*/
184 #define RTL8367B_PORT_STATUS_NWAY_FAULT BIT(9)/*GOOD*/
185 #define RTL8367B_PORT_STATUS_LINK_MASTER BIT(8)/*GOOD*/
186 #define RTL8367B_PORT_STATUS_NWAY BIT(7)/*GOOD*/
187 #define RTL8367B_PORT_STATUS_TXPAUSE BIT(6)/*GOOD*/
188 #define RTL8367B_PORT_STATUS_RXPAUSE BIT(5)/*GOOD*/
189 #define RTL8367B_PORT_STATUS_LINK BIT(4)/*GOOD*/
190 #define RTL8367B_PORT_STATUS_DUPLEX BIT(2)/*GOOD*/
191 #define RTL8367B_PORT_STATUS_SPEED_MASK 0x0003/*GOOD*/
192 #define RTL8367B_PORT_STATUS_SPEED_10 0/*GOOD*/
193 #define RTL8367B_PORT_STATUS_SPEED_100 1/*GOOD*/
194 #define RTL8367B_PORT_STATUS_SPEED_1000 2/*GOOD*/
195
196 #define RTL8367B_RTL_MAGIC_ID_REG 0x13c2
197 #define RTL8367B_RTL_MAGIC_ID_VAL 0x0249
198
199 #define RTL8367B_IA_CTRL_REG 0x1f00
200 #define RTL8367B_IA_CTRL_RW(_x) ((_x) << 1)
201 #define RTL8367B_IA_CTRL_RW_READ RTL8367B_IA_CTRL_RW(0)
202 #define RTL8367B_IA_CTRL_RW_WRITE RTL8367B_IA_CTRL_RW(1)
203 #define RTL8367B_IA_CTRL_CMD_MASK BIT(0)
204
205 #define RTL8367B_IA_STATUS_REG 0x1f01
206 #define RTL8367B_IA_STATUS_PHY_BUSY BIT(2)
207 #define RTL8367B_IA_STATUS_SDS_BUSY BIT(1)
208 #define RTL8367B_IA_STATUS_MDX_BUSY BIT(0)
209
210 #define RTL8367B_IA_ADDRESS_REG 0x1f02
211 #define RTL8367B_IA_WRITE_DATA_REG 0x1f03
212 #define RTL8367B_IA_READ_DATA_REG 0x1f04
213
214 #define RTL8367B_INTERNAL_PHY_REG(_a, _r) (0x2000 + 32 * (_a) + (_r))
215
216 #define RTL8367B_NUM_MIB_COUNTERS 58
217
218 #define RTL8367B_CPU_PORT_NUM 5
219 #define RTL8367B_NUM_PORTS 8
220 #define RTL8367B_NUM_VLANS 32
221 #define RTL8367B_NUM_VIDS 4096
222 #define RTL8367B_PRIORITYMAX 7
223 #define RTL8367B_FIDMAX 7
224
225 #define RTL8367B_PORT_0 BIT(0)
226 #define RTL8367B_PORT_1 BIT(1)
227 #define RTL8367B_PORT_2 BIT(2)
228 #define RTL8367B_PORT_3 BIT(3)
229 #define RTL8367B_PORT_4 BIT(4)
230 #define RTL8367B_PORT_E0 BIT(5) /* External port 0 */
231 #define RTL8367B_PORT_E1 BIT(6) /* External port 1 */
232 #define RTL8367B_PORT_E2 BIT(7) /* External port 2 */
233
234 #define RTL8367B_PORTS_ALL \
235 (RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 | \
236 RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E0 | \
237 RTL8367B_PORT_E1 | RTL8367B_PORT_E2)
238
239 #define RTL8367B_PORTS_ALL_BUT_CPU \
240 (RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 | \
241 RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E1 | \
242 RTL8367B_PORT_E2)
243
244 struct rtl8367b_initval {
245 u16 reg;
246 u16 val;
247 };
248
249 #define RTL8367B_MIB_RXB_ID 0 /* IfInOctets */
250 #define RTL8367B_MIB_TXB_ID 28 /* IfOutOctets */
251
252 static struct rtl8366_mib_counter
253 rtl8367b_mib_counters[RTL8367B_NUM_MIB_COUNTERS] = {
254 {0, 0, 4, "ifInOctets" },
255 {0, 4, 2, "dot3StatsFCSErrors" },
256 {0, 6, 2, "dot3StatsSymbolErrors" },
257 {0, 8, 2, "dot3InPauseFrames" },
258 {0, 10, 2, "dot3ControlInUnknownOpcodes" },
259 {0, 12, 2, "etherStatsFragments" },
260 {0, 14, 2, "etherStatsJabbers" },
261 {0, 16, 2, "ifInUcastPkts" },
262 {0, 18, 2, "etherStatsDropEvents" },
263 {0, 20, 2, "ifInMulticastPkts" },
264 {0, 22, 2, "ifInBroadcastPkts" },
265 {0, 24, 2, "inMldChecksumError" },
266 {0, 26, 2, "inIgmpChecksumError" },
267 {0, 28, 2, "inMldSpecificQuery" },
268 {0, 30, 2, "inMldGeneralQuery" },
269 {0, 32, 2, "inIgmpSpecificQuery" },
270 {0, 34, 2, "inIgmpGeneralQuery" },
271 {0, 36, 2, "inMldLeaves" },
272 {0, 38, 2, "inIgmpLeaves" },
273
274 {0, 40, 4, "etherStatsOctets" },
275 {0, 44, 2, "etherStatsUnderSizePkts" },
276 {0, 46, 2, "etherOversizeStats" },
277 {0, 48, 2, "etherStatsPkts64Octets" },
278 {0, 50, 2, "etherStatsPkts65to127Octets" },
279 {0, 52, 2, "etherStatsPkts128to255Octets" },
280 {0, 54, 2, "etherStatsPkts256to511Octets" },
281 {0, 56, 2, "etherStatsPkts512to1023Octets" },
282 {0, 58, 2, "etherStatsPkts1024to1518Octets" },
283
284 {0, 60, 4, "ifOutOctets" },
285 {0, 64, 2, "dot3StatsSingleCollisionFrames" },
286 {0, 66, 2, "dot3StatMultipleCollisionFrames" },
287 {0, 68, 2, "dot3sDeferredTransmissions" },
288 {0, 70, 2, "dot3StatsLateCollisions" },
289 {0, 72, 2, "etherStatsCollisions" },
290 {0, 74, 2, "dot3StatsExcessiveCollisions" },
291 {0, 76, 2, "dot3OutPauseFrames" },
292 {0, 78, 2, "ifOutDiscards" },
293 {0, 80, 2, "dot1dTpPortInDiscards" },
294 {0, 82, 2, "ifOutUcastPkts" },
295 {0, 84, 2, "ifOutMulticastPkts" },
296 {0, 86, 2, "ifOutBroadcastPkts" },
297 {0, 88, 2, "outOampduPkts" },
298 {0, 90, 2, "inOampduPkts" },
299 {0, 92, 2, "inIgmpJoinsSuccess" },
300 {0, 94, 2, "inIgmpJoinsFail" },
301 {0, 96, 2, "inMldJoinsSuccess" },
302 {0, 98, 2, "inMldJoinsFail" },
303 {0, 100, 2, "inReportSuppressionDrop" },
304 {0, 102, 2, "inLeaveSuppressionDrop" },
305 {0, 104, 2, "outIgmpReports" },
306 {0, 106, 2, "outIgmpLeaves" },
307 {0, 108, 2, "outIgmpGeneralQuery" },
308 {0, 110, 2, "outIgmpSpecificQuery" },
309 {0, 112, 2, "outMldReports" },
310 {0, 114, 2, "outMldLeaves" },
311 {0, 116, 2, "outMldGeneralQuery" },
312 {0, 118, 2, "outMldSpecificQuery" },
313 {0, 120, 2, "inKnownMulticastPkts" },
314 };
315
316 #define REG_RD(_smi, _reg, _val) \
317 do { \
318 err = rtl8366_smi_read_reg(_smi, _reg, _val); \
319 if (err) \
320 return err; \
321 } while (0)
322
323 #define REG_WR(_smi, _reg, _val) \
324 do { \
325 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
326 if (err) \
327 return err; \
328 } while (0)
329
330 #define REG_RMW(_smi, _reg, _mask, _val) \
331 do { \
332 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
333 if (err) \
334 return err; \
335 } while (0)
336
337 static const struct rtl8367b_initval rtl8367r_vb_initvals_0[] = {
338 {0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x0301, 0x0026}, {0x1722, 0x0E14},
339 {0x205F, 0x0002}, {0x2059, 0x1A00}, {0x205F, 0x0000}, {0x207F, 0x0002},
340 {0x2077, 0x0000}, {0x2078, 0x0000}, {0x2079, 0x0000}, {0x207A, 0x0000},
341 {0x207B, 0x0000}, {0x207F, 0x0000}, {0x205F, 0x0002}, {0x2053, 0x0000},
342 {0x2054, 0x0000}, {0x2055, 0x0000}, {0x2056, 0x0000}, {0x2057, 0x0000},
343 {0x205F, 0x0000}, {0x12A4, 0x110A}, {0x12A6, 0x150A}, {0x13F1, 0x0013},
344 {0x13F4, 0x0010}, {0x13F5, 0x0000}, {0x0018, 0x0F00}, {0x0038, 0x0F00},
345 {0x0058, 0x0F00}, {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x12B6, 0x0C02},
346 {0x12B7, 0x030F}, {0x12B8, 0x11FF}, {0x12BC, 0x0004}, {0x1362, 0x0115},
347 {0x1363, 0x0002}, {0x1363, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E},
348 {0x221F, 0x0007}, {0x221E, 0x002D}, {0x2218, 0xF030}, {0x221F, 0x0007},
349 {0x221E, 0x0023}, {0x2216, 0x0005}, {0x2215, 0x00B9}, {0x2219, 0x0044},
350 {0x2215, 0x00BA}, {0x2219, 0x0020}, {0x2215, 0x00BB}, {0x2219, 0x00C1},
351 {0x2215, 0x0148}, {0x2219, 0x0096}, {0x2215, 0x016E}, {0x2219, 0x0026},
352 {0x2216, 0x0000}, {0x2216, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},
353 {0x221F, 0x0007}, {0x221E, 0x0020}, {0x2215, 0x0D00}, {0x221F, 0x0000},
354 {0x221F, 0x0000}, {0x2217, 0x2160}, {0x221F, 0x0001}, {0x2210, 0xF25E},
355 {0x221F, 0x0007}, {0x221E, 0x0042}, {0x2215, 0x0F00}, {0x2215, 0x0F00},
356 {0x2216, 0x7408}, {0x2215, 0x0E00}, {0x2215, 0x0F00}, {0x2215, 0x0F01},
357 {0x2216, 0x4000}, {0x2215, 0x0E01}, {0x2215, 0x0F01}, {0x2215, 0x0F02},
358 {0x2216, 0x9400}, {0x2215, 0x0E02}, {0x2215, 0x0F02}, {0x2215, 0x0F03},
359 {0x2216, 0x7408}, {0x2215, 0x0E03}, {0x2215, 0x0F03}, {0x2215, 0x0F04},
360 {0x2216, 0x4008}, {0x2215, 0x0E04}, {0x2215, 0x0F04}, {0x2215, 0x0F05},
361 {0x2216, 0x9400}, {0x2215, 0x0E05}, {0x2215, 0x0F05}, {0x2215, 0x0F06},
362 {0x2216, 0x0803}, {0x2215, 0x0E06}, {0x2215, 0x0F06}, {0x2215, 0x0D00},
363 {0x2215, 0x0100}, {0x221F, 0x0001}, {0x2210, 0xF05E}, {0x221F, 0x0000},
364 {0x2217, 0x2100}, {0x221F, 0x0000}, {0x220D, 0x0003}, {0x220E, 0x0015},
365 {0x220D, 0x4003}, {0x220E, 0x0006}, {0x221F, 0x0000}, {0x2200, 0x1340},
366 {0x133F, 0x0010}, {0x12A0, 0x0058}, {0x12A1, 0x0058}, {0x133E, 0x000E},
367 {0x133F, 0x0030}, {0x221F, 0x0000}, {0x2210, 0x0166}, {0x221F, 0x0000},
368 {0x133E, 0x000E}, {0x133F, 0x0010}, {0x133F, 0x0030}, {0x133E, 0x000E},
369 {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8B6E},
370 {0x2206, 0x0000}, {0x220F, 0x0100}, {0x2205, 0x8000}, {0x2206, 0x0280},
371 {0x2206, 0x28F7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},
372 {0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},
373 {0x2206, 0x6602}, {0x2206, 0x80B9}, {0x2206, 0xE08B}, {0x2206, 0x8CE1},
374 {0x2206, 0x8B8D}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x8E1E},
375 {0x2206, 0x01A0}, {0x2206, 0x00E7}, {0x2206, 0xAEDB}, {0x2206, 0xEEE0},
376 {0x2206, 0x120E}, {0x2206, 0xEEE0}, {0x2206, 0x1300}, {0x2206, 0xEEE0},
377 {0x2206, 0x2001}, {0x2206, 0xEEE0}, {0x2206, 0x2166}, {0x2206, 0xEEE0},
378 {0x2206, 0xC463}, {0x2206, 0xEEE0}, {0x2206, 0xC5E8}, {0x2206, 0xEEE0},
379 {0x2206, 0xC699}, {0x2206, 0xEEE0}, {0x2206, 0xC7C2}, {0x2206, 0xEEE0},
380 {0x2206, 0xC801}, {0x2206, 0xEEE0}, {0x2206, 0xC913}, {0x2206, 0xEEE0},
381 {0x2206, 0xCA30}, {0x2206, 0xEEE0}, {0x2206, 0xCB3E}, {0x2206, 0xEEE0},
382 {0x2206, 0xDCE1}, {0x2206, 0xEEE0}, {0x2206, 0xDD00}, {0x2206, 0xEEE2},
383 {0x2206, 0x0001}, {0x2206, 0xEEE2}, {0x2206, 0x0100}, {0x2206, 0xEEE4},
384 {0x2206, 0x8860}, {0x2206, 0xEEE4}, {0x2206, 0x8902}, {0x2206, 0xEEE4},
385 {0x2206, 0x8C00}, {0x2206, 0xEEE4}, {0x2206, 0x8D30}, {0x2206, 0xEEEA},
386 {0x2206, 0x1480}, {0x2206, 0xEEEA}, {0x2206, 0x1503}, {0x2206, 0xEEEA},
387 {0x2206, 0xC600}, {0x2206, 0xEEEA}, {0x2206, 0xC706}, {0x2206, 0xEE85},
388 {0x2206, 0xEE00}, {0x2206, 0xEE85}, {0x2206, 0xEF00}, {0x2206, 0xEE8B},
389 {0x2206, 0x6750}, {0x2206, 0xEE8B}, {0x2206, 0x6632}, {0x2206, 0xEE8A},
390 {0x2206, 0xD448}, {0x2206, 0xEE8A}, {0x2206, 0xD548}, {0x2206, 0xEE8A},
391 {0x2206, 0xD649}, {0x2206, 0xEE8A}, {0x2206, 0xD7F8}, {0x2206, 0xEE8B},
392 {0x2206, 0x85E2}, {0x2206, 0xEE8B}, {0x2206, 0x8700}, {0x2206, 0xEEFF},
393 {0x2206, 0xF600}, {0x2206, 0xEEFF}, {0x2206, 0xF7FC}, {0x2206, 0x04F8},
394 {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2023}, {0x2206, 0xF620},
395 {0x2206, 0xE48B}, {0x2206, 0x8E02}, {0x2206, 0x2877}, {0x2206, 0x0225},
396 {0x2206, 0xC702}, {0x2206, 0x26A1}, {0x2206, 0x0281}, {0x2206, 0xB302},
397 {0x2206, 0x8496}, {0x2206, 0x0202}, {0x2206, 0xA102}, {0x2206, 0x27F1},
398 {0x2206, 0x0228}, {0x2206, 0xF902}, {0x2206, 0x2AA0}, {0x2206, 0x0282},
399 {0x2206, 0xB8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD21}, {0x2206, 0x08F6},
400 {0x2206, 0x21E4}, {0x2206, 0x8B8E}, {0x2206, 0x0202}, {0x2206, 0x80E0},
401 {0x2206, 0x8B8E}, {0x2206, 0xAD22}, {0x2206, 0x05F6}, {0x2206, 0x22E4},
402 {0x2206, 0x8B8E}, {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2305},
403 {0x2206, 0xF623}, {0x2206, 0xE48B}, {0x2206, 0x8EE0}, {0x2206, 0x8B8E},
404 {0x2206, 0xAD24}, {0x2206, 0x08F6}, {0x2206, 0x24E4}, {0x2206, 0x8B8E},
405 {0x2206, 0x0227}, {0x2206, 0x6AE0}, {0x2206, 0x8B8E}, {0x2206, 0xAD25},
406 {0x2206, 0x05F6}, {0x2206, 0x25E4}, {0x2206, 0x8B8E}, {0x2206, 0xE08B},
407 {0x2206, 0x8EAD}, {0x2206, 0x260B}, {0x2206, 0xF626}, {0x2206, 0xE48B},
408 {0x2206, 0x8E02}, {0x2206, 0x830D}, {0x2206, 0x021D}, {0x2206, 0x6BE0},
409 {0x2206, 0x8B8E}, {0x2206, 0xAD27}, {0x2206, 0x05F6}, {0x2206, 0x27E4},
410 {0x2206, 0x8B8E}, {0x2206, 0x0281}, {0x2206, 0x4402}, {0x2206, 0x045C},
411 {0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B83}, {0x2206, 0xAD23},
412 {0x2206, 0x30E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x2359},
413 {0x2206, 0x02E0}, {0x2206, 0x85EF}, {0x2206, 0xE585}, {0x2206, 0xEFAC},
414 {0x2206, 0x2907}, {0x2206, 0x1F01}, {0x2206, 0x9E51}, {0x2206, 0xAD29},
415 {0x2206, 0x20E0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x06E1},
416 {0x2206, 0x8B84}, {0x2206, 0xAD28}, {0x2206, 0x42E0}, {0x2206, 0x8B85},
417 {0x2206, 0xAD21}, {0x2206, 0x06E1}, {0x2206, 0x8B84}, {0x2206, 0xAD29},
418 {0x2206, 0x36BF}, {0x2206, 0x34BF}, {0x2206, 0x022C}, {0x2206, 0x31AE},
419 {0x2206, 0x2EE0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x10E0},
420 {0x2206, 0x8B84}, {0x2206, 0xF620}, {0x2206, 0xE48B}, {0x2206, 0x84EE},
421 {0x2206, 0x8ADA}, {0x2206, 0x00EE}, {0x2206, 0x8ADB}, {0x2206, 0x00E0},
422 {0x2206, 0x8B85}, {0x2206, 0xAD21}, {0x2206, 0x0CE0}, {0x2206, 0x8B84},
423 {0x2206, 0xF621}, {0x2206, 0xE48B}, {0x2206, 0x84EE}, {0x2206, 0x8B72},
424 {0x2206, 0xFFBF}, {0x2206, 0x34C2}, {0x2206, 0x022C}, {0x2206, 0x31FC},
425 {0x2206, 0x04F8}, {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B85},
426 {0x2206, 0xAD21}, {0x2206, 0x42E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0},
427 {0x2206, 0x2358}, {0x2206, 0xC059}, {0x2206, 0x021E}, {0x2206, 0x01E1},
428 {0x2206, 0x8B72}, {0x2206, 0x1F10}, {0x2206, 0x9E2F}, {0x2206, 0xE48B},
429 {0x2206, 0x72AD}, {0x2206, 0x2123}, {0x2206, 0xE18B}, {0x2206, 0x84F7},
430 {0x2206, 0x29E5}, {0x2206, 0x8B84}, {0x2206, 0xAC27}, {0x2206, 0x10AC},
431 {0x2206, 0x2605}, {0x2206, 0x0205}, {0x2206, 0x23AE}, {0x2206, 0x1602},
432 {0x2206, 0x0535}, {0x2206, 0x0282}, {0x2206, 0x30AE}, {0x2206, 0x0E02},
433 {0x2206, 0x056A}, {0x2206, 0x0282}, {0x2206, 0x75AE}, {0x2206, 0x0602},
434 {0x2206, 0x04DC}, {0x2206, 0x0282}, {0x2206, 0x04EF}, {0x2206, 0x96FE},
435 {0x2206, 0xFC04}, {0x2206, 0xF8F9}, {0x2206, 0xE08B}, {0x2206, 0x87AD},
436 {0x2206, 0x2321}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},
437 {0x2206, 0xAD26}, {0x2206, 0x18F6}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
438 {0x2206, 0xE5EA}, {0x2206, 0x15F6}, {0x2206, 0x26E4}, {0x2206, 0xEA14},
439 {0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
440 {0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},
441 {0x2206, 0xE08B}, {0x2206, 0x87AD}, {0x2206, 0x233A}, {0x2206, 0xAD22},
442 {0x2206, 0x37E0}, {0x2206, 0xE020}, {0x2206, 0xE1E0}, {0x2206, 0x21AC},
443 {0x2206, 0x212E}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},
444 {0x2206, 0xF627}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
445 {0x2206, 0xE2EA}, {0x2206, 0x12E3}, {0x2206, 0xEA13}, {0x2206, 0x5A8F},
446 {0x2206, 0x6A20}, {0x2206, 0xE6EA}, {0x2206, 0x12E7}, {0x2206, 0xEA13},
447 {0x2206, 0xF726}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
448 {0x2206, 0xF727}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
449 {0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B87},
450 {0x2206, 0xAD23}, {0x2206, 0x38AD}, {0x2206, 0x2135}, {0x2206, 0xE0E0},
451 {0x2206, 0x20E1}, {0x2206, 0xE021}, {0x2206, 0xAC21}, {0x2206, 0x2CE0},
452 {0x2206, 0xEA14}, {0x2206, 0xE1EA}, {0x2206, 0x15F6}, {0x2206, 0x27E4},
453 {0x2206, 0xEA14}, {0x2206, 0xE5EA}, {0x2206, 0x15E2}, {0x2206, 0xEA12},
454 {0x2206, 0xE3EA}, {0x2206, 0x135A}, {0x2206, 0x8FE6}, {0x2206, 0xEA12},
455 {0x2206, 0xE7EA}, {0x2206, 0x13F7}, {0x2206, 0x26E4}, {0x2206, 0xEA14},
456 {0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
457 {0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},
458 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2146},
459 {0x2206, 0xE0E0}, {0x2206, 0x22E1}, {0x2206, 0xE023}, {0x2206, 0x58C0},
460 {0x2206, 0x5902}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x651F},
461 {0x2206, 0x109E}, {0x2206, 0x33E4}, {0x2206, 0x8B65}, {0x2206, 0xAD21},
462 {0x2206, 0x22AD}, {0x2206, 0x272A}, {0x2206, 0xD400}, {0x2206, 0x01BF},
463 {0x2206, 0x34F2}, {0x2206, 0x022C}, {0x2206, 0xA2BF}, {0x2206, 0x34F5},
464 {0x2206, 0x022C}, {0x2206, 0xE0E0}, {0x2206, 0x8B67}, {0x2206, 0x1B10},
465 {0x2206, 0xAA14}, {0x2206, 0xE18B}, {0x2206, 0x660D}, {0x2206, 0x1459},
466 {0x2206, 0x0FAE}, {0x2206, 0x05E1}, {0x2206, 0x8B66}, {0x2206, 0x590F},
467 {0x2206, 0xBF85}, {0x2206, 0x6102}, {0x2206, 0x2CA2}, {0x2206, 0xEF96},
468 {0x2206, 0xFEFC}, {0x2206, 0x04F8}, {0x2206, 0xF9FA}, {0x2206, 0xFBEF},
469 {0x2206, 0x79E2}, {0x2206, 0x8AD2}, {0x2206, 0xAC19}, {0x2206, 0x2DE0},
470 {0x2206, 0xE036}, {0x2206, 0xE1E0}, {0x2206, 0x37EF}, {0x2206, 0x311F},
471 {0x2206, 0x325B}, {0x2206, 0x019E}, {0x2206, 0x1F7A}, {0x2206, 0x0159},
472 {0x2206, 0x019F}, {0x2206, 0x0ABF}, {0x2206, 0x348E}, {0x2206, 0x022C},
473 {0x2206, 0x31F6}, {0x2206, 0x06AE}, {0x2206, 0x0FF6}, {0x2206, 0x0302},
474 {0x2206, 0x0470}, {0x2206, 0xF703}, {0x2206, 0xF706}, {0x2206, 0xBF34},
475 {0x2206, 0x9302}, {0x2206, 0x2C31}, {0x2206, 0xAC1A}, {0x2206, 0x25E0},
476 {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x23EF}, {0x2206, 0x300D},
477 {0x2206, 0x311F}, {0x2206, 0x325B}, {0x2206, 0x029E}, {0x2206, 0x157A},
478 {0x2206, 0x0258}, {0x2206, 0xC4A0}, {0x2206, 0x0408}, {0x2206, 0xBF34},
479 {0x2206, 0x9E02}, {0x2206, 0x2C31}, {0x2206, 0xAE06}, {0x2206, 0xBF34},
480 {0x2206, 0x9C02}, {0x2206, 0x2C31}, {0x2206, 0xAC1B}, {0x2206, 0x4AE0},
481 {0x2206, 0xE012}, {0x2206, 0xE1E0}, {0x2206, 0x13EF}, {0x2206, 0x300D},
482 {0x2206, 0x331F}, {0x2206, 0x325B}, {0x2206, 0x1C9E}, {0x2206, 0x3AEF},
483 {0x2206, 0x325B}, {0x2206, 0x1C9F}, {0x2206, 0x09BF}, {0x2206, 0x3498},
484 {0x2206, 0x022C}, {0x2206, 0x3102}, {0x2206, 0x83C5}, {0x2206, 0x5A03},
485 {0x2206, 0x0D03}, {0x2206, 0x581C}, {0x2206, 0x1E20}, {0x2206, 0x0207},
486 {0x2206, 0xA0A0}, {0x2206, 0x000E}, {0x2206, 0x0284}, {0x2206, 0x17AD},
487 {0x2206, 0x1817}, {0x2206, 0xBF34}, {0x2206, 0x9A02}, {0x2206, 0x2C31},
488 {0x2206, 0xAE0F}, {0x2206, 0xBF34}, {0x2206, 0xC802}, {0x2206, 0x2C31},
489 {0x2206, 0xBF34}, {0x2206, 0xC502}, {0x2206, 0x2C31}, {0x2206, 0x0284},
490 {0x2206, 0x52E6}, {0x2206, 0x8AD2}, {0x2206, 0xEF97}, {0x2206, 0xFFFE},
491 {0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xBF34}, {0x2206, 0xDA02},
492 {0x2206, 0x2CE0}, {0x2206, 0xE58A}, {0x2206, 0xD3BF}, {0x2206, 0x34D4},
493 {0x2206, 0x022C}, {0x2206, 0xE00C}, {0x2206, 0x1159}, {0x2206, 0x02E0},
494 {0x2206, 0x8AD3}, {0x2206, 0x1E01}, {0x2206, 0xE48A}, {0x2206, 0xD3D1},
495 {0x2206, 0x00BF}, {0x2206, 0x34DA}, {0x2206, 0x022C}, {0x2206, 0xA2D1},
496 {0x2206, 0x01BF}, {0x2206, 0x34D4}, {0x2206, 0x022C}, {0x2206, 0xA2BF},
497 {0x2206, 0x34CB}, {0x2206, 0x022C}, {0x2206, 0xE0E5}, {0x2206, 0x8ACE},
498 {0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CE0}, {0x2206, 0xE58A},
499 {0x2206, 0xCFBF}, {0x2206, 0x8564}, {0x2206, 0x022C}, {0x2206, 0xE0E5},
500 {0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6A02}, {0x2206, 0x2CE0},
501 {0x2206, 0xE58A}, {0x2206, 0xD1FC}, {0x2206, 0x04F8}, {0x2206, 0xE18A},
502 {0x2206, 0xD1BF}, {0x2206, 0x856A}, {0x2206, 0x022C}, {0x2206, 0xA2E1},
503 {0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},
504 {0x2206, 0xE18A}, {0x2206, 0xCFBF}, {0x2206, 0x8567}, {0x2206, 0x022C},
505 {0x2206, 0xA2E1}, {0x2206, 0x8ACE}, {0x2206, 0xBF34}, {0x2206, 0xCB02},
506 {0x2206, 0x2CA2}, {0x2206, 0xE18A}, {0x2206, 0xD3BF}, {0x2206, 0x34DA},
507 {0x2206, 0x022C}, {0x2206, 0xA2E1}, {0x2206, 0x8AD3}, {0x2206, 0x0D11},
508 {0x2206, 0xBF34}, {0x2206, 0xD402}, {0x2206, 0x2CA2}, {0x2206, 0xFC04},
509 {0x2206, 0xF9A0}, {0x2206, 0x0405}, {0x2206, 0xE38A}, {0x2206, 0xD4AE},
510 {0x2206, 0x13A0}, {0x2206, 0x0805}, {0x2206, 0xE38A}, {0x2206, 0xD5AE},
511 {0x2206, 0x0BA0}, {0x2206, 0x0C05}, {0x2206, 0xE38A}, {0x2206, 0xD6AE},
512 {0x2206, 0x03E3}, {0x2206, 0x8AD7}, {0x2206, 0xEF13}, {0x2206, 0xBF34},
513 {0x2206, 0xCB02}, {0x2206, 0x2CA2}, {0x2206, 0xEF13}, {0x2206, 0x0D11},
514 {0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CA2}, {0x2206, 0xEF13},
515 {0x2206, 0x0D14}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},
516 {0x2206, 0xEF13}, {0x2206, 0x0D17}, {0x2206, 0xBF85}, {0x2206, 0x6A02},
517 {0x2206, 0x2CA2}, {0x2206, 0xFD04}, {0x2206, 0xF8E0}, {0x2206, 0x8B85},
518 {0x2206, 0xAD27}, {0x2206, 0x2DE0}, {0x2206, 0xE036}, {0x2206, 0xE1E0},
519 {0x2206, 0x37E1}, {0x2206, 0x8B73}, {0x2206, 0x1F10}, {0x2206, 0x9E20},
520 {0x2206, 0xE48B}, {0x2206, 0x73AC}, {0x2206, 0x200B}, {0x2206, 0xAC21},
521 {0x2206, 0x0DAC}, {0x2206, 0x250F}, {0x2206, 0xAC27}, {0x2206, 0x0EAE},
522 {0x2206, 0x0F02}, {0x2206, 0x84CC}, {0x2206, 0xAE0A}, {0x2206, 0x0284},
523 {0x2206, 0xD1AE}, {0x2206, 0x05AE}, {0x2206, 0x0302}, {0x2206, 0x84D8},
524 {0x2206, 0xFC04}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0x0402},
525 {0x2206, 0x84E5}, {0x2206, 0x0285}, {0x2206, 0x2804}, {0x2206, 0x0285},
526 {0x2206, 0x4904}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0xEE8B},
527 {0x2206, 0x6902}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B85},
528 {0x2206, 0xAD26}, {0x2206, 0x38D0}, {0x2206, 0x0B02}, {0x2206, 0x2B4D},
529 {0x2206, 0x5882}, {0x2206, 0x7882}, {0x2206, 0x9F2D}, {0x2206, 0xE08B},
530 {0x2206, 0x68E1}, {0x2206, 0x8B69}, {0x2206, 0x1F10}, {0x2206, 0x9EC8},
531 {0x2206, 0x10E4}, {0x2206, 0x8B68}, {0x2206, 0xE0E0}, {0x2206, 0x00E1},
532 {0x2206, 0xE001}, {0x2206, 0xF727}, {0x2206, 0xE4E0}, {0x2206, 0x00E5},
533 {0x2206, 0xE001}, {0x2206, 0xE2E0}, {0x2206, 0x20E3}, {0x2206, 0xE021},
534 {0x2206, 0xAD30}, {0x2206, 0xF7F6}, {0x2206, 0x27E4}, {0x2206, 0xE000},
535 {0x2206, 0xE5E0}, {0x2206, 0x01FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},
536 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2212},
537 {0x2206, 0xE0E0}, {0x2206, 0x14E1}, {0x2206, 0xE015}, {0x2206, 0xAD26},
538 {0x2206, 0x9CE1}, {0x2206, 0x85E0}, {0x2206, 0xBF85}, {0x2206, 0x6D02},
539 {0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x04F8},
540 {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B86}, {0x2206, 0xAD22},
541 {0x2206, 0x09E1}, {0x2206, 0x85E1}, {0x2206, 0xBF85}, {0x2206, 0x6D02},
542 {0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x0464},
543 {0x2206, 0xE48C}, {0x2206, 0xFDE4}, {0x2206, 0x80CA}, {0x2206, 0xE480},
544 {0x2206, 0x66E0}, {0x2206, 0x8E70}, {0x2206, 0xE076}, {0x2205, 0xE142},
545 {0x2206, 0x0701}, {0x2205, 0xE140}, {0x2206, 0x0405}, {0x220F, 0x0000},
546 {0x221F, 0x0000}, {0x2200, 0x1340}, {0x133E, 0x000E}, {0x133F, 0x0010},
547 {0x13EB, 0x11BB}
548 };
549
550 static const struct rtl8367b_initval rtl8367r_vb_initvals_1[] = {
551 {0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x1305, 0xC000}, {0x121E, 0x03CA},
552 {0x1233, 0x0352}, {0x1234, 0x0064}, {0x1237, 0x0096}, {0x1238, 0x0078},
553 {0x1239, 0x0084}, {0x123A, 0x0030}, {0x205F, 0x0002}, {0x2059, 0x1A00},
554 {0x205F, 0x0000}, {0x207F, 0x0002}, {0x2077, 0x0000}, {0x2078, 0x0000},
555 {0x2079, 0x0000}, {0x207A, 0x0000}, {0x207B, 0x0000}, {0x207F, 0x0000},
556 {0x205F, 0x0002}, {0x2053, 0x0000}, {0x2054, 0x0000}, {0x2055, 0x0000},
557 {0x2056, 0x0000}, {0x2057, 0x0000}, {0x205F, 0x0000}, {0x133F, 0x0030},
558 {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2205, 0x8B86}, {0x2206, 0x800E},
559 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x12A3, 0x2200}, {0x6107, 0xE58B},
560 {0x6103, 0xA970}, {0x0018, 0x0F00}, {0x0038, 0x0F00}, {0x0058, 0x0F00},
561 {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x133F, 0x0030}, {0x133E, 0x000E},
562 {0x221F, 0x0005}, {0x2205, 0x8B6E}, {0x2206, 0x0000}, {0x220F, 0x0100},
563 {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8000}, {0x2206, 0x0280},
564 {0x2206, 0x2BF7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},
565 {0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},
566 {0x2206, 0x6602}, {0x2206, 0x8044}, {0x2206, 0x0201}, {0x2206, 0x7CE0},
567 {0x2206, 0x8B8C}, {0x2206, 0xE18B}, {0x2206, 0x8D1E}, {0x2206, 0x01E1},
568 {0x2206, 0x8B8E}, {0x2206, 0x1E01}, {0x2206, 0xA000}, {0x2206, 0xE4AE},
569 {0x2206, 0xD8EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE}, {0x2206, 0x85C1},
570 {0x2206, 0x00EE}, {0x2206, 0x8AFC}, {0x2206, 0x07EE}, {0x2206, 0x8AFD},
571 {0x2206, 0x73EE}, {0x2206, 0xFFF6}, {0x2206, 0x00EE}, {0x2206, 0xFFF7},
572 {0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD20},
573 {0x2206, 0x0302}, {0x2206, 0x8050}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},
574 {0x2206, 0xE08B}, {0x2206, 0x85AD}, {0x2206, 0x2548}, {0x2206, 0xE08A},
575 {0x2206, 0xE4E1}, {0x2206, 0x8AE5}, {0x2206, 0x7C00}, {0x2206, 0x009E},
576 {0x2206, 0x35EE}, {0x2206, 0x8AE4}, {0x2206, 0x00EE}, {0x2206, 0x8AE5},
577 {0x2206, 0x00E0}, {0x2206, 0x8AFC}, {0x2206, 0xE18A}, {0x2206, 0xFDE2},
578 {0x2206, 0x85C0}, {0x2206, 0xE385}, {0x2206, 0xC102}, {0x2206, 0x2DAC},
579 {0x2206, 0xAD20}, {0x2206, 0x12EE}, {0x2206, 0x8AE4}, {0x2206, 0x03EE},
580 {0x2206, 0x8AE5}, {0x2206, 0xB7EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE},
581 {0x2206, 0x85C1}, {0x2206, 0x00AE}, {0x2206, 0x1115}, {0x2206, 0xE685},
582 {0x2206, 0xC0E7}, {0x2206, 0x85C1}, {0x2206, 0xAE08}, {0x2206, 0xEE85},
583 {0x2206, 0xC000}, {0x2206, 0xEE85}, {0x2206, 0xC100}, {0x2206, 0xFDFC},
584 {0x2206, 0x0400}, {0x2205, 0xE142}, {0x2206, 0x0701}, {0x2205, 0xE140},
585 {0x2206, 0x0405}, {0x220F, 0x0000}, {0x221F, 0x0000}, {0x133E, 0x000E},
586 {0x133F, 0x0010}, {0x13EB, 0x11BB}, {0x207F, 0x0002}, {0x2073, 0x1D22},
587 {0x207F, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E}, {0x2200, 0x1340},
588 {0x133E, 0x000E}, {0x133F, 0x0010},
589 };
590
591 static int rtl8367b_write_initvals(struct rtl8366_smi *smi,
592 const struct rtl8367b_initval *initvals,
593 int count)
594 {
595 int err;
596 int i;
597
598 for (i = 0; i < count; i++)
599 REG_WR(smi, initvals[i].reg, initvals[i].val);
600
601 return 0;
602 }
603
604 static int rtl8367b_read_phy_reg(struct rtl8366_smi *smi,
605 u32 phy_addr, u32 phy_reg, u32 *val)
606 {
607 int timeout;
608 u32 data;
609 int err;
610
611 if (phy_addr > RTL8367B_PHY_ADDR_MAX)
612 return -EINVAL;
613
614 if (phy_reg > RTL8367B_PHY_REG_MAX)
615 return -EINVAL;
616
617 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
618 if (data & RTL8367B_IA_STATUS_PHY_BUSY)
619 return -ETIMEDOUT;
620
621 /* prepare address */
622 REG_WR(smi, RTL8367B_IA_ADDRESS_REG,
623 RTL8367B_INTERNAL_PHY_REG(phy_addr, phy_reg));
624
625 /* send read command */
626 REG_WR(smi, RTL8367B_IA_CTRL_REG,
627 RTL8367B_IA_CTRL_CMD_MASK | RTL8367B_IA_CTRL_RW_READ);
628
629 timeout = 5;
630 do {
631 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
632 if ((data & RTL8367B_IA_STATUS_PHY_BUSY) == 0)
633 break;
634
635 if (timeout--) {
636 dev_err(smi->parent, "phy read timed out\n");
637 return -ETIMEDOUT;
638 }
639
640 udelay(1);
641 } while (1);
642
643 /* read data */
644 REG_RD(smi, RTL8367B_IA_READ_DATA_REG, val);
645
646 dev_dbg(smi->parent, "phy_read: addr:%02x, reg:%02x, val:%04x\n",
647 phy_addr, phy_reg, *val);
648 return 0;
649 }
650
651 static int rtl8367b_write_phy_reg(struct rtl8366_smi *smi,
652 u32 phy_addr, u32 phy_reg, u32 val)
653 {
654 int timeout;
655 u32 data;
656 int err;
657
658 dev_dbg(smi->parent, "phy_write: addr:%02x, reg:%02x, val:%04x\n",
659 phy_addr, phy_reg, val);
660
661 if (phy_addr > RTL8367B_PHY_ADDR_MAX)
662 return -EINVAL;
663
664 if (phy_reg > RTL8367B_PHY_REG_MAX)
665 return -EINVAL;
666
667 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
668 if (data & RTL8367B_IA_STATUS_PHY_BUSY)
669 return -ETIMEDOUT;
670
671 /* preapre data */
672 REG_WR(smi, RTL8367B_IA_WRITE_DATA_REG, val);
673
674 /* prepare address */
675 REG_WR(smi, RTL8367B_IA_ADDRESS_REG,
676 RTL8367B_INTERNAL_PHY_REG(phy_addr, phy_reg));
677
678 /* send write command */
679 REG_WR(smi, RTL8367B_IA_CTRL_REG,
680 RTL8367B_IA_CTRL_CMD_MASK | RTL8367B_IA_CTRL_RW_WRITE);
681
682 timeout = 5;
683 do {
684 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
685 if ((data & RTL8367B_IA_STATUS_PHY_BUSY) == 0)
686 break;
687
688 if (timeout--) {
689 dev_err(smi->parent, "phy write timed out\n");
690 return -ETIMEDOUT;
691 }
692
693 udelay(1);
694 } while (1);
695
696 return 0;
697 }
698
699 static int rtl8367b_init_regs(struct rtl8366_smi *smi)
700 {
701 const struct rtl8367b_initval *initvals;
702 u32 chip_ver;
703 u32 rlvid;
704 int count;
705 int err;
706
707 REG_WR(smi, RTL8367B_RTL_MAGIC_ID_REG, RTL8367B_RTL_MAGIC_ID_VAL);
708 REG_RD(smi, RTL8367B_CHIP_VER_REG, &chip_ver);
709
710 rlvid = (chip_ver >> RTL8367B_CHIP_VER_RLVID_SHIFT) &
711 RTL8367B_CHIP_VER_RLVID_MASK;
712
713 switch (rlvid) {
714 case 0:
715 initvals = rtl8367r_vb_initvals_0;
716 count = ARRAY_SIZE(rtl8367r_vb_initvals_0);
717 break;
718
719 case 1:
720 initvals = rtl8367r_vb_initvals_1;
721 count = ARRAY_SIZE(rtl8367r_vb_initvals_1);
722 break;
723
724 default:
725 dev_err(smi->parent, "unknow rlvid %u\n", rlvid);
726 return -ENODEV;
727 }
728
729 /* TODO: disable RLTP */
730
731 return rtl8367b_write_initvals(smi, initvals, count);
732 }
733
734 static int rtl8367b_reset_chip(struct rtl8366_smi *smi)
735 {
736 int timeout = 10;
737 int err;
738 u32 data;
739
740 REG_WR(smi, RTL8367B_CHIP_RESET_REG, RTL8367B_CHIP_RESET_HW);
741 msleep(RTL8367B_RESET_DELAY);
742
743 do {
744 REG_RD(smi, RTL8367B_CHIP_RESET_REG, &data);
745 if (!(data & RTL8367B_CHIP_RESET_HW))
746 break;
747
748 msleep(1);
749 } while (--timeout);
750
751 if (!timeout) {
752 dev_err(smi->parent, "chip reset timed out\n");
753 return -ETIMEDOUT;
754 }
755
756 return 0;
757 }
758
759 static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
760 enum rtl8367_extif_mode mode)
761 {
762 int err;
763
764 /* set port mode */
765 switch (mode) {
766 case RTL8367_EXTIF_MODE_RGMII:
767 case RTL8367_EXTIF_MODE_RGMII_33V:
768 REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
769 RTL8367B_DEBUG0_SEL33(id),
770 RTL8367B_DEBUG0_SEL33(id));
771 if (id <= 1) {
772 REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
773 RTL8367B_DEBUG0_DRI(id) |
774 RTL8367B_DEBUG0_DRI_RG(id) |
775 RTL8367B_DEBUG0_SLR(id),
776 RTL8367B_DEBUG0_DRI_RG(id) |
777 RTL8367B_DEBUG0_SLR(id));
778 REG_RMW(smi, RTL8367B_CHIP_DEBUG1_REG,
779 RTL8367B_DEBUG1_DN_MASK(id) |
780 RTL8367B_DEBUG1_DP_MASK(id),
781 (7 << RTL8367B_DEBUG1_DN_SHIFT(id)) |
782 (7 << RTL8367B_DEBUG1_DP_SHIFT(id)));
783 }
784 break;
785
786 case RTL8367_EXTIF_MODE_TMII_MAC:
787 case RTL8367_EXTIF_MODE_TMII_PHY:
788 REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG,
789 BIT((id + 1) % 2), BIT((id + 1) % 2));
790 break;
791
792 case RTL8367_EXTIF_MODE_GMII:
793 REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
794 RTL8367B_DEBUG0_SEL33(id),
795 RTL8367B_DEBUG0_SEL33(id));
796 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), BIT(6));
797 break;
798
799 case RTL8367_EXTIF_MODE_MII_MAC:
800 case RTL8367_EXTIF_MODE_MII_PHY:
801 case RTL8367_EXTIF_MODE_DISABLED:
802 REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG,
803 BIT((id + 1) % 2), 0);
804 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), 0);
805 break;
806
807 default:
808 dev_err(smi->parent,
809 "invalid mode for external interface %d\n", id);
810 return -EINVAL;
811 }
812
813 REG_RMW(smi, RTL8367B_DIS_REG,
814 RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id),
815 mode << RTL8367B_DIS_RGMII_SHIFT(id));
816
817 return 0;
818 }
819
820 static int rtl8367b_extif_set_force(struct rtl8366_smi *smi, int id,
821 struct rtl8367_port_ability *pa)
822 {
823 u32 mask;
824 u32 val;
825 int err;
826
827 mask = (RTL8367B_DI_FORCE_MODE |
828 RTL8367B_DI_FORCE_NWAY |
829 RTL8367B_DI_FORCE_TXPAUSE |
830 RTL8367B_DI_FORCE_RXPAUSE |
831 RTL8367B_DI_FORCE_LINK |
832 RTL8367B_DI_FORCE_DUPLEX |
833 RTL8367B_DI_FORCE_SPEED_MASK);
834
835 val = pa->speed;
836 val |= pa->force_mode ? RTL8367B_DI_FORCE_MODE : 0;
837 val |= pa->nway ? RTL8367B_DI_FORCE_NWAY : 0;
838 val |= pa->txpause ? RTL8367B_DI_FORCE_TXPAUSE : 0;
839 val |= pa->rxpause ? RTL8367B_DI_FORCE_RXPAUSE : 0;
840 val |= pa->link ? RTL8367B_DI_FORCE_LINK : 0;
841 val |= pa->duplex ? RTL8367B_DI_FORCE_DUPLEX : 0;
842
843 REG_RMW(smi, RTL8367B_DI_FORCE_REG(id), mask, val);
844
845 return 0;
846 }
847
848 static int rtl8367b_extif_set_rgmii_delay(struct rtl8366_smi *smi, int id,
849 unsigned txdelay, unsigned rxdelay)
850 {
851 u32 mask;
852 u32 val;
853 int err;
854
855 mask = (RTL8367B_EXT_RGMXF_RXDELAY_MASK |
856 (RTL8367B_EXT_RGMXF_TXDELAY_MASK <<
857 RTL8367B_EXT_RGMXF_TXDELAY_SHIFT));
858
859 val = rxdelay;
860 val |= txdelay << RTL8367B_EXT_RGMXF_TXDELAY_SHIFT;
861
862 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), mask, val);
863
864 return 0;
865 }
866
867 static int rtl8367b_extif_init(struct rtl8366_smi *smi, int id,
868 struct rtl8367_extif_config *cfg)
869 {
870 enum rtl8367_extif_mode mode;
871 int err;
872
873 mode = (cfg) ? cfg->mode : RTL8367_EXTIF_MODE_DISABLED;
874
875 err = rtl8367b_extif_set_mode(smi, id, mode);
876 if (err)
877 return err;
878
879 if (mode != RTL8367_EXTIF_MODE_DISABLED) {
880 err = rtl8367b_extif_set_force(smi, id, &cfg->ability);
881 if (err)
882 return err;
883
884 err = rtl8367b_extif_set_rgmii_delay(smi, id, cfg->txdelay,
885 cfg->rxdelay);
886 if (err)
887 return err;
888 }
889
890 return 0;
891 }
892
893 #ifdef CONFIG_OF
894 static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id,
895 const char *name)
896 {
897 struct rtl8367_extif_config *cfg;
898 const __be32 *prop;
899 int size;
900 int err;
901
902 prop = of_get_property(smi->parent->of_node, name, &size);
903 if (!prop)
904 return rtl8367b_extif_init(smi, id, NULL);
905
906 if (size != (9 * sizeof(*prop))) {
907 dev_err(smi->parent, "%s property is invalid\n", name);
908 return -EINVAL;
909 }
910
911 cfg = kzalloc(sizeof(struct rtl8367_extif_config), GFP_KERNEL);
912 if (!cfg)
913 return -ENOMEM;
914
915 cfg->txdelay = be32_to_cpup(prop++);
916 cfg->rxdelay = be32_to_cpup(prop++);
917 cfg->mode = be32_to_cpup(prop++);
918 cfg->ability.force_mode = be32_to_cpup(prop++);
919 cfg->ability.txpause = be32_to_cpup(prop++);
920 cfg->ability.rxpause = be32_to_cpup(prop++);
921 cfg->ability.link = be32_to_cpup(prop++);
922 cfg->ability.duplex = be32_to_cpup(prop++);
923 cfg->ability.speed = be32_to_cpup(prop++);
924
925 err = rtl8367b_extif_init(smi, id, cfg);
926 kfree(cfg);
927
928 return err;
929 }
930 #else
931 static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id,
932 const char *name)
933 {
934 return -EINVAL;
935 }
936 #endif
937
938 static int rtl8367b_setup(struct rtl8366_smi *smi)
939 {
940 struct rtl8367_platform_data *pdata;
941 int err;
942 int i;
943
944 pdata = smi->parent->platform_data;
945
946 err = rtl8367b_init_regs(smi);
947 if (err)
948 return err;
949
950 /* initialize external interfaces */
951 if (smi->parent->of_node) {
952 err = rtl8367b_extif_init_of(smi, 0, "realtek,extif0");
953 if (err)
954 return err;
955
956 err = rtl8367b_extif_init_of(smi, 1, "realtek,extif1");
957 if (err)
958 return err;
959 } else {
960 err = rtl8367b_extif_init(smi, 0, pdata->extif0_cfg);
961 if (err)
962 return err;
963
964 err = rtl8367b_extif_init(smi, 1, pdata->extif1_cfg);
965 if (err)
966 return err;
967 }
968
969 /* set maximum packet length to 1536 bytes */
970 REG_RMW(smi, RTL8367B_SWC0_REG, RTL8367B_SWC0_MAX_LENGTH_MASK,
971 RTL8367B_SWC0_MAX_LENGTH_1536);
972
973 /*
974 * discard VLAN tagged packets if the port is not a member of
975 * the VLAN with which the packets is associated.
976 */
977 REG_WR(smi, RTL8367B_VLAN_INGRESS_REG, RTL8367B_PORTS_ALL);
978
979 /*
980 * Setup egress tag mode for each port.
981 */
982 for (i = 0; i < RTL8367B_NUM_PORTS; i++)
983 REG_RMW(smi,
984 RTL8367B_PORT_MISC_CFG_REG(i),
985 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_MASK <<
986 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT,
987 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_ORIGINAL <<
988 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT);
989
990 return 0;
991 }
992
993 static int rtl8367b_get_mib_counter(struct rtl8366_smi *smi, int counter,
994 int port, unsigned long long *val)
995 {
996 struct rtl8366_mib_counter *mib;
997 int offset;
998 int i;
999 int err;
1000 u32 addr, data;
1001 u64 mibvalue;
1002
1003 if (port > RTL8367B_NUM_PORTS ||
1004 counter >= RTL8367B_NUM_MIB_COUNTERS)
1005 return -EINVAL;
1006
1007 mib = &rtl8367b_mib_counters[counter];
1008 addr = RTL8367B_MIB_COUNTER_PORT_OFFSET * port + mib->offset;
1009
1010 /*
1011 * Writing access counter address first
1012 * then ASIC will prepare 64bits counter wait for being retrived
1013 */
1014 REG_WR(smi, RTL8367B_MIB_ADDRESS_REG, addr >> 2);
1015
1016 /* read MIB control register */
1017 REG_RD(smi, RTL8367B_MIB_CTRL0_REG(0), &data);
1018
1019 if (data & RTL8367B_MIB_CTRL0_BUSY_MASK)
1020 return -EBUSY;
1021
1022 if (data & RTL8367B_MIB_CTRL0_RESET_MASK)
1023 return -EIO;
1024
1025 if (mib->length == 4)
1026 offset = 3;
1027 else
1028 offset = (mib->offset + 1) % 4;
1029
1030 mibvalue = 0;
1031 for (i = 0; i < mib->length; i++) {
1032 REG_RD(smi, RTL8367B_MIB_COUNTER_REG(offset - i), &data);
1033 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
1034 }
1035
1036 *val = mibvalue;
1037 return 0;
1038 }
1039
1040 static int rtl8367b_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
1041 struct rtl8366_vlan_4k *vlan4k)
1042 {
1043 u32 data[RTL8367B_TA_VLAN_NUM_WORDS];
1044 int err;
1045 int i;
1046
1047 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1048
1049 if (vid >= RTL8367B_NUM_VIDS)
1050 return -EINVAL;
1051
1052 /* write VID */
1053 REG_WR(smi, RTL8367B_TA_ADDR_REG, vid);
1054
1055 /* write table access control word */
1056 REG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_READ);
1057
1058 for (i = 0; i < ARRAY_SIZE(data); i++)
1059 REG_RD(smi, RTL8367B_TA_RDDATA_REG(i), &data[i]);
1060
1061 vlan4k->vid = vid;
1062 vlan4k->member = (data[0] >> RTL8367B_TA_VLAN0_MEMBER_SHIFT) &
1063 RTL8367B_TA_VLAN0_MEMBER_MASK;
1064 vlan4k->untag = (data[0] >> RTL8367B_TA_VLAN0_UNTAG_SHIFT) &
1065 RTL8367B_TA_VLAN0_UNTAG_MASK;
1066 vlan4k->fid = (data[1] >> RTL8367B_TA_VLAN1_FID_SHIFT) &
1067 RTL8367B_TA_VLAN1_FID_MASK;
1068
1069 return 0;
1070 }
1071
1072 static int rtl8367b_set_vlan_4k(struct rtl8366_smi *smi,
1073 const struct rtl8366_vlan_4k *vlan4k)
1074 {
1075 u32 data[RTL8367B_TA_VLAN_NUM_WORDS];
1076 int err;
1077 int i;
1078
1079 if (vlan4k->vid >= RTL8367B_NUM_VIDS ||
1080 vlan4k->member > RTL8367B_TA_VLAN0_MEMBER_MASK ||
1081 vlan4k->untag > RTL8367B_UNTAG_MASK ||
1082 vlan4k->fid > RTL8367B_FIDMAX)
1083 return -EINVAL;
1084
1085 memset(data, 0, sizeof(data));
1086
1087 data[0] = (vlan4k->member & RTL8367B_TA_VLAN0_MEMBER_MASK) <<
1088 RTL8367B_TA_VLAN0_MEMBER_SHIFT;
1089 data[0] |= (vlan4k->untag & RTL8367B_TA_VLAN0_UNTAG_MASK) <<
1090 RTL8367B_TA_VLAN0_UNTAG_SHIFT;
1091 data[1] = (vlan4k->fid & RTL8367B_TA_VLAN1_FID_MASK) <<
1092 RTL8367B_TA_VLAN1_FID_SHIFT;
1093
1094 for (i = 0; i < ARRAY_SIZE(data); i++)
1095 REG_WR(smi, RTL8367B_TA_WRDATA_REG(i), data[i]);
1096
1097 /* write VID */
1098 REG_WR(smi, RTL8367B_TA_ADDR_REG,
1099 vlan4k->vid & RTL8367B_TA_VLAN_VID_MASK);
1100
1101 /* write table access control word */
1102 REG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_WRITE);
1103
1104 return 0;
1105 }
1106
1107 static int rtl8367b_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
1108 struct rtl8366_vlan_mc *vlanmc)
1109 {
1110 u32 data[RTL8367B_VLAN_MC_NUM_WORDS];
1111 int err;
1112 int i;
1113
1114 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1115
1116 if (index >= RTL8367B_NUM_VLANS)
1117 return -EINVAL;
1118
1119 for (i = 0; i < ARRAY_SIZE(data); i++)
1120 REG_RD(smi, RTL8367B_VLAN_MC_BASE(index) + i, &data[i]);
1121
1122 vlanmc->member = (data[0] >> RTL8367B_VLAN_MC0_MEMBER_SHIFT) &
1123 RTL8367B_VLAN_MC0_MEMBER_MASK;
1124 vlanmc->fid = (data[1] >> RTL8367B_VLAN_MC1_FID_SHIFT) &
1125 RTL8367B_VLAN_MC1_FID_MASK;
1126 vlanmc->vid = (data[3] >> RTL8367B_VLAN_MC3_EVID_SHIFT) &
1127 RTL8367B_VLAN_MC3_EVID_MASK;
1128
1129 return 0;
1130 }
1131
1132 static int rtl8367b_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
1133 const struct rtl8366_vlan_mc *vlanmc)
1134 {
1135 u32 data[RTL8367B_VLAN_MC_NUM_WORDS];
1136 int err;
1137 int i;
1138
1139 if (index >= RTL8367B_NUM_VLANS ||
1140 vlanmc->vid >= RTL8367B_NUM_VIDS ||
1141 vlanmc->priority > RTL8367B_PRIORITYMAX ||
1142 vlanmc->member > RTL8367B_VLAN_MC0_MEMBER_MASK ||
1143 vlanmc->untag > RTL8367B_UNTAG_MASK ||
1144 vlanmc->fid > RTL8367B_FIDMAX)
1145 return -EINVAL;
1146
1147 data[0] = (vlanmc->member & RTL8367B_VLAN_MC0_MEMBER_MASK) <<
1148 RTL8367B_VLAN_MC0_MEMBER_SHIFT;
1149 data[1] = (vlanmc->fid & RTL8367B_VLAN_MC1_FID_MASK) <<
1150 RTL8367B_VLAN_MC1_FID_SHIFT;
1151 data[2] = 0;
1152 data[3] = (vlanmc->vid & RTL8367B_VLAN_MC3_EVID_MASK) <<
1153 RTL8367B_VLAN_MC3_EVID_SHIFT;
1154
1155 for (i = 0; i < ARRAY_SIZE(data); i++)
1156 REG_WR(smi, RTL8367B_VLAN_MC_BASE(index) + i, data[i]);
1157
1158 return 0;
1159 }
1160
1161 static int rtl8367b_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
1162 {
1163 u32 data;
1164 int err;
1165
1166 if (port >= RTL8367B_NUM_PORTS)
1167 return -EINVAL;
1168
1169 REG_RD(smi, RTL8367B_VLAN_PVID_CTRL_REG(port), &data);
1170
1171 *val = (data >> RTL8367B_VLAN_PVID_CTRL_SHIFT(port)) &
1172 RTL8367B_VLAN_PVID_CTRL_MASK;
1173
1174 return 0;
1175 }
1176
1177 static int rtl8367b_set_mc_index(struct rtl8366_smi *smi, int port, int index)
1178 {
1179 if (port >= RTL8367B_NUM_PORTS || index >= RTL8367B_NUM_VLANS)
1180 return -EINVAL;
1181
1182 return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_PVID_CTRL_REG(port),
1183 RTL8367B_VLAN_PVID_CTRL_MASK <<
1184 RTL8367B_VLAN_PVID_CTRL_SHIFT(port),
1185 (index & RTL8367B_VLAN_PVID_CTRL_MASK) <<
1186 RTL8367B_VLAN_PVID_CTRL_SHIFT(port));
1187 }
1188
1189 static int rtl8367b_enable_vlan(struct rtl8366_smi *smi, int enable)
1190 {
1191 return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_CTRL_REG,
1192 RTL8367B_VLAN_CTRL_ENABLE,
1193 (enable) ? RTL8367B_VLAN_CTRL_ENABLE : 0);
1194 }
1195
1196 static int rtl8367b_enable_vlan4k(struct rtl8366_smi *smi, int enable)
1197 {
1198 return 0;
1199 }
1200
1201 static int rtl8367b_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
1202 {
1203 unsigned max = RTL8367B_NUM_VLANS;
1204
1205 if (smi->vlan4k_enabled)
1206 max = RTL8367B_NUM_VIDS - 1;
1207
1208 if (vlan == 0 || vlan >= max)
1209 return 0;
1210
1211 return 1;
1212 }
1213
1214 static int rtl8367b_enable_port(struct rtl8366_smi *smi, int port, int enable)
1215 {
1216 int err;
1217
1218 REG_WR(smi, RTL8367B_PORT_ISOLATION_REG(port),
1219 (enable) ? RTL8367B_PORTS_ALL : 0);
1220
1221 return 0;
1222 }
1223
1224 static int rtl8367b_sw_reset_mibs(struct switch_dev *dev,
1225 const struct switch_attr *attr,
1226 struct switch_val *val)
1227 {
1228 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1229
1230 return rtl8366_smi_rmwr(smi, RTL8367B_MIB_CTRL0_REG(0), 0,
1231 RTL8367B_MIB_CTRL0_GLOBAL_RESET_MASK);
1232 }
1233
1234 static int rtl8367b_sw_get_port_link(struct switch_dev *dev,
1235 int port,
1236 struct switch_port_link *link)
1237 {
1238 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1239 u32 data = 0;
1240 u32 speed;
1241
1242 if (port >= RTL8367B_NUM_PORTS)
1243 return -EINVAL;
1244
1245 rtl8366_smi_read_reg(smi, RTL8367B_PORT_STATUS_REG(port), &data);
1246
1247 link->link = !!(data & RTL8367B_PORT_STATUS_LINK);
1248 if (!link->link)
1249 return 0;
1250
1251 link->duplex = !!(data & RTL8367B_PORT_STATUS_DUPLEX);
1252 link->rx_flow = !!(data & RTL8367B_PORT_STATUS_RXPAUSE);
1253 link->tx_flow = !!(data & RTL8367B_PORT_STATUS_TXPAUSE);
1254 link->aneg = !!(data & RTL8367B_PORT_STATUS_NWAY);
1255
1256 speed = (data & RTL8367B_PORT_STATUS_SPEED_MASK);
1257 switch (speed) {
1258 case 0:
1259 link->speed = SWITCH_PORT_SPEED_10;
1260 break;
1261 case 1:
1262 link->speed = SWITCH_PORT_SPEED_100;
1263 break;
1264 case 2:
1265 link->speed = SWITCH_PORT_SPEED_1000;
1266 break;
1267 default:
1268 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1269 break;
1270 }
1271
1272 return 0;
1273 }
1274
1275 static int rtl8367b_sw_get_max_length(struct switch_dev *dev,
1276 const struct switch_attr *attr,
1277 struct switch_val *val)
1278 {
1279 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1280 u32 data;
1281
1282 rtl8366_smi_read_reg(smi, RTL8367B_SWC0_REG, &data);
1283 val->value.i = (data & RTL8367B_SWC0_MAX_LENGTH_MASK) >>
1284 RTL8367B_SWC0_MAX_LENGTH_SHIFT;
1285
1286 return 0;
1287 }
1288
1289 static int rtl8367b_sw_set_max_length(struct switch_dev *dev,
1290 const struct switch_attr *attr,
1291 struct switch_val *val)
1292 {
1293 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1294 u32 max_len;
1295
1296 switch (val->value.i) {
1297 case 0:
1298 max_len = RTL8367B_SWC0_MAX_LENGTH_1522;
1299 break;
1300 case 1:
1301 max_len = RTL8367B_SWC0_MAX_LENGTH_1536;
1302 break;
1303 case 2:
1304 max_len = RTL8367B_SWC0_MAX_LENGTH_1552;
1305 break;
1306 case 3:
1307 max_len = RTL8367B_SWC0_MAX_LENGTH_16000;
1308 break;
1309 default:
1310 return -EINVAL;
1311 }
1312
1313 return rtl8366_smi_rmwr(smi, RTL8367B_SWC0_REG,
1314 RTL8367B_SWC0_MAX_LENGTH_MASK, max_len);
1315 }
1316
1317
1318 static int rtl8367b_sw_reset_port_mibs(struct switch_dev *dev,
1319 const struct switch_attr *attr,
1320 struct switch_val *val)
1321 {
1322 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1323 int port;
1324
1325 port = val->port_vlan;
1326 if (port >= RTL8367B_NUM_PORTS)
1327 return -EINVAL;
1328
1329 return rtl8366_smi_rmwr(smi, RTL8367B_MIB_CTRL0_REG(port / 8), 0,
1330 RTL8367B_MIB_CTRL0_PORT_RESET_MASK(port % 8));
1331 }
1332
1333 static int rtl8367b_sw_get_port_stats(struct switch_dev *dev, int port,
1334 struct switch_port_stats *stats)
1335 {
1336 return (rtl8366_sw_get_port_stats(dev, port, stats,
1337 RTL8367B_MIB_TXB_ID, RTL8367B_MIB_RXB_ID));
1338 }
1339
1340 static struct switch_attr rtl8367b_globals[] = {
1341 {
1342 .type = SWITCH_TYPE_INT,
1343 .name = "enable_vlan",
1344 .description = "Enable VLAN mode",
1345 .set = rtl8366_sw_set_vlan_enable,
1346 .get = rtl8366_sw_get_vlan_enable,
1347 .max = 1,
1348 .ofs = 1
1349 }, {
1350 .type = SWITCH_TYPE_INT,
1351 .name = "enable_vlan4k",
1352 .description = "Enable VLAN 4K mode",
1353 .set = rtl8366_sw_set_vlan_enable,
1354 .get = rtl8366_sw_get_vlan_enable,
1355 .max = 1,
1356 .ofs = 2
1357 }, {
1358 .type = SWITCH_TYPE_NOVAL,
1359 .name = "reset_mibs",
1360 .description = "Reset all MIB counters",
1361 .set = rtl8367b_sw_reset_mibs,
1362 }, {
1363 .type = SWITCH_TYPE_INT,
1364 .name = "max_length",
1365 .description = "Get/Set the maximum length of valid packets"
1366 "(0:1522, 1:1536, 2:1552, 3:16000)",
1367 .set = rtl8367b_sw_set_max_length,
1368 .get = rtl8367b_sw_get_max_length,
1369 .max = 3,
1370 }
1371 };
1372
1373 static struct switch_attr rtl8367b_port[] = {
1374 {
1375 .type = SWITCH_TYPE_NOVAL,
1376 .name = "reset_mib",
1377 .description = "Reset single port MIB counters",
1378 .set = rtl8367b_sw_reset_port_mibs,
1379 }, {
1380 .type = SWITCH_TYPE_STRING,
1381 .name = "mib",
1382 .description = "Get MIB counters for port",
1383 .max = 33,
1384 .set = NULL,
1385 .get = rtl8366_sw_get_port_mib,
1386 },
1387 };
1388
1389 static struct switch_attr rtl8367b_vlan[] = {
1390 {
1391 .type = SWITCH_TYPE_STRING,
1392 .name = "info",
1393 .description = "Get vlan information",
1394 .max = 1,
1395 .set = NULL,
1396 .get = rtl8366_sw_get_vlan_info,
1397 },
1398 };
1399
1400 static const struct switch_dev_ops rtl8367b_sw_ops = {
1401 .attr_global = {
1402 .attr = rtl8367b_globals,
1403 .n_attr = ARRAY_SIZE(rtl8367b_globals),
1404 },
1405 .attr_port = {
1406 .attr = rtl8367b_port,
1407 .n_attr = ARRAY_SIZE(rtl8367b_port),
1408 },
1409 .attr_vlan = {
1410 .attr = rtl8367b_vlan,
1411 .n_attr = ARRAY_SIZE(rtl8367b_vlan),
1412 },
1413
1414 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1415 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1416 .get_port_pvid = rtl8366_sw_get_port_pvid,
1417 .set_port_pvid = rtl8366_sw_set_port_pvid,
1418 .reset_switch = rtl8366_sw_reset_switch,
1419 .get_port_link = rtl8367b_sw_get_port_link,
1420 .get_port_stats = rtl8367b_sw_get_port_stats,
1421 };
1422
1423 static int rtl8367b_switch_init(struct rtl8366_smi *smi)
1424 {
1425 struct switch_dev *dev = &smi->sw_dev;
1426 int err;
1427
1428 dev->name = "RTL8367B";
1429 dev->cpu_port = smi->cpu_port;
1430 dev->ports = RTL8367B_NUM_PORTS;
1431 dev->vlans = RTL8367B_NUM_VIDS;
1432 dev->ops = &rtl8367b_sw_ops;
1433 dev->alias = dev_name(smi->parent);
1434
1435 err = register_switch(dev, NULL);
1436 if (err)
1437 dev_err(smi->parent, "switch registration failed\n");
1438
1439 return err;
1440 }
1441
1442 static void rtl8367b_switch_cleanup(struct rtl8366_smi *smi)
1443 {
1444 unregister_switch(&smi->sw_dev);
1445 }
1446
1447 static int rtl8367b_mii_read(struct mii_bus *bus, int addr, int reg)
1448 {
1449 struct rtl8366_smi *smi = bus->priv;
1450 u32 val = 0;
1451 int err;
1452
1453 err = rtl8367b_read_phy_reg(smi, addr, reg, &val);
1454 if (err)
1455 return 0xffff;
1456
1457 return val;
1458 }
1459
1460 static int rtl8367b_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1461 {
1462 struct rtl8366_smi *smi = bus->priv;
1463 u32 t;
1464 int err;
1465
1466 err = rtl8367b_write_phy_reg(smi, addr, reg, val);
1467 if (err)
1468 return err;
1469
1470 /* flush write */
1471 (void) rtl8367b_read_phy_reg(smi, addr, reg, &t);
1472
1473 return err;
1474 }
1475
1476 static int rtl8367b_detect(struct rtl8366_smi *smi)
1477 {
1478 const char *chip_name;
1479 u32 chip_num;
1480 u32 chip_ver;
1481 u32 chip_mode;
1482 int ret;
1483
1484 /* TODO: improve chip detection */
1485 rtl8366_smi_write_reg(smi, RTL8367B_RTL_MAGIC_ID_REG,
1486 RTL8367B_RTL_MAGIC_ID_VAL);
1487
1488 ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_NUMBER_REG, &chip_num);
1489 if (ret) {
1490 dev_err(smi->parent, "unable to read %s register\n",
1491 "chip number");
1492 return ret;
1493 }
1494
1495 ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_VER_REG, &chip_ver);
1496 if (ret) {
1497 dev_err(smi->parent, "unable to read %s register\n",
1498 "chip version");
1499 return ret;
1500 }
1501
1502 ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_MODE_REG, &chip_mode);
1503 if (ret) {
1504 dev_err(smi->parent, "unable to read %s register\n",
1505 "chip mode");
1506 return ret;
1507 }
1508
1509 switch (chip_ver) {
1510 case 0x1000:
1511 chip_name = "8367RB";
1512 break;
1513 case 0x1010:
1514 chip_name = "8367R-VB";
1515 break;
1516 default:
1517 dev_err(smi->parent,
1518 "unknown chip num:%04x ver:%04x, mode:%04x\n",
1519 chip_num, chip_ver, chip_mode);
1520 return -ENODEV;
1521 }
1522
1523 dev_info(smi->parent, "RTL%s chip found\n", chip_name);
1524
1525 return 0;
1526 }
1527
1528 static struct rtl8366_smi_ops rtl8367b_smi_ops = {
1529 .detect = rtl8367b_detect,
1530 .reset_chip = rtl8367b_reset_chip,
1531 .setup = rtl8367b_setup,
1532
1533 .mii_read = rtl8367b_mii_read,
1534 .mii_write = rtl8367b_mii_write,
1535
1536 .get_vlan_mc = rtl8367b_get_vlan_mc,
1537 .set_vlan_mc = rtl8367b_set_vlan_mc,
1538 .get_vlan_4k = rtl8367b_get_vlan_4k,
1539 .set_vlan_4k = rtl8367b_set_vlan_4k,
1540 .get_mc_index = rtl8367b_get_mc_index,
1541 .set_mc_index = rtl8367b_set_mc_index,
1542 .get_mib_counter = rtl8367b_get_mib_counter,
1543 .is_vlan_valid = rtl8367b_is_vlan_valid,
1544 .enable_vlan = rtl8367b_enable_vlan,
1545 .enable_vlan4k = rtl8367b_enable_vlan4k,
1546 .enable_port = rtl8367b_enable_port,
1547 };
1548
1549 static int rtl8367b_probe(struct platform_device *pdev)
1550 {
1551 struct rtl8366_smi *smi;
1552 int err;
1553
1554 smi = rtl8366_smi_probe(pdev);
1555 if (IS_ERR(smi))
1556 return PTR_ERR(smi);
1557
1558 smi->clk_delay = 1500;
1559 smi->cmd_read = 0xb9;
1560 smi->cmd_write = 0xb8;
1561 smi->ops = &rtl8367b_smi_ops;
1562 smi->num_ports = RTL8367B_NUM_PORTS;
1563 if (of_property_read_u32(pdev->dev.of_node, "cpu_port", &smi->cpu_port)
1564 || smi->cpu_port >= smi->num_ports)
1565 smi->cpu_port = RTL8367B_CPU_PORT_NUM;
1566 smi->num_vlan_mc = RTL8367B_NUM_VLANS;
1567 smi->mib_counters = rtl8367b_mib_counters;
1568 smi->num_mib_counters = ARRAY_SIZE(rtl8367b_mib_counters);
1569
1570 err = rtl8366_smi_init(smi);
1571 if (err)
1572 goto err_free_smi;
1573
1574 platform_set_drvdata(pdev, smi);
1575
1576 err = rtl8367b_switch_init(smi);
1577 if (err)
1578 goto err_clear_drvdata;
1579
1580 return 0;
1581
1582 err_clear_drvdata:
1583 platform_set_drvdata(pdev, NULL);
1584 rtl8366_smi_cleanup(smi);
1585 err_free_smi:
1586 kfree(smi);
1587 return err;
1588 }
1589
1590 static int rtl8367b_remove(struct platform_device *pdev)
1591 {
1592 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1593
1594 if (smi) {
1595 rtl8367b_switch_cleanup(smi);
1596 platform_set_drvdata(pdev, NULL);
1597 rtl8366_smi_cleanup(smi);
1598 kfree(smi);
1599 }
1600
1601 return 0;
1602 }
1603
1604 static void rtl8367b_shutdown(struct platform_device *pdev)
1605 {
1606 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1607
1608 if (smi)
1609 rtl8367b_reset_chip(smi);
1610 }
1611
1612 #ifdef CONFIG_OF
1613 static const struct of_device_id rtl8367b_match[] = {
1614 { .compatible = "realtek,rtl8367b" },
1615 {},
1616 };
1617 MODULE_DEVICE_TABLE(of, rtl8367b_match);
1618 #endif
1619
1620 static struct platform_driver rtl8367b_driver = {
1621 .driver = {
1622 .name = RTL8367B_DRIVER_NAME,
1623 .owner = THIS_MODULE,
1624 #ifdef CONFIG_OF
1625 .of_match_table = of_match_ptr(rtl8367b_match),
1626 #endif
1627 },
1628 .probe = rtl8367b_probe,
1629 .remove = rtl8367b_remove,
1630 .shutdown = rtl8367b_shutdown,
1631 };
1632
1633 module_platform_driver(rtl8367b_driver);
1634
1635 MODULE_DESCRIPTION("Realtek RTL8367B ethernet switch driver");
1636 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1637 MODULE_LICENSE("GPL v2");
1638 MODULE_ALIAS("platform:" RTL8367B_DRIVER_NAME);
1639
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