target/linux/imx6/patches-3.10/0007-ARM-dtsi-enable-ahci-sata-on-imx6q-platforms.patch

   1 From: Richard Zhu <r65037@freescale.com>
   2 Subject: [PATCH] ARM: dtsi: enable ahci sata on imx6q platforms
   3
   4 Only imx6q has the ahci sata controller, enable
   5 it on imx6q platforms.
   6
   7 Signed-off-by: Richard Zhu <r65037@freescale.com>
   8 Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
   9 ---
  10  arch/arm/boot/dts/imx6q-sabreauto.dts | 4 ++++
  11  arch/arm/boot/dts/imx6q-sabrelite.dts | 4 ++++
  12  arch/arm/boot/dts/imx6q-sabresd.dts   | 4 ++++
  13  arch/arm/boot/dts/imx6q.dtsi          | 9 +++++++++
  14  4 files changed, 21 insertions(+)
  15
  16 --- a/arch/arm/boot/dts/imx6q-sabreauto.dts
  17 +++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
  18 @@ -33,3 +33,7 @@
  19                 };
  20         };
  21  };
  22 +
  23 +&sata {
  24 +       status = "okay";
  25 +};
  26 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts
  27 +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
  28 @@ -65,6 +65,10 @@
  29         };
  30  };
  31
  32 +&sata {
  33 +       status = "okay";
  34 +};
  35 +
  36  &ecspi1 {
  37         fsl,spi-num-chipselects = <1>;
  38         cs-gpios = <&gpio3 19 0>;
  39 --- a/arch/arm/boot/dts/imx6q-sabresd.dts
  40 +++ b/arch/arm/boot/dts/imx6q-sabresd.dts
  41 @@ -37,3 +37,7 @@
  42                 };
  43         };
  44  };
  45 +
  46 +&sata {
  47 +       status = "okay";
  48 +};
  49 --- a/arch/arm/boot/dts/imx6q.dtsi
  50 +++ b/arch/arm/boot/dts/imx6q.dtsi
  51 @@ -332,6 +332,15 @@
  52                         };
  53                 };
  54
  55 +               sata: sata@02200000 {
  56 +                       compatible = "fsl,imx6q-ahci";
  57 +                       reg = <0x02200000 0x4000>;
  58 +                       interrupts = <0 39 0x04>;
  59 +                       clocks =  <&clks 154>, <&clks 187>, <&clks 105>;
  60 +                       clock-names = "sata", "sata_ref", "ahb";
  61 +                       status = "disabled";
  62 +               };
  63 +
  64                 ipu2: ipu@02800000 {
  65                         #crtc-cells = <1>;
  66                         compatible = "fsl,imx6q-ipu";