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ipq806x: add fab scaling support
[openwrt/staging/wigyori.git] / target / linux / ipq806x / files-4.19 / arch / arm / boot / dts / qcom-ipq8064.dtsi
1 /dts-v1/;
2
3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/gpio/gpio.h>
12
13 / {
14 model = "Qualcomm IPQ8064";
15 compatible = "qcom,ipq8064";
16 interrupt-parent = <&intc>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 compatible = "qcom,krait";
24 enable-method = "qcom,kpss-acc-v1";
25 device_type = "cpu";
26 reg = <0>;
27 next-level-cache = <&L2>;
28 qcom,acc = <&acpu0_aux>;
29 qcom,saw = <&saw0>;
30 clocks = <&kraitcc 0>, <&kraitcc 4>;
31 clock-names = "cpu", "l2";
32 clock-latency = <100000>;
33 cpu-supply = <&smb208_s2a>;
34 operating-points-v2 = <&opp_table0>;
35 voltage-tolerance = <5>;
36 cooling-min-state = <0>;
37 cooling-max-state = <10>;
38 #cooling-cells = <2>;
39 cpu-idle-states = <&CPU_SPC>;
40 };
41
42 cpu1: cpu@1 {
43 compatible = "qcom,krait";
44 enable-method = "qcom,kpss-acc-v1";
45 device_type = "cpu";
46 reg = <1>;
47 next-level-cache = <&L2>;
48 qcom,acc = <&acpu1_aux>;
49 qcom,saw = <&saw1>;
50 clocks = <&kraitcc 1>, <&kraitcc 4>;
51 clock-names = "cpu", "l2";
52 clock-latency = <100000>;
53 cpu-supply = <&smb208_s2b>;
54 operating-points-v2 = <&opp_table0>;
55 voltage-tolerance = <5>;
56 cooling-min-state = <0>;
57 cooling-max-state = <10>;
58 #cooling-cells = <2>;
59 cpu-idle-states = <&CPU_SPC>;
60 };
61
62 L2: l2-cache {
63 compatible = "cache";
64 cache-level = <2>;
65 qcom,saw = <&saw_l2>;
66 };
67
68 qcom,l2 {
69 qcom,l2-rates = <384000000 1000000000 1200000000>;
70 qcom,l2-cpufreq = <384000000 600000000 1200000000>;
71 qcom,l2-volt = <1100000 1100000 1150000>;
72 qcom,l2-supply = <&smb208_s1a>;
73 };
74
75 idle-states {
76 CPU_SPC: spc {
77 compatible = "qcom,idle-state-spc",
78 "arm,idle-state";
79 status = "okay";
80 entry-latency-us = <400>;
81 exit-latency-us = <900>;
82 min-residency-us = <3000>;
83 };
84 };
85 };
86
87 opp_table0: opp_table0 {
88 compatible = "operating-points-v2-qcom-cpu";
89 nvmem-cells = <&speedbin_efuse>;
90
91 opp-384000000 {
92 opp-hz = /bits/ 64 <384000000>;
93 opp-microvolt-speed0-pvs0-v0 = <1000000>;
94 opp-microvolt-speed0-pvs1-v0 = <925000>;
95 opp-microvolt-speed0-pvs2-v0 = <875000>;
96 opp-microvolt-speed0-pvs3-v0 = <800000>;
97 opp-supported-hw = <0x1>;
98 clock-latency-ns = <100000>;
99 };
100
101 opp-600000000 {
102 opp-hz = /bits/ 64 <600000000>;
103 opp-microvolt-speed0-pvs0-v0 = <1050000>;
104 opp-microvolt-speed0-pvs1-v0 = <975000>;
105 opp-microvolt-speed0-pvs2-v0 = <925000>;
106 opp-microvolt-speed0-pvs3-v0 = <850000>;
107 opp-supported-hw = <0x1>;
108 clock-latency-ns = <100000>;
109 };
110
111 opp-800000000 {
112 opp-hz = /bits/ 64 <800000000>;
113 opp-microvolt-speed0-pvs0-v0 = <1100000>;
114 opp-microvolt-speed0-pvs1-v0 = <1025000>;
115 opp-microvolt-speed0-pvs2-v0 = <995000>;
116 opp-microvolt-speed0-pvs3-v0 = <900000>;
117 opp-supported-hw = <0x1>;
118 clock-latency-ns = <100000>;
119 };
120
121 opp-1000000000 {
122 opp-hz = /bits/ 64 <1000000000>;
123 opp-microvolt-speed0-pvs0-v0 = <1150000>;
124 opp-microvolt-speed0-pvs1-v0 = <1075000>;
125 opp-microvolt-speed0-pvs2-v0 = <1025000>;
126 opp-microvolt-speed0-pvs3-v0 = <950000>;
127 opp-supported-hw = <0x1>;
128 clock-latency-ns = <100000>;
129 };
130
131 opp-1200000000 {
132 opp-hz = /bits/ 64 <1200000000>;
133 opp-microvolt-speed0-pvs0-v0 = <1200000>;
134 opp-microvolt-speed0-pvs1-v0 = <1125000>;
135 opp-microvolt-speed0-pvs2-v0 = <1075000>;
136 opp-microvolt-speed0-pvs3-v0 = <1000000>;
137 opp-supported-hw = <0x1>;
138 clock-latency-ns = <100000>;
139 };
140
141 opp-1400000000 {
142 opp-hz = /bits/ 64 <1400000000>;
143 opp-microvolt-speed0-pvs0-v0 = <1250000>;
144 opp-microvolt-speed0-pvs1-v0 = <1175000>;
145 opp-microvolt-speed0-pvs2-v0 = <1125000>;
146 opp-microvolt-speed0-pvs3-v0 = <1050000>;
147 opp-supported-hw = <0x1>;
148 clock-latency-ns = <100000>;
149 };
150
151 };
152
153 thermal-zones {
154 tsens_tz_sensor0 {
155 polling-delay-passive = <0>;
156 polling-delay = <0>;
157 thermal-sensors = <&tsens 0>;
158
159 trips {
160 cpu-critical-hi {
161 temperature = <125000>;
162 hysteresis = <2000>;
163 type = "critical_high";
164 };
165
166 cpu-config-hi {
167 temperature = <105000>;
168 hysteresis = <2000>;
169 type = "configurable_hi";
170 };
171
172 cpu-config-lo {
173 temperature = <95000>;
174 hysteresis = <2000>;
175 type = "configurable_lo";
176 };
177
178 cpu-critical-low {
179 temperature = <0>;
180 hysteresis = <2000>;
181 type = "critical_low";
182 };
183 };
184 };
185
186 tsens_tz_sensor1 {
187 polling-delay-passive = <0>;
188 polling-delay = <0>;
189 thermal-sensors = <&tsens 1>;
190
191 trips {
192 cpu-critical-hi {
193 temperature = <125000>;
194 hysteresis = <2000>;
195 type = "critical_high";
196 };
197
198 cpu-config-hi {
199 temperature = <105000>;
200 hysteresis = <2000>;
201 type = "configurable_hi";
202 };
203
204 cpu-config-lo {
205 temperature = <95000>;
206 hysteresis = <2000>;
207 type = "configurable_lo";
208 };
209
210 cpu-critical-low {
211 temperature = <0>;
212 hysteresis = <2000>;
213 type = "critical_low";
214 };
215 };
216 };
217
218 tsens_tz_sensor2 {
219 polling-delay-passive = <0>;
220 polling-delay = <0>;
221 thermal-sensors = <&tsens 2>;
222
223 trips {
224 cpu-critical-hi {
225 temperature = <125000>;
226 hysteresis = <2000>;
227 type = "critical_high";
228 };
229
230 cpu-config-hi {
231 temperature = <105000>;
232 hysteresis = <2000>;
233 type = "configurable_hi";
234 };
235
236 cpu-config-lo {
237 temperature = <95000>;
238 hysteresis = <2000>;
239 type = "configurable_lo";
240 };
241
242 cpu-critical-low {
243 temperature = <0>;
244 hysteresis = <2000>;
245 type = "critical_low";
246 };
247 };
248 };
249
250 tsens_tz_sensor3 {
251 polling-delay-passive = <0>;
252 polling-delay = <0>;
253 thermal-sensors = <&tsens 3>;
254
255 trips {
256 cpu-critical-hi {
257 temperature = <125000>;
258 hysteresis = <2000>;
259 type = "critical_high";
260 };
261
262 cpu-config-hi {
263 temperature = <105000>;
264 hysteresis = <2000>;
265 type = "configurable_hi";
266 };
267
268 cpu-config-lo {
269 temperature = <95000>;
270 hysteresis = <2000>;
271 type = "configurable_lo";
272 };
273
274 cpu-critical-low {
275 temperature = <0>;
276 hysteresis = <2000>;
277 type = "critical_low";
278 };
279 };
280 };
281
282 tsens_tz_sensor4 {
283 polling-delay-passive = <0>;
284 polling-delay = <0>;
285 thermal-sensors = <&tsens 4>;
286
287 trips {
288 cpu-critical-hi {
289 temperature = <125000>;
290 hysteresis = <2000>;
291 type = "critical_high";
292 };
293
294 cpu-config-hi {
295 temperature = <105000>;
296 hysteresis = <2000>;
297 type = "configurable_hi";
298 };
299
300 cpu-config-lo {
301 temperature = <95000>;
302 hysteresis = <2000>;
303 type = "configurable_lo";
304 };
305
306 cpu-critical-low {
307 temperature = <0>;
308 hysteresis = <2000>;
309 type = "critical_low";
310 };
311 };
312 };
313
314 tsens_tz_sensor5 {
315 polling-delay-passive = <0>;
316 polling-delay = <0>;
317 thermal-sensors = <&tsens 5>;
318
319 trips {
320 cpu-critical-hi {
321 temperature = <125000>;
322 hysteresis = <2000>;
323 type = "critical_high";
324 };
325
326 cpu-config-hi {
327 temperature = <105000>;
328 hysteresis = <2000>;
329 type = "configurable_hi";
330 };
331
332 cpu-config-lo {
333 temperature = <95000>;
334 hysteresis = <2000>;
335 type = "configurable_lo";
336 };
337
338 cpu-critical-low {
339 temperature = <0>;
340 hysteresis = <2000>;
341 type = "critical_low";
342 };
343 };
344 };
345
346 tsens_tz_sensor6 {
347 polling-delay-passive = <0>;
348 polling-delay = <0>;
349 thermal-sensors = <&tsens 6>;
350
351 trips {
352 cpu-critical-hi {
353 temperature = <125000>;
354 hysteresis = <2000>;
355 type = "critical_high";
356 };
357
358 cpu-config-hi {
359 temperature = <105000>;
360 hysteresis = <2000>;
361 type = "configurable_hi";
362 };
363
364 cpu-config-lo {
365 temperature = <95000>;
366 hysteresis = <2000>;
367 type = "configurable_lo";
368 };
369
370 cpu-critical-low {
371 temperature = <0>;
372 hysteresis = <2000>;
373 type = "critical_low";
374 };
375 };
376 };
377
378 tsens_tz_sensor7 {
379 polling-delay-passive = <0>;
380 polling-delay = <0>;
381 thermal-sensors = <&tsens 7>;
382
383 trips {
384 cpu-critical-hi {
385 temperature = <125000>;
386 hysteresis = <2000>;
387 type = "critical_high";
388 };
389
390 cpu-config-hi {
391 temperature = <105000>;
392 hysteresis = <2000>;
393 type = "configurable_hi";
394 };
395
396 cpu-config-lo {
397 temperature = <95000>;
398 hysteresis = <2000>;
399 type = "configurable_lo";
400 };
401
402 cpu-critical-low {
403 temperature = <0>;
404 hysteresis = <2000>;
405 type = "critical_low";
406 };
407 };
408 };
409
410 tsens_tz_sensor8 {
411 polling-delay-passive = <0>;
412 polling-delay = <0>;
413 thermal-sensors = <&tsens 8>;
414
415 trips {
416 cpu-critical-hi {
417 temperature = <125000>;
418 hysteresis = <2000>;
419 type = "critical_high";
420 };
421
422 cpu-config-hi {
423 temperature = <105000>;
424 hysteresis = <2000>;
425 type = "configurable_hi";
426 };
427
428 cpu-config-lo {
429 temperature = <95000>;
430 hysteresis = <2000>;
431 type = "configurable_lo";
432 };
433
434 cpu-critical-low {
435 temperature = <0>;
436 hysteresis = <2000>;
437 type = "critical_low";
438 };
439 };
440 };
441
442 tsens_tz_sensor9 {
443 polling-delay-passive = <0>;
444 polling-delay = <0>;
445 thermal-sensors = <&tsens 9>;
446
447 trips {
448 cpu-critical-hi {
449 temperature = <125000>;
450 hysteresis = <2000>;
451 type = "critical_high";
452 };
453
454 cpu-config-hi {
455 temperature = <105000>;
456 hysteresis = <2000>;
457 type = "configurable_hi";
458 };
459
460 cpu-config-lo {
461 temperature = <95000>;
462 hysteresis = <2000>;
463 type = "configurable_lo";
464 };
465
466 cpu-critical-low {
467 temperature = <0>;
468 hysteresis = <2000>;
469 type = "critical_low";
470 };
471 };
472 };
473
474 tsens_tz_sensor10 {
475 polling-delay-passive = <0>;
476 polling-delay = <0>;
477 thermal-sensors = <&tsens 10>;
478
479 trips {
480 cpu-critical-hi {
481 temperature = <125000>;
482 hysteresis = <2000>;
483 type = "critical_high";
484 };
485
486 cpu-config-hi {
487 temperature = <105000>;
488 hysteresis = <2000>;
489 type = "configurable_hi";
490 };
491
492 cpu-config-lo {
493 temperature = <95000>;
494 hysteresis = <2000>;
495 type = "configurable_lo";
496 };
497
498 cpu-critical-low {
499 temperature = <0>;
500 hysteresis = <2000>;
501 type = "critical_low";
502 };
503 };
504 };
505 };
506
507 cpu-pmu {
508 compatible = "qcom,krait-pmu";
509 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
510 IRQ_TYPE_LEVEL_HIGH)>;
511 };
512
513 reserved-memory {
514 #address-cells = <1>;
515 #size-cells = <1>;
516 ranges;
517
518 nss@40000000 {
519 reg = <0x40000000 0x1000000>;
520 no-map;
521 };
522
523 smem: smem@41000000 {
524 reg = <0x41000000 0x200000>;
525 no-map;
526 };
527 };
528
529 clocks {
530 cxo_board {
531 compatible = "fixed-clock";
532 #clock-cells = <0>;
533 clock-frequency = <25000000>;
534 };
535
536 pxo_board {
537 compatible = "fixed-clock";
538 #clock-cells = <0>;
539 clock-frequency = <25000000>;
540 };
541
542 sleep_clk: sleep_clk {
543 compatible = "fixed-clock";
544 clock-frequency = <32768>;
545 #clock-cells = <0>;
546 };
547 };
548
549 fab-scaling {
550 compatible = "qcom,fab-scaling";
551 clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
552 clock-names = "apps-fab-clk", "ddr-fab-clk";
553 fab_freq_high = <533000000>;
554 fab_freq_nominal = <400000000>;
555 cpu_freq_threshold = <1000000000>;
556 };
557
558 firmware {
559 scm {
560 compatible = "qcom,scm-ipq806x";
561 };
562 };
563
564 soc: soc {
565 #address-cells = <1>;
566 #size-cells = <1>;
567 ranges;
568 compatible = "simple-bus";
569
570 lpass@28100000 {
571 compatible = "qcom,lpass-cpu";
572 status = "disabled";
573 clocks = <&lcc AHBIX_CLK>,
574 <&lcc MI2S_OSR_CLK>,
575 <&lcc MI2S_BIT_CLK>;
576 clock-names = "ahbix-clk",
577 "mi2s-osr-clk",
578 "mi2s-bit-clk";
579 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
580 interrupt-names = "lpass-irq-lpaif";
581 reg = <0x28100000 0x10000>;
582 reg-names = "lpass-lpaif";
583 };
584
585 qfprom: qfprom@700000 {
586 compatible = "qcom,qfprom", "syscon";
587 reg = <0x700000 0x1000>;
588 #address-cells = <1>;
589 #size-cells = <1>;
590 status = "okay";
591 tsens_calib: calib@400 {
592 reg = <0x400 0xb>;
593 };
594 tsens_backup: backup@410 {
595 reg = <0x410 0xb>;
596 };
597 speedbin_efuse: speedbin@0c0 {
598 reg = <0x0c0 0x4>;
599 };
600 };
601
602 rpm@108000 {
603 compatible = "qcom,rpm-ipq8064";
604 reg = <0x108000 0x1000>;
605 qcom,ipc = <&l2cc 0x8 2>;
606
607 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
610 interrupt-names = "ack",
611 "err",
612 "wakeup";
613
614 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
615 clock-names = "ram";
616
617 #address-cells = <1>;
618 #size-cells = <0>;
619
620 rpmcc: clock-controller {
621 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
622 #clock-cells = <1>;
623 };
624
625 regulators {
626 compatible = "qcom,rpm-smb208-regulators";
627
628 smb208_s1a: s1a {
629 regulator-min-microvolt = <1050000>;
630 regulator-max-microvolt = <1150000>;
631
632 qcom,switch-mode-frequency = <1200000>;
633
634 };
635
636 smb208_s1b: s1b {
637 regulator-min-microvolt = <1050000>;
638 regulator-max-microvolt = <1150000>;
639
640 qcom,switch-mode-frequency = <1200000>;
641 };
642
643 smb208_s2a: s2a {
644 regulator-min-microvolt = < 800000>;
645 regulator-max-microvolt = <1250000>;
646
647 qcom,switch-mode-frequency = <1200000>;
648 };
649
650 smb208_s2b: s2b {
651 regulator-min-microvolt = < 800000>;
652 regulator-max-microvolt = <1250000>;
653
654 qcom,switch-mode-frequency = <1200000>;
655 };
656 };
657 };
658
659 rng@1a500000 {
660 compatible = "qcom,prng";
661 reg = <0x1a500000 0x200>;
662 clocks = <&gcc PRNG_CLK>;
663 clock-names = "core";
664 };
665
666 qcom_pinmux: pinmux@800000 {
667 compatible = "qcom,ipq8064-pinctrl";
668 reg = <0x800000 0x4000>;
669
670 gpio-controller;
671 #gpio-cells = <2>;
672 interrupt-controller;
673 #interrupt-cells = <2>;
674 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
675
676 pcie0_pins: pcie0_pinmux {
677 mux {
678 pins = "gpio3";
679 function = "pcie1_rst";
680 drive-strength = <12>;
681 bias-disable;
682 };
683 };
684
685 pcie1_pins: pcie1_pinmux {
686 mux {
687 pins = "gpio48";
688 function = "pcie2_rst";
689 drive-strength = <12>;
690 bias-disable;
691 };
692 };
693
694 pcie2_pins: pcie2_pinmux {
695 mux {
696 pins = "gpio63";
697 function = "pcie3_rst";
698 drive-strength = <12>;
699 bias-disable;
700 output-low;
701 };
702 };
703
704 spi_pins: spi_pins {
705 mux {
706 pins = "gpio18", "gpio19", "gpio21";
707 function = "gsbi5";
708 drive-strength = <10>;
709 bias-none;
710 };
711 };
712
713 leds_pins: leds_pins {
714 mux {
715 pins = "gpio7", "gpio8", "gpio9",
716 "gpio26", "gpio53";
717 function = "gpio";
718 drive-strength = <2>;
719 bias-pull-down;
720 output-low;
721 };
722 };
723
724 buttons_pins: buttons_pins {
725 mux {
726 pins = "gpio54";
727 drive-strength = <2>;
728 bias-pull-up;
729 };
730 };
731 };
732
733 intc: interrupt-controller@2000000 {
734 compatible = "qcom,msm-qgic2";
735 interrupt-controller;
736 #interrupt-cells = <3>;
737 reg = <0x02000000 0x1000>,
738 <0x02002000 0x1000>;
739 };
740
741 timer@200a000 {
742 compatible = "qcom,kpss-timer",
743 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
744 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
745 IRQ_TYPE_EDGE_RISING)>,
746 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
747 IRQ_TYPE_EDGE_RISING)>,
748 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
749 IRQ_TYPE_EDGE_RISING)>,
750 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
751 IRQ_TYPE_EDGE_RISING)>,
752 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
753 IRQ_TYPE_EDGE_RISING)>;
754 reg = <0x0200a000 0x100>;
755 clock-frequency = <25000000>,
756 <32768>;
757 clocks = <&sleep_clk>;
758 clock-names = "sleep";
759 cpu-offset = <0x80000>;
760 };
761
762 acpu0_aux: clock-controller@2088000 {
763 compatible = "qcom,kpss-acc-v1";
764 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
765 clock-output-names = "acpu0_aux";
766 };
767
768 acpu1_aux: clock-controller@2098000 {
769 compatible = "qcom,kpss-acc-v1";
770 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
771 clock-output-names = "acpu1_aux";
772 };
773
774 l2cc: clock-controller@2011000 {
775 compatible = "qcom,kpss-gcc", "syscon";
776 reg = <0x2011000 0x1000>;
777 clock-output-names = "acpu_l2_aux";
778 };
779
780 kraitcc: clock-controller {
781 compatible = "qcom,krait-cc-v1";
782 #clock-cells = <1>;
783 };
784
785 saw0: regulator@2089000 {
786 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
787 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
788 regulator;
789 };
790
791 saw1: regulator@2099000 {
792 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
793 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
794 regulator;
795 };
796
797 saw_l2: regulator@02012000 {
798 compatible = "qcom,saw2", "syscon";
799 reg = <0x02012000 0x1000>;
800 regulator;
801 };
802
803 sic_non_secure: sic-non-secure@12100000 {
804 compatible = "syscon";
805 reg = <0x12100000 0x10000>;
806 };
807
808 gsbi2: gsbi@12480000 {
809 compatible = "qcom,gsbi-v1.0.0";
810 cell-index = <2>;
811 reg = <0x12480000 0x100>;
812 clocks = <&gcc GSBI2_H_CLK>;
813 clock-names = "iface";
814 #address-cells = <1>;
815 #size-cells = <1>;
816 ranges;
817 status = "disabled";
818
819 syscon-tcsr = <&tcsr>;
820
821 uart2: serial@12490000 {
822 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
823 reg = <0x12490000 0x1000>,
824 <0x12480000 0x1000>;
825 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
827 clock-names = "core", "iface";
828 status = "disabled";
829 };
830
831 i2c@124a0000 {
832 compatible = "qcom,i2c-qup-v1.1.1";
833 reg = <0x124a0000 0x1000>;
834 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
835
836 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
837 clock-names = "core", "iface";
838 status = "disabled";
839
840 #address-cells = <1>;
841 #size-cells = <0>;
842 };
843
844 };
845
846 gsbi4: gsbi@16300000 {
847 compatible = "qcom,gsbi-v1.0.0";
848 cell-index = <4>;
849 reg = <0x16300000 0x100>;
850 clocks = <&gcc GSBI4_H_CLK>;
851 clock-names = "iface";
852 #address-cells = <1>;
853 #size-cells = <1>;
854 ranges;
855 status = "disabled";
856
857 syscon-tcsr = <&tcsr>;
858
859 gsbi4_serial: serial@16340000 {
860 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
861 reg = <0x16340000 0x1000>,
862 <0x16300000 0x1000>;
863 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
864 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
865 clock-names = "core", "iface";
866 status = "disabled";
867 };
868
869 i2c@16380000 {
870 compatible = "qcom,i2c-qup-v1.1.1";
871 reg = <0x16380000 0x1000>;
872 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
873
874 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
875 clock-names = "core", "iface";
876 status = "disabled";
877
878 #address-cells = <1>;
879 #size-cells = <0>;
880 };
881 };
882
883 gsbi5: gsbi@1a200000 {
884 compatible = "qcom,gsbi-v1.0.0";
885 cell-index = <5>;
886 reg = <0x1a200000 0x100>;
887 clocks = <&gcc GSBI5_H_CLK>;
888 clock-names = "iface";
889 #address-cells = <1>;
890 #size-cells = <1>;
891 ranges;
892 status = "disabled";
893
894 syscon-tcsr = <&tcsr>;
895
896 uart5: serial@1a240000 {
897 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
898 reg = <0x1a240000 0x1000>,
899 <0x1a200000 0x1000>;
900 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
901 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
902 clock-names = "core", "iface";
903 status = "disabled";
904 };
905
906 i2c@1a280000 {
907 compatible = "qcom,i2c-qup-v1.1.1";
908 reg = <0x1a280000 0x1000>;
909 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
910
911 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
912 clock-names = "core", "iface";
913 status = "disabled";
914
915 #address-cells = <1>;
916 #size-cells = <0>;
917 };
918
919 spi@1a280000 {
920 compatible = "qcom,spi-qup-v1.1.1";
921 reg = <0x1a280000 0x1000>;
922 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
923
924 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
925 clock-names = "core", "iface";
926 status = "disabled";
927
928 #address-cells = <1>;
929 #size-cells = <0>;
930 };
931 };
932
933 gsbi7: gsbi@16600000 {
934 status = "disabled";
935 compatible = "qcom,gsbi-v1.0.0";
936 cell-index = <7>;
937 reg = <0x16600000 0x100>;
938 clocks = <&gcc GSBI7_H_CLK>;
939 clock-names = "iface";
940 #address-cells = <1>;
941 #size-cells = <1>;
942 ranges;
943 syscon-tcsr = <&tcsr>;
944
945 gsbi7_serial: serial@16640000 {
946 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
947 reg = <0x16640000 0x1000>,
948 <0x16600000 0x1000>;
949 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
951 clock-names = "core", "iface";
952 status = "disabled";
953 };
954 };
955
956 sata_phy: sata-phy@1b400000 {
957 compatible = "qcom,ipq806x-sata-phy";
958 reg = <0x1b400000 0x200>;
959
960 clocks = <&gcc SATA_PHY_CFG_CLK>;
961 clock-names = "cfg";
962
963 #phy-cells = <0>;
964 status = "disabled";
965 };
966
967 sata: sata@29000000 {
968 compatible = "qcom,ipq806x-ahci", "generic-ahci";
969 reg = <0x29000000 0x180>;
970
971 ports-implemented = <0x1>;
972
973 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
974
975 clocks = <&gcc SFAB_SATA_S_H_CLK>,
976 <&gcc SATA_H_CLK>,
977 <&gcc SATA_A_CLK>,
978 <&gcc SATA_RXOOB_CLK>,
979 <&gcc SATA_PMALIVE_CLK>;
980 clock-names = "slave_face", "iface", "core",
981 "rxoob", "pmalive";
982
983 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
984 assigned-clock-rates = <100000000>, <100000000>;
985
986 phys = <&sata_phy>;
987 phy-names = "sata-phy";
988 status = "disabled";
989 };
990
991 qcom,ssbi@500000 {
992 compatible = "qcom,ssbi";
993 reg = <0x00500000 0x1000>;
994 qcom,controller-type = "pmic-arbiter";
995 };
996
997 gcc: clock-controller@900000 {
998 compatible = "qcom,gcc-ipq8064";
999 reg = <0x00900000 0x4000>;
1000 #clock-cells = <1>;
1001 #reset-cells = <1>;
1002 #power-domain-cells = <1>;
1003 };
1004
1005 tsens: thermal-sensor@900000 {
1006 compatible = "qcom,ipq8064-tsens";
1007 reg = <0x900000 0x3680>;
1008 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
1009 nvmem-cell-names = "calib", "calib_backup";
1010 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
1011 #thermal-sensor-cells = <1>;
1012 };
1013
1014 tcsr: syscon@1a400000 {
1015 compatible = "qcom,tcsr-ipq8064", "syscon";
1016 reg = <0x1a400000 0x100>;
1017 };
1018
1019 lcc: clock-controller@28000000 {
1020 compatible = "qcom,lcc-ipq8064";
1021 reg = <0x28000000 0x1000>;
1022 #clock-cells = <1>;
1023 #reset-cells = <1>;
1024 };
1025
1026 sfpb_mutex_block: syscon@1200600 {
1027 compatible = "syscon";
1028 reg = <0x01200600 0x100>;
1029 };
1030
1031 hs_phy_0: hs_phy_0 {
1032 compatible = "qcom,dwc3-hs-usb-phy";
1033 regmap = <&usb3_0>;
1034 clocks = <&gcc USB30_0_UTMI_CLK>;
1035 clock-names = "ref";
1036 #phy-cells = <0>;
1037 };
1038
1039 ss_phy_0: ss_phy_0 {
1040 compatible = "qcom,dwc3-ss-usb-phy";
1041 regmap = <&usb3_0>;
1042 clocks = <&gcc USB30_0_MASTER_CLK>;
1043 clock-names = "ref";
1044 #phy-cells = <0>;
1045 };
1046
1047 usb3_0: usb3@110f8800 {
1048 compatible = "qcom,dwc3", "syscon";
1049 #address-cells = <1>;
1050 #size-cells = <1>;
1051 reg = <0x110f8800 0x8000>;
1052 clocks = <&gcc USB30_0_MASTER_CLK>;
1053 clock-names = "core";
1054
1055 ranges;
1056
1057 resets = <&gcc USB30_0_MASTER_RESET>;
1058 reset-names = "master";
1059
1060 status = "disabled";
1061
1062 dwc3_0: dwc3@11000000 {
1063 compatible = "snps,dwc3";
1064 reg = <0x11000000 0xcd00>;
1065 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1066 phys = <&hs_phy_0>, <&ss_phy_0>;
1067 phy-names = "usb2-phy", "usb3-phy";
1068 dr_mode = "host";
1069 snps,dis_u3_susphy_quirk;
1070 };
1071 };
1072
1073 hs_phy_1: hs_phy_1 {
1074 compatible = "qcom,dwc3-hs-usb-phy";
1075 regmap = <&usb3_1>;
1076 clocks = <&gcc USB30_1_UTMI_CLK>;
1077 clock-names = "ref";
1078 #phy-cells = <0>;
1079 };
1080
1081 ss_phy_1: ss_phy_1 {
1082 compatible = "qcom,dwc3-ss-usb-phy";
1083 regmap = <&usb3_1>;
1084 clocks = <&gcc USB30_1_MASTER_CLK>;
1085 clock-names = "ref";
1086 #phy-cells = <0>;
1087 };
1088
1089 usb3_1: usb3@100f8800 {
1090 compatible = "qcom,dwc3", "syscon";
1091 #address-cells = <1>;
1092 #size-cells = <1>;
1093 reg = <0x100f8800 0x8000>;
1094 clocks = <&gcc USB30_1_MASTER_CLK>;
1095 clock-names = "core";
1096
1097 ranges;
1098
1099 resets = <&gcc USB30_1_MASTER_RESET>;
1100 reset-names = "master";
1101
1102 status = "disabled";
1103
1104 dwc3_1: dwc3@10000000 {
1105 compatible = "snps,dwc3";
1106 reg = <0x10000000 0xcd00>;
1107 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1108 phys = <&hs_phy_1>, <&ss_phy_1>;
1109 phy-names = "usb2-phy", "usb3-phy";
1110 dr_mode = "host";
1111 snps,dis_u3_susphy_quirk;
1112 };
1113 };
1114
1115 pcie0: pci@1b500000 {
1116 compatible = "qcom,pcie-ipq8064";
1117 reg = <0x1b500000 0x1000
1118 0x1b502000 0x80
1119 0x1b600000 0x100
1120 0x0ff00000 0x100000>;
1121 reg-names = "dbi", "elbi", "parf", "config";
1122 device_type = "pci";
1123 linux,pci-domain = <0>;
1124 bus-range = <0x00 0xff>;
1125 num-lanes = <1>;
1126 #address-cells = <3>;
1127 #size-cells = <2>;
1128
1129 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
1130 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
1131
1132 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1133 interrupt-names = "msi";
1134 #interrupt-cells = <1>;
1135 interrupt-map-mask = <0 0 0 0x7>;
1136 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1137 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1138 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1139 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1140
1141 clocks = <&gcc PCIE_A_CLK>,
1142 <&gcc PCIE_H_CLK>,
1143 <&gcc PCIE_PHY_CLK>,
1144 <&gcc PCIE_AUX_CLK>,
1145 <&gcc PCIE_ALT_REF_CLK>;
1146 clock-names = "core", "iface", "phy", "aux", "ref";
1147
1148 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1149 assigned-clock-rates = <100000000>;
1150
1151 resets = <&gcc PCIE_ACLK_RESET>,
1152 <&gcc PCIE_HCLK_RESET>,
1153 <&gcc PCIE_POR_RESET>,
1154 <&gcc PCIE_PCI_RESET>,
1155 <&gcc PCIE_PHY_RESET>,
1156 <&gcc PCIE_EXT_RESET>;
1157 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1158
1159 pinctrl-0 = <&pcie0_pins>;
1160 pinctrl-names = "default";
1161
1162 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1163
1164 phy-tx0-term-offset = <7>;
1165
1166 status = "disabled";
1167 };
1168
1169 pcie1: pci@1b700000 {
1170 compatible = "qcom,pcie-ipq8064";
1171 reg = <0x1b700000 0x1000
1172 0x1b702000 0x80
1173 0x1b800000 0x100
1174 0x31f00000 0x100000>;
1175 reg-names = "dbi", "elbi", "parf", "config";
1176 device_type = "pci";
1177 linux,pci-domain = <1>;
1178 bus-range = <0x00 0xff>;
1179 num-lanes = <1>;
1180 #address-cells = <3>;
1181 #size-cells = <2>;
1182
1183 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
1184 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1185
1186 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1187 interrupt-names = "msi";
1188 #interrupt-cells = <1>;
1189 interrupt-map-mask = <0 0 0 0x7>;
1190 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1191 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1192 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1193 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1194
1195 clocks = <&gcc PCIE_1_A_CLK>,
1196 <&gcc PCIE_1_H_CLK>,
1197 <&gcc PCIE_1_PHY_CLK>,
1198 <&gcc PCIE_1_AUX_CLK>,
1199 <&gcc PCIE_1_ALT_REF_CLK>;
1200 clock-names = "core", "iface", "phy", "aux", "ref";
1201
1202 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1203 assigned-clock-rates = <100000000>;
1204
1205 resets = <&gcc PCIE_1_ACLK_RESET>,
1206 <&gcc PCIE_1_HCLK_RESET>,
1207 <&gcc PCIE_1_POR_RESET>,
1208 <&gcc PCIE_1_PCI_RESET>,
1209 <&gcc PCIE_1_PHY_RESET>,
1210 <&gcc PCIE_1_EXT_RESET>;
1211 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1212
1213 pinctrl-0 = <&pcie1_pins>;
1214 pinctrl-names = "default";
1215
1216 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1217
1218 phy-tx0-term-offset = <7>;
1219
1220 status = "disabled";
1221 };
1222
1223 pcie2: pci@1b900000 {
1224 compatible = "qcom,pcie-ipq8064";
1225 reg = <0x1b900000 0x1000
1226 0x1b902000 0x80
1227 0x1ba00000 0x100
1228 0x35f00000 0x100000>;
1229 reg-names = "dbi", "elbi", "parf", "config";
1230 device_type = "pci";
1231 linux,pci-domain = <2>;
1232 bus-range = <0x00 0xff>;
1233 num-lanes = <1>;
1234 #address-cells = <3>;
1235 #size-cells = <2>;
1236
1237 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
1238 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1239
1240 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1241 interrupt-names = "msi";
1242 #interrupt-cells = <1>;
1243 interrupt-map-mask = <0 0 0 0x7>;
1244 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1245 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1246 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1247 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1248
1249 clocks = <&gcc PCIE_2_A_CLK>,
1250 <&gcc PCIE_2_H_CLK>,
1251 <&gcc PCIE_2_PHY_CLK>,
1252 <&gcc PCIE_2_AUX_CLK>,
1253 <&gcc PCIE_2_ALT_REF_CLK>;
1254 clock-names = "core", "iface", "phy", "aux", "ref";
1255
1256 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1257 assigned-clock-rates = <100000000>;
1258
1259 resets = <&gcc PCIE_2_ACLK_RESET>,
1260 <&gcc PCIE_2_HCLK_RESET>,
1261 <&gcc PCIE_2_POR_RESET>,
1262 <&gcc PCIE_2_PCI_RESET>,
1263 <&gcc PCIE_2_PHY_RESET>,
1264 <&gcc PCIE_2_EXT_RESET>;
1265 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1266
1267 pinctrl-0 = <&pcie2_pins>;
1268 pinctrl-names = "default";
1269
1270 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1271
1272 phy-tx0-term-offset = <7>;
1273
1274 status = "disabled";
1275 };
1276
1277 adm_dma: dma@18300000 {
1278 compatible = "qcom,adm";
1279 reg = <0x18300000 0x100000>;
1280 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1281 #dma-cells = <1>;
1282
1283 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1284 clock-names = "core", "iface";
1285
1286 resets = <&gcc ADM0_RESET>,
1287 <&gcc ADM0_PBUS_RESET>,
1288 <&gcc ADM0_C0_RESET>,
1289 <&gcc ADM0_C1_RESET>,
1290 <&gcc ADM0_C2_RESET>;
1291 reset-names = "clk", "pbus", "c0", "c1", "c2";
1292 qcom,ee = <0>;
1293
1294 status = "disabled";
1295 };
1296
1297 nand: nand@1ac00000 {
1298 compatible = "qcom,ipq806x-nand";
1299 reg = <0x1ac00000 0x800>;
1300
1301 clocks = <&gcc EBI2_CLK>,
1302 <&gcc EBI2_AON_CLK>;
1303 clock-names = "core", "aon";
1304
1305 dmas = <&adm_dma 3>;
1306 dma-names = "rxtx";
1307 qcom,cmd-crci = <15>;
1308 qcom,data-crci = <3>;
1309
1310 status = "disabled";
1311
1312 #address-cells = <1>;
1313 #size-cells = <0>;
1314 };
1315
1316 nss_common: syscon@03000000 {
1317 compatible = "syscon";
1318 reg = <0x03000000 0x0000FFFF>;
1319 };
1320
1321 qsgmii_csr: syscon@1bb00000 {
1322 compatible = "syscon";
1323 reg = <0x1bb00000 0x000001FF>;
1324 };
1325
1326 stmmac_axi_setup: stmmac-axi-config {
1327 snps,wr_osr_lmt = <7>;
1328 snps,rd_osr_lmt = <7>;
1329 snps,blen = <16 0 0 0 0 0 0>;
1330 };
1331
1332 gmac0: ethernet@37000000 {
1333 device_type = "network";
1334 compatible = "qcom,ipq806x-gmac";
1335 reg = <0x37000000 0x200000>;
1336 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1337 interrupt-names = "macirq";
1338
1339 snps,axi-config = <&stmmac_axi_setup>;
1340 snps,pbl = <32>;
1341 snps,aal = <1>;
1342
1343 qcom,nss-common = <&nss_common>;
1344 qcom,qsgmii-csr = <&qsgmii_csr>;
1345
1346 clocks = <&gcc GMAC_CORE1_CLK>;
1347 clock-names = "stmmaceth";
1348
1349 resets = <&gcc GMAC_CORE1_RESET>;
1350 reset-names = "stmmaceth";
1351
1352 status = "disabled";
1353 };
1354
1355 gmac1: ethernet@37200000 {
1356 device_type = "network";
1357 compatible = "qcom,ipq806x-gmac";
1358 reg = <0x37200000 0x200000>;
1359 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1360 interrupt-names = "macirq";
1361
1362 snps,axi-config = <&stmmac_axi_setup>;
1363 snps,pbl = <32>;
1364 snps,aal = <1>;
1365
1366 qcom,nss-common = <&nss_common>;
1367 qcom,qsgmii-csr = <&qsgmii_csr>;
1368
1369 clocks = <&gcc GMAC_CORE2_CLK>;
1370 clock-names = "stmmaceth";
1371
1372 resets = <&gcc GMAC_CORE2_RESET>;
1373 reset-names = "stmmaceth";
1374
1375 status = "disabled";
1376 };
1377
1378 gmac2: ethernet@37400000 {
1379 device_type = "network";
1380 compatible = "qcom,ipq806x-gmac";
1381 reg = <0x37400000 0x200000>;
1382 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1383 interrupt-names = "macirq";
1384
1385 snps,axi-config = <&stmmac_axi_setup>;
1386 snps,pbl = <32>;
1387 snps,aal = <1>;
1388
1389 qcom,nss-common = <&nss_common>;
1390 qcom,qsgmii-csr = <&qsgmii_csr>;
1391
1392 clocks = <&gcc GMAC_CORE3_CLK>;
1393 clock-names = "stmmaceth";
1394
1395 resets = <&gcc GMAC_CORE3_RESET>;
1396 reset-names = "stmmaceth";
1397
1398 status = "disabled";
1399 };
1400
1401 gmac3: ethernet@37600000 {
1402 device_type = "network";
1403 compatible = "qcom,ipq806x-gmac";
1404 reg = <0x37600000 0x200000>;
1405 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1406 interrupt-names = "macirq";
1407
1408 snps,axi-config = <&stmmac_axi_setup>;
1409 snps,pbl = <32>;
1410 snps,aal = <1>;
1411
1412 qcom,nss-common = <&nss_common>;
1413 qcom,qsgmii-csr = <&qsgmii_csr>;
1414
1415 clocks = <&gcc GMAC_CORE4_CLK>;
1416 clock-names = "stmmaceth";
1417
1418 resets = <&gcc GMAC_CORE4_RESET>;
1419 reset-names = "stmmaceth";
1420
1421 status = "disabled";
1422 };
1423
1424 /* Temporary fixed regulator */
1425 vsdcc_fixed: vsdcc-regulator {
1426 compatible = "regulator-fixed";
1427 regulator-name = "SDCC Power";
1428 regulator-min-microvolt = <3300000>;
1429 regulator-max-microvolt = <3300000>;
1430 regulator-always-on;
1431 };
1432
1433 sdcc1bam:dma@12402000 {
1434 compatible = "qcom,bam-v1.3.0";
1435 reg = <0x12402000 0x8000>;
1436 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1437 clocks = <&gcc SDC1_H_CLK>;
1438 clock-names = "bam_clk";
1439 #dma-cells = <1>;
1440 qcom,ee = <0>;
1441 };
1442
1443 sdcc3bam:dma@12182000 {
1444 compatible = "qcom,bam-v1.3.0";
1445 reg = <0x12182000 0x8000>;
1446 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1447 clocks = <&gcc SDC3_H_CLK>;
1448 clock-names = "bam_clk";
1449 #dma-cells = <1>;
1450 qcom,ee = <0>;
1451 };
1452
1453 amba {
1454 compatible = "arm,amba-bus";
1455 #address-cells = <1>;
1456 #size-cells = <1>;
1457 ranges;
1458 sdcc1: sdcc@12400000 {
1459 status = "disabled";
1460 compatible = "arm,pl18x", "arm,primecell";
1461 arm,primecell-periphid = <0x00051180>;
1462 reg = <0x12400000 0x2000>;
1463 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1464 interrupt-names = "cmd_irq";
1465 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1466 clock-names = "mclk", "apb_pclk";
1467 bus-width = <8>;
1468 max-frequency = <96000000>;
1469 non-removable;
1470 cap-sd-highspeed;
1471 cap-mmc-highspeed;
1472 vmmc-supply = <&vsdcc_fixed>;
1473 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1474 dma-names = "tx", "rx";
1475 };
1476
1477 sdcc3: sdcc@12180000 {
1478 compatible = "arm,pl18x", "arm,primecell";
1479 arm,primecell-periphid = <0x00051180>;
1480 status = "disabled";
1481 reg = <0x12180000 0x2000>;
1482 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1483 interrupt-names = "cmd_irq";
1484 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1485 clock-names = "mclk", "apb_pclk";
1486 bus-width = <8>;
1487 cap-sd-highspeed;
1488 cap-mmc-highspeed;
1489 max-frequency = <192000000>;
1490 #mmc-ddr-1_8v;
1491 sd-uhs-sdr104;
1492 sd-uhs-ddr50;
1493 vqmmc-supply = <&vsdcc_fixed>;
1494 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1495 dma-names = "tx", "rx";
1496 };
1497 };
1498 };
1499
1500 sfpb_mutex: sfpb-mutex {
1501 compatible = "qcom,sfpb-mutex";
1502 syscon = <&sfpb_mutex_block 4 4>;
1503
1504 #hwlock-cells = <1>;
1505 };
1506
1507 smem {
1508 compatible = "qcom,smem";
1509 memory-region = <&smem>;
1510 hwlocks = <&sfpb_mutex 3>;
1511 };
1512 };
Staging tree of Zoltan Herpai