target/linux/ipq806x/patches-4.19/0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B.patch

   1 From edff8f777c6321ca89bb950a382f409c4a126e28 Mon Sep 17 00:00:00 2001
   2 From: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
   3 Date: Thu, 15 Dec 2016 17:38:18 +0530
   4 Subject: pcie: Set PCIE MRRS and MPS to 256B
   5
   6 Set Max Read Request Size and Max Payload Size to 256 bytes,
   7 per chip team recommendation.
   8
   9 Change-Id: I097004be2ced1b3096ffc10c318aae0b2bb155e8
  10 Signed-off-by: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
  11 ---
  12  drivers/pci/host/pcie-qcom.c | 37 +++++++++++++++++++++++++++++++++++++
  13  1 file changed, 37 insertions(+)
  14
  15 (limited to 'drivers/pci/host/pcie-qcom.c')
  16
  17 --- a/drivers/pci/controller/dwc/pcie-qcom.c
  18 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
  19 @@ -124,6 +124,14 @@
  20
  21  #define PCIE20_LNK_CONTROL2_LINK_STATUS2        0xA0
  22
  23 +#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
  24 +#define __mask(a, b)   (((1 << ((a) + 1)) - 1) & ~((1 << (b)) - 1))
  25 +#define PCIE20_DEV_CAS                 0x78
  26 +#define PCIE20_MRRS_MASK               __mask(14, 12)
  27 +#define PCIE20_MRRS(x)                 __set(x, 14, 12)
  28 +#define PCIE20_MPS_MASK                        __mask(7, 5)
  29 +#define PCIE20_MPS(x)                  __set(x, 7, 5)
  30 +
  31  #define QCOM_PCIE_2_1_0_MAX_SUPPLY     3
  32  struct qcom_pcie_resources_2_1_0 {
  33         struct clk *iface_clk;
  34 @@ -1475,6 +1483,35 @@ err_pm_runtime_put:
  35         return ret;
  36  }
  37
  38 +static void qcom_pcie_fixup_final(struct pci_dev *dev)
  39 +{
  40 +       int cap, err;
  41 +       u16 ctl, reg_val;
  42 +
  43 +       cap = pci_pcie_cap(dev);
  44 +       if (!cap)
  45 +               return;
  46 +
  47 +       err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
  48 +
  49 +       if (err)
  50 +               return;
  51 +
  52 +       reg_val = ctl;
  53 +
  54 +       if (((reg_val & PCIE20_MRRS_MASK) >> 12) > 1)
  55 +               reg_val = (reg_val & ~(PCIE20_MRRS_MASK)) | PCIE20_MRRS(0x1);
  56 +
  57 +       if (((ctl & PCIE20_MPS_MASK) >> 5) > 1)
  58 +               reg_val = (reg_val & ~(PCIE20_MPS_MASK)) | PCIE20_MPS(0x1);
  59 +
  60 +       err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, reg_val);
  61 +
  62 +       if (err)
  63 +               pr_err("pcie config write failed %d\n", err);
  64 +}
  65 +DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, qcom_pcie_fixup_final);
  66 +
  67  static const struct of_device_id qcom_pcie_match[] = {
  68         { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
  69         { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },