target/linux/ipq806x/patches/0036-pinctrl-msm-Correct-interrupt-code-for-TLMM-v2.patch

   1 From 32787a9bba5a1ebeea891fd7aab954e6d344892a Mon Sep 17 00:00:00 2001
   2 From: Bjorn Andersson <bjorn.andersson@sonymobile.com>
   3 Date: Mon, 31 Mar 2014 14:49:54 -0700
   4 Subject: [PATCH 036/182] pinctrl: msm: Correct interrupt code for TLMM v2
   5
   6 Acking interrupts are done differently between on v2 and v3, so add an extra
   7 attribute to the pingroup struct to let the platform definitions control this.
   8 Also make sure to start dual edge detection by detecting the rising edge.
   9
  10 Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
  11 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  12 ---
  13  drivers/pinctrl/pinctrl-msm.c |    6 +++++-
  14  drivers/pinctrl/pinctrl-msm.h |    1 +
  15  2 files changed, 6 insertions(+), 1 deletion(-)
  16
  17 --- a/drivers/pinctrl/pinctrl-msm.c
  18 +++ b/drivers/pinctrl/pinctrl-msm.c
  19 @@ -665,7 +665,10 @@ static void msm_gpio_irq_ack(struct irq_
  20         spin_lock_irqsave(&pctrl->lock, flags);
  21
  22         val = readl(pctrl->regs + g->intr_status_reg);
  23 -       val &= ~BIT(g->intr_status_bit);
  24 +       if (g->intr_ack_high)
  25 +               val |= BIT(g->intr_status_bit);
  26 +       else
  27 +               val &= ~BIT(g->intr_status_bit);
  28         writel(val, pctrl->regs + g->intr_status_reg);
  29
  30         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
  31 @@ -744,6 +747,7 @@ static int msm_gpio_irq_set_type(struct
  32                         break;
  33                 case IRQ_TYPE_EDGE_BOTH:
  34                         val |= BIT(g->intr_detection_bit);
  35 +                       val |= BIT(g->intr_polarity_bit);
  36                         break;
  37                 case IRQ_TYPE_LEVEL_LOW:
  38                         break;
  39 --- a/drivers/pinctrl/pinctrl-msm.h
  40 +++ b/drivers/pinctrl/pinctrl-msm.h
  41 @@ -84,6 +84,7 @@ struct msm_pingroup {
  42
  43         unsigned intr_enable_bit:5;
  44         unsigned intr_status_bit:5;
  45 +       unsigned intr_ack_high:1;
  46
  47         unsigned intr_target_bit:5;
  48         unsigned intr_raw_status_bit:5;