target/linux/ipq806x/patches/0179-spi-qup-Add-DMA-capabilities.patch

   1 From 8322bafdcee1d7eaf15540ff013415bff1eacb28 Mon Sep 17 00:00:00 2001
   2 From: Andy Gross <agross@codeaurora.org>
   3 Date: Thu, 26 Jun 2014 10:50:24 -0500
   4 Subject: [PATCH 179/182] spi: qup: Add DMA capabilities
   5
   6 This patch adds DMA capabilities to the spi-qup driver.  If DMA channels are
   7 present, the QUP will use DMA instead of block mode for transfers to/from SPI
   8 peripherals for transactions larger greater than the length of a block.
   9
  10 Signed-off-by: Andy Gross <agross@codeaurora.org>
  11 ---
  12  drivers/spi/spi-qup.c |  361 ++++++++++++++++++++++++++++++++++++++++++++++---
  13  1 file changed, 340 insertions(+), 21 deletions(-)
  14
  15 diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
  16 index c137226..28754ae 100644
  17 --- a/drivers/spi/spi-qup.c
  18 +++ b/drivers/spi/spi-qup.c
  19 @@ -22,6 +22,8 @@
  20  #include <linux/platform_device.h>
  21  #include <linux/pm_runtime.h>
  22  #include <linux/spi/spi.h>
  23 +#include <linux/dmaengine.h>
  24 +#include <linux/dma-mapping.h>
  25
  26  #define QUP_CONFIG                     0x0000
  27  #define QUP_STATE                      0x0004
  28 @@ -116,6 +118,8 @@
  29
  30  #define SPI_NUM_CHIPSELECTS            4
  31
  32 +#define SPI_MAX_XFER                   (SZ_64K - 64)
  33 +
  34  /* high speed mode is when bus rate is greater then 26MHz */
  35  #define SPI_HS_MIN_RATE                        26000000
  36  #define SPI_MAX_RATE                   50000000
  37 @@ -143,6 +147,14 @@ struct spi_qup {
  38         int                     tx_bytes;
  39         int                     rx_bytes;
  40         int                     qup_v1;
  41 +       int                     use_dma;
  42 +
  43 +       struct dma_chan         *rx_chan;
  44 +       struct dma_slave_config rx_conf;
  45 +       struct dma_chan         *tx_chan;
  46 +       struct dma_slave_config tx_conf;
  47 +       void *dummy;
  48 +       atomic_t                dma_outstanding;
  49  };
  50
  51
  52 @@ -266,6 +278,221 @@ static void spi_qup_fifo_write(struct spi_qup *controller,
  53         }
  54  }
  55
  56 +static void qup_dma_callback(void *data)
  57 +{
  58 +       struct spi_qup *controller = data;
  59 +
  60 +       if (atomic_dec_and_test(&controller->dma_outstanding))
  61 +               complete(&controller->done);
  62 +}
  63 +
  64 +static int spi_qup_do_dma(struct spi_qup *controller, struct spi_transfer *xfer)
  65 +{
  66 +       struct dma_async_tx_descriptor *rxd, *txd;
  67 +       dma_cookie_t rx_cookie, tx_cookie;
  68 +       u32 xfer_len, rx_align = 0, tx_align = 0, n_words;
  69 +       struct scatterlist tx_sg[2], rx_sg[2];
  70 +       int ret = 0;
  71 +       u32 bytes_to_xfer = xfer->len;
  72 +       u32 offset = 0;
  73 +       u32 rx_nents = 0, tx_nents = 0;
  74 +       dma_addr_t rx_dma = 0, tx_dma = 0, rx_dummy_dma = 0, tx_dummy_dma = 0;
  75 +
  76 +
  77 +       if (xfer->rx_buf) {
  78 +               rx_dma = dma_map_single(controller->dev, xfer->rx_buf,
  79 +                       xfer->len, DMA_FROM_DEVICE);
  80 +
  81 +               if (dma_mapping_error(controller->dev, rx_dma)) {
  82 +                       ret = -ENOMEM;
  83 +                       return ret;
  84 +               }
  85 +
  86 +               /* check to see if we need dummy buffer for leftover bytes */
  87 +               rx_align = xfer->len % controller->in_blk_sz;
  88 +               if (rx_align) {
  89 +                       rx_dummy_dma = dma_map_single(controller->dev,
  90 +                               controller->dummy, controller->in_fifo_sz,
  91 +                               DMA_FROM_DEVICE);
  92 +
  93 +                       if (dma_mapping_error(controller->dev, rx_dummy_dma)) {
  94 +                               ret = -ENOMEM;
  95 +                               goto err_map_rx_dummy;
  96 +                       }
  97 +               }
  98 +       }
  99 +
 100 +       if (xfer->tx_buf) {
 101 +               tx_dma = dma_map_single(controller->dev,
 102 +                       (void *)xfer->tx_buf, xfer->len, DMA_TO_DEVICE);
 103 +
 104 +               if (dma_mapping_error(controller->dev, tx_dma)) {
 105 +                       ret = -ENOMEM;
 106 +                       goto err_map_tx;
 107 +               }
 108 +
 109 +               /* check to see if we need dummy buffer for leftover bytes */
 110 +               tx_align = xfer->len % controller->out_blk_sz;
 111 +               if (tx_align) {
 112 +                       memcpy(controller->dummy + SZ_1K,
 113 +                               xfer->tx_buf + xfer->len - tx_align,
 114 +                               tx_align);
 115 +                       memset(controller->dummy + SZ_1K + tx_align, 0,
 116 +                               controller->out_blk_sz - tx_align);
 117 +
 118 +                       tx_dummy_dma = dma_map_single(controller->dev,
 119 +                               controller->dummy + SZ_1K,
 120 +                               controller->out_blk_sz, DMA_TO_DEVICE);
 121 +
 122 +                       if (dma_mapping_error(controller->dev, tx_dummy_dma)) {
 123 +                               ret = -ENOMEM;
 124 +                               goto err_map_tx_dummy;
 125 +                       }
 126 +               }
 127 +       }
 128 +
 129 +       atomic_set(&controller->dma_outstanding, 0);
 130 +
 131 +       while (bytes_to_xfer > 0) {
 132 +               xfer_len = min_t(u32, bytes_to_xfer, SPI_MAX_XFER);
 133 +               n_words = DIV_ROUND_UP(xfer_len, controller->w_size);
 134 +
 135 +               /* write out current word count to controller */
 136 +               writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
 137 +               writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
 138 +
 139 +               reinit_completion(&controller->done);
 140 +
 141 +               if (xfer->tx_buf) {
 142 +                       /* recalc align for each transaction */
 143 +                       tx_align = xfer_len % controller->out_blk_sz;
 144 +
 145 +                       if (tx_align)
 146 +                               tx_nents = 2;
 147 +                       else
 148 +                               tx_nents = 1;
 149 +
 150 +                       /* initialize scatterlists */
 151 +                       sg_init_table(tx_sg, tx_nents);
 152 +                       sg_dma_len(&tx_sg[0]) = xfer_len - tx_align;
 153 +                       sg_dma_address(&tx_sg[0]) = tx_dma + offset;
 154 +
 155 +                       /* account for non block size transfer */
 156 +                       if (tx_align) {
 157 +                               sg_dma_len(&tx_sg[1]) = controller->out_blk_sz;
 158 +                               sg_dma_address(&tx_sg[1]) = tx_dummy_dma;
 159 +                       }
 160 +
 161 +                       txd = dmaengine_prep_slave_sg(controller->tx_chan,
 162 +                                       tx_sg, tx_nents, DMA_MEM_TO_DEV, 0);
 163 +                       if (!txd) {
 164 +                               ret = -ENOMEM;
 165 +                               goto err_unmap;
 166 +                       }
 167 +
 168 +                       atomic_inc(&controller->dma_outstanding);
 169 +
 170 +                       txd->callback = qup_dma_callback;
 171 +                       txd->callback_param = controller;
 172 +
 173 +                       tx_cookie = dmaengine_submit(txd);
 174 +
 175 +                       dma_async_issue_pending(controller->tx_chan);
 176 +               }
 177 +
 178 +               if (xfer->rx_buf) {
 179 +                       /* recalc align for each transaction */
 180 +                       rx_align = xfer_len % controller->in_blk_sz;
 181 +
 182 +                       if (rx_align)
 183 +                               rx_nents = 2;
 184 +                       else
 185 +                               rx_nents = 1;
 186 +
 187 +                       /* initialize scatterlists */
 188 +                       sg_init_table(rx_sg, rx_nents);
 189 +                       sg_dma_address(&rx_sg[0]) = rx_dma + offset;
 190 +                       sg_dma_len(&rx_sg[0]) = xfer_len - rx_align;
 191 +
 192 +                       /* account for non block size transfer */
 193 +                       if (rx_align) {
 194 +                               sg_dma_len(&rx_sg[1]) = controller->in_blk_sz;
 195 +                               sg_dma_address(&rx_sg[1]) = rx_dummy_dma;
 196 +                       }
 197 +
 198 +                       rxd = dmaengine_prep_slave_sg(controller->rx_chan,
 199 +                                       rx_sg, rx_nents, DMA_DEV_TO_MEM, 0);
 200 +                       if (!rxd) {
 201 +                               ret = -ENOMEM;
 202 +                               goto err_unmap;
 203 +                       }
 204 +
 205 +                       atomic_inc(&controller->dma_outstanding);
 206 +
 207 +                       rxd->callback = qup_dma_callback;
 208 +                       rxd->callback_param = controller;
 209 +
 210 +                       rx_cookie = dmaengine_submit(rxd);
 211 +
 212 +                       dma_async_issue_pending(controller->rx_chan);
 213 +               }
 214 +
 215 +               if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
 216 +                       dev_warn(controller->dev, "cannot set EXECUTE state\n");
 217 +                       goto err_unmap;
 218 +               }
 219 +
 220 +               if (!wait_for_completion_timeout(&controller->done,
 221 +                       msecs_to_jiffies(1000))) {
 222 +                       ret = -ETIMEDOUT;
 223 +
 224 +                       /* clear out all the DMA transactions */
 225 +                       if (xfer->tx_buf)
 226 +                               dmaengine_terminate_all(controller->tx_chan);
 227 +                       if (xfer->rx_buf)
 228 +                               dmaengine_terminate_all(controller->rx_chan);
 229 +
 230 +                       goto err_unmap;
 231 +               }
 232 +
 233 +               if (rx_align)
 234 +                       memcpy(xfer->rx_buf + offset + xfer->len - rx_align,
 235 +                               controller->dummy, rx_align);
 236 +
 237 +               /* adjust remaining bytes to transfer */
 238 +               bytes_to_xfer -= xfer_len;
 239 +               offset += xfer_len;
 240 +
 241 +
 242 +               /* reset mini-core state so we can program next transaction */
 243 +               if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
 244 +                       dev_err(controller->dev, "cannot set RESET state\n");
 245 +                       goto err_unmap;
 246 +               }
 247 +       }
 248 +
 249 +       ret = 0;
 250 +
 251 +err_unmap:
 252 +       if (tx_align)
 253 +               dma_unmap_single(controller->dev, tx_dummy_dma,
 254 +                       controller->out_fifo_sz, DMA_TO_DEVICE);
 255 +err_map_tx_dummy:
 256 +       if (xfer->tx_buf)
 257 +               dma_unmap_single(controller->dev, tx_dma, xfer->len,
 258 +                       DMA_TO_DEVICE);
 259 +err_map_tx:
 260 +       if (rx_align)
 261 +               dma_unmap_single(controller->dev, rx_dummy_dma,
 262 +                       controller->in_fifo_sz, DMA_FROM_DEVICE);
 263 +err_map_rx_dummy:
 264 +       if (xfer->rx_buf)
 265 +               dma_unmap_single(controller->dev, rx_dma, xfer->len,
 266 +                       DMA_FROM_DEVICE);
 267 +
 268 +       return ret;
 269 +}
 270 +
 271  static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
 272  {
 273         struct spi_qup *controller = dev_id;
 274 @@ -315,11 +542,13 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
 275                 error = -EIO;
 276         }
 277
 278 -       if (opflags & QUP_OP_IN_SERVICE_FLAG)
 279 -               spi_qup_fifo_read(controller, xfer);
 280 +       if (!controller->use_dma) {
 281 +               if (opflags & QUP_OP_IN_SERVICE_FLAG)
 282 +                       spi_qup_fifo_read(controller, xfer);
 283
 284 -       if (opflags & QUP_OP_OUT_SERVICE_FLAG)
 285 -               spi_qup_fifo_write(controller, xfer);
 286 +               if (opflags & QUP_OP_OUT_SERVICE_FLAG)
 287 +                       spi_qup_fifo_write(controller, xfer);
 288 +       }
 289
 290         spin_lock_irqsave(&controller->lock, flags);
 291         controller->error = error;
 292 @@ -339,6 +568,8 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
 293         struct spi_qup *controller = spi_master_get_devdata(spi->master);
 294         u32 config, iomode, mode;
 295         int ret, n_words, w_size;
 296 +       size_t dma_align = dma_get_cache_alignment();
 297 +       u32 dma_available = 0;
 298
 299         if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
 300                 dev_err(controller->dev, "too big size for loopback %d > %d\n",
 301 @@ -367,6 +598,13 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
 302         n_words = xfer->len / w_size;
 303         controller->w_size = w_size;
 304
 305 +       if (controller->rx_chan &&
 306 +               IS_ALIGNED((size_t)xfer->tx_buf, dma_align) &&
 307 +               IS_ALIGNED((size_t)xfer->rx_buf, dma_align) &&
 308 +               !is_vmalloc_addr(xfer->tx_buf) &&
 309 +               !is_vmalloc_addr(xfer->rx_buf))
 310 +               dma_available = 1;
 311 +
 312         if (n_words <= (controller->in_fifo_sz / sizeof(u32))) {
 313                 mode = QUP_IO_M_MODE_FIFO;
 314                 writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
 315 @@ -374,19 +612,30 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
 316                 /* must be zero for FIFO */
 317                 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
 318                 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
 319 -       } else {
 320 +               controller->use_dma = 0;
 321 +       } else if (!dma_available) {
 322                 mode = QUP_IO_M_MODE_BLOCK;
 323                 writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
 324                 writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
 325                 /* must be zero for BLOCK and BAM */
 326                 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 327                 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 328 +               controller->use_dma = 0;
 329 +       } else {
 330 +               mode = QUP_IO_M_MODE_DMOV;
 331 +               writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 332 +               writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 333 +               controller->use_dma = 1;
 334         }
 335
 336         iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
 337         /* Set input and output transfer mode */
 338         iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
 339 -       iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
 340 +       if (!controller->use_dma)
 341 +               iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
 342 +       else
 343 +               iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN;
 344 +
 345         iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
 346         iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
 347
 348 @@ -419,11 +668,20 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
 349         config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
 350         config |= xfer->bits_per_word - 1;
 351         config |= QUP_CONFIG_SPI_MODE;
 352 +
 353 +       if (controller->use_dma) {
 354 +               if (!xfer->tx_buf)
 355 +                       config |= QUP_CONFIG_NO_OUTPUT;
 356 +               if (!xfer->rx_buf)
 357 +                       config |= QUP_CONFIG_NO_INPUT;
 358 +       }
 359 +
 360         writel_relaxed(config, controller->base + QUP_CONFIG);
 361
 362         /* only write to OPERATIONAL_MASK when register is present */
 363         if (!controller->qup_v1)
 364                 writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK);
 365 +
 366         return 0;
 367  }
 368
 369 @@ -452,26 +710,32 @@ static int spi_qup_transfer_one(struct spi_master *master,
 370         controller->tx_bytes = 0;
 371         spin_unlock_irqrestore(&controller->lock, flags);
 372
 373 -       if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
 374 -               dev_warn(controller->dev, "cannot set RUN state\n");
 375 -               goto exit;
 376 -       }
 377 +       if (controller->use_dma) {
 378 +               ret = spi_qup_do_dma(controller, xfer);
 379 +       } else {
 380 +               if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
 381 +                       dev_warn(controller->dev, "cannot set RUN state\n");
 382 +                       goto exit;
 383 +               }
 384
 385 -       if (spi_qup_set_state(controller, QUP_STATE_PAUSE)) {
 386 -               dev_warn(controller->dev, "cannot set PAUSE state\n");
 387 -               goto exit;
 388 -       }
 389 +               if (spi_qup_set_state(controller, QUP_STATE_PAUSE)) {
 390 +                       dev_warn(controller->dev, "cannot set PAUSE state\n");
 391 +                       goto exit;
 392 +               }
 393
 394 -       spi_qup_fifo_write(controller, xfer);
 395 +               spi_qup_fifo_write(controller, xfer);
 396
 397 -       if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
 398 -               dev_warn(controller->dev, "cannot set EXECUTE state\n");
 399 -               goto exit;
 400 -       }
 401 +               if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
 402 +                       dev_warn(controller->dev, "cannot set EXECUTE state\n");
 403 +                       goto exit;
 404 +               }
 405
 406 -       if (!wait_for_completion_timeout(&controller->done, timeout))
 407 -               ret = -ETIMEDOUT;
 408 +               if (!ret && !wait_for_completion_timeout(&controller->done,
 409 +                               timeout))
 410 +                       ret = -ETIMEDOUT;
 411 +       }
 412  exit:
 413 +
 414         spi_qup_set_state(controller, QUP_STATE_RESET);
 415         spin_lock_irqsave(&controller->lock, flags);
 416         controller->xfer = NULL;
 417 @@ -553,6 +817,7 @@ static int spi_qup_probe(struct platform_device *pdev)
 418         master->transfer_one = spi_qup_transfer_one;
 419         master->dev.of_node = pdev->dev.of_node;
 420         master->auto_runtime_pm = true;
 421 +       master->dma_alignment = dma_get_cache_alignment();
 422
 423         platform_set_drvdata(pdev, master);
 424
 425 @@ -612,6 +877,55 @@ static int spi_qup_probe(struct platform_device *pdev)
 426         writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN,
 427                        base + SPI_ERROR_FLAGS_EN);
 428
 429 +       /* allocate dma resources, if available */
 430 +       controller->rx_chan = dma_request_slave_channel(&pdev->dev, "rx");
 431 +       if (controller->rx_chan) {
 432 +               controller->tx_chan =
 433 +                       dma_request_slave_channel(&pdev->dev, "tx");
 434 +
 435 +               if (!controller->tx_chan) {
 436 +                       dev_err(&pdev->dev, "Failed to allocate dma tx chan");
 437 +                       dma_release_channel(controller->rx_chan);
 438 +               }
 439 +
 440 +               /* set DMA parameters */
 441 +               controller->rx_conf.device_fc = 1;
 442 +               controller->rx_conf.src_addr = res->start + QUP_INPUT_FIFO;
 443 +               controller->rx_conf.src_maxburst = controller->in_blk_sz;
 444 +
 445 +               controller->tx_conf.device_fc = 1;
 446 +               controller->tx_conf.dst_addr = res->start + QUP_OUTPUT_FIFO;
 447 +               controller->tx_conf.dst_maxburst = controller->out_blk_sz;
 448 +
 449 +               if (dmaengine_slave_config(controller->rx_chan,
 450 +                               &controller->rx_conf)) {
 451 +                       dev_err(&pdev->dev, "failed to configure RX channel\n");
 452 +
 453 +                       dma_release_channel(controller->rx_chan);
 454 +                       dma_release_channel(controller->tx_chan);
 455 +                       controller->tx_chan = NULL;
 456 +                       controller->rx_chan = NULL;
 457 +               } else if (dmaengine_slave_config(controller->tx_chan,
 458 +                               &controller->tx_conf)) {
 459 +                       dev_err(&pdev->dev, "failed to configure TX channel\n");
 460 +
 461 +                       dma_release_channel(controller->rx_chan);
 462 +                       dma_release_channel(controller->tx_chan);
 463 +                       controller->tx_chan = NULL;
 464 +                       controller->rx_chan = NULL;
 465 +               }
 466 +
 467 +               controller->dummy = devm_kmalloc(controller->dev, PAGE_SIZE,
 468 +                       GFP_KERNEL);
 469 +
 470 +               if (!controller->dummy) {
 471 +                       dma_release_channel(controller->rx_chan);
 472 +                       dma_release_channel(controller->tx_chan);
 473 +                       controller->tx_chan = NULL;
 474 +                       controller->rx_chan = NULL;
 475 +               }
 476 +       }
 477 +
 478         /* if earlier version of the QUP, disable INPUT_OVERRUN */
 479         if (controller->qup_v1)
 480                 writel_relaxed(QUP_ERROR_OUTPUT_OVER_RUN |
 481 @@ -730,6 +1044,11 @@ static int spi_qup_remove(struct platform_device *pdev)
 482         if (ret)
 483                 return ret;
 484
 485 +       if (controller->rx_chan)
 486 +               dma_release_channel(controller->rx_chan);
 487 +       if (controller->tx_chan)
 488 +               dma_release_channel(controller->tx_chan);
 489 +
 490         clk_disable_unprepare(controller->cclk);
 491         clk_disable_unprepare(controller->iclk);
 492
 493 --
 494 1.7.10.4
 495