12af82b8ceaf87db146180f6e13bda553f1469be
[openwrt/staging/wigyori.git] / target / linux / lantiq / files-5.4 / arch / mips / boot / dts / lantiq / ar9.dtsi
1 #include <dt-bindings/gpio/gpio.h>
2
3 / {
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "lantiq,xway", "lantiq,ar9";
7
8 aliases {
9 serial0 = &asc1;
10 };
11
12 chosen {
13 stdout-path = "serial0:115200n8";
14 };
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 compatible = "mips,mips34K";
22 reg = <0>;
23 };
24 };
25
26 reboot {
27 compatible = "syscon-reboot";
28
29 regmap = <&rcu0>;
30 offset = <0x10>;
31 mask = <0x40000000>;
32 };
33
34 biu@1f800000 {
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "lantiq,biu", "simple-bus";
38 reg = <0x1f800000 0x800000>;
39 ranges = <0x0 0x1f800000 0x7fffff>;
40
41 icu0: icu@80200 {
42 #interrupt-cells = <1>;
43 interrupt-controller;
44 compatible = "lantiq,icu";
45 reg = <0x80200 0x28
46 0x80228 0x28
47 0x80250 0x28
48 0x80278 0x28
49 0x802a0 0x28>;
50 };
51
52 watchdog@803f0 {
53 compatible = "lantiq,xrx100-wdt", "lantiq,xrx100-wdt";
54 reg = <0x803f0 0x10>;
55
56 regmap = <&rcu0>;
57 };
58 };
59
60 sram@1f000000 {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 compatible = "lantiq,sram", "simple-bus";
64 reg = <0x1f000000 0x800000>;
65 ranges = <0x0 0x1f000000 0x7fffff>;
66
67 eiu0: eiu@101000 {
68 #interrupt-cells = <1>;
69 interrupt-controller;
70 compatible = "lantiq,eiu-xway";
71 reg = <0x101000 0x1000>;
72 interrupt-parent = <&icu0>;
73 lantiq,eiu-irqs = <166 135 66 40 41 42>;
74 };
75
76 pmu0: pmu@102000 {
77 compatible = "lantiq,pmu-xway";
78 reg = <0x102000 0x1000>;
79 };
80
81 cgu0: cgu@103000 {
82 compatible = "lantiq,cgu-xway";
83 reg = <0x103000 0x1000>;
84 #clock-cells = <1>;
85 };
86
87 rcu0: rcu@203000 {
88 #address-cells = <1>;
89 #size-cells = <1>;
90 compatible = "lantiq,xrx100-rcu", "simple-mfd", "syscon";
91 reg = <0x203000 0x1000>;
92 ranges = <0x0 0x203000 0x100>;
93 big-endian;
94
95 reset: reset-controller@10 {
96 compatible = "lantiq,xrx100-reset", "lantiq,danube-reset";
97 reg = <0x10 4>, <0x14 4>;
98
99 #reset-cells = <2>;
100 };
101
102 usb_phy0: usb2-phy@18 {
103 compatible = "lantiq,xrx100-usb2-phy";
104 reg = <0x18 4>;
105 status = "disabled";
106
107 resets = <&reset 4 4>;
108 reset-names = "ctrl";
109 #phy-cells = <0>;
110 };
111
112 usb_phy1: usb2-phy@34 {
113 compatible = "lantiq,xrx100-usb2-phy";
114 reg = <0x34 4>;
115 status = "disabled";
116
117 resets = <&reset 28 28>;
118 reset-names = "ctrl";
119 #phy-cells = <0>;
120 };
121 };
122 };
123
124 fpi@10000000 {
125 #address-cells = <1>;
126 #size-cells = <1>;
127 compatible = "lantiq,fpi", "simple-bus";
128 ranges = <0x0 0x10000000 0xeefffff>;
129 reg = <0x10000000 0xef00000>;
130
131 localbus: localbus@0 {
132 #address-cells = <2>;
133 #size-cells = <1>;
134 ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
135 1 0 0x4000000 0x4000010>; /* addsel1 */
136 compatible = "lantiq,localbus", "simple-bus";
137 };
138
139 gptu@e100a00 {
140 compatible = "lantiq,gptu-xway";
141 reg = <0xe100a00 0x100>;
142 interrupt-parent = <&icu0>;
143 interrupts = <126 127 128 129 130 131>;
144 };
145
146 asc0: serial@e100400 {
147 compatible = "lantiq,asc";
148 reg = <0xe100400 0x400>;
149 interrupt-parent = <&icu0>;
150 interrupts = <104 105 106>;
151 status = "disabled";
152 };
153
154 spi: spi@e100800 {
155 compatible = "lantiq,xrx100-spi";
156 reg = <0xe100800 0x100>;
157 interrupt-parent = <&icu0>;
158 interrupts = <22 23 24>;
159 interrupt-names = "spi_rx", "spi_tx", "spi_err",
160 "spi_frm";
161 #address-cells = <1>;
162 #size-cells = <0>;
163 pinctrl-names = "default";
164 pinctrl-0 = <&spi_pins>, <&spi_cs4_pins>;
165 status = "disabled";
166 };
167
168 gpio: pinmux@e100b10 {
169 compatible = "lantiq,xrx100-pinctrl";
170 #gpio-cells = <2>;
171 gpio-controller;
172 reg = <0xe100b10 0xa0>;
173
174 mdio_pins: mdio {
175 mux {
176 lantiq,groups = "mdio";
177 lantiq,function = "mdio";
178 };
179 };
180
181 nand_pins: nand {
182 mux-0 {
183 lantiq,groups = "nand cle", "nand ale",
184 "nand rd";
185 lantiq,function = "ebu";
186 lantiq,output = <1>;
187 lantiq,open-drain = <0>;
188 lantiq,pull = <0>;
189 };
190 mux-1 {
191 lantiq,groups = "nand rdy";
192 lantiq,function = "ebu";
193 lantiq,output = <0>;
194 lantiq,pull = <2>;
195 };
196 };
197
198 nand_cs1_pins: nand-cs1 {
199 mux {
200 lantiq,groups = "nand cs1";
201 lantiq,function = "ebu";
202 lantiq,open-drain = <0>;
203 lantiq,pull = <0>;
204 };
205 };
206
207 pci_gnt1_pins: pci-gnt1 {
208 mux {
209 lantiq,groups = "gnt1";
210 lantiq,function = "pci";
211 lantiq,output = <1>;
212 lantiq,open-drain = <0>;
213 lantiq,pull = <0>;
214 };
215 };
216
217 pci_gnt2_pins: pci-gnt2 {
218 mux {
219 lantiq,groups = "gnt2";
220 lantiq,function = "pci";
221 lantiq,output = <1>;
222 lantiq,open-drain = <0>;
223 lantiq,pull = <0>;
224 };
225 };
226
227 pci_gnt3_pins: pci-gnt3 {
228 mux {
229 lantiq,groups = "gnt3";
230 lantiq,function = "pci";
231 lantiq,output = <1>;
232 lantiq,open-drain = <0>;
233 lantiq,pull = <0>;
234 };
235 };
236
237 pci_gnt4_pins: pci-gnt4 {
238 mux {
239 lantiq,groups = "gnt4";
240 lantiq,function = "pci";
241 lantiq,output = <1>;
242 lantiq,open-drain = <0>;
243 lantiq,pull = <0>;
244 };
245 };
246
247 pci_req1_pins: pci-req1 {
248 mux {
249 lantiq,groups = "req1";
250 lantiq,function = "pci";
251 lantiq,output = <0>;
252 lantiq,open-drain = <1>;
253 lantiq,pull = <2>;
254 };
255 };
256
257 pci_req2_pins: pci-req2 {
258 mux {
259 lantiq,groups = "req2";
260 lantiq,function = "pci";
261 lantiq,output = <0>;
262 lantiq,open-drain = <1>;
263 lantiq,pull = <2>;
264 };
265 };
266
267 pci_req3_pins: pci-req3 {
268 mux {
269 lantiq,groups = "req3";
270 lantiq,function = "pci";
271 lantiq,output = <0>;
272 lantiq,open-drain = <1>;
273 lantiq,pull = <2>;
274 };
275 };
276
277 pci_req4_pins: pci-req4 {
278 mux {
279 lantiq,groups = "req4";
280 lantiq,function = "pci";
281 lantiq,output = <0>;
282 lantiq,open-drain = <1>;
283 lantiq,pull = <2>;
284 };
285 };
286
287 spi_pins: spi {
288 mux-0 {
289 lantiq,groups = "spi_di";
290 lantiq,function = "spi";
291 };
292 mux-1 {
293 lantiq,groups = "spi_do", "spi_clk";
294 lantiq,function = "spi";
295 lantiq,output = <1>;
296 };
297 };
298
299 spi_cs4_pins: spi-cs4 {
300 mux {
301 lantiq,groups = "spi_cs4";
302 lantiq,function = "spi";
303 lantiq,output = <1>;
304 };
305 };
306
307 stp_pins: stp {
308 mux {
309 lantiq,groups = "stp";
310 lantiq,function = "stp";
311 lantiq,pull = <0>;
312 lantiq,open-drain = <0>;
313 lantiq,output = <1>;
314 };
315 };
316 };
317
318 stp: stp@e100bb0 {
319 #gpio-cells = <2>;
320 compatible = "lantiq,gpio-stp-xway";
321 gpio-controller;
322 reg = <0xe100bb0 0x40>;
323
324 pinctrl-0 = <&stp_pins>;
325 pinctrl-names = "default";
326
327 status = "disabled";
328 };
329
330 asc1: serial@e100c00 {
331 compatible = "lantiq,asc";
332 reg = <0xe100c00 0x400>;
333 interrupt-parent = <&icu0>;
334 interrupts = <112 113 114>;
335 };
336
337 usb0: usb@e101000 {
338 compatible = "lantiq,arx100-usb";
339 reg = <0xe101000 0x1000
340 0xe120000 0x3f000>;
341 interrupt-parent = <&icu0>;
342 interrupts = <62 91>;
343 dr_mode = "host";
344 phys = <&usb_phy0>;
345 phy-names = "usb2-phy";
346 status = "disabled";
347 };
348
349 usb1: usb@e106000 {
350 compatible = "lantiq,arx100-usb";
351 reg = <0xe106000 0x1000
352 0xe1e0000 0x3f000>;
353 interrupt-parent = <&icu0>;
354 interrupts = <91>;
355 dr_mode = "host";
356 phys = <&usb_phy1>;
357 phy-names = "usb2-phy";
358 status = "disabled";
359 };
360
361 deu@e103100 {
362 compatible = "lantiq,deu-arx100";
363 reg = <0xe103100 0xf00>;
364 };
365
366 dma0: dma@e104100 {
367 compatible = "lantiq,dma-xway";
368 reg = <0xe104100 0x800>;
369 };
370
371 ebu0: ebu@e105300 {
372 compatible = "lantiq,ebu-xway";
373 reg = <0xe105300 0x100>;
374 };
375
376 mei@e116000 {
377 compatible = "lantiq,mei-xway";
378 reg = <0xe116000 0x9c>;
379 interrupt-parent = <&icu0>;
380 interrupts = <63>;
381 };
382
383 gsw: etop@e180000 {
384 compatible = "lantiq,etop-xway";
385 reg = <0xe180000 0x40000
386 0xe108000 0x200>;
387 interrupt-parent = <&icu0>;
388 interrupts = <73 72>;
389 mac-address = [ 00 11 22 33 44 55 ];
390 pinctrl-0 = <&mdio_pins>;
391 pinctrl-names = "default";
392 };
393
394 ppe@e234000 {
395 compatible = "lantiq,ppe-arx100";
396 reg = <0xe234000 0x3ffd>;
397 interrupt-parent = <&icu0>;
398 interrupts = <96>;
399 };
400
401 pci0: pci@e105400 {
402 status = "disabled";
403 #address-cells = <3>;
404 #size-cells = <2>;
405 #interrupt-cells = <1>;
406 compatible = "lantiq,pci-xway";
407 bus-range = <0x0 0x0>;
408 ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
409 0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */
410 reg = <0x7000000 0x8000 /* config space */
411 0xe105400 0x400>; /* pci bridge */
412 lantiq,bus-clock = <33333333>;
413 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
414 interrupt-map = <0x7000 0 0 1 &icu0 30 1>;
415 req-mask = <0x1>;
416 };
417 };
418
419 adsl {
420 compatible = "lantiq,adsl-arx100";
421 };
422 };