target/linux/lantiq/patches-5.4/0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch

   1 From c8eedcadc38a5e6008d3990fbe0a5285b30335fc Mon Sep 17 00:00:00 2001
   2 From: Mathias Kresin <dev@kresin.me>
   3 Date: Sun, 7 Jul 2019 21:48:56 +0200
   4 Subject: [PATCH] MIPS: lantiq: Add GPHY Firmware loader
   5
   6 Upstream, the GPHY Firmware loader has been merged into the DSA switch
   7 driver. But we don't use the driver yet, so bring it back.
   8
   9 Signed-off-by: Mathias Kresin <dev@kresin.me>
  10 ---
  11  .../bindings/mips/lantiq/rcu-gphy.txt         |  36 +++
  12  .../devicetree/bindings/mips/lantiq/rcu.txt   |  18 ++
  13  arch/mips/configs/xway_defconfig              |   1 +
  14  arch/mips/lantiq/Kconfig                      |   4 +
  15  drivers/soc/lantiq/Makefile                   |   1 +
  16  drivers/soc/lantiq/gphy.c                     | 224 ++++++++++++++++++
  17  6 files changed, 284 insertions(+)
  18  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
  19  create mode 100644 drivers/soc/lantiq/gphy.c
  20
  21 --- /dev/null
  22 +++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
  23 @@ -0,0 +1,37 @@
  24 +Lantiq XWAY SoC GPHY binding
  25 +============================
  26 +
  27 +This binding describes a software-defined ethernet PHY, provided by the RCU
  28 +module on newer Lantiq XWAY SoCs (xRX200 and newer).
  29 +
  30 +-------------------------------------------------------------------------------
  31 +Required properties:
  32 +- compatible           : Should be one of
  33 +                               "lantiq,xrx200-gphy"
  34 +                               "lantiq,xrx200a1x-gphy"
  35 +                               "lantiq,xrx200a2x-gphy"
  36 +                               "lantiq,xrx300-gphy"
  37 +                               "lantiq,xrx330-gphy"
  38 +- reg                  : Addrress of the GPHY FW load address register
  39 +- resets               : Must reference the RCU GPHY reset bit
  40 +- reset-names          : One entry, value must be "gphy" or optional "gphy2"
  41 +- clocks               : A reference to the (PMU) GPHY clock gate
  42 +
  43 +Optional properties:
  44 +- lantiq,gphy-mode     : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
  45 +                         <dt-bindings/mips/lantiq_xway_gphy.h>
  46 +
  47 +
  48 +-------------------------------------------------------------------------------
  49 +Example for the GPHys on the xRX200 SoCs:
  50 +
  51 +#include <dt-bindings/mips/lantiq_rcu_gphy.h>
  52 +       gphy0: gphy@20 {
  53 +               compatible = "lantiq,xrx200a2x-gphy";
  54 +               reg = <0x20 0x4>;
  55 +
  56 +               resets = <&reset0 31 30>, <&reset1 7 7>;
  57 +               reset-names = "gphy", "gphy2";
  58 +               clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
  59 +               lantiq,gphy-mode = <GPHY_MODE_GE>;
  60 +       };
  61 --- a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
  62 +++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
  63 @@ -26,6 +26,24 @@ Example of the RCU bindings on a xRX200
  64                 ranges = <0x0 0x203000 0x100>;
  65                 big-endian;
  66
  67 +               gphy0: gphy@20 {
  68 +                       compatible = "lantiq,xrx200a2x-gphy";
  69 +                       reg = <0x20 0x4>;
  70 +
  71 +                       resets = <&reset0 31 30>, <&reset1 7 7>;
  72 +                       reset-names = "gphy", "gphy2";
  73 +                       lantiq,gphy-mode = <GPHY_MODE_GE>;
  74 +               };
  75 +
  76 +               gphy1: gphy@68 {
  77 +                       compatible = "lantiq,xrx200a2x-gphy";
  78 +                       reg = <0x68 0x4>;
  79 +
  80 +                       resets = <&reset0 29 28>, <&reset1 6 6>;
  81 +                       reset-names = "gphy", "gphy2";
  82 +                       lantiq,gphy-mode = <GPHY_MODE_GE>;
  83 +               };
  84 +
  85                 reset0: reset-controller@10 {
  86                         compatible = "lantiq,xrx200-reset";
  87                         reg = <0x10 4>, <0x14 4>;
  88 --- a/arch/mips/configs/xway_defconfig
  89 +++ b/arch/mips/configs/xway_defconfig
  90 @@ -13,6 +13,7 @@ CONFIG_EMBEDDED=y
  91  # CONFIG_COMPAT_BRK is not set
  92  CONFIG_LANTIQ=y
  93  CONFIG_PCI_LANTIQ=y
  94 +CONFIG_XRX200_PHY_FW=y
  95  CONFIG_CPU_MIPS32_R2=y
  96  CONFIG_MIPS_VPE_LOADER=y
  97  CONFIG_NR_CPUS=2
  98 --- a/arch/mips/lantiq/Kconfig
  99 +++ b/arch/mips/lantiq/Kconfig
 100 @@ -62,4 +62,8 @@ config PCIE_LANTIQ_MSI
 101         depends on PCIE_LANTIQ && PCI_MSI
 102         default y
 103
 104 +config XRX200_PHY_FW
 105 +       bool "XRX200 PHY firmware loader"
 106 +       depends on SOC_XWAY
 107 +
 108  endif
 109 --- a/drivers/soc/lantiq/Makefile
 110 +++ b/drivers/soc/lantiq/Makefile
 111 @@ -1,2 +1,3 @@
 112  # SPDX-License-Identifier: GPL-2.0-only
 113  obj-y                          += fpi-bus.o
 114 +obj-$(CONFIG_XRX200_PHY_FW)    += gphy.o
 115 --- /dev/null
 116 +++ b/drivers/soc/lantiq/gphy.c
 117 @@ -0,0 +1,235 @@
 118 +/*
 119 + *  This program is free software; you can redistribute it and/or modify it
 120 + *  under the terms of the GNU General Public License version 2 as published
 121 + *  by the Free Software Foundation.
 122 + *
 123 + *  Copyright (C) 2012 John Crispin <blogic@phrozen.org>
 124 + *  Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
 125 + *  Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
 126 + */
 127 +
 128 +#include <linux/clk.h>
 129 +#include <linux/delay.h>
 130 +#include <linux/dma-mapping.h>
 131 +#include <linux/firmware.h>
 132 +#include <linux/mfd/syscon.h>
 133 +#include <linux/module.h>
 134 +#include <linux/reboot.h>
 135 +#include <linux/regmap.h>
 136 +#include <linux/reset.h>
 137 +#include <linux/of_device.h>
 138 +#include <linux/of_platform.h>
 139 +#include <linux/property.h>
 140 +#include <dt-bindings/mips/lantiq_rcu_gphy.h>
 141 +
 142 +#include <lantiq_soc.h>
 143 +
 144 +#define XRX200_GPHY_FW_ALIGN   (16 * 1024)
 145 +
 146 +struct xway_gphy_priv {
 147 +       struct clk *gphy_clk_gate;
 148 +       struct reset_control *gphy_reset;
 149 +       struct reset_control *gphy_reset2;
 150 +       void __iomem *membase;
 151 +       char *fw_name;
 152 +};
 153 +
 154 +struct xway_gphy_match_data {
 155 +       char *fe_firmware_name;
 156 +       char *ge_firmware_name;
 157 +};
 158 +
 159 +static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
 160 +       .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
 161 +       .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
 162 +};
 163 +
 164 +static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
 165 +       .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
 166 +       .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
 167 +};
 168 +
 169 +static const struct xway_gphy_match_data xrx300_gphy_data = {
 170 +       .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
 171 +       .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
 172 +};
 173 +
 174 +static const struct of_device_id xway_gphy_match[] = {
 175 +       { .compatible = "lantiq,xrx200-gphy", .data = NULL },
 176 +       { .compatible = "lantiq,xrx200a1x-gphy", .data = &xrx200a1x_gphy_data },
 177 +       { .compatible = "lantiq,xrx200a2x-gphy", .data = &xrx200a2x_gphy_data },
 178 +       { .compatible = "lantiq,xrx300-gphy", .data = &xrx300_gphy_data },
 179 +       { .compatible = "lantiq,xrx330-gphy", .data = &xrx300_gphy_data },
 180 +       {},
 181 +};
 182 +MODULE_DEVICE_TABLE(of, xway_gphy_match);
 183 +
 184 +static int xway_gphy_load(struct device *dev, struct xway_gphy_priv *priv,
 185 +                         dma_addr_t *dev_addr)
 186 +{
 187 +       const struct firmware *fw;
 188 +       void *fw_addr;
 189 +       dma_addr_t dma_addr;
 190 +       size_t size;
 191 +       int ret;
 192 +
 193 +       ret = request_firmware(&fw, priv->fw_name, dev);
 194 +       if (ret) {
 195 +               dev_err(dev, "failed to load firmware: %s, error: %i\n",
 196 +                       priv->fw_name, ret);
 197 +               return ret;
 198 +       }
 199 +
 200 +       /*
 201 +        * GPHY cores need the firmware code in a persistent and contiguous
 202 +        * memory area with a 16 kB boundary aligned start address.
 203 +        */
 204 +       size = fw->size + XRX200_GPHY_FW_ALIGN;
 205 +
 206 +       fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
 207 +       if (fw_addr) {
 208 +               fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
 209 +               *dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
 210 +               memcpy(fw_addr, fw->data, fw->size);
 211 +       } else {
 212 +               dev_err(dev, "failed to alloc firmware memory\n");
 213 +               ret = -ENOMEM;
 214 +       }
 215 +
 216 +       release_firmware(fw);
 217 +
 218 +       return ret;
 219 +}
 220 +
 221 +static int xway_gphy_of_probe(struct platform_device *pdev,
 222 +                             struct xway_gphy_priv *priv)
 223 +{
 224 +       struct device *dev = &pdev->dev;
 225 +       const struct xway_gphy_match_data *gphy_fw_name_cfg;
 226 +       u32 gphy_mode;
 227 +       int ret;
 228 +       struct resource *res_gphy;
 229 +
 230 +       gphy_fw_name_cfg = of_device_get_match_data(dev);
 231 +
 232 +       if (of_device_is_compatible(pdev->dev.of_node, "lantiq,xrx200-gphy"))
 233 +               switch (ltq_soc_type()) {
 234 +               case SOC_TYPE_VR9:
 235 +                       gphy_fw_name_cfg = &xrx200a1x_gphy_data;
 236 +                       break;
 237 +               case SOC_TYPE_VR9_2:
 238 +                       gphy_fw_name_cfg = &xrx200a2x_gphy_data;
 239 +                       break;
 240 +               }
 241 +
 242 +       priv->gphy_clk_gate = devm_clk_get(dev, NULL);
 243 +       if (IS_ERR(priv->gphy_clk_gate)) {
 244 +               dev_err(dev, "Failed to lookup gate clock\n");
 245 +               return PTR_ERR(priv->gphy_clk_gate);
 246 +       }
 247 +
 248 +       res_gphy = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 249 +       priv->membase = devm_ioremap_resource(dev, res_gphy);
 250 +       if (IS_ERR(priv->membase))
 251 +               return PTR_ERR(priv->membase);
 252 +
 253 +       priv->gphy_reset = devm_reset_control_get(dev, "gphy");
 254 +       if (IS_ERR(priv->gphy_reset)) {
 255 +               if (PTR_ERR(priv->gphy_reset) != -EPROBE_DEFER)
 256 +                       dev_err(dev, "Failed to lookup gphy reset\n");
 257 +               return PTR_ERR(priv->gphy_reset);
 258 +       }
 259 +
 260 +       priv->gphy_reset2 = devm_reset_control_get_optional(dev, "gphy2");
 261 +       if (IS_ERR(priv->gphy_reset2))
 262 +               return PTR_ERR(priv->gphy_reset2);
 263 +
 264 +       ret = device_property_read_u32(dev, "lantiq,gphy-mode", &gphy_mode);
 265 +       /* Default to GE mode */
 266 +       if (ret)
 267 +               gphy_mode = GPHY_MODE_GE;
 268 +
 269 +       switch (gphy_mode) {
 270 +       case GPHY_MODE_FE:
 271 +               priv->fw_name = gphy_fw_name_cfg->fe_firmware_name;
 272 +               break;
 273 +       case GPHY_MODE_GE:
 274 +               priv->fw_name = gphy_fw_name_cfg->ge_firmware_name;
 275 +               break;
 276 +       default:
 277 +               dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
 278 +               return -EINVAL;
 279 +       }
 280 +
 281 +       return 0;
 282 +}
 283 +
 284 +static int xway_gphy_probe(struct platform_device *pdev)
 285 +{
 286 +       struct device *dev = &pdev->dev;
 287 +       struct xway_gphy_priv *priv;
 288 +       dma_addr_t fw_addr = 0;
 289 +       int ret;
 290 +
 291 +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 292 +       if (!priv)
 293 +               return -ENOMEM;
 294 +
 295 +       ret = xway_gphy_of_probe(pdev, priv);
 296 +       if (ret)
 297 +               return ret;
 298 +
 299 +       ret = clk_prepare_enable(priv->gphy_clk_gate);
 300 +       if (ret)
 301 +               return ret;
 302 +
 303 +       ret = xway_gphy_load(dev, priv, &fw_addr);
 304 +       if (ret) {
 305 +               clk_disable_unprepare(priv->gphy_clk_gate);
 306 +               return ret;
 307 +       }
 308 +
 309 +       reset_control_assert(priv->gphy_reset);
 310 +       reset_control_assert(priv->gphy_reset2);
 311 +
 312 +       iowrite32be(fw_addr, priv->membase);
 313 +
 314 +       reset_control_deassert(priv->gphy_reset);
 315 +       reset_control_deassert(priv->gphy_reset2);
 316 +
 317 +       platform_set_drvdata(pdev, priv);
 318 +
 319 +       return ret;
 320 +}
 321 +
 322 +static int xway_gphy_remove(struct platform_device *pdev)
 323 +{
 324 +       struct xway_gphy_priv *priv = platform_get_drvdata(pdev);
 325 +
 326 +       iowrite32be(0, priv->membase);
 327 +
 328 +       clk_disable_unprepare(priv->gphy_clk_gate);
 329 +
 330 +       return 0;
 331 +}
 332 +
 333 +static struct platform_driver xway_gphy_driver = {
 334 +       .probe = xway_gphy_probe,
 335 +       .remove = xway_gphy_remove,
 336 +       .driver = {
 337 +               .name = "xway-rcu-gphy",
 338 +               .of_match_table = xway_gphy_match,
 339 +       },
 340 +};
 341 +
 342 +module_platform_driver(xway_gphy_driver);
 343 +
 344 +MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
 345 +MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
 346 +MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
 347 +MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
 348 +MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
 349 +MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
 350 +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
 351 +MODULE_DESCRIPTION("Lantiq XWAY GPHY Firmware Loader");
 352 +MODULE_LICENSE("GPL");