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kernel: bump 4.9 to 4.9.87
[openwrt/staging/wigyori.git] / target / linux / layerscape / patches-4.9 / 302-dts-support-layercape.patch
1 From 1806d342beb334c8cb0a438315ad5529262b2791 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Wed, 17 Jan 2018 14:52:50 +0800
4 Subject: [PATCH 04/30] dts: support layercape
5
6 This is an integrated patch for layerscape dts support.
7
8 Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
9 Signed-off-by: Alison Wang <b18965@freescale.com>
10 Signed-off-by: Li Yang <leoyang.li@nxp.com>
11 Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
12 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
13 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
14 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
15 Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
16 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
17 Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
18 Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
19 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
20 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
21 Signed-off-by: Changming Huang <jerry.huang@nxp.com>
22 Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
23 Signed-off-by: Meng Yi <meng.yi@nxp.com>
24 Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
25 Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
26 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
27 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
28 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
29 ---
30 arch/arm/boot/dts/alpine.dtsi | 2 +-
31 arch/arm/boot/dts/axm55xx.dtsi | 2 +-
32 arch/arm/boot/dts/ecx-2000.dts | 2 +-
33 arch/arm/boot/dts/imx6ul.dtsi | 4 +-
34 arch/arm/boot/dts/keystone.dtsi | 4 +-
35 arch/arm/boot/dts/ls1021a-qds.dts | 21 +
36 arch/arm/boot/dts/ls1021a-twr.dts | 25 +
37 arch/arm/boot/dts/ls1021a.dtsi | 197 +++--
38 arch/arm/boot/dts/mt6580.dtsi | 2 +-
39 arch/arm/boot/dts/mt6589.dtsi | 2 +-
40 arch/arm/boot/dts/mt8127.dtsi | 2 +-
41 arch/arm/boot/dts/mt8135.dtsi | 2 +-
42 arch/arm/boot/dts/rk3288.dtsi | 2 +-
43 arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
44 arch/arm/boot/dts/sun7i-a20.dtsi | 4 +-
45 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
46 arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
47 arch/arm64/boot/dts/freescale/Makefile | 17 +
48 .../boot/dts/freescale/fsl-ls1012a-2g5rdb.dts | 123 +++
49 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 177 ++++
50 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 202 +++++
51 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 138 ++++
52 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 602 ++++++++++++++
53 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi | 45 +
54 .../boot/dts/freescale/fsl-ls1043a-qds-sdk.dts | 69 ++
55 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 171 +++-
56 .../boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts | 69 ++
57 .../boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts | 117 +++
58 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 113 ++-
59 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 308 ++++++-
60 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi | 48 ++
61 .../boot/dts/freescale/fsl-ls1046a-qds-sdk.dts | 110 +++
62 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 363 ++++++++
63 .../boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts | 83 ++
64 .../boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts | 110 +++
65 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 218 +++++
66 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 800 ++++++++++++++++++
67 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts | 173 ++++
68 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 236 ++++++
69 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 825 ++++++++++++++++++
70 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 191 ++---
71 arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 169 ++--
72 arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 9 +-
73 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 763 +++--------------
74 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts | 161 ++++
75 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts | 162 ++++
76 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts | 140 ++++
77 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 195 +++++
78 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi | 198 +++++
79 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 161 ++++
80 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 919 +++++++++++++++++++++
81 .../boot/dts/freescale/qoriq-bman1-portals.dtsi | 81 ++
82 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi | 73 ++
83 .../boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi | 43 +
84 .../boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi | 43 +
85 .../boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi | 42 +
86 .../boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi | 42 +
87 .../boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi | 42 +
88 .../boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi | 42 +
89 .../boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi | 42 +
90 .../boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi | 42 +
91 .../boot/dts/freescale/qoriq-fman3-0-6oh.dtsi | 47 ++
92 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi | 130 +++
93 .../boot/dts/freescale/qoriq-qman1-portals.dtsi | 104 +++
94 arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi | 10 +
95 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 4 +-
96 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 4 +-
97 67 files changed, 8231 insertions(+), 1022 deletions(-)
98 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
99 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
100 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
101 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
102 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
103 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
104 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
105 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
106 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
107 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
108 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
109 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
110 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
111 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
112 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
113 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
114 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
115 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
116 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
117 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
118 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
119 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
120 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
121 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
122 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
123 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
124 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
125 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
126 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
127 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
128 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
129 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
130 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
131 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
132 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
133 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
134 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
135 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
136 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
137
138 --- a/arch/arm/boot/dts/alpine.dtsi
139 +++ b/arch/arm/boot/dts/alpine.dtsi
140 @@ -93,7 +93,7 @@
141 interrupt-controller;
142 reg = <0x0 0xfb001000 0x0 0x1000>,
143 <0x0 0xfb002000 0x0 0x2000>,
144 - <0x0 0xfb004000 0x0 0x1000>,
145 + <0x0 0xfb004000 0x0 0x2000>,
146 <0x0 0xfb006000 0x0 0x2000>;
147 interrupts =
148 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
149 --- a/arch/arm/boot/dts/axm55xx.dtsi
150 +++ b/arch/arm/boot/dts/axm55xx.dtsi
151 @@ -62,7 +62,7 @@
152 #address-cells = <0>;
153 interrupt-controller;
154 reg = <0x20 0x01001000 0 0x1000>,
155 - <0x20 0x01002000 0 0x1000>,
156 + <0x20 0x01002000 0 0x2000>,
157 <0x20 0x01004000 0 0x2000>,
158 <0x20 0x01006000 0 0x2000>;
159 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
160 --- a/arch/arm/boot/dts/ecx-2000.dts
161 +++ b/arch/arm/boot/dts/ecx-2000.dts
162 @@ -99,7 +99,7 @@
163 interrupt-controller;
164 interrupts = <1 9 0xf04>;
165 reg = <0xfff11000 0x1000>,
166 - <0xfff12000 0x1000>,
167 + <0xfff12000 0x2000>,
168 <0xfff14000 0x2000>,
169 <0xfff16000 0x2000>;
170 };
171 --- a/arch/arm/boot/dts/imx6ul.dtsi
172 +++ b/arch/arm/boot/dts/imx6ul.dtsi
173 @@ -89,11 +89,11 @@
174 };
175
176 intc: interrupt-controller@00a01000 {
177 - compatible = "arm,cortex-a7-gic";
178 + compatible = "arm,gic-400", "arm,cortex-a7-gic";
179 #interrupt-cells = <3>;
180 interrupt-controller;
181 reg = <0x00a01000 0x1000>,
182 - <0x00a02000 0x1000>,
183 + <0x00a02000 0x2000>,
184 <0x00a04000 0x2000>,
185 <0x00a06000 0x2000>;
186 };
187 --- a/arch/arm/boot/dts/keystone.dtsi
188 +++ b/arch/arm/boot/dts/keystone.dtsi
189 @@ -30,12 +30,12 @@
190 };
191
192 gic: interrupt-controller {
193 - compatible = "arm,cortex-a15-gic";
194 + compatible = "arm,gic-400", "arm,cortex-a15-gic";
195 #interrupt-cells = <3>;
196 interrupt-controller;
197 reg = <0x0 0x02561000 0x0 0x1000>,
198 <0x0 0x02562000 0x0 0x2000>,
199 - <0x0 0x02564000 0x0 0x1000>,
200 + <0x0 0x02564000 0x0 0x2000>,
201 <0x0 0x02566000 0x0 0x2000>;
202 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
203 IRQ_TYPE_LEVEL_HIGH)>;
204 --- a/arch/arm/boot/dts/ls1021a-qds.dts
205 +++ b/arch/arm/boot/dts/ls1021a-qds.dts
206 @@ -124,6 +124,19 @@
207 };
208 };
209
210 +&qspi {
211 + num-cs = <2>;
212 + status = "okay";
213 +
214 + qflash0: s25fl128s@0 {
215 + compatible = "spansion,m25p80";
216 + #address-cells = <1>;
217 + #size-cells = <1>;
218 + spi-max-frequency = <20000000>;
219 + reg = <0>;
220 + };
221 +};
222 +
223 &enet0 {
224 tbi-handle = <&tbi0>;
225 phy-handle = <&sgmii_phy1c>;
226 @@ -331,3 +344,11 @@
227 &uart1 {
228 status = "okay";
229 };
230 +
231 +&can0 {
232 + status = "okay";
233 +};
234 +
235 +&can1 {
236 + status = "okay";
237 +};
238 --- a/arch/arm/boot/dts/ls1021a-twr.dts
239 +++ b/arch/arm/boot/dts/ls1021a-twr.dts
240 @@ -142,6 +142,19 @@
241 };
242 };
243
244 +&qspi {
245 + num-cs = <2>;
246 + status = "okay";
247 +
248 + qflash0: n25q128a13@0 {
249 + compatible = "n25q128a13", "jedec,spi-nor";
250 + #address-cells = <1>;
251 + #size-cells = <1>;
252 + spi-max-frequency = <20000000>;
253 + reg = <0>;
254 + };
255 +};
256 +
257 &enet0 {
258 tbi-handle = <&tbi1>;
259 phy-handle = <&sgmii_phy2>;
260 @@ -228,6 +241,10 @@
261 };
262 };
263
264 +&esdhc {
265 + status = "okay";
266 +};
267 +
268 &sai1 {
269 status = "okay";
270 };
271 @@ -243,3 +260,11 @@
272 &uart1 {
273 status = "okay";
274 };
275 +
276 +&can0 {
277 + status = "okay";
278 +};
279 +
280 +&can1 {
281 + status = "okay";
282 +};
283 --- a/arch/arm/boot/dts/ls1021a.dtsi
284 +++ b/arch/arm/boot/dts/ls1021a.dtsi
285 @@ -74,17 +74,24 @@
286 compatible = "arm,cortex-a7";
287 device_type = "cpu";
288 reg = <0xf00>;
289 - clocks = <&cluster1_clk>;
290 + clocks = <&clockgen 1 0>;
291 };
292
293 cpu@f01 {
294 compatible = "arm,cortex-a7";
295 device_type = "cpu";
296 reg = <0xf01>;
297 - clocks = <&cluster1_clk>;
298 + clocks = <&clockgen 1 0>;
299 };
300 };
301
302 + sysclk: sysclk {
303 + compatible = "fixed-clock";
304 + #clock-cells = <0>;
305 + clock-frequency = <100000000>;
306 + clock-output-names = "sysclk";
307 + };
308 +
309 timer {
310 compatible = "arm,armv7-timer";
311 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
312 @@ -108,11 +115,11 @@
313 ranges;
314
315 gic: interrupt-controller@1400000 {
316 - compatible = "arm,cortex-a7-gic";
317 + compatible = "arm,gic-400", "arm,cortex-a7-gic";
318 #interrupt-cells = <3>;
319 interrupt-controller;
320 reg = <0x0 0x1401000 0x0 0x1000>,
321 - <0x0 0x1402000 0x0 0x1000>,
322 + <0x0 0x1402000 0x0 0x2000>,
323 <0x0 0x1404000 0x0 0x2000>,
324 <0x0 0x1406000 0x0 0x2000>;
325 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
326 @@ -120,14 +127,14 @@
327 };
328
329 msi1: msi-controller@1570e00 {
330 - compatible = "fsl,1s1021a-msi";
331 + compatible = "fsl,ls1021a-msi";
332 reg = <0x0 0x1570e00 0x0 0x8>;
333 msi-controller;
334 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
335 };
336
337 msi2: msi-controller@1570e08 {
338 - compatible = "fsl,1s1021a-msi";
339 + compatible = "fsl,ls1021a-msi";
340 reg = <0x0 0x1570e08 0x0 0x8>;
341 msi-controller;
342 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
343 @@ -137,16 +144,17 @@
344 compatible = "fsl,ifc", "simple-bus";
345 reg = <0x0 0x1530000 0x0 0x10000>;
346 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
347 + big-endian;
348 };
349
350 dcfg: dcfg@1ee0000 {
351 compatible = "fsl,ls1021a-dcfg", "syscon";
352 - reg = <0x0 0x1ee0000 0x0 0x10000>;
353 + reg = <0x0 0x1ee0000 0x0 0x1000>;
354 big-endian;
355 };
356
357 esdhc: esdhc@1560000 {
358 - compatible = "fsl,esdhc";
359 + compatible = "fsl,ls1021a-esdhc","fsl,esdhc";
360 reg = <0x0 0x1560000 0x0 0x10000>;
361 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
362 clock-frequency = <0>;
363 @@ -163,7 +171,7 @@
364 <0x0 0x20220520 0x0 0x4>;
365 reg-names = "ahci", "sata-ecc";
366 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
367 - clocks = <&platform_clk 1>;
368 + clocks = <&clockgen 4 1>;
369 dma-coherent;
370 status = "disabled";
371 };
372 @@ -214,41 +222,10 @@
373 };
374
375 clockgen: clocking@1ee1000 {
376 - #address-cells = <1>;
377 - #size-cells = <1>;
378 - ranges = <0x0 0x0 0x1ee1000 0x10000>;
379 -
380 - sysclk: sysclk {
381 - compatible = "fixed-clock";
382 - #clock-cells = <0>;
383 - clock-output-names = "sysclk";
384 - };
385 -
386 - cga_pll1: pll@800 {
387 - compatible = "fsl,qoriq-core-pll-2.0";
388 - #clock-cells = <1>;
389 - reg = <0x800 0x10>;
390 - clocks = <&sysclk>;
391 - clock-output-names = "cga-pll1", "cga-pll1-div2",
392 - "cga-pll1-div4";
393 - };
394 -
395 - platform_clk: pll@c00 {
396 - compatible = "fsl,qoriq-core-pll-2.0";
397 - #clock-cells = <1>;
398 - reg = <0xc00 0x10>;
399 - clocks = <&sysclk>;
400 - clock-output-names = "platform-clk", "platform-clk-div2";
401 - };
402 -
403 - cluster1_clk: clk0c0@0 {
404 - compatible = "fsl,qoriq-core-mux-2.0";
405 - #clock-cells = <0>;
406 - reg = <0x0 0x10>;
407 - clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
408 - clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
409 - clock-output-names = "cluster1-clk";
410 - };
411 + compatible = "fsl,ls1021a-clockgen";
412 + reg = <0x0 0x1ee1000 0x0 0x1000>;
413 + #clock-cells = <2>;
414 + clocks = <&sysclk>;
415 };
416
417 dspi0: dspi@2100000 {
418 @@ -258,7 +235,7 @@
419 reg = <0x0 0x2100000 0x0 0x10000>;
420 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
421 clock-names = "dspi";
422 - clocks = <&platform_clk 1>;
423 + clocks = <&clockgen 4 1>;
424 spi-num-chipselects = <6>;
425 big-endian;
426 status = "disabled";
427 @@ -271,12 +248,27 @@
428 reg = <0x0 0x2110000 0x0 0x10000>;
429 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
430 clock-names = "dspi";
431 - clocks = <&platform_clk 1>;
432 + clocks = <&clockgen 4 1>;
433 spi-num-chipselects = <6>;
434 big-endian;
435 status = "disabled";
436 };
437
438 + qspi: quadspi@1550000 {
439 + compatible = "fsl,ls1021a-qspi";
440 + #address-cells = <1>;
441 + #size-cells = <0>;
442 + reg = <0x0 0x1550000 0x0 0x10000>,
443 + <0x0 0x40000000 0x0 0x4000000>;
444 + reg-names = "QuadSPI", "QuadSPI-memory";
445 + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
446 + clock-names = "qspi_en", "qspi";
447 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
448 + big-endian;
449 + amba-base = <0x40000000>;
450 + status = "disabled";
451 + };
452 +
453 i2c0: i2c@2180000 {
454 compatible = "fsl,vf610-i2c";
455 #address-cells = <1>;
456 @@ -284,7 +276,7 @@
457 reg = <0x0 0x2180000 0x0 0x10000>;
458 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
459 clock-names = "i2c";
460 - clocks = <&platform_clk 1>;
461 + clocks = <&clockgen 4 1>;
462 status = "disabled";
463 };
464
465 @@ -295,7 +287,7 @@
466 reg = <0x0 0x2190000 0x0 0x10000>;
467 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
468 clock-names = "i2c";
469 - clocks = <&platform_clk 1>;
470 + clocks = <&clockgen 4 1>;
471 status = "disabled";
472 };
473
474 @@ -306,7 +298,7 @@
475 reg = <0x0 0x21a0000 0x0 0x10000>;
476 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
477 clock-names = "i2c";
478 - clocks = <&platform_clk 1>;
479 + clocks = <&clockgen 4 1>;
480 status = "disabled";
481 };
482
483 @@ -399,7 +391,7 @@
484 compatible = "fsl,ls1021a-lpuart";
485 reg = <0x0 0x2960000 0x0 0x1000>;
486 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
487 - clocks = <&platform_clk 1>;
488 + clocks = <&clockgen 4 1>;
489 clock-names = "ipg";
490 status = "disabled";
491 };
492 @@ -408,7 +400,7 @@
493 compatible = "fsl,ls1021a-lpuart";
494 reg = <0x0 0x2970000 0x0 0x1000>;
495 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
496 - clocks = <&platform_clk 1>;
497 + clocks = <&clockgen 4 1>;
498 clock-names = "ipg";
499 status = "disabled";
500 };
501 @@ -417,7 +409,7 @@
502 compatible = "fsl,ls1021a-lpuart";
503 reg = <0x0 0x2980000 0x0 0x1000>;
504 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
505 - clocks = <&platform_clk 1>;
506 + clocks = <&clockgen 4 1>;
507 clock-names = "ipg";
508 status = "disabled";
509 };
510 @@ -426,7 +418,7 @@
511 compatible = "fsl,ls1021a-lpuart";
512 reg = <0x0 0x2990000 0x0 0x1000>;
513 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
514 - clocks = <&platform_clk 1>;
515 + clocks = <&clockgen 4 1>;
516 clock-names = "ipg";
517 status = "disabled";
518 };
519 @@ -435,16 +427,26 @@
520 compatible = "fsl,ls1021a-lpuart";
521 reg = <0x0 0x29a0000 0x0 0x1000>;
522 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
523 - clocks = <&platform_clk 1>;
524 + clocks = <&clockgen 4 1>;
525 clock-names = "ipg";
526 status = "disabled";
527 };
528
529 + ftm0: ftm0@29d0000 {
530 + compatible = "fsl,ls1021a-ftm";
531 + reg = <0x0 0x29d0000 0x0 0x10000>,
532 + <0x0 0x1ee2140 0x0 0x4>;
533 + reg-names = "ftm", "FlexTimer1";
534 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
535 + big-endian;
536 + status = "okay";
537 + };
538 +
539 wdog0: watchdog@2ad0000 {
540 compatible = "fsl,imx21-wdt";
541 reg = <0x0 0x2ad0000 0x0 0x10000>;
542 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
543 - clocks = <&platform_clk 1>;
544 + clocks = <&clockgen 4 1>;
545 clock-names = "wdog-en";
546 big-endian;
547 };
548 @@ -454,8 +456,8 @@
549 compatible = "fsl,vf610-sai";
550 reg = <0x0 0x2b50000 0x0 0x10000>;
551 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
552 - clocks = <&platform_clk 1>, <&platform_clk 1>,
553 - <&platform_clk 1>, <&platform_clk 1>;
554 + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
555 + <&clockgen 4 1>, <&clockgen 4 1>;
556 clock-names = "bus", "mclk1", "mclk2", "mclk3";
557 dma-names = "tx", "rx";
558 dmas = <&edma0 1 47>,
559 @@ -468,8 +470,8 @@
560 compatible = "fsl,vf610-sai";
561 reg = <0x0 0x2b60000 0x0 0x10000>;
562 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
563 - clocks = <&platform_clk 1>, <&platform_clk 1>,
564 - <&platform_clk 1>, <&platform_clk 1>;
565 + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
566 + <&clockgen 4 1>, <&clockgen 4 1>;
567 clock-names = "bus", "mclk1", "mclk2", "mclk3";
568 dma-names = "tx", "rx";
569 dmas = <&edma0 1 45>,
570 @@ -489,16 +491,31 @@
571 dma-channels = <32>;
572 big-endian;
573 clock-names = "dmamux0", "dmamux1";
574 - clocks = <&platform_clk 1>,
575 - <&platform_clk 1>;
576 + clocks = <&clockgen 4 1>,
577 + <&clockgen 4 1>;
578 + };
579 +
580 + qdma: qdma@8390000 {
581 + compatible = "fsl,ls1021a-qdma";
582 + reg = <0x0 0x8398000 0x0 0x1000>, /* Controller regs */
583 + <0x0 0x8399000 0x0 0x1000>, /* Status regs */
584 + <0x0 0x839a000 0x0 0x2000>; /* Block regs */
585 + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
586 + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
587 + interrupt-names = "qdma-error", "qdma-queue";
588 + channels = <8>;
589 + queues = <2>;
590 + status-sizes = <64>;
591 + queue-sizes = <64 64>;
592 + big-endian;
593 };
594
595 dcu: dcu@2ce0000 {
596 compatible = "fsl,ls1021a-dcu";
597 reg = <0x0 0x2ce0000 0x0 0x10000>;
598 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
599 - clocks = <&platform_clk 0>,
600 - <&platform_clk 0>;
601 + clocks = <&clockgen 4 0>,
602 + <&clockgen 4 0>;
603 clock-names = "dcu", "pix";
604 big-endian;
605 status = "disabled";
606 @@ -626,6 +643,8 @@
607 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
608 dr_mode = "host";
609 snps,quirk-frame-length-adjustment = <0x20>;
610 + configure-gfladj;
611 + dma-coherent;
612 snps,dis_rxdet_inp3_quirk;
613 };
614
615 @@ -634,7 +653,9 @@
616 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
617 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
618 reg-names = "regs", "config";
619 - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
620 + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
621 + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
622 + interrupt-names = "pme", "aer";
623 fsl,pcie-scfg = <&scfg 0>;
624 #address-cells = <3>;
625 #size-cells = <2>;
626 @@ -643,7 +664,7 @@
627 bus-range = <0x0 0xff>;
628 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
629 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
630 - msi-parent = <&msi1>;
631 + msi-parent = <&msi1>, <&msi2>;
632 #interrupt-cells = <1>;
633 interrupt-map-mask = <0 0 0 7>;
634 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
635 @@ -657,7 +678,9 @@
636 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
637 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
638 reg-names = "regs", "config";
639 - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
640 + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
641 + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
642 + interrupt-names = "pme", "aer";
643 fsl,pcie-scfg = <&scfg 1>;
644 #address-cells = <3>;
645 #size-cells = <2>;
646 @@ -666,7 +689,7 @@
647 bus-range = <0x0 0xff>;
648 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
649 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
650 - msi-parent = <&msi2>;
651 + msi-parent = <&msi1>, <&msi2>;
652 #interrupt-cells = <1>;
653 interrupt-map-mask = <0 0 0 7>;
654 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
655 @@ -674,5 +697,45 @@
656 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
657 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
658 };
659 +
660 + can0: can@2a70000 {
661 + compatible = "fsl,ls1021ar2-flexcan";
662 + reg = <0x0 0x2a70000 0x0 0x1000>;
663 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
664 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
665 + clock-names = "ipg", "per";
666 + big-endian;
667 + status = "disabled";
668 + };
669 +
670 + can1: can@2a80000 {
671 + compatible = "fsl,ls1021ar2-flexcan";
672 + reg = <0x0 0x2a80000 0x0 0x1000>;
673 + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
674 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
675 + clock-names = "ipg", "per";
676 + big-endian;
677 + status = "disabled";
678 + };
679 +
680 + can2: can@2a90000 {
681 + compatible = "fsl,ls1021ar2-flexcan";
682 + reg = <0x0 0x2a90000 0x0 0x1000>;
683 + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
684 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
685 + clock-names = "ipg", "per";
686 + big-endian;
687 + status = "disabled";
688 + };
689 +
690 + can3: can@2aa0000 {
691 + compatible = "fsl,ls1021ar2-flexcan";
692 + reg = <0x0 0x2aa0000 0x0 0x1000>;
693 + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
694 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
695 + clock-names = "ipg", "per";
696 + big-endian;
697 + status = "disabled";
698 + };
699 };
700 };
701 --- a/arch/arm/boot/dts/mt6580.dtsi
702 +++ b/arch/arm/boot/dts/mt6580.dtsi
703 @@ -91,7 +91,7 @@
704 #interrupt-cells = <3>;
705 interrupt-parent = <&gic>;
706 reg = <0x10211000 0x1000>,
707 - <0x10212000 0x1000>,
708 + <0x10212000 0x2000>,
709 <0x10214000 0x2000>,
710 <0x10216000 0x2000>;
711 };
712 --- a/arch/arm/boot/dts/mt6589.dtsi
713 +++ b/arch/arm/boot/dts/mt6589.dtsi
714 @@ -102,7 +102,7 @@
715 #interrupt-cells = <3>;
716 interrupt-parent = <&gic>;
717 reg = <0x10211000 0x1000>,
718 - <0x10212000 0x1000>,
719 + <0x10212000 0x2000>,
720 <0x10214000 0x2000>,
721 <0x10216000 0x2000>;
722 };
723 --- a/arch/arm/boot/dts/mt8127.dtsi
724 +++ b/arch/arm/boot/dts/mt8127.dtsi
725 @@ -129,7 +129,7 @@
726 #interrupt-cells = <3>;
727 interrupt-parent = <&gic>;
728 reg = <0 0x10211000 0 0x1000>,
729 - <0 0x10212000 0 0x1000>,
730 + <0 0x10212000 0 0x2000>,
731 <0 0x10214000 0 0x2000>,
732 <0 0x10216000 0 0x2000>;
733 };
734 --- a/arch/arm/boot/dts/mt8135.dtsi
735 +++ b/arch/arm/boot/dts/mt8135.dtsi
736 @@ -221,7 +221,7 @@
737 #interrupt-cells = <3>;
738 interrupt-parent = <&gic>;
739 reg = <0 0x10211000 0 0x1000>,
740 - <0 0x10212000 0 0x1000>,
741 + <0 0x10212000 0 0x2000>,
742 <0 0x10214000 0 0x2000>,
743 <0 0x10216000 0 0x2000>;
744 };
745 --- a/arch/arm/boot/dts/rk3288.dtsi
746 +++ b/arch/arm/boot/dts/rk3288.dtsi
747 @@ -1109,7 +1109,7 @@
748 #address-cells = <0>;
749
750 reg = <0xffc01000 0x1000>,
751 - <0xffc02000 0x1000>,
752 + <0xffc02000 0x2000>,
753 <0xffc04000 0x2000>,
754 <0xffc06000 0x2000>;
755 interrupts = <GIC_PPI 9 0xf04>;
756 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
757 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
758 @@ -791,7 +791,7 @@
759 gic: interrupt-controller@01c81000 {
760 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
761 reg = <0x01c81000 0x1000>,
762 - <0x01c82000 0x1000>,
763 + <0x01c82000 0x2000>,
764 <0x01c84000 0x2000>,
765 <0x01c86000 0x2000>;
766 interrupt-controller;
767 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
768 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
769 @@ -1685,9 +1685,9 @@
770 };
771
772 gic: interrupt-controller@01c81000 {
773 - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
774 + compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
775 reg = <0x01c81000 0x1000>,
776 - <0x01c82000 0x1000>,
777 + <0x01c82000 0x2000>,
778 <0x01c84000 0x2000>,
779 <0x01c86000 0x2000>;
780 interrupt-controller;
781 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
782 +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
783 @@ -488,7 +488,7 @@
784 gic: interrupt-controller@01c81000 {
785 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
786 reg = <0x01c81000 0x1000>,
787 - <0x01c82000 0x1000>,
788 + <0x01c82000 0x2000>,
789 <0x01c84000 0x2000>,
790 <0x01c86000 0x2000>;
791 interrupt-controller;
792 --- a/arch/arm/boot/dts/sun9i-a80.dtsi
793 +++ b/arch/arm/boot/dts/sun9i-a80.dtsi
794 @@ -613,7 +613,7 @@
795 gic: interrupt-controller@01c41000 {
796 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
797 reg = <0x01c41000 0x1000>,
798 - <0x01c42000 0x1000>,
799 + <0x01c42000 0x2000>,
800 <0x01c44000 0x2000>,
801 <0x01c46000 0x2000>;
802 interrupt-controller;
803 --- a/arch/arm64/boot/dts/freescale/Makefile
804 +++ b/arch/arm64/boot/dts/freescale/Makefile
805 @@ -1,8 +1,25 @@
806 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
807 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
808 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
809 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-2g5rdb.dtb
810 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
811 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb
812 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
813 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb
814 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb
815 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
816 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb
817 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
818 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb
819 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb
820 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
821 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
822 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
823 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
824 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
825 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
826 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
827 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
828
829 always := $(dtb-y)
830 subdir-y := $(dts-dirs)
831 --- /dev/null
832 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
833 @@ -0,0 +1,123 @@
834 +/*
835 + * Device Tree file for NXP LS1012A 2G5RDB Board.
836 + *
837 + * Copyright 2017 NXP
838 + *
839 + * Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
840 + *
841 + * This file is dual-licensed: you can use it either under the terms
842 + * of the GPLv2 or the X11 license, at your option. Note that this dual
843 + * licensing only applies to this file, and not this project as a
844 + * whole.
845 + *
846 + * a) This library is free software; you can redistribute it and/or
847 + * modify it under the terms of the GNU General Public License as
848 + * published by the Free Software Foundation; either version 2 of the
849 + * License, or (at your option) any later version.
850 + *
851 + * This library is distributed in the hope that it will be useful,
852 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
853 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
854 + * GNU General Public License for more details.
855 + *
856 + * Or, alternatively,
857 + *
858 + * b) Permission is hereby granted, free of charge, to any person
859 + * obtaining a copy of this software and associated documentation
860 + * files (the "Software"), to deal in the Software without
861 + * restriction, including without limitation the rights to use,
862 + * copy, modify, merge, publish, distribute, sublicense, and/or
863 + * sell copies of the Software, and to permit persons to whom the
864 + * Software is furnished to do so, subject to the following
865 + * conditions:
866 + *
867 + * The above copyright notice and this permission notice shall be
868 + * included in all copies or substantial portions of the Software.
869 + *
870 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
871 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
872 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
873 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
874 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
875 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
876 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
877 + * OTHER DEALINGS IN THE SOFTWARE.
878 + */
879 +/dts-v1/;
880 +
881 +#include "fsl-ls1012a.dtsi"
882 +
883 +/ {
884 + model = "LS1012A 2G5RDB Board";
885 + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
886 +
887 + aliases {
888 + ethernet0 = &pfe_mac0;
889 + ethernet1 = &pfe_mac1;
890 + };
891 +};
892 +
893 +&duart0 {
894 + status = "okay";
895 +};
896 +
897 +&i2c0 {
898 + status = "okay";
899 +};
900 +
901 +&qspi {
902 + num-cs = <2>;
903 + bus-num = <0>;
904 + status = "okay";
905 +
906 + qflash0: s25fs512s@0 {
907 + compatible = "spansion,m25p80";
908 + #address-cells = <1>;
909 + #size-cells = <1>;
910 + spi-max-frequency = <20000000>;
911 + m25p,fast-read;
912 + reg = <0>;
913 + };
914 +};
915 +
916 +&sata {
917 + status = "okay";
918 +};
919 +
920 +&pfe {
921 + status = "okay";
922 + #address-cells = <1>;
923 + #size-cells = <0>;
924 +
925 + ethernet@0 {
926 + compatible = "fsl,pfe-gemac-port";
927 + #address-cells = <1>;
928 + #size-cells = <0>;
929 + reg = <0x0>; /* GEM_ID */
930 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
931 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
932 + fsl,mdio-mux-val = <0x0>;
933 + phy-mode = "sgmii-2500";
934 + fsl,pfe-phy-if-flags = <0x0>;
935 +
936 + mdio@0 {
937 + reg = <0x1>; /* enabled/disabled */
938 + };
939 + };
940 +
941 + ethernet@1 {
942 + compatible = "fsl,pfe-gemac-port";
943 + #address-cells = <1>;
944 + #size-cells = <0>;
945 + reg = <0x1>; /* GEM_ID */
946 + fsl,gemac-bus-id = < 0x0>; /* BUS_ID */
947 + fsl,gemac-phy-id = < 0x2>; /* PHY_ID */
948 + fsl,mdio-mux-val = <0x0>;
949 + phy-mode = "sgmii-2500";
950 + fsl,pfe-phy-if-flags = <0x0>;
951 +
952 + mdio@0 {
953 + reg = <0x0>; /* enabled/disabled */
954 + };
955 + };
956 +};
957 --- /dev/null
958 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
959 @@ -0,0 +1,177 @@
960 +/*
961 + * Device Tree file for Freescale LS1012A Freedom Board.
962 + *
963 + * Copyright 2016 Freescale Semiconductor, Inc.
964 + *
965 + * This file is dual-licensed: you can use it either under the terms
966 + * of the GPLv2 or the X11 license, at your option. Note that this dual
967 + * licensing only applies to this file, and not this project as a
968 + * whole.
969 + *
970 + * a) This library is free software; you can redistribute it and/or
971 + * modify it under the terms of the GNU General Public License as
972 + * published by the Free Software Foundation; either version 2 of the
973 + * License, or (at your option) any later version.
974 + *
975 + * This library is distributed in the hope that it will be useful,
976 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
977 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
978 + * GNU General Public License for more details.
979 + *
980 + * Or, alternatively,
981 + *
982 + * b) Permission is hereby granted, free of charge, to any person
983 + * obtaining a copy of this software and associated documentation
984 + * files (the "Software"), to deal in the Software without
985 + * restriction, including without limitation the rights to use,
986 + * copy, modify, merge, publish, distribute, sublicense, and/or
987 + * sell copies of the Software, and to permit persons to whom the
988 + * Software is furnished to do so, subject to the following
989 + * conditions:
990 + *
991 + * The above copyright notice and this permission notice shall be
992 + * included in all copies or substantial portions of the Software.
993 + *
994 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
995 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
996 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
997 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
998 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
999 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1000 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1001 + * OTHER DEALINGS IN THE SOFTWARE.
1002 + */
1003 +/dts-v1/;
1004 +
1005 +#include "fsl-ls1012a.dtsi"
1006 +
1007 +/ {
1008 + model = "LS1012A Freedom Board";
1009 + compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
1010 +
1011 + aliases {
1012 + ethernet0 = &pfe_mac0;
1013 + ethernet1 = &pfe_mac1;
1014 + };
1015 +
1016 + sys_mclk: clock-mclk {
1017 + compatible = "fixed-clock";
1018 + #clock-cells = <0>;
1019 + clock-frequency = <25000000>;
1020 + };
1021 +
1022 + reg_1p8v: regulator-1p8v {
1023 + compatible = "regulator-fixed";
1024 + regulator-name = "1P8V";
1025 + regulator-min-microvolt = <1800000>;
1026 + regulator-max-microvolt = <1800000>;
1027 + regulator-always-on;
1028 + };
1029 +
1030 + sound {
1031 + compatible = "simple-audio-card";
1032 + simple-audio-card,format = "i2s";
1033 + simple-audio-card,widgets =
1034 + "Microphone", "Microphone Jack",
1035 + "Headphone", "Headphone Jack",
1036 + "Speaker", "Speaker Ext",
1037 + "Line", "Line In Jack";
1038 + simple-audio-card,routing =
1039 + "MIC_IN", "Microphone Jack",
1040 + "Microphone Jack", "Mic Bias",
1041 + "LINE_IN", "Line In Jack",
1042 + "Headphone Jack", "HP_OUT",
1043 + "Speaker Ext", "LINE_OUT";
1044 +
1045 + simple-audio-card,cpu {
1046 + sound-dai = <&sai2>;
1047 + frame-master;
1048 + bitclock-master;
1049 + };
1050 +
1051 + simple-audio-card,codec {
1052 + sound-dai = <&codec>;
1053 + frame-master;
1054 + bitclock-master;
1055 + system-clock-frequency = <25000000>;
1056 + };
1057 + };
1058 +};
1059 +
1060 +&duart0 {
1061 + status = "okay";
1062 +};
1063 +
1064 +&i2c0 {
1065 + status = "okay";
1066 +
1067 + codec: sgtl5000@a {
1068 + #sound-dai-cells = <0>;
1069 + compatible = "fsl,sgtl5000";
1070 + reg = <0xa>;
1071 + VDDA-supply = <&reg_1p8v>;
1072 + VDDIO-supply = <&reg_1p8v>;
1073 + clocks = <&sys_mclk>;
1074 + };
1075 +};
1076 +
1077 +&qspi {
1078 + num-cs = <1>;
1079 + bus-num = <0>;
1080 + status = "okay";
1081 +
1082 + qflash0: s25fs512s@0 {
1083 + compatible = "spansion,m25p80";
1084 + #address-cells = <1>;
1085 + #size-cells = <1>;
1086 + m25p,fast-read;
1087 + spi-max-frequency = <20000000>;
1088 + reg = <0>;
1089 + };
1090 +};
1091 +
1092 +&pfe {
1093 + status = "okay";
1094 + #address-cells = <1>;
1095 + #size-cells = <0>;
1096 +
1097 + ethernet@0 {
1098 + compatible = "fsl,pfe-gemac-port";
1099 + #address-cells = <1>;
1100 + #size-cells = <0>;
1101 + reg = <0x0>; /* GEM_ID */
1102 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1103 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
1104 + fsl,mdio-mux-val = <0x0>;
1105 + phy-mode = "sgmii";
1106 + fsl,pfe-phy-if-flags = <0x0>;
1107 +
1108 + mdio@0 {
1109 + reg = <0x1>; /* enabled/disabled */
1110 + };
1111 + };
1112 +
1113 + ethernet@1 {
1114 + compatible = "fsl,pfe-gemac-port";
1115 + #address-cells = <1>;
1116 + #size-cells = <0>;
1117 + reg = <0x1>; /* GEM_ID */
1118 + fsl,gemac-bus-id = <0x1>; /* BUS_ID */
1119 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
1120 + fsl,mdio-mux-val = <0x0>;
1121 + phy-mode = "sgmii";
1122 + fsl,pfe-phy-if-flags = <0x0>;
1123 +
1124 + mdio@0 {
1125 + reg = <0x0>; /* enabled/disabled */
1126 + };
1127 + };
1128 +};
1129 +
1130 +&sai2 {
1131 + status = "okay";
1132 +};
1133 +
1134 +&sata {
1135 + status = "okay";
1136 +};
1137 --- /dev/null
1138 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
1139 @@ -0,0 +1,202 @@
1140 +/*
1141 + * Device Tree file for Freescale LS1012A QDS Board.
1142 + *
1143 + * Copyright 2016 Freescale Semiconductor, Inc.
1144 + *
1145 + * This file is dual-licensed: you can use it either under the terms
1146 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1147 + * licensing only applies to this file, and not this project as a
1148 + * whole.
1149 + *
1150 + * a) This library is free software; you can redistribute it and/or
1151 + * modify it under the terms of the GNU General Public License as
1152 + * published by the Free Software Foundation; either version 2 of the
1153 + * License, or (at your option) any later version.
1154 + *
1155 + * This library is distributed in the hope that it will be useful,
1156 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1157 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1158 + * GNU General Public License for more details.
1159 + *
1160 + * Or, alternatively,
1161 + *
1162 + * b) Permission is hereby granted, free of charge, to any person
1163 + * obtaining a copy of this software and associated documentation
1164 + * files (the "Software"), to deal in the Software without
1165 + * restriction, including without limitation the rights to use,
1166 + * copy, modify, merge, publish, distribute, sublicense, and/or
1167 + * sell copies of the Software, and to permit persons to whom the
1168 + * Software is furnished to do so, subject to the following
1169 + * conditions:
1170 + *
1171 + * The above copyright notice and this permission notice shall be
1172 + * included in all copies or substantial portions of the Software.
1173 + *
1174 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1175 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1176 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1177 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1178 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1179 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1180 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1181 + * OTHER DEALINGS IN THE SOFTWARE.
1182 + */
1183 +/dts-v1/;
1184 +
1185 +#include "fsl-ls1012a.dtsi"
1186 +
1187 +/ {
1188 + model = "LS1012A QDS Board";
1189 + compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
1190 +
1191 + aliases {
1192 + ethernet0 = &pfe_mac0;
1193 + ethernet1 = &pfe_mac1;
1194 + };
1195 +
1196 + sys_mclk: clock-mclk {
1197 + compatible = "fixed-clock";
1198 + #clock-cells = <0>;
1199 + clock-frequency = <24576000>;
1200 + };
1201 +
1202 + reg_3p3v: regulator-3p3v {
1203 + compatible = "regulator-fixed";
1204 + regulator-name = "3P3V";
1205 + regulator-min-microvolt = <3300000>;
1206 + regulator-max-microvolt = <3300000>;
1207 + regulator-always-on;
1208 + };
1209 +
1210 + sound {
1211 + compatible = "simple-audio-card";
1212 + simple-audio-card,format = "i2s";
1213 + simple-audio-card,widgets =
1214 + "Microphone", "Microphone Jack",
1215 + "Headphone", "Headphone Jack",
1216 + "Speaker", "Speaker Ext",
1217 + "Line", "Line In Jack";
1218 + simple-audio-card,routing =
1219 + "MIC_IN", "Microphone Jack",
1220 + "Microphone Jack", "Mic Bias",
1221 + "LINE_IN", "Line In Jack",
1222 + "Headphone Jack", "HP_OUT",
1223 + "Speaker Ext", "LINE_OUT";
1224 +
1225 + simple-audio-card,cpu {
1226 + sound-dai = <&sai2>;
1227 + frame-master;
1228 + bitclock-master;
1229 + };
1230 +
1231 + simple-audio-card,codec {
1232 + sound-dai = <&codec>;
1233 + frame-master;
1234 + bitclock-master;
1235 + system-clock-frequency = <24576000>;
1236 + };
1237 + };
1238 +};
1239 +
1240 +&pcie {
1241 + status = "okay";
1242 +};
1243 +
1244 +&duart0 {
1245 + status = "okay";
1246 +};
1247 +
1248 +&i2c0 {
1249 + status = "okay";
1250 +
1251 + pca9547@77 {
1252 + compatible = "nxp,pca9547";
1253 + reg = <0x77>;
1254 + #address-cells = <1>;
1255 + #size-cells = <0>;
1256 +
1257 + i2c@4 {
1258 + #address-cells = <1>;
1259 + #size-cells = <0>;
1260 + reg = <0x4>;
1261 +
1262 + codec: sgtl5000@a {
1263 + #sound-dai-cells = <0>;
1264 + compatible = "fsl,sgtl5000";
1265 + reg = <0xa>;
1266 + VDDA-supply = <&reg_3p3v>;
1267 + VDDIO-supply = <&reg_3p3v>;
1268 + clocks = <&sys_mclk>;
1269 + };
1270 + };
1271 + };
1272 +};
1273 +
1274 +&qspi {
1275 + num-cs = <2>;
1276 + bus-num = <0>;
1277 + status = "okay";
1278 +
1279 + qflash0: s25fs512s@0 {
1280 + compatible = "spansion,m25p80";
1281 + #address-cells = <1>;
1282 + #size-cells = <1>;
1283 + spi-max-frequency = <20000000>;
1284 + m25p,fast-read;
1285 + reg = <0>;
1286 + };
1287 +};
1288 +
1289 +&pfe {
1290 + status = "okay";
1291 + #address-cells = <1>;
1292 + #size-cells = <0>;
1293 +
1294 + ethernet@0 {
1295 + compatible = "fsl,pfe-gemac-port";
1296 + #address-cells = <1>;
1297 + #size-cells = <0>;
1298 + reg = <0x0>; /* GEM_ID */
1299 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1300 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
1301 + fsl,mdio-mux-val = <0x2>;
1302 + phy-mode = "sgmii-2500";
1303 + fsl,pfe-phy-if-flags = <0x0>;
1304 +
1305 + mdio@0 {
1306 + reg = <0x1>; /* enabled/disabled */
1307 + };
1308 + };
1309 +
1310 + ethernet@1 {
1311 + compatible = "fsl,pfe-gemac-port";
1312 + #address-cells = <1>;
1313 + #size-cells = <0>;
1314 + reg = <0x1>; /* GEM_ID */
1315 + fsl,gemac-bus-id = <0x1>; /* BUS_ID */
1316 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
1317 + fsl,mdio-mux-val = <0x3>;
1318 + phy-mode = "sgmii-2500";
1319 + fsl,pfe-phy-if-flags = <0x0>;
1320 +
1321 + mdio@0 {
1322 + reg = <0x0>; /* enabled/disabled */
1323 + };
1324 + };
1325 +};
1326 +
1327 +&sai2 {
1328 + status = "okay";
1329 +};
1330 +
1331 +&sata {
1332 + status = "okay";
1333 +};
1334 +
1335 +&esdhc0 {
1336 + status = "okay";
1337 +};
1338 +
1339 +&esdhc1 {
1340 + status = "okay";
1341 +};
1342 --- /dev/null
1343 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
1344 @@ -0,0 +1,138 @@
1345 +/*
1346 + * Device Tree file for Freescale LS1012A RDB Board.
1347 + *
1348 + * Copyright 2016 Freescale Semiconductor, Inc.
1349 + *
1350 + * This file is dual-licensed: you can use it either under the terms
1351 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1352 + * licensing only applies to this file, and not this project as a
1353 + * whole.
1354 + *
1355 + * a) This library is free software; you can redistribute it and/or
1356 + * modify it under the terms of the GNU General Public License as
1357 + * published by the Free Software Foundation; either version 2 of the
1358 + * License, or (at your option) any later version.
1359 + *
1360 + * This library is distributed in the hope that it will be useful,
1361 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1362 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1363 + * GNU General Public License for more details.
1364 + *
1365 + * Or, alternatively,
1366 + *
1367 + * b) Permission is hereby granted, free of charge, to any person
1368 + * obtaining a copy of this software and associated documentation
1369 + * files (the "Software"), to deal in the Software without
1370 + * restriction, including without limitation the rights to use,
1371 + * copy, modify, merge, publish, distribute, sublicense, and/or
1372 + * sell copies of the Software, and to permit persons to whom the
1373 + * Software is furnished to do so, subject to the following
1374 + * conditions:
1375 + *
1376 + * The above copyright notice and this permission notice shall be
1377 + * included in all copies or substantial portions of the Software.
1378 + *
1379 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1380 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1381 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1382 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1383 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1384 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1385 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1386 + * OTHER DEALINGS IN THE SOFTWARE.
1387 + */
1388 +/dts-v1/;
1389 +
1390 +#include "fsl-ls1012a.dtsi"
1391 +
1392 +/ {
1393 + model = "LS1012A RDB Board";
1394 + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
1395 +
1396 + aliases {
1397 + ethernet0 = &pfe_mac0;
1398 + ethernet1 = &pfe_mac1;
1399 + };
1400 +};
1401 +
1402 +&pcie {
1403 + status = "okay";
1404 +};
1405 +
1406 +&duart0 {
1407 + status = "okay";
1408 +};
1409 +
1410 +&i2c0 {
1411 + status = "okay";
1412 +};
1413 +
1414 +&qspi {
1415 + num-cs = <2>;
1416 + bus-num = <0>;
1417 + status = "okay";
1418 +
1419 + qflash0: s25fs512s@0 {
1420 + compatible = "spansion,m25p80";
1421 + #address-cells = <1>;
1422 + #size-cells = <1>;
1423 + spi-max-frequency = <20000000>;
1424 + m25p,fast-read;
1425 + reg = <0>;
1426 + };
1427 +};
1428 +
1429 +&sata {
1430 + status = "okay";
1431 +};
1432 +
1433 +&esdhc0 {
1434 + sd-uhs-sdr104;
1435 + sd-uhs-sdr50;
1436 + sd-uhs-sdr25;
1437 + sd-uhs-sdr12;
1438 + status = "okay";
1439 +};
1440 +
1441 +&esdhc1 {
1442 + mmc-hs200-1_8v;
1443 + status = "okay";
1444 +};
1445 +
1446 +&pfe {
1447 + status = "okay";
1448 + #address-cells = <1>;
1449 + #size-cells = <0>;
1450 +
1451 + ethernet@0 {
1452 + compatible = "fsl,pfe-gemac-port";
1453 + #address-cells = <1>;
1454 + #size-cells = <0>;
1455 + reg = <0x0>; /* GEM_ID */
1456 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1457 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
1458 + fsl,mdio-mux-val = <0x0>;
1459 + phy-mode = "sgmii";
1460 + fsl,pfe-phy-if-flags = <0x0>;
1461 +
1462 + mdio@0 {
1463 + reg = <0x1>; /* enabled/disabled */
1464 + };
1465 + };
1466 +
1467 + ethernet@1 {
1468 + compatible = "fsl,pfe-gemac-port";
1469 + #address-cells = <1>;
1470 + #size-cells = <0>;
1471 + reg = <0x1>; /* GEM_ID */
1472 + fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
1473 + fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
1474 + fsl,mdio-mux-val = <0x0>;
1475 + phy-mode = "rgmii-txid";
1476 + fsl,pfe-phy-if-flags = <0x0>;
1477 +
1478 + mdio@0 {
1479 + reg = <0x0>; /* enabled/disabled */
1480 + };
1481 + };
1482 +};
1483 --- /dev/null
1484 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
1485 @@ -0,0 +1,602 @@
1486 +/*
1487 + * Device Tree Include file for Freescale Layerscape-1012A family SoC.
1488 + *
1489 + * Copyright 2016 Freescale Semiconductor, Inc.
1490 + *
1491 + * This file is dual-licensed: you can use it either under the terms
1492 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1493 + * licensing only applies to this file, and not this project as a
1494 + * whole.
1495 + *
1496 + * a) This library is free software; you can redistribute it and/or
1497 + * modify it under the terms of the GNU General Public License as
1498 + * published by the Free Software Foundation; either version 2 of the
1499 + * License, or (at your option) any later version.
1500 + *
1501 + * This library is distributed in the hope that it will be useful,
1502 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1503 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1504 + * GNU General Public License for more details.
1505 + *
1506 + * Or, alternatively,
1507 + *
1508 + * b) Permission is hereby granted, free of charge, to any person
1509 + * obtaining a copy of this software and associated documentation
1510 + * files (the "Software"), to deal in the Software without
1511 + * restriction, including without limitation the rights to use,
1512 + * copy, modify, merge, publish, distribute, sublicense, and/or
1513 + * sell copies of the Software, and to permit persons to whom the
1514 + * Software is furnished to do so, subject to the following
1515 + * conditions:
1516 + *
1517 + * The above copyright notice and this permission notice shall be
1518 + * included in all copies or substantial portions of the Software.
1519 + *
1520 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1521 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1522 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1523 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1524 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1525 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1526 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1527 + * OTHER DEALINGS IN THE SOFTWARE.
1528 + */
1529 +
1530 +#include <dt-bindings/interrupt-controller/arm-gic.h>
1531 +#include <dt-bindings/thermal/thermal.h>
1532 +
1533 +/ {
1534 + compatible = "fsl,ls1012a";
1535 + interrupt-parent = <&gic>;
1536 + #address-cells = <2>;
1537 + #size-cells = <2>;
1538 +
1539 + aliases {
1540 + crypto = &crypto;
1541 + rtic_a = &rtic_a;
1542 + rtic_b = &rtic_b;
1543 + rtic_c = &rtic_c;
1544 + rtic_d = &rtic_d;
1545 + sec_mon = &sec_mon;
1546 + };
1547 +
1548 + cpus {
1549 + #address-cells = <1>;
1550 + #size-cells = <0>;
1551 +
1552 + cpu0: cpu@0 {
1553 + device_type = "cpu";
1554 + compatible = "arm,cortex-a53";
1555 + reg = <0x0>;
1556 + clocks = <&clockgen 1 0>;
1557 + #cooling-cells = <2>;
1558 + cpu-idle-states = <&CPU_PH20>;
1559 + };
1560 + };
1561 +
1562 + idle-states {
1563 + /*
1564 + * PSCI node is not added default, U-boot will add missing
1565 + * parts if it determines to use PSCI.
1566 + */
1567 + entry-method = "arm,psci";
1568 +
1569 + CPU_PH20: cpu-ph20 {
1570 + compatible = "arm,idle-state";
1571 + idle-state-name = "PH20";
1572 + arm,psci-suspend-param = <0x0>;
1573 + entry-latency-us = <1000>;
1574 + exit-latency-us = <1000>;
1575 + min-residency-us = <3000>;
1576 + };
1577 + };
1578 +
1579 + sysclk: sysclk {
1580 + compatible = "fixed-clock";
1581 + #clock-cells = <0>;
1582 + clock-frequency = <125000000>;
1583 + clock-output-names = "sysclk";
1584 + };
1585 +
1586 + coreclk: coreclk {
1587 + compatible = "fixed-clock";
1588 + #clock-cells = <0>;
1589 + clock-frequency = <100000000>;
1590 + clock-output-names = "coreclk";
1591 + };
1592 +
1593 + timer {
1594 + compatible = "arm,armv8-timer";
1595 + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
1596 + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
1597 + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
1598 + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
1599 + };
1600 +
1601 + pmu {
1602 + compatible = "arm,armv8-pmuv3";
1603 + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
1604 + };
1605 +
1606 + gic: interrupt-controller@1400000 {
1607 + compatible = "arm,gic-400";
1608 + #interrupt-cells = <3>;
1609 + interrupt-controller;
1610 + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
1611 + <0x0 0x1402000 0 0x2000>, /* GICC */
1612 + <0x0 0x1404000 0 0x2000>, /* GICH */
1613 + <0x0 0x1406000 0 0x2000>; /* GICV */
1614 + interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
1615 + };
1616 +
1617 + reboot {
1618 + compatible = "syscon-reboot";
1619 + regmap = <&dcfg>;
1620 + offset = <0xb0>;
1621 + mask = <0x02>;
1622 + };
1623 +
1624 + soc {
1625 + compatible = "simple-bus";
1626 + #address-cells = <2>;
1627 + #size-cells = <2>;
1628 + ranges;
1629 +
1630 + scfg: scfg@1570000 {
1631 + compatible = "fsl,ls1012a-scfg", "syscon";
1632 + reg = <0x0 0x1570000 0x0 0x10000>;
1633 + big-endian;
1634 + };
1635 +
1636 + crypto: crypto@1700000 {
1637 + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
1638 + "fsl,sec-v4.0";
1639 + fsl,sec-era = <8>;
1640 + #address-cells = <1>;
1641 + #size-cells = <1>;
1642 + ranges = <0x0 0x00 0x1700000 0x100000>;
1643 + reg = <0x00 0x1700000 0x0 0x100000>;
1644 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1645 +
1646 + sec_jr0: jr@10000 {
1647 + compatible = "fsl,sec-v5.4-job-ring",
1648 + "fsl,sec-v5.0-job-ring",
1649 + "fsl,sec-v4.0-job-ring";
1650 + reg = <0x10000 0x10000>;
1651 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1652 + };
1653 +
1654 + sec_jr1: jr@20000 {
1655 + compatible = "fsl,sec-v5.4-job-ring",
1656 + "fsl,sec-v5.0-job-ring",
1657 + "fsl,sec-v4.0-job-ring";
1658 + reg = <0x20000 0x10000>;
1659 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1660 + };
1661 +
1662 + sec_jr2: jr@30000 {
1663 + compatible = "fsl,sec-v5.4-job-ring",
1664 + "fsl,sec-v5.0-job-ring",
1665 + "fsl,sec-v4.0-job-ring";
1666 + reg = <0x30000 0x10000>;
1667 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1668 + };
1669 +
1670 + sec_jr3: jr@40000 {
1671 + compatible = "fsl,sec-v5.4-job-ring",
1672 + "fsl,sec-v5.0-job-ring",
1673 + "fsl,sec-v4.0-job-ring";
1674 + reg = <0x40000 0x10000>;
1675 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1676 + };
1677 +
1678 + caam-dma {
1679 + compatible = "fsl,sec-v5.4-dma",
1680 + "fsl,sec-v5.0-dma",
1681 + "fsl,sec-v4.0-dma";
1682 + };
1683 +
1684 + rtic@60000 {
1685 + compatible = "fsl,sec-v5.4-rtic",
1686 + "fsl,sec-v5.0-rtic",
1687 + "fsl,sec-v4.0-rtic";
1688 + #address-cells = <1>;
1689 + #size-cells = <1>;
1690 + reg = <0x60000 0x100 0x60e00 0x18>;
1691 + ranges = <0x0 0x60100 0x500>;
1692 +
1693 + rtic_a: rtic-a@0 {
1694 + compatible = "fsl,sec-v5.4-rtic-memory",
1695 + "fsl,sec-v5.0-rtic-memory",
1696 + "fsl,sec-v4.0-rtic-memory";
1697 + reg = <0x00 0x20 0x100 0x100>;
1698 + };
1699 +
1700 + rtic_b: rtic-b@20 {
1701 + compatible = "fsl,sec-v5.4-rtic-memory",
1702 + "fsl,sec-v5.0-rtic-memory",
1703 + "fsl,sec-v4.0-rtic-memory";
1704 + reg = <0x20 0x20 0x200 0x100>;
1705 + };
1706 +
1707 + rtic_c: rtic-c@40 {
1708 + compatible = "fsl,sec-v5.4-rtic-memory",
1709 + "fsl,sec-v5.0-rtic-memory",
1710 + "fsl,sec-v4.0-rtic-memory";
1711 + reg = <0x40 0x20 0x300 0x100>;
1712 + };
1713 +
1714 + rtic_d: rtic-d@60 {
1715 + compatible = "fsl,sec-v5.4-rtic-memory",
1716 + "fsl,sec-v5.0-rtic-memory",
1717 + "fsl,sec-v4.0-rtic-memory";
1718 + reg = <0x60 0x20 0x400 0x100>;
1719 + };
1720 + };
1721 + };
1722 +
1723 + sec_mon: sec_mon@1e90000 {
1724 + compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
1725 + "fsl,sec-v4.0-mon";
1726 + reg = <0x0 0x1e90000 0x0 0x10000>;
1727 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
1728 + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1729 + };
1730 +
1731 + dcfg: dcfg@1ee0000 {
1732 + compatible = "fsl,ls1012a-dcfg",
1733 + "syscon";
1734 + reg = <0x0 0x1ee0000 0x0 0x10000>;
1735 + big-endian;
1736 + };
1737 +
1738 + clockgen: clocking@1ee1000 {
1739 + compatible = "fsl,ls1012a-clockgen";
1740 + reg = <0x0 0x1ee1000 0x0 0x1000>;
1741 + #clock-cells = <2>;
1742 + clocks = <&sysclk &coreclk>;
1743 + clock-names = "sysclk", "coreclk";
1744 + };
1745 +
1746 + tmu: tmu@1f00000 {
1747 + compatible = "fsl,qoriq-tmu";
1748 + reg = <0x0 0x1f00000 0x0 0x10000>;
1749 + interrupts = <0 33 0x4>;
1750 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
1751 + fsl,tmu-calibration = <0x00000000 0x00000026
1752 + 0x00000001 0x0000002d
1753 + 0x00000002 0x00000032
1754 + 0x00000003 0x00000039
1755 + 0x00000004 0x0000003f
1756 + 0x00000005 0x00000046
1757 + 0x00000006 0x0000004d
1758 + 0x00000007 0x00000054
1759 + 0x00000008 0x0000005a
1760 + 0x00000009 0x00000061
1761 + 0x0000000a 0x0000006a
1762 + 0x0000000b 0x00000071
1763 +
1764 + 0x00010000 0x00000025
1765 + 0x00010001 0x0000002c
1766 + 0x00010002 0x00000035
1767 + 0x00010003 0x0000003d
1768 + 0x00010004 0x00000045
1769 + 0x00010005 0x0000004e
1770 + 0x00010006 0x00000057
1771 + 0x00010007 0x00000061
1772 + 0x00010008 0x0000006b
1773 + 0x00010009 0x00000076
1774 +
1775 + 0x00020000 0x00000029
1776 + 0x00020001 0x00000033
1777 + 0x00020002 0x0000003d
1778 + 0x00020003 0x00000049
1779 + 0x00020004 0x00000056
1780 + 0x00020005 0x00000061
1781 + 0x00020006 0x0000006d
1782 +
1783 + 0x00030000 0x00000021
1784 + 0x00030001 0x0000002a
1785 + 0x00030002 0x0000003c
1786 + 0x00030003 0x0000004e>;
1787 + big-endian;
1788 + #thermal-sensor-cells = <1>;
1789 + };
1790 +
1791 + thermal-zones {
1792 + cpu_thermal: cpu-thermal {
1793 + polling-delay-passive = <1000>;
1794 + polling-delay = <5000>;
1795 + thermal-sensors = <&tmu 0>;
1796 +
1797 + trips {
1798 + cpu_alert: cpu-alert {
1799 + temperature = <85000>;
1800 + hysteresis = <2000>;
1801 + type = "passive";
1802 + };
1803 +
1804 + cpu_crit: cpu-crit {
1805 + temperature = <95000>;
1806 + hysteresis = <2000>;
1807 + type = "critical";
1808 + };
1809 + };
1810 +
1811 + cooling-maps {
1812 + map0 {
1813 + trip = <&cpu_alert>;
1814 + cooling-device =
1815 + <&cpu0 THERMAL_NO_LIMIT
1816 + THERMAL_NO_LIMIT>;
1817 + };
1818 + };
1819 + };
1820 + };
1821 +
1822 + esdhc0: esdhc@1560000 {
1823 + compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
1824 + reg = <0x0 0x1560000 0x0 0x10000>;
1825 + interrupts = <0 62 0x4>;
1826 + clocks = <&clockgen 4 0>;
1827 + voltage-ranges = <1800 1800 3300 3300>;
1828 + sdhci,auto-cmd12;
1829 + big-endian;
1830 + bus-width = <4>;
1831 + status = "disabled";
1832 + };
1833 +
1834 + esdhc1: esdhc@1580000 {
1835 + compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
1836 + reg = <0x0 0x1580000 0x0 0x10000>;
1837 + interrupts = <0 65 0x4>;
1838 + clocks = <&clockgen 4 0>;
1839 + voltage-ranges = <1800 1800 3300 3300>;
1840 + sdhci,auto-cmd12;
1841 + big-endian;
1842 + broken-cd;
1843 + bus-width = <4>;
1844 + status = "disabled";
1845 + };
1846 +
1847 + rcpm: rcpm@1ee2000 {
1848 + compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1";
1849 + reg = <0x0 0x1ee2000 0x0 0x1000>;
1850 + fsl,#rcpm-wakeup-cells = <1>;
1851 + };
1852 +
1853 + ftm0: ftm0@29d0000 {
1854 + compatible = "fsl,ls1012a-ftm";
1855 + reg = <0x0 0x29d0000 0x0 0x10000>,
1856 + <0x0 0x1ee2140 0x0 0x4>;
1857 + reg-names = "ftm", "FlexTimer1";
1858 + interrupts = <0 86 0x4>;
1859 + big-endian;
1860 + };
1861 +
1862 + i2c0: i2c@2180000 {
1863 + compatible = "fsl,vf610-i2c";
1864 + #address-cells = <1>;
1865 + #size-cells = <0>;
1866 + reg = <0x0 0x2180000 0x0 0x10000>;
1867 + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
1868 + clocks = <&clockgen 4 3>;
1869 + status = "disabled";
1870 + };
1871 +
1872 + i2c1: i2c@2190000 {
1873 + compatible = "fsl,vf610-i2c";
1874 + #address-cells = <1>;
1875 + #size-cells = <0>;
1876 + reg = <0x0 0x2190000 0x0 0x10000>;
1877 + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
1878 + clocks = <&clockgen 4 3>;
1879 + status = "disabled";
1880 + };
1881 +
1882 + duart0: serial@21c0500 {
1883 + compatible = "fsl,ns16550", "ns16550a";
1884 + reg = <0x00 0x21c0500 0x0 0x100>;
1885 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
1886 + clocks = <&clockgen 4 0>;
1887 + status = "disabled";
1888 + };
1889 +
1890 + duart1: serial@21c0600 {
1891 + compatible = "fsl,ns16550", "ns16550a";
1892 + reg = <0x00 0x21c0600 0x0 0x100>;
1893 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
1894 + clocks = <&clockgen 4 0>;
1895 + status = "disabled";
1896 + };
1897 +
1898 + gpio0: gpio@2300000 {
1899 + compatible = "fsl,qoriq-gpio";
1900 + reg = <0x0 0x2300000 0x0 0x10000>;
1901 + interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
1902 + gpio-controller;
1903 + #gpio-cells = <2>;
1904 + interrupt-controller;
1905 + #interrupt-cells = <2>;
1906 + };
1907 +
1908 + gpio1: gpio@2310000 {
1909 + compatible = "fsl,qoriq-gpio";
1910 + reg = <0x0 0x2310000 0x0 0x10000>;
1911 + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
1912 + gpio-controller;
1913 + #gpio-cells = <2>;
1914 + interrupt-controller;
1915 + #interrupt-cells = <2>;
1916 + };
1917 +
1918 + qspi: quadspi@1550000 {
1919 + compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
1920 + #address-cells = <1>;
1921 + #size-cells = <0>;
1922 + reg = <0x0 0x1550000 0x0 0x10000>,
1923 + <0x0 0x40000000 0x0 0x10000000>;
1924 + reg-names = "QuadSPI", "QuadSPI-memory";
1925 + interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
1926 + clock-names = "qspi_en", "qspi";
1927 + clocks = <&clockgen 4 0>, <&clockgen 4 0>;
1928 + big-endian;
1929 + fsl,qspi-has-second-chip;
1930 + status = "disabled";
1931 + };
1932 +
1933 + wdog0: wdog@2ad0000 {
1934 + compatible = "fsl,ls1012a-wdt",
1935 + "fsl,imx21-wdt";
1936 + reg = <0x0 0x2ad0000 0x0 0x10000>;
1937 + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
1938 + clocks = <&clockgen 4 0>;
1939 + big-endian;
1940 + };
1941 +
1942 + sai1: sai@2b50000 {
1943 + #sound-dai-cells = <0>;
1944 + compatible = "fsl,vf610-sai";
1945 + reg = <0x0 0x2b50000 0x0 0x10000>;
1946 + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
1947 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
1948 + <&clockgen 4 3>, <&clockgen 4 3>;
1949 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
1950 + dma-names = "tx", "rx";
1951 + dmas = <&edma0 1 47>,
1952 + <&edma0 1 46>;
1953 + status = "disabled";
1954 + };
1955 +
1956 + sai2: sai@2b60000 {
1957 + #sound-dai-cells = <0>;
1958 + compatible = "fsl,vf610-sai";
1959 + reg = <0x0 0x2b60000 0x0 0x10000>;
1960 + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
1961 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
1962 + <&clockgen 4 3>, <&clockgen 4 3>;
1963 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
1964 + dma-names = "tx", "rx";
1965 + dmas = <&edma0 1 45>,
1966 + <&edma0 1 44>;
1967 + status = "disabled";
1968 + };
1969 +
1970 + edma0: edma@2c00000 {
1971 + #dma-cells = <2>;
1972 + compatible = "fsl,vf610-edma";
1973 + reg = <0x0 0x2c00000 0x0 0x10000>,
1974 + <0x0 0x2c10000 0x0 0x10000>,
1975 + <0x0 0x2c20000 0x0 0x10000>;
1976 + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
1977 + <0 103 IRQ_TYPE_LEVEL_HIGH>;
1978 + interrupt-names = "edma-tx", "edma-err";
1979 + dma-channels = <32>;
1980 + big-endian;
1981 + clock-names = "dmamux0", "dmamux1";
1982 + clocks = <&clockgen 4 3>,
1983 + <&clockgen 4 3>;
1984 + };
1985 +
1986 + usb0: usb3@2f00000 {
1987 + compatible = "snps,dwc3";
1988 + reg = <0x0 0x2f00000 0x0 0x10000>;
1989 + interrupts = <0 60 0x4>;
1990 + dr_mode = "host";
1991 + snps,quirk-frame-length-adjustment = <0x20>;
1992 + snps,dis_rxdet_inp3_quirk;
1993 + };
1994 +
1995 + usb1: usb2@8600000 {
1996 + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
1997 + reg = <0x0 0x8600000 0x0 0x1000>;
1998 + interrupts = <0 139 0x4>;
1999 + dr_mode = "host";
2000 + phy_type = "ulpi";
2001 + };
2002 +
2003 + sata: sata@3200000 {
2004 + compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
2005 + reg = <0x0 0x3200000 0x0 0x10000>,
2006 + <0x0 0x20140520 0x0 0x4>;
2007 + reg-names = "ahci", "sata-ecc";
2008 + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
2009 + clocks = <&clockgen 4 0>;
2010 + dma-coherent;
2011 + status = "disabled";
2012 + };
2013 +
2014 + msi: msi-controller1@1572000 {
2015 + compatible = "fsl,ls1012a-msi";
2016 + reg = <0x0 0x1572000 0x0 0x8>;
2017 + msi-controller;
2018 + interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
2019 + };
2020 +
2021 + pcie: pcie@3400000 {
2022 + compatible = "fsl,ls1012a-pcie", "snps,dw-pcie";
2023 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
2024 + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
2025 + reg-names = "regs", "config";
2026 + interrupts = <0 118 0x4>, /* AER interrupt */
2027 + <0 117 0x4>; /* PME interrupt */
2028 + interrupt-names = "aer", "pme";
2029 + #address-cells = <3>;
2030 + #size-cells = <2>;
2031 + device_type = "pci";
2032 + num-lanes = <4>;
2033 + bus-range = <0x0 0xff>;
2034 + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
2035 + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
2036 + msi-parent = <&msi>;
2037 + #interrupt-cells = <1>;
2038 + interrupt-map-mask = <0 0 0 7>;
2039 + interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
2040 + <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
2041 + <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
2042 + <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
2043 + status = "disabled";
2044 + };
2045 + };
2046 +
2047 + reserved-memory {
2048 + #address-cells = <2>;
2049 + #size-cells = <2>;
2050 + ranges;
2051 +
2052 + pfe_reserved: packetbuffer@83400000 {
2053 + reg = <0 0x83400000 0 0xc00000>;
2054 + };
2055 + };
2056 +
2057 + pfe: pfe@04000000 {
2058 + compatible = "fsl,pfe";
2059 + reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
2060 + <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
2061 + reg-names = "pfe", "pfe-ddr";
2062 + fsl,pfe-num-interfaces = <0x2>;
2063 + interrupts = <0 172 0x4>, /* HIF interrupt */
2064 + <0 173 0x4>, /*HIF_NOCPY interrupt */
2065 + <0 174 0x4>; /* WoL interrupt */
2066 + interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
2067 + memory-region = <&pfe_reserved>;
2068 + fsl,pfe-scfg = <&scfg 0>;
2069 + fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
2070 + clocks = <&clockgen 4 0>;
2071 + clock-names = "pfe";
2072 +
2073 + status = "okay";
2074 + pfe_mac0: ethernet@0 {
2075 + };
2076 +
2077 + pfe_mac1: ethernet@1 {
2078 + };
2079 + };
2080 +
2081 + firmware {
2082 + optee {
2083 + compatible = "linaro,optee-tz";
2084 + method = "smc";
2085 + };
2086 + };
2087 +};
2088 --- /dev/null
2089 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
2090 @@ -0,0 +1,45 @@
2091 +/*
2092 + * QorIQ FMan v3 device tree nodes for ls1043
2093 + *
2094 + * Copyright 2015-2016 Freescale Semiconductor Inc.
2095 + *
2096 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2097 + */
2098 +
2099 +&soc {
2100 +
2101 +/* include used FMan blocks */
2102 +#include "qoriq-fman3-0.dtsi"
2103 +#include "qoriq-fman3-0-1g-0.dtsi"
2104 +#include "qoriq-fman3-0-1g-1.dtsi"
2105 +#include "qoriq-fman3-0-1g-2.dtsi"
2106 +#include "qoriq-fman3-0-1g-3.dtsi"
2107 +#include "qoriq-fman3-0-1g-4.dtsi"
2108 +#include "qoriq-fman3-0-1g-5.dtsi"
2109 +#include "qoriq-fman3-0-10g-0.dtsi"
2110 +
2111 +};
2112 +
2113 +&fman0 {
2114 + /* these aliases provide the FMan ports mapping */
2115 + enet0: ethernet@e0000 {
2116 + };
2117 +
2118 + enet1: ethernet@e2000 {
2119 + };
2120 +
2121 + enet2: ethernet@e4000 {
2122 + };
2123 +
2124 + enet3: ethernet@e6000 {
2125 + };
2126 +
2127 + enet4: ethernet@e8000 {
2128 + };
2129 +
2130 + enet5: ethernet@ea000 {
2131 + };
2132 +
2133 + enet6: ethernet@f0000 {
2134 + };
2135 +};
2136 --- /dev/null
2137 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
2138 @@ -0,0 +1,69 @@
2139 +/*
2140 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2141 + *
2142 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2143 + *
2144 + * Mingkai Hu <Mingkai.hu@freescale.com>
2145 + *
2146 + * This file is dual-licensed: you can use it either under the terms
2147 + * of the GPLv2 or the X11 license, at your option. Note that this dual
2148 + * licensing only applies to this file, and not this project as a
2149 + * whole.
2150 + *
2151 + * a) This library is free software; you can redistribute it and/or
2152 + * modify it under the terms of the GNU General Public License as
2153 + * published by the Free Software Foundation; either version 2 of the
2154 + * License, or (at your option) any later version.
2155 + *
2156 + * This library is distributed in the hope that it will be useful,
2157 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2158 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2159 + * GNU General Public License for more details.
2160 + *
2161 + * Or, alternatively,
2162 + *
2163 + * b) Permission is hereby granted, free of charge, to any person
2164 + * obtaining a copy of this software and associated documentation
2165 + * files (the "Software"), to deal in the Software without
2166 + * restriction, including without limitation the rights to use,
2167 + * copy, modify, merge, publish, distribute, sublicense, and/or
2168 + * sell copies of the Software, and to permit persons to whom the
2169 + * Software is furnished to do so, subject to the following
2170 + * conditions:
2171 + *
2172 + * The above copyright notice and this permission notice shall be
2173 + * included in all copies or substantial portions of the Software.
2174 + *
2175 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
2176 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
2177 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2178 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
2179 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
2180 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2181 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2182 + * OTHER DEALINGS IN THE SOFTWARE.
2183 + */
2184 +
2185 +#include "fsl-ls1043a-qds.dts"
2186 +
2187 +&bman_fbpr {
2188 + compatible = "fsl,bman-fbpr";
2189 + alloc-ranges = <0 0 0x10000 0>;
2190 +};
2191 +&qman_fqd {
2192 + compatible = "fsl,qman-fqd";
2193 + alloc-ranges = <0 0 0x10000 0>;
2194 +};
2195 +&qman_pfdr {
2196 + compatible = "fsl,qman-pfdr";
2197 + alloc-ranges = <0 0 0x10000 0>;
2198 +};
2199 +
2200 +&soc {
2201 +#include "qoriq-dpaa-eth.dtsi"
2202 +#include "qoriq-fman3-0-6oh.dtsi"
2203 +};
2204 +
2205 +&fman0 {
2206 + compatible = "fsl,fman", "simple-bus";
2207 +};
2208 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
2209 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
2210 @@ -1,7 +1,7 @@
2211 /*
2212 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2213 *
2214 - * Copyright 2014-2015, Freescale Semiconductor
2215 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2216 *
2217 * Mingkai Hu <Mingkai.hu@freescale.com>
2218 *
2219 @@ -45,7 +45,7 @@
2220 */
2221
2222 /dts-v1/;
2223 -/include/ "fsl-ls1043a.dtsi"
2224 +#include "fsl-ls1043a.dtsi"
2225
2226 / {
2227 model = "LS1043A QDS Board";
2228 @@ -60,6 +60,22 @@
2229 serial1 = &duart1;
2230 serial2 = &duart2;
2231 serial3 = &duart3;
2232 + sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
2233 + sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
2234 + sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
2235 + sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
2236 + qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
2237 + qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
2238 + qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
2239 + qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
2240 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
2241 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
2242 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
2243 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
2244 + emi1_slot1 = &ls1043mdio_s1;
2245 + emi1_slot2 = &ls1043mdio_s2;
2246 + emi1_slot3 = &ls1043mdio_s3;
2247 + emi1_slot4 = &ls1043mdio_s4;
2248 };
2249
2250 chosen {
2251 @@ -97,8 +113,11 @@
2252 };
2253
2254 fpga: board-control@2,0 {
2255 - compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
2256 + #address-cells = <1>;
2257 + #size-cells = <1>;
2258 + compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-bus";
2259 reg = <0x2 0x0 0x0000100>;
2260 + ranges = <0 2 0 0x100>;
2261 };
2262 };
2263
2264 @@ -181,3 +200,149 @@
2265 reg = <0>;
2266 };
2267 };
2268 +
2269 +#include "fsl-ls1043-post.dtsi"
2270 +
2271 +&fman0 {
2272 + ethernet@e0000 {
2273 + phy-handle = <&qsgmii_phy_s2_p1>;
2274 + phy-connection-type = "sgmii";
2275 + };
2276 +
2277 + ethernet@e2000 {
2278 + phy-handle = <&qsgmii_phy_s2_p2>;
2279 + phy-connection-type = "sgmii";
2280 + };
2281 +
2282 + ethernet@e4000 {
2283 + phy-handle = <&rgmii_phy1>;
2284 + phy-connection-type = "rgmii";
2285 + };
2286 +
2287 + ethernet@e6000 {
2288 + phy-handle = <&rgmii_phy2>;
2289 + phy-connection-type = "rgmii";
2290 + };
2291 +
2292 + ethernet@e8000 {
2293 + phy-handle = <&qsgmii_phy_s2_p3>;
2294 + phy-connection-type = "sgmii";
2295 + };
2296 +
2297 + ethernet@ea000 {
2298 + phy-handle = <&qsgmii_phy_s2_p4>;
2299 + phy-connection-type = "sgmii";
2300 + };
2301 +
2302 + ethernet@f0000 { /* DTSEC9/10GEC1 */
2303 + fixed-link = <1 1 10000 0 0>;
2304 + phy-connection-type = "xgmii";
2305 + };
2306 +};
2307 +
2308 +&fpga {
2309 + mdio-mux-emi1 {
2310 + compatible = "mdio-mux-mmioreg", "mdio-mux";
2311 + mdio-parent-bus = <&mdio0>;
2312 + #address-cells = <1>;
2313 + #size-cells = <0>;
2314 + reg = <0x54 1>; /* BRDCFG4 */
2315 + mux-mask = <0xe0>; /* EMI1 */
2316 +
2317 + /* On-board RGMII1 PHY */
2318 + ls1043mdio0: mdio@0 {
2319 + reg = <0>;
2320 + #address-cells = <1>;
2321 + #size-cells = <0>;
2322 +
2323 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
2324 + reg = <0x1>;
2325 + };
2326 + };
2327 +
2328 + /* On-board RGMII2 PHY */
2329 + ls1043mdio1: mdio@1 {
2330 + reg = <0x20>;
2331 + #address-cells = <1>;
2332 + #size-cells = <0>;
2333 +
2334 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
2335 + reg = <0x2>;
2336 + };
2337 + };
2338 +
2339 + /* Slot 1 */
2340 + ls1043mdio_s1: mdio@2 {
2341 + reg = <0x40>;
2342 + #address-cells = <1>;
2343 + #size-cells = <0>;
2344 + status = "disabled";
2345 +
2346 + qsgmii_phy_s1_p1: ethernet-phy@4 {
2347 + reg = <0x4>;
2348 + };
2349 + qsgmii_phy_s1_p2: ethernet-phy@5 {
2350 + reg = <0x5>;
2351 + };
2352 + qsgmii_phy_s1_p3: ethernet-phy@6 {
2353 + reg = <0x6>;
2354 + };
2355 + qsgmii_phy_s1_p4: ethernet-phy@7 {
2356 + reg = <0x7>;
2357 + };
2358 +
2359 + sgmii_phy_s1_p1: ethernet-phy@1c {
2360 + reg = <0x1c>;
2361 + };
2362 + };
2363 +
2364 + /* Slot 2 */
2365 + ls1043mdio_s2: mdio@3 {
2366 + reg = <0x60>;
2367 + #address-cells = <1>;
2368 + #size-cells = <0>;
2369 + status = "disabled";
2370 +
2371 + qsgmii_phy_s2_p1: ethernet-phy@8 {
2372 + reg = <0x8>;
2373 + };
2374 + qsgmii_phy_s2_p2: ethernet-phy@9 {
2375 + reg = <0x9>;
2376 + };
2377 + qsgmii_phy_s2_p3: ethernet-phy@a {
2378 + reg = <0xa>;
2379 + };
2380 + qsgmii_phy_s2_p4: ethernet-phy@b {
2381 + reg = <0xb>;
2382 + };
2383 +
2384 + sgmii_phy_s2_p1: ethernet-phy@1c {
2385 + reg = <0x1c>;
2386 + };
2387 + };
2388 +
2389 + /* Slot 3 */
2390 + ls1043mdio_s3: mdio@4 {
2391 + reg = <0x80>;
2392 + #address-cells = <1>;
2393 + #size-cells = <0>;
2394 + status = "disabled";
2395 +
2396 + sgmii_phy_s3_p1: ethernet-phy@1c {
2397 + reg = <0x1c>;
2398 + };
2399 + };
2400 +
2401 + /* Slot 4 */
2402 + ls1043mdio_s4: mdio@5 {
2403 + reg = <0xa0>;
2404 + #address-cells = <1>;
2405 + #size-cells = <0>;
2406 + status = "disabled";
2407 +
2408 + sgmii_phy_s4_p1: ethernet-phy@1c {
2409 + reg = <0x1c>;
2410 + };
2411 + };
2412 + };
2413 +};
2414 --- /dev/null
2415 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
2416 @@ -0,0 +1,69 @@
2417 +/*
2418 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2419 + *
2420 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2421 + *
2422 + * Mingkai Hu <Mingkai.hu@freescale.com>
2423 + *
2424 + * This file is dual-licensed: you can use it either under the terms
2425 + * of the GPLv2 or the X11 license, at your option. Note that this dual
2426 + * licensing only applies to this file, and not this project as a
2427 + * whole.
2428 + *
2429 + * a) This library is free software; you can redistribute it and/or
2430 + * modify it under the terms of the GNU General Public License as
2431 + * published by the Free Software Foundation; either version 2 of the
2432 + * License, or (at your option) any later version.
2433 + *
2434 + * This library is distributed in the hope that it will be useful,
2435 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2436 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2437 + * GNU General Public License for more details.
2438 + *
2439 + * Or, alternatively,
2440 + *
2441 + * b) Permission is hereby granted, free of charge, to any person
2442 + * obtaining a copy of this software and associated documentation
2443 + * files (the "Software"), to deal in the Software without
2444 + * restriction, including without limitation the rights to use,
2445 + * copy, modify, merge, publish, distribute, sublicense, and/or
2446 + * sell copies of the Software, and to permit persons to whom the
2447 + * Software is furnished to do so, subject to the following
2448 + * conditions:
2449 + *
2450 + * The above copyright notice and this permission notice shall be
2451 + * included in all copies or substantial portions of the Software.
2452 + *
2453 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
2454 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
2455 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2456 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
2457 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
2458 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2459 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2460 + * OTHER DEALINGS IN THE SOFTWARE.
2461 + */
2462 +
2463 +#include "fsl-ls1043a-rdb.dts"
2464 +
2465 +&bman_fbpr {
2466 + compatible = "fsl,bman-fbpr";
2467 + alloc-ranges = <0 0 0x10000 0>;
2468 +};
2469 +&qman_fqd {
2470 + compatible = "fsl,qman-fqd";
2471 + alloc-ranges = <0 0 0x10000 0>;
2472 +};
2473 +&qman_pfdr {
2474 + compatible = "fsl,qman-pfdr";
2475 + alloc-ranges = <0 0 0x10000 0>;
2476 +};
2477 +
2478 +&soc {
2479 +#include "qoriq-dpaa-eth.dtsi"
2480 +#include "qoriq-fman3-0-6oh.dtsi"
2481 +};
2482 +
2483 +&fman0 {
2484 + compatible = "fsl,fman", "simple-bus";
2485 +};
2486 --- /dev/null
2487 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
2488 @@ -0,0 +1,117 @@
2489 +/*
2490 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2491 + *
2492 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2493 + *
2494 + * This file is licensed under the terms of the GNU General Public
2495 + * License version 2. This program is licensed "as is" without any
2496 + * warranty of any kind, whether express or implied.
2497 + */
2498 +
2499 +#include "fsl-ls1043a-rdb-sdk.dts"
2500 +
2501 +&soc {
2502 + bp7: buffer-pool@7 {
2503 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2504 + fsl,bpid = <7>;
2505 + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
2506 + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
2507 + };
2508 +
2509 + bp8: buffer-pool@8 {
2510 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2511 + fsl,bpid = <8>;
2512 + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
2513 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
2514 + };
2515 +
2516 + bp9: buffer-pool@9 {
2517 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2518 + fsl,bpid = <9>;
2519 + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
2520 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
2521 + };
2522 +
2523 + fsl,dpaa {
2524 + compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
2525 +
2526 + ethernet@0 {
2527 + compatible = "fsl,dpa-ethernet-init";
2528 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2529 + fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
2530 + fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
2531 + };
2532 +
2533 + ethernet@1 {
2534 + compatible = "fsl,dpa-ethernet-init";
2535 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2536 + fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
2537 + fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
2538 + };
2539 +
2540 + ethernet@2 {
2541 + compatible = "fsl,dpa-ethernet-init";
2542 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2543 + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
2544 + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
2545 + };
2546 +
2547 + ethernet@3 {
2548 + compatible = "fsl,dpa-ethernet-init";
2549 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2550 + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
2551 + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
2552 + };
2553 +
2554 + ethernet@4 {
2555 + compatible = "fsl,dpa-ethernet-init";
2556 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2557 + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
2558 + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
2559 + };
2560 +
2561 + ethernet@5 {
2562 + compatible = "fsl,dpa-ethernet-init";
2563 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2564 + fsl,qman-frame-queues-rx = <0x60 1 0x61 1>;
2565 + fsl,qman-frame-queues-tx = <0x80 1 0x81 1>;
2566 + };
2567 +
2568 + ethernet@8 {
2569 + compatible = "fsl,dpa-ethernet-init";
2570 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2571 + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
2572 + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
2573 +
2574 + };
2575 + dpa-fman0-oh@2 {
2576 + compatible = "fsl,dpa-oh";
2577 + /* Define frame queues for the OH port*/
2578 + /* <OH Rx error, OH Rx default> */
2579 + fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>;
2580 + fsl,fman-oh-port = <&fman0_oh2>;
2581 + };
2582 + };
2583 +};
2584 +/ {
2585 + reserved-memory {
2586 + #address-cells = <2>;
2587 + #size-cells = <2>;
2588 + ranges;
2589 +
2590 + usdpaa_mem: usdpaa_mem {
2591 + compatible = "fsl,usdpaa-mem";
2592 + alloc-ranges = <0 0 0x10000 0>;
2593 + size = <0 0x10000000>;
2594 + alignment = <0 0x10000000>;
2595 + };
2596 + };
2597 +};
2598 +
2599 +&fman0 {
2600 + fman0_oh2: port@83000 {
2601 + cell-index = <1>;
2602 + compatible = "fsl,fman-port-oh";
2603 + reg = <0x83000 0x1000>;
2604 + };
2605 +};
2606 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2607 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2608 @@ -1,7 +1,7 @@
2609 /*
2610 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2611 *
2612 - * Copyright 2014-2015, Freescale Semiconductor
2613 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2614 *
2615 * Mingkai Hu <Mingkai.hu@freescale.com>
2616 *
2617 @@ -45,7 +45,7 @@
2618 */
2619
2620 /dts-v1/;
2621 -/include/ "fsl-ls1043a.dtsi"
2622 +#include "fsl-ls1043a.dtsi"
2623
2624 / {
2625 model = "LS1043A RDB Board";
2626 @@ -86,6 +86,10 @@
2627 compatible = "pericom,pt7c4338";
2628 reg = <0x68>;
2629 };
2630 + rtc@51 {
2631 + compatible = "nxp,pcf85263";
2632 + reg = <0x51>;
2633 + };
2634 };
2635
2636 &ifc {
2637 @@ -130,6 +134,38 @@
2638 reg = <0>;
2639 spi-max-frequency = <1000000>; /* input clock */
2640 };
2641 +
2642 + slic@2 {
2643 + compatible = "maxim,ds26522";
2644 + reg = <2>;
2645 + spi-max-frequency = <2000000>;
2646 + fsl,spi-cs-sck-delay = <100>;
2647 + fsl,spi-sck-cs-delay = <50>;
2648 + };
2649 +
2650 + slic@3 {
2651 + compatible = "maxim,ds26522";
2652 + reg = <3>;
2653 + spi-max-frequency = <2000000>;
2654 + fsl,spi-cs-sck-delay = <100>;
2655 + fsl,spi-sck-cs-delay = <50>;
2656 + };
2657 +};
2658 +
2659 +&uqe {
2660 + ucc_hdlc: ucc@2000 {
2661 + compatible = "fsl,ucc-hdlc";
2662 + rx-clock-name = "clk8";
2663 + tx-clock-name = "clk9";
2664 + fsl,rx-sync-clock = "rsync_pin";
2665 + fsl,tx-sync-clock = "tsync_pin";
2666 + fsl,tx-timeslot-mask = <0xfffffffe>;
2667 + fsl,rx-timeslot-mask = <0xfffffffe>;
2668 + fsl,tdm-framer-type = "e1";
2669 + fsl,tdm-id = <0>;
2670 + fsl,siram-entry-id = <0>;
2671 + fsl,tdm-interface;
2672 + };
2673 };
2674
2675 &duart0 {
2676 @@ -139,3 +175,76 @@
2677 &duart1 {
2678 status = "okay";
2679 };
2680 +
2681 +#include "fsl-ls1043-post.dtsi"
2682 +
2683 +&fman0 {
2684 + ethernet@e0000 {
2685 + phy-handle = <&qsgmii_phy1>;
2686 + phy-connection-type = "qsgmii";
2687 + };
2688 +
2689 + ethernet@e2000 {
2690 + phy-handle = <&qsgmii_phy2>;
2691 + phy-connection-type = "qsgmii";
2692 + };
2693 +
2694 + ethernet@e4000 {
2695 + phy-handle = <&rgmii_phy1>;
2696 + phy-connection-type = "rgmii-txid";
2697 + };
2698 +
2699 + ethernet@e6000 {
2700 + phy-handle = <&rgmii_phy2>;
2701 + phy-connection-type = "rgmii-txid";
2702 + };
2703 +
2704 + ethernet@e8000 {
2705 + phy-handle = <&qsgmii_phy3>;
2706 + phy-connection-type = "qsgmii";
2707 + };
2708 +
2709 + ethernet@ea000 {
2710 + phy-handle = <&qsgmii_phy4>;
2711 + phy-connection-type = "qsgmii";
2712 + };
2713 +
2714 + ethernet@f0000 { /* 10GEC1 */
2715 + phy-handle = <&aqr105_phy>;
2716 + phy-connection-type = "xgmii";
2717 + };
2718 +
2719 + mdio@fc000 {
2720 + rgmii_phy1: ethernet-phy@1 {
2721 + reg = <0x1>;
2722 + };
2723 +
2724 + rgmii_phy2: ethernet-phy@2 {
2725 + reg = <0x2>;
2726 + };
2727 +
2728 + qsgmii_phy1: ethernet-phy@4 {
2729 + reg = <0x4>;
2730 + };
2731 +
2732 + qsgmii_phy2: ethernet-phy@5 {
2733 + reg = <0x5>;
2734 + };
2735 +
2736 + qsgmii_phy3: ethernet-phy@6 {
2737 + reg = <0x6>;
2738 + };
2739 +
2740 + qsgmii_phy4: ethernet-phy@7 {
2741 + reg = <0x7>;
2742 + };
2743 + };
2744 +
2745 + mdio@fd000 {
2746 + aqr105_phy: ethernet-phy@1 {
2747 + compatible = "ethernet-phy-ieee802.3-c45";
2748 + interrupts = <0 132 4>;
2749 + reg = <0x1>;
2750 + };
2751 + };
2752 +};
2753 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2754 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2755 @@ -1,7 +1,7 @@
2756 /*
2757 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2758 *
2759 - * Copyright 2014-2015, Freescale Semiconductor
2760 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2761 *
2762 * Mingkai Hu <Mingkai.hu@freescale.com>
2763 *
2764 @@ -44,12 +44,25 @@
2765 * OTHER DEALINGS IN THE SOFTWARE.
2766 */
2767
2768 +#include <dt-bindings/thermal/thermal.h>
2769 +
2770 / {
2771 compatible = "fsl,ls1043a";
2772 interrupt-parent = <&gic>;
2773 #address-cells = <2>;
2774 #size-cells = <2>;
2775
2776 + aliases {
2777 + fman0 = &fman0;
2778 + ethernet0 = &enet0;
2779 + ethernet1 = &enet1;
2780 + ethernet2 = &enet2;
2781 + ethernet3 = &enet3;
2782 + ethernet4 = &enet4;
2783 + ethernet5 = &enet5;
2784 + ethernet6 = &enet6;
2785 + };
2786 +
2787 cpus {
2788 #address-cells = <1>;
2789 #size-cells = <0>;
2790 @@ -66,6 +79,8 @@
2791 reg = <0x0>;
2792 clocks = <&clockgen 1 0>;
2793 next-level-cache = <&l2>;
2794 + #cooling-cells = <2>;
2795 + cpu-idle-states = <&CPU_PH20>;
2796 };
2797
2798 cpu1: cpu@1 {
2799 @@ -74,6 +89,7 @@
2800 reg = <0x1>;
2801 clocks = <&clockgen 1 0>;
2802 next-level-cache = <&l2>;
2803 + cpu-idle-states = <&CPU_PH20>;
2804 };
2805
2806 cpu2: cpu@2 {
2807 @@ -82,6 +98,7 @@
2808 reg = <0x2>;
2809 clocks = <&clockgen 1 0>;
2810 next-level-cache = <&l2>;
2811 + cpu-idle-states = <&CPU_PH20>;
2812 };
2813
2814 cpu3: cpu@3 {
2815 @@ -90,6 +107,7 @@
2816 reg = <0x3>;
2817 clocks = <&clockgen 1 0>;
2818 next-level-cache = <&l2>;
2819 + cpu-idle-states = <&CPU_PH20>;
2820 };
2821
2822 l2: l2-cache {
2823 @@ -97,12 +115,56 @@
2824 };
2825 };
2826
2827 + idle-states {
2828 + /*
2829 + * PSCI node is not added default, U-boot will add missing
2830 + * parts if it determines to use PSCI.
2831 + */
2832 + entry-method = "arm,psci";
2833 +
2834 + CPU_PH20: cpu-ph20 {
2835 + compatible = "arm,idle-state";
2836 + idle-state-name = "PH20";
2837 + arm,psci-suspend-param = <0x0>;
2838 + entry-latency-us = <1000>;
2839 + exit-latency-us = <1000>;
2840 + min-residency-us = <3000>;
2841 + };
2842 + };
2843 +
2844 memory@80000000 {
2845 device_type = "memory";
2846 reg = <0x0 0x80000000 0 0x80000000>;
2847 /* DRAM space 1, size: 2GiB DRAM */
2848 };
2849
2850 + reserved-memory {
2851 + #address-cells = <2>;
2852 + #size-cells = <2>;
2853 + ranges;
2854 +
2855 + bman_fbpr: bman-fbpr {
2856 + compatible = "shared-dma-pool";
2857 + size = <0 0x1000000>;
2858 + alignment = <0 0x1000000>;
2859 + no-map;
2860 + };
2861 +
2862 + qman_fqd: qman-fqd {
2863 + compatible = "shared-dma-pool";
2864 + size = <0 0x400000>;
2865 + alignment = <0 0x400000>;
2866 + no-map;
2867 + };
2868 +
2869 + qman_pfdr: qman-pfdr {
2870 + compatible = "shared-dma-pool";
2871 + size = <0 0x2000000>;
2872 + alignment = <0 0x2000000>;
2873 + no-map;
2874 + };
2875 + };
2876 +
2877 sysclk: sysclk {
2878 compatible = "fixed-clock";
2879 #clock-cells = <0>;
2880 @@ -149,7 +211,7 @@
2881 interrupts = <1 9 0xf08>;
2882 };
2883
2884 - soc {
2885 + soc: soc {
2886 compatible = "simple-bus";
2887 #address-cells = <2>;
2888 #size-cells = <2>;
2889 @@ -213,13 +275,14 @@
2890
2891 dcfg: dcfg@1ee0000 {
2892 compatible = "fsl,ls1043a-dcfg", "syscon";
2893 - reg = <0x0 0x1ee0000 0x0 0x10000>;
2894 + reg = <0x0 0x1ee0000 0x0 0x1000>;
2895 big-endian;
2896 };
2897
2898 ifc: ifc@1530000 {
2899 compatible = "fsl,ifc", "simple-bus";
2900 reg = <0x0 0x1530000 0x0 0x10000>;
2901 + big-endian;
2902 interrupts = <0 43 0x4>;
2903 };
2904
2905 @@ -255,6 +318,103 @@
2906 big-endian;
2907 };
2908
2909 + tmu: tmu@1f00000 {
2910 + compatible = "fsl,qoriq-tmu";
2911 + reg = <0x0 0x1f00000 0x0 0x10000>;
2912 + interrupts = <0 33 0x4>;
2913 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
2914 + fsl,tmu-calibration = <0x00000000 0x00000026
2915 + 0x00000001 0x0000002d
2916 + 0x00000002 0x00000032
2917 + 0x00000003 0x00000039
2918 + 0x00000004 0x0000003f
2919 + 0x00000005 0x00000046
2920 + 0x00000006 0x0000004d
2921 + 0x00000007 0x00000054
2922 + 0x00000008 0x0000005a
2923 + 0x00000009 0x00000061
2924 + 0x0000000a 0x0000006a
2925 + 0x0000000b 0x00000071
2926 +
2927 + 0x00010000 0x00000025
2928 + 0x00010001 0x0000002c
2929 + 0x00010002 0x00000035
2930 + 0x00010003 0x0000003d
2931 + 0x00010004 0x00000045
2932 + 0x00010005 0x0000004e
2933 + 0x00010006 0x00000057
2934 + 0x00010007 0x00000061
2935 + 0x00010008 0x0000006b
2936 + 0x00010009 0x00000076
2937 +
2938 + 0x00020000 0x00000029
2939 + 0x00020001 0x00000033
2940 + 0x00020002 0x0000003d
2941 + 0x00020003 0x00000049
2942 + 0x00020004 0x00000056
2943 + 0x00020005 0x00000061
2944 + 0x00020006 0x0000006d
2945 +
2946 + 0x00030000 0x00000021
2947 + 0x00030001 0x0000002a
2948 + 0x00030002 0x0000003c
2949 + 0x00030003 0x0000004e>;
2950 + #thermal-sensor-cells = <1>;
2951 + };
2952 +
2953 + thermal-zones {
2954 + cpu_thermal: cpu-thermal {
2955 + polling-delay-passive = <1000>;
2956 + polling-delay = <5000>;
2957 +
2958 + thermal-sensors = <&tmu 3>;
2959 +
2960 + trips {
2961 + cpu_alert: cpu-alert {
2962 + temperature = <85000>;
2963 + hysteresis = <2000>;
2964 + type = "passive";
2965 + };
2966 + cpu_crit: cpu-crit {
2967 + temperature = <95000>;
2968 + hysteresis = <2000>;
2969 + type = "critical";
2970 + };
2971 + };
2972 +
2973 + cooling-maps {
2974 + map0 {
2975 + trip = <&cpu_alert>;
2976 + cooling-device =
2977 + <&cpu0 THERMAL_NO_LIMIT
2978 + THERMAL_NO_LIMIT>;
2979 + };
2980 + };
2981 + };
2982 + };
2983 +
2984 + qman: qman@1880000 {
2985 + compatible = "fsl,qman";
2986 + reg = <0x00 0x1880000 0x0 0x10000>;
2987 + interrupts = <0 45 0x4>;
2988 + memory-region = <&qman_fqd &qman_pfdr>;
2989 + };
2990 +
2991 + bman: bman@1890000 {
2992 + compatible = "fsl,bman";
2993 + reg = <0x00 0x1890000 0x0 0x10000>;
2994 + interrupts = <0 45 0x4>;
2995 + memory-region = <&bman_fbpr>;
2996 + };
2997 +
2998 + bportals: bman-portals@508000000 {
2999 + ranges = <0x0 0x5 0x08000000 0x8000000>;
3000 + };
3001 +
3002 + qportals: qman-portals@500000000 {
3003 + ranges = <0x0 0x5 0x00000000 0x8000000>;
3004 + };
3005 +
3006 dspi0: dspi@2100000 {
3007 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
3008 #address-cells = <1>;
3009 @@ -396,6 +556,72 @@
3010 #interrupt-cells = <2>;
3011 };
3012
3013 + uqe: uqe@2400000 {
3014 + #address-cells = <1>;
3015 + #size-cells = <1>;
3016 + device_type = "qe";
3017 + compatible = "fsl,qe", "simple-bus";
3018 + ranges = <0x0 0x0 0x2400000 0x40000>;
3019 + reg = <0x0 0x2400000 0x0 0x480>;
3020 + brg-frequency = <100000000>;
3021 + bus-frequency = <200000000>;
3022 +
3023 + fsl,qe-num-riscs = <1>;
3024 + fsl,qe-num-snums = <28>;
3025 +
3026 + qeic: qeic@80 {
3027 + compatible = "fsl,qe-ic";
3028 + reg = <0x80 0x80>;
3029 + #address-cells = <0>;
3030 + interrupt-controller;
3031 + #interrupt-cells = <1>;
3032 + interrupts = <0 77 0x04 0 77 0x04>;
3033 + };
3034 +
3035 + si1: si@700 {
3036 + #address-cells = <1>;
3037 + #size-cells = <0>;
3038 + compatible = "fsl,ls1043-qe-si",
3039 + "fsl,t1040-qe-si";
3040 + reg = <0x700 0x80>;
3041 + };
3042 +
3043 + siram1: siram@1000 {
3044 + #address-cells = <1>;
3045 + #size-cells = <1>;
3046 + compatible = "fsl,ls1043-qe-siram",
3047 + "fsl,t1040-qe-siram";
3048 + reg = <0x1000 0x800>;
3049 + };
3050 +
3051 + ucc@2000 {
3052 + cell-index = <1>;
3053 + reg = <0x2000 0x200>;
3054 + interrupts = <32>;
3055 + interrupt-parent = <&qeic>;
3056 + };
3057 +
3058 + ucc@2200 {
3059 + cell-index = <3>;
3060 + reg = <0x2200 0x200>;
3061 + interrupts = <34>;
3062 + interrupt-parent = <&qeic>;
3063 + };
3064 +
3065 + muram@10000 {
3066 + #address-cells = <1>;
3067 + #size-cells = <1>;
3068 + compatible = "fsl,qe-muram", "fsl,cpm-muram";
3069 + ranges = <0x0 0x10000 0x6000>;
3070 +
3071 + data-only@0 {
3072 + compatible = "fsl,qe-muram-data",
3073 + "fsl,cpm-muram-data";
3074 + reg = <0x0 0x6000>;
3075 + };
3076 + };
3077 + };
3078 +
3079 lpuart0: serial@2950000 {
3080 compatible = "fsl,ls1021a-lpuart";
3081 reg = <0x0 0x2950000 0x0 0x1000>;
3082 @@ -450,6 +676,16 @@
3083 status = "disabled";
3084 };
3085
3086 + ftm0: ftm0@29d0000 {
3087 + compatible = "fsl,ls1043a-ftm";
3088 + reg = <0x0 0x29d0000 0x0 0x10000>,
3089 + <0x0 0x1ee2140 0x0 0x4>;
3090 + reg-names = "ftm", "FlexTimer1";
3091 + interrupts = <0 86 0x4>;
3092 + big-endian;
3093 + status = "okay";
3094 + };
3095 +
3096 wdog0: wdog@2ad0000 {
3097 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
3098 reg = <0x0 0x2ad0000 0x0 0x10000>;
3099 @@ -482,6 +718,8 @@
3100 dr_mode = "host";
3101 snps,quirk-frame-length-adjustment = <0x20>;
3102 snps,dis_rxdet_inp3_quirk;
3103 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
3104 + snps,dma-snooping;
3105 };
3106
3107 usb1: usb3@3000000 {
3108 @@ -491,6 +729,9 @@
3109 dr_mode = "host";
3110 snps,quirk-frame-length-adjustment = <0x20>;
3111 snps,dis_rxdet_inp3_quirk;
3112 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
3113 + snps,dma-snooping;
3114 + configure-gfladj;
3115 };
3116
3117 usb2: usb3@3100000 {
3118 @@ -500,32 +741,52 @@
3119 dr_mode = "host";
3120 snps,quirk-frame-length-adjustment = <0x20>;
3121 snps,dis_rxdet_inp3_quirk;
3122 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
3123 + snps,dma-snooping;
3124 + configure-gfladj;
3125 };
3126
3127 sata: sata@3200000 {
3128 compatible = "fsl,ls1043a-ahci";
3129 - reg = <0x0 0x3200000 0x0 0x10000>;
3130 + reg = <0x0 0x3200000 0x0 0x10000>,
3131 + <0x0 0x20140520 0x0 0x4>;
3132 + reg-names = "ahci", "sata-ecc";
3133 interrupts = <0 69 0x4>;
3134 clocks = <&clockgen 4 0>;
3135 dma-coherent;
3136 };
3137
3138 + qdma: qdma@8380000 {
3139 + compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
3140 + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
3141 + <0x0 0x8390000 0x0 0x10000>, /* Status regs */
3142 + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
3143 + interrupts = <0 152 0x4>,
3144 + <0 39 0x4>;
3145 + interrupt-names = "qdma-error", "qdma-queue";
3146 + channels = <8>;
3147 + queues = <2>;
3148 + status-sizes = <64>;
3149 + queue-sizes = <64 64>;
3150 + big-endian;
3151 + };
3152 +
3153 msi1: msi-controller1@1571000 {
3154 - compatible = "fsl,1s1043a-msi";
3155 + compatible = "fsl,ls1043a-msi";
3156 reg = <0x0 0x1571000 0x0 0x8>;
3157 msi-controller;
3158 interrupts = <0 116 0x4>;
3159 };
3160
3161 msi2: msi-controller2@1572000 {
3162 - compatible = "fsl,1s1043a-msi";
3163 + compatible = "fsl,ls1043a-msi";
3164 reg = <0x0 0x1572000 0x0 0x8>;
3165 msi-controller;
3166 interrupts = <0 126 0x4>;
3167 };
3168
3169 msi3: msi-controller3@1573000 {
3170 - compatible = "fsl,1s1043a-msi";
3171 + compatible = "fsl,ls1043a-msi";
3172 reg = <0x0 0x1573000 0x0 0x8>;
3173 msi-controller;
3174 interrupts = <0 160 0x4>;
3175 @@ -536,9 +797,9 @@
3176 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
3177 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
3178 reg-names = "regs", "config";
3179 - interrupts = <0 118 0x4>, /* controller interrupt */
3180 - <0 117 0x4>; /* PME interrupt */
3181 - interrupt-names = "intr", "pme";
3182 + interrupts = <0 117 0x4>, /* PME interrupt */
3183 + <0 118 0x4>; /* aer interrupt */
3184 + interrupt-names = "pme", "aer";
3185 #address-cells = <3>;
3186 #size-cells = <2>;
3187 device_type = "pci";
3188 @@ -547,7 +808,7 @@
3189 bus-range = <0x0 0xff>;
3190 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
3191 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
3192 - msi-parent = <&msi1>;
3193 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
3194 #interrupt-cells = <1>;
3195 interrupt-map-mask = <0 0 0 7>;
3196 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
3197 @@ -561,9 +822,9 @@
3198 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
3199 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
3200 reg-names = "regs", "config";
3201 - interrupts = <0 128 0x4>,
3202 - <0 127 0x4>;
3203 - interrupt-names = "intr", "pme";
3204 + interrupts = <0 127 0x4>,
3205 + <0 128 0x4>;
3206 + interrupt-names = "pme", "aer";
3207 #address-cells = <3>;
3208 #size-cells = <2>;
3209 device_type = "pci";
3210 @@ -572,7 +833,7 @@
3211 bus-range = <0x0 0xff>;
3212 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
3213 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
3214 - msi-parent = <&msi2>;
3215 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
3216 #interrupt-cells = <1>;
3217 interrupt-map-mask = <0 0 0 7>;
3218 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
3219 @@ -586,9 +847,9 @@
3220 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
3221 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
3222 reg-names = "regs", "config";
3223 - interrupts = <0 162 0x4>,
3224 - <0 161 0x4>;
3225 - interrupt-names = "intr", "pme";
3226 + interrupts = <0 161 0x4>,
3227 + <0 162 0x4>;
3228 + interrupt-names = "pme", "aer";
3229 #address-cells = <3>;
3230 #size-cells = <2>;
3231 device_type = "pci";
3232 @@ -597,7 +858,7 @@
3233 bus-range = <0x0 0xff>;
3234 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
3235 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
3236 - msi-parent = <&msi3>;
3237 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
3238 #interrupt-cells = <1>;
3239 interrupt-map-mask = <0 0 0 7>;
3240 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
3241 @@ -607,4 +868,13 @@
3242 };
3243 };
3244
3245 + firmware {
3246 + optee {
3247 + compatible = "linaro,optee-tz";
3248 + method = "smc";
3249 + };
3250 + };
3251 };
3252 +
3253 +#include "qoriq-qman1-portals.dtsi"
3254 +#include "qoriq-bman1-portals.dtsi"
3255 --- /dev/null
3256 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
3257 @@ -0,0 +1,48 @@
3258 +/*
3259 + * QorIQ FMan v3 device tree nodes for ls1046
3260 + *
3261 + * Copyright 2015-2016 Freescale Semiconductor Inc.
3262 + *
3263 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3264 + */
3265 +
3266 +&soc {
3267 +
3268 +/* include used FMan blocks */
3269 +#include "qoriq-fman3-0.dtsi"
3270 +#include "qoriq-fman3-0-1g-0.dtsi"
3271 +#include "qoriq-fman3-0-1g-1.dtsi"
3272 +#include "qoriq-fman3-0-1g-2.dtsi"
3273 +#include "qoriq-fman3-0-1g-3.dtsi"
3274 +#include "qoriq-fman3-0-1g-4.dtsi"
3275 +#include "qoriq-fman3-0-1g-5.dtsi"
3276 +#include "qoriq-fman3-0-10g-0.dtsi"
3277 +#include "qoriq-fman3-0-10g-1.dtsi"
3278 +};
3279 +
3280 +&fman0 {
3281 + /* these aliases provide the FMan ports mapping */
3282 + enet0: ethernet@e0000 {
3283 + };
3284 +
3285 + enet1: ethernet@e2000 {
3286 + };
3287 +
3288 + enet2: ethernet@e4000 {
3289 + };
3290 +
3291 + enet3: ethernet@e6000 {
3292 + };
3293 +
3294 + enet4: ethernet@e8000 {
3295 + };
3296 +
3297 + enet5: ethernet@ea000 {
3298 + };
3299 +
3300 + enet6: ethernet@f0000 {
3301 + };
3302 +
3303 + enet7: ethernet@f2000 {
3304 + };
3305 +};
3306 --- /dev/null
3307 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
3308 @@ -0,0 +1,110 @@
3309 +/*
3310 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3311 + *
3312 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
3313 + *
3314 + * Mingkai Hu <Mingkai.hu@freescale.com>
3315 + *
3316 + * This file is dual-licensed: you can use it either under the terms
3317 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3318 + * licensing only applies to this file, and not this project as a
3319 + * whole.
3320 + *
3321 + * a) This library is free software; you can redistribute it and/or
3322 + * modify it under the terms of the GNU General Public License as
3323 + * published by the Free Software Foundation; either version 2 of the
3324 + * License, or (at your option) any later version.
3325 + *
3326 + * This library is distributed in the hope that it will be useful,
3327 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3328 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3329 + * GNU General Public License for more details.
3330 + *
3331 + * Or, alternatively,
3332 + *
3333 + * b) Permission is hereby granted, free of charge, to any person
3334 + * obtaining a copy of this software and associated documentation
3335 + * files (the "Software"), to deal in the Software without
3336 + * restriction, including without limitation the rights to use,
3337 + * copy, modify, merge, publish, distribute, sublicense, and/or
3338 + * sell copies of the Software, and to permit persons to whom the
3339 + * Software is furnished to do so, subject to the following
3340 + * conditions:
3341 + *
3342 + * The above copyright notice and this permission notice shall be
3343 + * included in all copies or substantial portions of the Software.
3344 + *
3345 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3346 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3347 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3348 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3349 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3350 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3351 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3352 + * OTHER DEALINGS IN THE SOFTWARE.
3353 + */
3354 +
3355 +#include "fsl-ls1046a-qds.dts"
3356 +
3357 +&bman_fbpr {
3358 + compatible = "fsl,bman-fbpr";
3359 + alloc-ranges = <0 0 0x10000 0>;
3360 +};
3361 +&qman_fqd {
3362 + compatible = "fsl,qman-fqd";
3363 + alloc-ranges = <0 0 0x10000 0>;
3364 +};
3365 +&qman_pfdr {
3366 + compatible = "fsl,qman-pfdr";
3367 + alloc-ranges = <0 0 0x10000 0>;
3368 +};
3369 +
3370 +&soc {
3371 +#include "qoriq-dpaa-eth.dtsi"
3372 +#include "qoriq-fman3-0-6oh.dtsi"
3373 +};
3374 +
3375 +&fsldpaa {
3376 + ethernet@9 {
3377 + compatible = "fsl,dpa-ethernet";
3378 + fsl,fman-mac = <&enet7>;
3379 + dma-coherent;
3380 + };
3381 +};
3382 +
3383 +&fman0 {
3384 + compatible = "fsl,fman", "simple-bus";
3385 +};
3386 +
3387 +&dspi {
3388 + bus-num = <0>;
3389 + status = "okay";
3390 +
3391 + flash@0 {
3392 + #address-cells = <1>;
3393 + #size-cells = <1>;
3394 + compatible = "n25q128a11", "jedec,spi-nor";
3395 + reg = <0>;
3396 + spi-max-frequency = <10000000>;
3397 + };
3398 +
3399 + flash@1 {
3400 + #address-cells = <1>;
3401 + #size-cells = <1>;
3402 + compatible = "sst25wf040b", "jedec,spi-nor";
3403 + spi-cpol;
3404 + spi-cpha;
3405 + reg = <1>;
3406 + spi-max-frequency = <10000000>;
3407 + };
3408 +
3409 + flash@2 {
3410 + #address-cells = <1>;
3411 + #size-cells = <1>;
3412 + compatible = "en25s64", "jedec,spi-nor";
3413 + spi-cpol;
3414 + spi-cpha;
3415 + reg = <2>;
3416 + spi-max-frequency = <10000000>;
3417 + };
3418 +};
3419 --- /dev/null
3420 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
3421 @@ -0,0 +1,363 @@
3422 +/*
3423 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3424 + *
3425 + * Copyright 2016 Freescale Semiconductor, Inc.
3426 + *
3427 + * Shaohui Xie <Shaohui.Xie@nxp.com>
3428 + *
3429 + * This file is dual-licensed: you can use it either under the terms
3430 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3431 + * licensing only applies to this file, and not this project as a
3432 + * whole.
3433 + *
3434 + * a) This library is free software; you can redistribute it and/or
3435 + * modify it under the terms of the GNU General Public License as
3436 + * published by the Free Software Foundation; either version 2 of the
3437 + * License, or (at your option) any later version.
3438 + *
3439 + * This library is distributed in the hope that it will be useful,
3440 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3441 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3442 + * GNU General Public License for more details.
3443 + *
3444 + * Or, alternatively,
3445 + *
3446 + * b) Permission is hereby granted, free of charge, to any person
3447 + * obtaining a copy of this software and associated documentation
3448 + * files (the "Software"), to deal in the Software without
3449 + * restriction, including without limitation the rights to use,
3450 + * copy, modify, merge, publish, distribute, sublicense, and/or
3451 + * sell copies of the Software, and to permit persons to whom the
3452 + * Software is furnished to do so, subject to the following
3453 + * conditions:
3454 + *
3455 + * The above copyright notice and this permission notice shall be
3456 + * included in all copies or substantial portions of the Software.
3457 + *
3458 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3459 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3460 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3461 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3462 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3463 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3464 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3465 + * OTHER DEALINGS IN THE SOFTWARE.
3466 + */
3467 +
3468 +/dts-v1/;
3469 +
3470 +#include "fsl-ls1046a.dtsi"
3471 +
3472 +/ {
3473 + model = "LS1046A QDS Board";
3474 + compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
3475 +
3476 + aliases {
3477 + gpio0 = &gpio0;
3478 + gpio1 = &gpio1;
3479 + gpio2 = &gpio2;
3480 + gpio3 = &gpio3;
3481 + serial0 = &duart0;
3482 + serial1 = &duart1;
3483 + serial2 = &duart2;
3484 + serial3 = &duart3;
3485 +
3486 + emi1_slot1 = &ls1046mdio_s1;
3487 + emi1_slot2 = &ls1046mdio_s2;
3488 + emi1_slot4 = &ls1046mdio_s4;
3489 +
3490 + sgmii_s1_p1 = &sgmii_phy_s1_p1;
3491 + sgmii_s1_p2 = &sgmii_phy_s1_p2;
3492 + sgmii_s1_p3 = &sgmii_phy_s1_p3;
3493 + sgmii_s1_p4 = &sgmii_phy_s1_p4;
3494 + sgmii_s4_p1 = &sgmii_phy_s4_p1;
3495 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
3496 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
3497 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
3498 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
3499 + };
3500 +
3501 + chosen {
3502 + stdout-path = "serial0:115200n8";
3503 + };
3504 +};
3505 +
3506 +&dspi {
3507 + bus-num = <0>;
3508 + status = "okay";
3509 +
3510 + flash@0 {
3511 + #address-cells = <1>;
3512 + #size-cells = <1>;
3513 + compatible = "n25q128a11", "jedec,spi-nor";
3514 + reg = <0>;
3515 + spi-max-frequency = <10000000>;
3516 + };
3517 +
3518 + flash@1 {
3519 + #address-cells = <1>;
3520 + #size-cells = <1>;
3521 + compatible = "sst25wf040b", "jedec,spi-nor";
3522 + spi-cpol;
3523 + spi-cpha;
3524 + reg = <1>;
3525 + spi-max-frequency = <10000000>;
3526 + };
3527 +
3528 + flash@2 {
3529 + #address-cells = <1>;
3530 + #size-cells = <1>;
3531 + compatible = "en25s64", "jedec,spi-nor";
3532 + spi-cpol;
3533 + spi-cpha;
3534 + reg = <2>;
3535 + spi-max-frequency = <10000000>;
3536 + };
3537 +};
3538 +
3539 +&duart0 {
3540 + status = "okay";
3541 +};
3542 +
3543 +&duart1 {
3544 + status = "okay";
3545 +};
3546 +
3547 +&i2c0 {
3548 + status = "okay";
3549 +
3550 + pca9547@77 {
3551 + compatible = "nxp,pca9547";
3552 + reg = <0x77>;
3553 + #address-cells = <1>;
3554 + #size-cells = <0>;
3555 +
3556 + i2c@2 {
3557 + #address-cells = <1>;
3558 + #size-cells = <0>;
3559 + reg = <0x2>;
3560 +
3561 + ina220@40 {
3562 + compatible = "ti,ina220";
3563 + reg = <0x40>;
3564 + shunt-resistor = <1000>;
3565 + };
3566 +
3567 + ina220@41 {
3568 + compatible = "ti,ina220";
3569 + reg = <0x41>;
3570 + shunt-resistor = <1000>;
3571 + };
3572 + };
3573 +
3574 + i2c@3 {
3575 + #address-cells = <1>;
3576 + #size-cells = <0>;
3577 + reg = <0x3>;
3578 +
3579 + rtc@51 {
3580 + compatible = "nxp,pcf2129";
3581 + reg = <0x51>;
3582 + /* IRQ10_B */
3583 + interrupts = <0 150 0x4>;
3584 + };
3585 +
3586 + eeprom@56 {
3587 + compatible = "atmel,24c512";
3588 + reg = <0x56>;
3589 + };
3590 +
3591 + eeprom@57 {
3592 + compatible = "atmel,24c512";
3593 + reg = <0x57>;
3594 + };
3595 +
3596 + temp-sensor@4c {
3597 + compatible = "adi,adt7461a";
3598 + reg = <0x4c>;
3599 + };
3600 + };
3601 + };
3602 +};
3603 +
3604 +&ifc {
3605 + #address-cells = <2>;
3606 + #size-cells = <1>;
3607 + /* NOR, NAND Flashes and FPGA on board */
3608 + ranges = <0x0 0x0 0x0 0x60000000 0x08000000
3609 + 0x1 0x0 0x0 0x7e800000 0x00010000
3610 + 0x2 0x0 0x0 0x7fb00000 0x00000100>;
3611 + status = "okay";
3612 +
3613 + nor@0,0 {
3614 + compatible = "cfi-flash";
3615 + reg = <0x0 0x0 0x8000000>;
3616 + bank-width = <2>;
3617 + device-width = <1>;
3618 + };
3619 +
3620 + nand@1,0 {
3621 + compatible = "fsl,ifc-nand";
3622 + reg = <0x1 0x0 0x10000>;
3623 + };
3624 +
3625 + fpga: board-control@2,0 {
3626 + compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-bus";
3627 + reg = <0x2 0x0 0x0000100>;
3628 + ranges = <0 2 0 0x100>;
3629 + };
3630 +};
3631 +
3632 +&lpuart0 {
3633 + status = "okay";
3634 +};
3635 +
3636 +&qspi {
3637 + num-cs = <2>;
3638 + bus-num = <0>;
3639 + status = "okay";
3640 +
3641 + qflash0: s25fl128s@0 {
3642 + compatible = "spansion,m25p80";
3643 + #address-cells = <1>;
3644 + #size-cells = <1>;
3645 + spi-max-frequency = <20000000>;
3646 + reg = <0>;
3647 + };
3648 +};
3649 +
3650 +#include "fsl-ls1046-post.dtsi"
3651 +
3652 +&fman0 {
3653 + ethernet@e0000 {
3654 + phy-handle = <&qsgmii_phy_s2_p1>;
3655 + phy-connection-type = "sgmii";
3656 + };
3657 +
3658 + ethernet@e2000 {
3659 + phy-handle = <&sgmii_phy_s4_p1>;
3660 + phy-connection-type = "sgmii";
3661 + };
3662 +
3663 + ethernet@e4000 {
3664 + phy-handle = <&rgmii_phy1>;
3665 + phy-connection-type = "rgmii";
3666 + };
3667 +
3668 + ethernet@e6000 {
3669 + phy-handle = <&rgmii_phy2>;
3670 + phy-connection-type = "rgmii";
3671 + };
3672 +
3673 + ethernet@e8000 {
3674 + phy-handle = <&sgmii_phy_s1_p3>;
3675 + phy-connection-type = "sgmii";
3676 + };
3677 +
3678 + ethernet@ea000 {
3679 + phy-handle = <&sgmii_phy_s1_p4>;
3680 + phy-connection-type = "sgmii";
3681 + };
3682 +
3683 + ethernet@f0000 { /* DTSEC9/10GEC1 */
3684 + phy-handle = <&sgmii_phy_s1_p1>;
3685 + phy-connection-type = "xgmii";
3686 + };
3687 +
3688 + ethernet@f2000 { /* DTSEC10/10GEC2 */
3689 + phy-handle = <&sgmii_phy_s1_p2>;
3690 + phy-connection-type = "xgmii";
3691 + };
3692 +};
3693 +
3694 +&fpga {
3695 + #address-cells = <1>;
3696 + #size-cells = <1>;
3697 + mdio-mux-emi1 {
3698 + compatible = "mdio-mux-mmioreg", "mdio-mux";
3699 + mdio-parent-bus = <&mdio0>;
3700 + #address-cells = <1>;
3701 + #size-cells = <0>;
3702 + reg = <0x54 1>; /* BRDCFG4 */
3703 + mux-mask = <0xe0>; /* EMI1 */
3704 +
3705 + /* On-board RGMII1 PHY */
3706 + ls1046mdio0: mdio@0 {
3707 + reg = <0>;
3708 + #address-cells = <1>;
3709 + #size-cells = <0>;
3710 +
3711 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
3712 + reg = <0x1>;
3713 + };
3714 + };
3715 +
3716 + /* On-board RGMII2 PHY */
3717 + ls1046mdio1: mdio@1 {
3718 + reg = <0x20>;
3719 + #address-cells = <1>;
3720 + #size-cells = <0>;
3721 +
3722 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
3723 + reg = <0x2>;
3724 + };
3725 + };
3726 +
3727 + /* Slot 1 */
3728 + ls1046mdio_s1: mdio@2 {
3729 + reg = <0x40>;
3730 + #address-cells = <1>;
3731 + #size-cells = <0>;
3732 + status = "disabled";
3733 +
3734 + sgmii_phy_s1_p1: ethernet-phy@1c {
3735 + reg = <0x1c>;
3736 + };
3737 +
3738 + sgmii_phy_s1_p2: ethernet-phy@1d {
3739 + reg = <0x1d>;
3740 + };
3741 +
3742 + sgmii_phy_s1_p3: ethernet-phy@1e {
3743 + reg = <0x1e>;
3744 + };
3745 +
3746 + sgmii_phy_s1_p4: ethernet-phy@1f {
3747 + reg = <0x1f>;
3748 + };
3749 + };
3750 +
3751 + /* Slot 2 */
3752 + ls1046mdio_s2: mdio@3 {
3753 + reg = <0x60>;
3754 + #address-cells = <1>;
3755 + #size-cells = <0>;
3756 + status = "disabled";
3757 +
3758 + qsgmii_phy_s2_p1: ethernet-phy@8 {
3759 + reg = <0x8>;
3760 + };
3761 + qsgmii_phy_s2_p2: ethernet-phy@9 {
3762 + reg = <0x9>;
3763 + };
3764 + qsgmii_phy_s2_p3: ethernet-phy@a {
3765 + reg = <0xa>;
3766 + };
3767 + qsgmii_phy_s2_p4: ethernet-phy@b {
3768 + reg = <0xb>;
3769 + };
3770 + };
3771 +
3772 + /* Slot 4 */
3773 + ls1046mdio_s4: mdio@5 {
3774 + reg = <0x80>;
3775 + #address-cells = <1>;
3776 + #size-cells = <0>;
3777 + status = "disabled";
3778 +
3779 + sgmii_phy_s4_p1: ethernet-phy@1c {
3780 + reg = <0x1c>;
3781 + };
3782 + };
3783 + };
3784 +};
3785 --- /dev/null
3786 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
3787 @@ -0,0 +1,83 @@
3788 +/*
3789 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3790 + *
3791 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
3792 + *
3793 + * Mingkai Hu <Mingkai.hu@freescale.com>
3794 + *
3795 + * This file is dual-licensed: you can use it either under the terms
3796 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3797 + * licensing only applies to this file, and not this project as a
3798 + * whole.
3799 + *
3800 + * a) This library is free software; you can redistribute it and/or
3801 + * modify it under the terms of the GNU General Public License as
3802 + * published by the Free Software Foundation; either version 2 of the
3803 + * License, or (at your option) any later version.
3804 + *
3805 + * This library is distributed in the hope that it will be useful,
3806 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3807 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3808 + * GNU General Public License for more details.
3809 + *
3810 + * Or, alternatively,
3811 + *
3812 + * b) Permission is hereby granted, free of charge, to any person
3813 + * obtaining a copy of this software and associated documentation
3814 + * files (the "Software"), to deal in the Software without
3815 + * restriction, including without limitation the rights to use,
3816 + * copy, modify, merge, publish, distribute, sublicense, and/or
3817 + * sell copies of the Software, and to permit persons to whom the
3818 + * Software is furnished to do so, subject to the following
3819 + * conditions:
3820 + *
3821 + * The above copyright notice and this permission notice shall be
3822 + * included in all copies or substantial portions of the Software.
3823 + *
3824 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3825 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3826 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3827 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3828 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3829 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3830 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3831 + * OTHER DEALINGS IN THE SOFTWARE.
3832 + */
3833 +
3834 +#include "fsl-ls1046a-rdb.dts"
3835 +
3836 +&bman_fbpr {
3837 + compatible = "fsl,bman-fbpr";
3838 + alloc-ranges = <0 0 0x10000 0>;
3839 +};
3840 +&qman_fqd {
3841 + compatible = "fsl,qman-fqd";
3842 + alloc-ranges = <0 0 0x10000 0>;
3843 +};
3844 +&qman_pfdr {
3845 + compatible = "fsl,qman-pfdr";
3846 + alloc-ranges = <0 0 0x10000 0>;
3847 +};
3848 +
3849 +&soc {
3850 +#include "qoriq-dpaa-eth.dtsi"
3851 +#include "qoriq-fman3-0-6oh.dtsi"
3852 +};
3853 +
3854 +&fsldpaa {
3855 + ethernet@0 {
3856 + status = "disabled";
3857 + };
3858 + ethernet@1 {
3859 + status = "disabled";
3860 + };
3861 + ethernet@9 {
3862 + compatible = "fsl,dpa-ethernet";
3863 + fsl,fman-mac = <&enet7>;
3864 + dma-coherent;
3865 + };
3866 +};
3867 +
3868 +&fman0 {
3869 + compatible = "fsl,fman", "simple-bus";
3870 +};
3871 --- /dev/null
3872 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
3873 @@ -0,0 +1,110 @@
3874 +/*
3875 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3876 + *
3877 + * Copyright 2016 Freescale Semiconductor, Inc.
3878 + *
3879 + * This file is licensed under the terms of the GNU General Public
3880 + * License version 2. This program is licensed "as is" without any
3881 + * warranty of any kind, whether express or implied.
3882 + */
3883 +
3884 +#include "fsl-ls1046a-rdb-sdk.dts"
3885 +
3886 +&soc {
3887 + bp7: buffer-pool@7 {
3888 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3889 + fsl,bpid = <7>;
3890 + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
3891 + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
3892 + };
3893 +
3894 + bp8: buffer-pool@8 {
3895 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3896 + fsl,bpid = <8>;
3897 + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
3898 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
3899 + };
3900 +
3901 + bp9: buffer-pool@9 {
3902 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3903 + fsl,bpid = <9>;
3904 + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
3905 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
3906 + };
3907 +
3908 + fsl,dpaa {
3909 + compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
3910 +
3911 + ethernet@2 {
3912 + compatible = "fsl,dpa-ethernet-init";
3913 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3914 + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
3915 + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
3916 + };
3917 +
3918 + ethernet@3 {
3919 + compatible = "fsl,dpa-ethernet-init";
3920 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3921 + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
3922 + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
3923 + };
3924 +
3925 + ethernet@4 {
3926 + compatible = "fsl,dpa-ethernet-init";
3927 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3928 + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
3929 + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
3930 + };
3931 +
3932 + ethernet@5 {
3933 + compatible = "fsl,dpa-ethernet-init";
3934 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3935 + fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>;
3936 + fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>;
3937 + };
3938 +
3939 + ethernet@8 {
3940 + compatible = "fsl,dpa-ethernet-init";
3941 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3942 + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
3943 + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
3944 + };
3945 +
3946 + ethernet@9 {
3947 + compatible = "fsl,dpa-ethernet-init";
3948 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3949 + fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>;
3950 + fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>;
3951 + };
3952 +
3953 + dpa-fman0-oh@2 {
3954 + compatible = "fsl,dpa-oh";
3955 + /* Define frame queues for the OH port*/
3956 + /* <OH Rx error, OH Rx default> */
3957 + fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
3958 + fsl,fman-oh-port = <&fman0_oh2>;
3959 + };
3960 + };
3961 +};
3962 +/ {
3963 + reserved-memory {
3964 + #address-cells = <2>;
3965 + #size-cells = <2>;
3966 + ranges;
3967 +
3968 + usdpaa_mem: usdpaa_mem {
3969 + compatible = "fsl,usdpaa-mem";
3970 + alloc-ranges = <0 0 0x10000 0>;
3971 + size = <0 0x10000000>;
3972 + alignment = <0 0x10000000>;
3973 + };
3974 + };
3975 +};
3976 +
3977 +&fman0 {
3978 + fman0_oh2: port@83000 {
3979 + cell-index = <1>;
3980 + compatible = "fsl,fman-port-oh";
3981 + reg = <0x83000 0x1000>;
3982 + };
3983 +};
3984 --- /dev/null
3985 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
3986 @@ -0,0 +1,218 @@
3987 +/*
3988 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3989 + *
3990 + * Copyright 2016 Freescale Semiconductor, Inc.
3991 + *
3992 + * Mingkai Hu <mingkai.hu@nxp.com>
3993 + *
3994 + * This file is dual-licensed: you can use it either under the terms
3995 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3996 + * licensing only applies to this file, and not this project as a
3997 + * whole.
3998 + *
3999 + * a) This library is free software; you can redistribute it and/or
4000 + * modify it under the terms of the GNU General Public License as
4001 + * published by the Free Software Foundation; either version 2 of the
4002 + * License, or (at your option) any later version.
4003 + *
4004 + * This library is distributed in the hope that it will be useful,
4005 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4006 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4007 + * GNU General Public License for more details.
4008 + *
4009 + * Or, alternatively,
4010 + *
4011 + * b) Permission is hereby granted, free of charge, to any person
4012 + * obtaining a copy of this software and associated documentation
4013 + * files (the "Software"), to deal in the Software without
4014 + * restriction, including without limitation the rights to use,
4015 + * copy, modify, merge, publish, distribute, sublicense, and/or
4016 + * sell copies of the Software, and to permit persons to whom the
4017 + * Software is furnished to do so, subject to the following
4018 + * conditions:
4019 + *
4020 + * The above copyright notice and this permission notice shall be
4021 + * included in all copies or substantial portions of the Software.
4022 + *
4023 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
4024 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
4025 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
4026 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
4027 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
4028 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
4029 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
4030 + * OTHER DEALINGS IN THE SOFTWARE.
4031 + */
4032 +
4033 +/dts-v1/;
4034 +
4035 +#include "fsl-ls1046a.dtsi"
4036 +
4037 +/ {
4038 + model = "LS1046A RDB Board";
4039 + compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
4040 +
4041 + aliases {
4042 + serial0 = &duart0;
4043 + serial1 = &duart1;
4044 + serial2 = &duart2;
4045 + serial3 = &duart3;
4046 + };
4047 +
4048 + chosen {
4049 + stdout-path = "serial0:115200n8";
4050 + };
4051 +};
4052 +
4053 +&esdhc {
4054 + mmc-hs200-1_8v;
4055 + sd-uhs-sdr104;
4056 + sd-uhs-sdr50;
4057 + sd-uhs-sdr25;
4058 + sd-uhs-sdr12;
4059 +};
4060 +
4061 +&duart0 {
4062 + status = "okay";
4063 +};
4064 +
4065 +&duart1 {
4066 + status = "okay";
4067 +};
4068 +
4069 +&i2c0 {
4070 + status = "okay";
4071 +
4072 + ina220@40 {
4073 + compatible = "ti,ina220";
4074 + reg = <0x40>;
4075 + shunt-resistor = <1000>;
4076 + };
4077 +
4078 + temp-sensor@4c {
4079 + compatible = "adi,adt7461";
4080 + reg = <0x4c>;
4081 + };
4082 +
4083 + eeprom@56 {
4084 + compatible = "atmel,24c512";
4085 + reg = <0x52>;
4086 + };
4087 +
4088 + eeprom@57 {
4089 + compatible = "atmel,24c512";
4090 + reg = <0x53>;
4091 + };
4092 +};
4093 +
4094 +&i2c3 {
4095 + status = "okay";
4096 +
4097 + rtc@51 {
4098 + compatible = "nxp,pcf2129";
4099 + reg = <0x51>;
4100 + };
4101 +};
4102 +
4103 +&ifc {
4104 + #address-cells = <2>;
4105 + #size-cells = <1>;
4106 + /* NAND Flashe and CPLD on board */
4107 + ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
4108 + 0x2 0x0 0x0 0x7fb00000 0x00000100>;
4109 + status = "okay";
4110 +
4111 + nand@0,0 {
4112 + compatible = "fsl,ifc-nand";
4113 + #address-cells = <1>;
4114 + #size-cells = <1>;
4115 + reg = <0x0 0x0 0x10000>;
4116 + };
4117 +
4118 + cpld: board-control@2,0 {
4119 + compatible = "fsl,ls1046ardb-cpld";
4120 + reg = <0x2 0x0 0x0000100>;
4121 + };
4122 +};
4123 +
4124 +&qspi {
4125 + num-cs = <2>;
4126 + bus-num = <0>;
4127 + status = "okay";
4128 +
4129 + qflash0: s25fs512s@0 {
4130 + compatible = "spansion,m25p80";
4131 + #address-cells = <1>;
4132 + #size-cells = <1>;
4133 + spi-max-frequency = <20000000>;
4134 + reg = <0>;
4135 + };
4136 +
4137 + qflash1: s25fs512s@1 {
4138 + compatible = "spansion,m25p80";
4139 + #address-cells = <1>;
4140 + #size-cells = <1>;
4141 + spi-max-frequency = <20000000>;
4142 + reg = <1>;
4143 + };
4144 +};
4145 +
4146 +#include "fsl-ls1046-post.dtsi"
4147 +
4148 +&fman0 {
4149 + ethernet@e4000 {
4150 + phy-handle = <&rgmii_phy1>;
4151 + phy-connection-type = "rgmii";
4152 + };
4153 +
4154 + ethernet@e6000 {
4155 + phy-handle = <&rgmii_phy2>;
4156 + phy-connection-type = "rgmii";
4157 + };
4158 +
4159 + ethernet@e8000 {
4160 + phy-handle = <&sgmii_phy1>;
4161 + phy-connection-type = "sgmii";
4162 + };
4163 +
4164 + ethernet@ea000 {
4165 + phy-handle = <&sgmii_phy2>;
4166 + phy-connection-type = "sgmii";
4167 + };
4168 +
4169 + ethernet@f0000 { /* 10GEC1 */
4170 + phy-handle = <&aqr106_phy>;
4171 + phy-connection-type = "xgmii";
4172 + };
4173 +
4174 + ethernet@f2000 { /* 10GEC2 */
4175 + fixed-link = <0 1 1000 0 0>;
4176 + phy-connection-type = "xgmii";
4177 + };
4178 +
4179 + mdio@fc000 {
4180 + rgmii_phy1: ethernet-phy@1 {
4181 + reg = <0x1>;
4182 + };
4183 +
4184 + rgmii_phy2: ethernet-phy@2 {
4185 + reg = <0x2>;
4186 + };
4187 +
4188 + sgmii_phy1: ethernet-phy@3 {
4189 + reg = <0x3>;
4190 + };
4191 +
4192 + sgmii_phy2: ethernet-phy@4 {
4193 + reg = <0x4>;
4194 + };
4195 + };
4196 +
4197 + mdio@fd000 {
4198 + aqr106_phy: ethernet-phy@0 {
4199 + compatible = "ethernet-phy-ieee802.3-c45";
4200 + interrupts = <0 131 4>;
4201 + reg = <0x0>;
4202 + };
4203 + };
4204 +};
4205 --- /dev/null
4206 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
4207 @@ -0,0 +1,800 @@
4208 +/*
4209 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4210 + *
4211 + * Copyright 2016 Freescale Semiconductor, Inc.
4212 + *
4213 + * Mingkai Hu <mingkai.hu@nxp.com>
4214 + *
4215 + * This file is dual-licensed: you can use it either under the terms
4216 + * of the GPLv2 or the X11 license, at your option. Note that this dual
4217 + * licensing only applies to this file, and not this project as a
4218 + * whole.
4219 + *
4220 + * a) This library is free software; you can redistribute it and/or
4221 + * modify it under the terms of the GNU General Public License as
4222 + * published by the Free Software Foundation; either version 2 of the
4223 + * License, or (at your option) any later version.
4224 + *
4225 + * This library is distributed in the hope that it will be useful,
4226 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4227 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4228 + * GNU General Public License for more details.
4229 + *
4230 + * Or, alternatively,
4231 + *
4232 + * b) Permission is hereby granted, free of charge, to any person
4233 + * obtaining a copy of this software and associated documentation
4234 + * files (the "Software"), to deal in the Software without
4235 + * restriction, including without limitation the rights to use,
4236 + * copy, modify, merge, publish, distribute, sublicense, and/or
4237 + * sell copies of the Software, and to permit persons to whom the
4238 + * Software is furnished to do so, subject to the following
4239 + * conditions:
4240 + *
4241 + * The above copyright notice and this permission notice shall be
4242 + * included in all copies or substantial portions of the Software.
4243 + *
4244 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
4245 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
4246 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
4247 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
4248 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
4249 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
4250 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
4251 + * OTHER DEALINGS IN THE SOFTWARE.
4252 + */
4253 +
4254 +#include <dt-bindings/interrupt-controller/arm-gic.h>
4255 +#include <dt-bindings/thermal/thermal.h>
4256 +
4257 +/ {
4258 + compatible = "fsl,ls1046a";
4259 + interrupt-parent = <&gic>;
4260 + #address-cells = <2>;
4261 + #size-cells = <2>;
4262 +
4263 + aliases {
4264 + crypto = &crypto;
4265 + fman0 = &fman0;
4266 + ethernet0 = &enet0;
4267 + ethernet1 = &enet1;
4268 + ethernet2 = &enet2;
4269 + ethernet3 = &enet3;
4270 + ethernet4 = &enet4;
4271 + ethernet5 = &enet5;
4272 + ethernet6 = &enet6;
4273 + ethernet7 = &enet7;
4274 + };
4275 +
4276 + cpus {
4277 + #address-cells = <1>;
4278 + #size-cells = <0>;
4279 +
4280 + cpu0: cpu@0 {
4281 + device_type = "cpu";
4282 + compatible = "arm,cortex-a72";
4283 + reg = <0x0>;
4284 + clocks = <&clockgen 1 0>;
4285 + next-level-cache = <&l2>;
4286 + cpu-idle-states = <&CPU_PH20>;
4287 + #cooling-cells = <2>;
4288 + };
4289 +
4290 + cpu1: cpu@1 {
4291 + device_type = "cpu";
4292 + compatible = "arm,cortex-a72";
4293 + reg = <0x1>;
4294 + clocks = <&clockgen 1 0>;
4295 + next-level-cache = <&l2>;
4296 + cpu-idle-states = <&CPU_PH20>;
4297 + };
4298 +
4299 + cpu2: cpu@2 {
4300 + device_type = "cpu";
4301 + compatible = "arm,cortex-a72";
4302 + reg = <0x2>;
4303 + clocks = <&clockgen 1 0>;
4304 + next-level-cache = <&l2>;
4305 + cpu-idle-states = <&CPU_PH20>;
4306 + };
4307 +
4308 + cpu3: cpu@3 {
4309 + device_type = "cpu";
4310 + compatible = "arm,cortex-a72";
4311 + reg = <0x3>;
4312 + clocks = <&clockgen 1 0>;
4313 + next-level-cache = <&l2>;
4314 + cpu-idle-states = <&CPU_PH20>;
4315 + };
4316 +
4317 + l2: l2-cache {
4318 + compatible = "cache";
4319 + };
4320 + };
4321 +
4322 + idle-states {
4323 + /*
4324 + * PSCI node is not added default, U-boot will add missing
4325 + * parts if it determines to use PSCI.
4326 + */
4327 + entry-method = "arm,psci";
4328 +
4329 + CPU_PH20: cpu-ph20 {
4330 + compatible = "arm,idle-state";
4331 + idle-state-name = "PH20";
4332 + arm,psci-suspend-param = <0x0>;
4333 + entry-latency-us = <1000>;
4334 + exit-latency-us = <1000>;
4335 + min-residency-us = <3000>;
4336 + };
4337 + };
4338 +
4339 + memory@80000000 {
4340 + device_type = "memory";
4341 + };
4342 +
4343 + sysclk: sysclk {
4344 + compatible = "fixed-clock";
4345 + #clock-cells = <0>;
4346 + clock-frequency = <100000000>;
4347 + clock-output-names = "sysclk";
4348 + };
4349 +
4350 + reboot {
4351 + compatible ="syscon-reboot";
4352 + regmap = <&dcfg>;
4353 + offset = <0xb0>;
4354 + mask = <0x02>;
4355 + };
4356 +
4357 + timer {
4358 + compatible = "arm,armv8-timer";
4359 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
4360 + IRQ_TYPE_LEVEL_LOW)>,
4361 + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
4362 + IRQ_TYPE_LEVEL_LOW)>,
4363 + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
4364 + IRQ_TYPE_LEVEL_LOW)>,
4365 + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
4366 + IRQ_TYPE_LEVEL_LOW)>;
4367 + };
4368 +
4369 + pmu {
4370 + compatible = "arm,cortex-a72-pmu";
4371 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4372 + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4373 + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
4374 + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
4375 + interrupt-affinity = <&cpu0>,
4376 + <&cpu1>,
4377 + <&cpu2>,
4378 + <&cpu3>;
4379 + };
4380 +
4381 + gic: interrupt-controller@1400000 {
4382 + compatible = "arm,gic-400";
4383 + #interrupt-cells = <3>;
4384 + interrupt-controller;
4385 + reg = <0x0 0x1410000 0 0x10000>, /* GICD */
4386 + <0x0 0x1420000 0 0x20000>, /* GICC */
4387 + <0x0 0x1440000 0 0x20000>, /* GICH */
4388 + <0x0 0x1460000 0 0x20000>; /* GICV */
4389 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
4390 + IRQ_TYPE_LEVEL_LOW)>;
4391 + };
4392 +
4393 + soc: soc {
4394 + compatible = "simple-bus";
4395 + #address-cells = <2>;
4396 + #size-cells = <2>;
4397 + ranges;
4398 +
4399 + ddr: memory-controller@1080000 {
4400 + compatible = "fsl,qoriq-memory-controller";
4401 + reg = <0x0 0x1080000 0x0 0x1000>;
4402 + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
4403 + big-endian;
4404 + };
4405 +
4406 + ifc: ifc@1530000 {
4407 + compatible = "fsl,ifc", "simple-bus";
4408 + reg = <0x0 0x1530000 0x0 0x10000>;
4409 + big-endian;
4410 + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
4411 + };
4412 +
4413 + qspi: quadspi@1550000 {
4414 + compatible = "fsl,ls1021a-qspi";
4415 + #address-cells = <1>;
4416 + #size-cells = <0>;
4417 + reg = <0x0 0x1550000 0x0 0x10000>,
4418 + <0x0 0x40000000 0x0 0x10000000>;
4419 + reg-names = "QuadSPI", "QuadSPI-memory";
4420 + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
4421 + clock-names = "qspi_en", "qspi";
4422 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
4423 + big-endian;
4424 + fsl,qspi-has-second-chip;
4425 + status = "disabled";
4426 + };
4427 +
4428 + esdhc: esdhc@1560000 {
4429 + compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
4430 + reg = <0x0 0x1560000 0x0 0x10000>;
4431 + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
4432 + clocks = <&clockgen 2 1>;
4433 + voltage-ranges = <1800 1800 3300 3300>;
4434 + sdhci,auto-cmd12;
4435 + big-endian;
4436 + bus-width = <4>;
4437 + };
4438 +
4439 + scfg: scfg@1570000 {
4440 + compatible = "fsl,ls1046a-scfg", "syscon";
4441 + reg = <0x0 0x1570000 0x0 0x10000>;
4442 + big-endian;
4443 + };
4444 +
4445 + crypto: crypto@1700000 {
4446 + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
4447 + "fsl,sec-v4.0";
4448 + fsl,sec-era = <8>;
4449 + #address-cells = <1>;
4450 + #size-cells = <1>;
4451 + ranges = <0x0 0x00 0x1700000 0x100000>;
4452 + reg = <0x00 0x1700000 0x0 0x100000>;
4453 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
4454 +
4455 + sec_jr0: jr@10000 {
4456 + compatible = "fsl,sec-v5.4-job-ring",
4457 + "fsl,sec-v5.0-job-ring",
4458 + "fsl,sec-v4.0-job-ring";
4459 + reg = <0x10000 0x10000>;
4460 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
4461 + };
4462 +
4463 + sec_jr1: jr@20000 {
4464 + compatible = "fsl,sec-v5.4-job-ring",
4465 + "fsl,sec-v5.0-job-ring",
4466 + "fsl,sec-v4.0-job-ring";
4467 + reg = <0x20000 0x10000>;
4468 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4469 + };
4470 +
4471 + sec_jr2: jr@30000 {
4472 + compatible = "fsl,sec-v5.4-job-ring",
4473 + "fsl,sec-v5.0-job-ring",
4474 + "fsl,sec-v4.0-job-ring";
4475 + reg = <0x30000 0x10000>;
4476 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
4477 + };
4478 +
4479 + sec_jr3: jr@40000 {
4480 + compatible = "fsl,sec-v5.4-job-ring",
4481 + "fsl,sec-v5.0-job-ring",
4482 + "fsl,sec-v4.0-job-ring";
4483 + reg = <0x40000 0x10000>;
4484 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
4485 + };
4486 + };
4487 +
4488 + qman: qman@1880000 {
4489 + compatible = "fsl,qman";
4490 + reg = <0x00 0x1880000 0x0 0x10000>;
4491 + interrupts = <0 45 0x4>;
4492 + memory-region = <&qman_fqd &qman_pfdr>;
4493 +
4494 + };
4495 +
4496 + bman: bman@1890000 {
4497 + compatible = "fsl,bman";
4498 + reg = <0x00 0x1890000 0x0 0x10000>;
4499 + interrupts = <0 45 0x4>;
4500 + memory-region = <&bman_fbpr>;
4501 +
4502 + };
4503 +
4504 + qportals: qman-portals@500000000 {
4505 + ranges = <0x0 0x5 0x00000000 0x8000000>;
4506 + };
4507 +
4508 + bportals: bman-portals@508000000 {
4509 + ranges = <0x0 0x5 0x08000000 0x8000000>;
4510 + };
4511 +
4512 + dcfg: dcfg@1ee0000 {
4513 + compatible = "fsl,ls1046a-dcfg", "syscon";
4514 + reg = <0x0 0x1ee0000 0x0 0x1000>;
4515 + big-endian;
4516 + };
4517 +
4518 + clockgen: clocking@1ee1000 {
4519 + compatible = "fsl,ls1046a-clockgen";
4520 + reg = <0x0 0x1ee1000 0x0 0x1000>;
4521 + #clock-cells = <2>;
4522 + clocks = <&sysclk>;
4523 + };
4524 +
4525 + tmu: tmu@1f00000 {
4526 + compatible = "fsl,qoriq-tmu";
4527 + reg = <0x0 0x1f00000 0x0 0x10000>;
4528 + interrupts = <0 33 0x4>;
4529 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
4530 + fsl,tmu-calibration =
4531 + /* Calibration data group 1 */
4532 + <0x00000000 0x00000026
4533 + 0x00000001 0x0000002d
4534 + 0x00000002 0x00000032
4535 + 0x00000003 0x00000039
4536 + 0x00000004 0x0000003f
4537 + 0x00000005 0x00000046
4538 + 0x00000006 0x0000004d
4539 + 0x00000007 0x00000054
4540 + 0x00000008 0x0000005a
4541 + 0x00000009 0x00000061
4542 + 0x0000000a 0x0000006a
4543 + 0x0000000b 0x00000071
4544 + /* Calibration data group 2 */
4545 + 0x00010000 0x00000025
4546 + 0x00010001 0x0000002c
4547 + 0x00010002 0x00000035
4548 + 0x00010003 0x0000003d
4549 + 0x00010004 0x00000045
4550 + 0x00010005 0x0000004e
4551 + 0x00010006 0x00000057
4552 + 0x00010007 0x00000061
4553 + 0x00010008 0x0000006b
4554 + 0x00010009 0x00000076
4555 + /* Calibration data group 3 */
4556 + 0x00020000 0x00000029
4557 + 0x00020001 0x00000033
4558 + 0x00020002 0x0000003d
4559 + 0x00020003 0x00000049
4560 + 0x00020004 0x00000056
4561 + 0x00020005 0x00000061
4562 + 0x00020006 0x0000006d
4563 + /* Calibration data group 4 */
4564 + 0x00030000 0x00000021
4565 + 0x00030001 0x0000002a
4566 + 0x00030002 0x0000003c
4567 + 0x00030003 0x0000004e>;
4568 + big-endian;
4569 + #thermal-sensor-cells = <1>;
4570 + };
4571 +
4572 + thermal-zones {
4573 + cpu_thermal: cpu-thermal {
4574 + polling-delay-passive = <1000>;
4575 + polling-delay = <5000>;
4576 + thermal-sensors = <&tmu 3>;
4577 +
4578 + trips {
4579 + cpu_alert: cpu-alert {
4580 + temperature = <85000>;
4581 + hysteresis = <2000>;
4582 + type = "passive";
4583 + };
4584 +
4585 + cpu_crit: cpu-crit {
4586 + temperature = <95000>;
4587 + hysteresis = <2000>;
4588 + type = "critical";
4589 + };
4590 + };
4591 +
4592 + cooling-maps {
4593 + map0 {
4594 + trip = <&cpu_alert>;
4595 + cooling-device =
4596 + <&cpu0 THERMAL_NO_LIMIT
4597 + THERMAL_NO_LIMIT>;
4598 + };
4599 + };
4600 + };
4601 + };
4602 +
4603 + dspi: dspi@2100000 {
4604 + compatible = "fsl,ls1021a-v1.0-dspi";
4605 + #address-cells = <1>;
4606 + #size-cells = <0>;
4607 + reg = <0x0 0x2100000 0x0 0x10000>;
4608 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
4609 + clock-names = "dspi";
4610 + clocks = <&clockgen 4 1>;
4611 + spi-num-chipselects = <5>;
4612 + big-endian;
4613 + status = "disabled";
4614 + };
4615 +
4616 + i2c0: i2c@2180000 {
4617 + compatible = "fsl,vf610-i2c";
4618 + #address-cells = <1>;
4619 + #size-cells = <0>;
4620 + reg = <0x0 0x2180000 0x0 0x10000>;
4621 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
4622 + clocks = <&clockgen 4 1>;
4623 + dmas = <&edma0 1 39>,
4624 + <&edma0 1 38>;
4625 + dma-names = "tx", "rx";
4626 + status = "disabled";
4627 + };
4628 +
4629 + i2c1: i2c@2190000 {
4630 + compatible = "fsl,vf610-i2c";
4631 + #address-cells = <1>;
4632 + #size-cells = <0>;
4633 + reg = <0x0 0x2190000 0x0 0x10000>;
4634 + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
4635 + clocks = <&clockgen 4 1>;
4636 + status = "disabled";
4637 + };
4638 +
4639 + i2c2: i2c@21a0000 {
4640 + compatible = "fsl,vf610-i2c";
4641 + #address-cells = <1>;
4642 + #size-cells = <0>;
4643 + reg = <0x0 0x21a0000 0x0 0x10000>;
4644 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
4645 + clocks = <&clockgen 4 1>;
4646 + status = "disabled";
4647 + };
4648 +
4649 + i2c3: i2c@21b0000 {
4650 + compatible = "fsl,vf610-i2c";
4651 + #address-cells = <1>;
4652 + #size-cells = <0>;
4653 + reg = <0x0 0x21b0000 0x0 0x10000>;
4654 + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
4655 + clocks = <&clockgen 4 1>;
4656 + status = "disabled";
4657 + };
4658 +
4659 + duart0: serial@21c0500 {
4660 + compatible = "fsl,ns16550", "ns16550a";
4661 + reg = <0x00 0x21c0500 0x0 0x100>;
4662 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
4663 + clocks = <&clockgen 4 1>;
4664 + };
4665 +
4666 + duart1: serial@21c0600 {
4667 + compatible = "fsl,ns16550", "ns16550a";
4668 + reg = <0x00 0x21c0600 0x0 0x100>;
4669 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
4670 + clocks = <&clockgen 4 1>;
4671 + };
4672 +
4673 + duart2: serial@21d0500 {
4674 + compatible = "fsl,ns16550", "ns16550a";
4675 + reg = <0x0 0x21d0500 0x0 0x100>;
4676 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
4677 + clocks = <&clockgen 4 1>;
4678 + };
4679 +
4680 + duart3: serial@21d0600 {
4681 + compatible = "fsl,ns16550", "ns16550a";
4682 + reg = <0x0 0x21d0600 0x0 0x100>;
4683 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
4684 + clocks = <&clockgen 4 1>;
4685 + };
4686 +
4687 + gpio0: gpio@2300000 {
4688 + compatible = "fsl,qoriq-gpio";
4689 + reg = <0x0 0x2300000 0x0 0x10000>;
4690 + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
4691 + gpio-controller;
4692 + #gpio-cells = <2>;
4693 + interrupt-controller;
4694 + #interrupt-cells = <2>;
4695 + };
4696 +
4697 + gpio1: gpio@2310000 {
4698 + compatible = "fsl,qoriq-gpio";
4699 + reg = <0x0 0x2310000 0x0 0x10000>;
4700 + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
4701 + gpio-controller;
4702 + #gpio-cells = <2>;
4703 + interrupt-controller;
4704 + #interrupt-cells = <2>;
4705 + };
4706 +
4707 + gpio2: gpio@2320000 {
4708 + compatible = "fsl,qoriq-gpio";
4709 + reg = <0x0 0x2320000 0x0 0x10000>;
4710 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
4711 + gpio-controller;
4712 + #gpio-cells = <2>;
4713 + interrupt-controller;
4714 + #interrupt-cells = <2>;
4715 + };
4716 +
4717 + gpio3: gpio@2330000 {
4718 + compatible = "fsl,qoriq-gpio";
4719 + reg = <0x0 0x2330000 0x0 0x10000>;
4720 + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
4721 + gpio-controller;
4722 + #gpio-cells = <2>;
4723 + interrupt-controller;
4724 + #interrupt-cells = <2>;
4725 + };
4726 +
4727 + lpuart0: serial@2950000 {
4728 + compatible = "fsl,ls1021a-lpuart";
4729 + reg = <0x0 0x2950000 0x0 0x1000>;
4730 + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
4731 + clocks = <&clockgen 4 0>;
4732 + clock-names = "ipg";
4733 + status = "disabled";
4734 + };
4735 +
4736 + lpuart1: serial@2960000 {
4737 + compatible = "fsl,ls1021a-lpuart";
4738 + reg = <0x0 0x2960000 0x0 0x1000>;
4739 + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
4740 + clocks = <&clockgen 4 1>;
4741 + clock-names = "ipg";
4742 + status = "disabled";
4743 + };
4744 +
4745 + lpuart2: serial@2970000 {
4746 + compatible = "fsl,ls1021a-lpuart";
4747 + reg = <0x0 0x2970000 0x0 0x1000>;
4748 + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
4749 + clocks = <&clockgen 4 1>;
4750 + clock-names = "ipg";
4751 + status = "disabled";
4752 + };
4753 +
4754 + lpuart3: serial@2980000 {
4755 + compatible = "fsl,ls1021a-lpuart";
4756 + reg = <0x0 0x2980000 0x0 0x1000>;
4757 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
4758 + clocks = <&clockgen 4 1>;
4759 + clock-names = "ipg";
4760 + status = "disabled";
4761 + };
4762 +
4763 + lpuart4: serial@2990000 {
4764 + compatible = "fsl,ls1021a-lpuart";
4765 + reg = <0x0 0x2990000 0x0 0x1000>;
4766 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
4767 + clocks = <&clockgen 4 1>;
4768 + clock-names = "ipg";
4769 + status = "disabled";
4770 + };
4771 +
4772 + lpuart5: serial@29a0000 {
4773 + compatible = "fsl,ls1021a-lpuart";
4774 + reg = <0x0 0x29a0000 0x0 0x1000>;
4775 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
4776 + clocks = <&clockgen 4 1>;
4777 + clock-names = "ipg";
4778 + status = "disabled";
4779 + };
4780 +
4781 + ftm0: ftm0@29d0000 {
4782 + compatible = "fsl,ls1046a-ftm";
4783 + reg = <0x0 0x29d0000 0x0 0x10000>,
4784 + <0x0 0x1ee2140 0x0 0x4>;
4785 + reg-names = "ftm", "FlexTimer1";
4786 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
4787 + big-endian;
4788 + };
4789 +
4790 + wdog0: watchdog@2ad0000 {
4791 + compatible = "fsl,imx21-wdt";
4792 + reg = <0x0 0x2ad0000 0x0 0x10000>;
4793 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4794 + clocks = <&clockgen 4 1>;
4795 + big-endian;
4796 + };
4797 +
4798 + edma0: edma@2c00000 {
4799 + #dma-cells = <2>;
4800 + compatible = "fsl,vf610-edma";
4801 + reg = <0x0 0x2c00000 0x0 0x10000>,
4802 + <0x0 0x2c10000 0x0 0x10000>,
4803 + <0x0 0x2c20000 0x0 0x10000>;
4804 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4805 + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
4806 + interrupt-names = "edma-tx", "edma-err";
4807 + dma-channels = <32>;
4808 + big-endian;
4809 + clock-names = "dmamux0", "dmamux1";
4810 + clocks = <&clockgen 4 1>,
4811 + <&clockgen 4 1>;
4812 + };
4813 +
4814 + usb0: usb@2f00000 {
4815 + compatible = "snps,dwc3";
4816 + reg = <0x0 0x2f00000 0x0 0x10000>;
4817 + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
4818 + dr_mode = "host";
4819 + snps,quirk-frame-length-adjustment = <0x20>;
4820 + snps,dis_rxdet_inp3_quirk;
4821 + };
4822 +
4823 + usb1: usb@3000000 {
4824 + compatible = "snps,dwc3";
4825 + reg = <0x0 0x3000000 0x0 0x10000>;
4826 + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
4827 + dr_mode = "host";
4828 + snps,quirk-frame-length-adjustment = <0x20>;
4829 + snps,dis_rxdet_inp3_quirk;
4830 + };
4831 +
4832 + usb2: usb@3100000 {
4833 + compatible = "snps,dwc3";
4834 + reg = <0x0 0x3100000 0x0 0x10000>;
4835 + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
4836 + dr_mode = "host";
4837 + snps,quirk-frame-length-adjustment = <0x20>;
4838 + snps,dis_rxdet_inp3_quirk;
4839 + };
4840 +
4841 + sata: sata@3200000 {
4842 + compatible = "fsl,ls1046a-ahci";
4843 + reg = <0x0 0x3200000 0x0 0x10000>,
4844 + <0x0 0x20140520 0x0 0x4>;
4845 + reg-names = "ahci", "sata-ecc";
4846 + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
4847 + clocks = <&clockgen 4 1>;
4848 + dma-coherent;
4849 + };
4850 +
4851 + qdma: qdma@8380000 {
4852 + compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
4853 + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
4854 + <0x0 0x8390000 0x0 0x10000>, /* Status regs */
4855 + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
4856 + interrupts = <0 153 0x4>,
4857 + <0 39 0x4>;
4858 + interrupt-names = "qdma-error", "qdma-queue";
4859 + channels = <8>;
4860 + queues = <2>;
4861 + status-sizes = <64>;
4862 + queue-sizes = <64 64>;
4863 + big-endian;
4864 + };
4865 +
4866 + msi1: msi-controller@1580000 {
4867 + compatible = "fsl,ls1046a-msi";
4868 + msi-controller;
4869 + reg = <0x0 0x1580000 0x0 0x10000>;
4870 + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4871 + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4872 + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4873 + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
4874 + };
4875 +
4876 + msi2: msi-controller@1590000 {
4877 + compatible = "fsl,ls1046a-msi";
4878 + msi-controller;
4879 + reg = <0x0 0x1590000 0x0 0x10000>;
4880 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
4881 + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
4882 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
4883 + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
4884 + };
4885 +
4886 + msi3: msi-controller@15a0000 {
4887 + compatible = "fsl,ls1046a-msi";
4888 + msi-controller;
4889 + reg = <0x0 0x15a0000 0x0 0x10000>;
4890 + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
4891 + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
4892 + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
4893 + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
4894 + };
4895 +
4896 + pcie@3400000 {
4897 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
4898 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
4899 + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
4900 + reg-names = "regs", "config";
4901 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
4902 + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
4903 + interrupt-names = "pme", "aer";
4904 + #address-cells = <3>;
4905 + #size-cells = <2>;
4906 + device_type = "pci";
4907 + dma-coherent;
4908 + num-lanes = <4>;
4909 + bus-range = <0x0 0xff>;
4910 + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
4911 + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
4912 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
4913 + #interrupt-cells = <1>;
4914 + interrupt-map-mask = <0 0 0 7>;
4915 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4916 + <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4917 + <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4918 + <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
4919 + };
4920 +
4921 + pcie@3500000 {
4922 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
4923 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
4924 + 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
4925 + reg-names = "regs", "config";
4926 + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
4927 + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
4928 + interrupt-names = "pme", "aer";
4929 + #address-cells = <3>;
4930 + #size-cells = <2>;
4931 + device_type = "pci";
4932 + dma-coherent;
4933 + num-lanes = <2>;
4934 + bus-range = <0x0 0xff>;
4935 + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
4936 + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
4937 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
4938 + #interrupt-cells = <1>;
4939 + interrupt-map-mask = <0 0 0 7>;
4940 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
4941 + <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
4942 + <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
4943 + <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
4944 + };
4945 +
4946 + pcie@3600000 {
4947 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
4948 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
4949 + 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
4950 + reg-names = "regs", "config";
4951 + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
4952 + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
4953 + interrupt-names = "pme", "aer";
4954 + #address-cells = <3>;
4955 + #size-cells = <2>;
4956 + device_type = "pci";
4957 + dma-coherent;
4958 + num-lanes = <2>;
4959 + bus-range = <0x0 0xff>;
4960 + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
4961 + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
4962 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
4963 + #interrupt-cells = <1>;
4964 + interrupt-map-mask = <0 0 0 7>;
4965 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
4966 + <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
4967 + <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
4968 + <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
4969 + };
4970 +
4971 + };
4972 +
4973 + reserved-memory {
4974 + #address-cells = <2>;
4975 + #size-cells = <2>;
4976 + ranges;
4977 +
4978 + bman_fbpr: bman-fbpr {
4979 + compatible = "shared-dma-pool";
4980 + size = <0 0x1000000>;
4981 + alignment = <0 0x1000000>;
4982 + no-map;
4983 + };
4984 + qman_fqd: qman-fqd {
4985 + compatible = "shared-dma-pool";
4986 + size = <0 0x800000>;
4987 + alignment = <0 0x800000>;
4988 + no-map;
4989 + };
4990 + qman_pfdr: qman-pfdr {
4991 + compatible = "shared-dma-pool";
4992 + size = <0 0x2000000>;
4993 + alignment = <0 0x2000000>;
4994 + no-map;
4995 + };
4996 + };
4997 +
4998 + firmware {
4999 + optee {
5000 + compatible = "linaro,optee-tz";
5001 + method = "smc";
5002 + };
5003 + };
5004 +};
5005 +
5006 +#include "qoriq-qman1-portals.dtsi"
5007 +#include "qoriq-bman1-portals.dtsi"
5008 --- /dev/null
5009 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
5010 @@ -0,0 +1,173 @@
5011 +/*
5012 + * Device Tree file for NXP LS1088A QDS Board.
5013 + *
5014 + * Copyright 2017 NXP
5015 + *
5016 + * Harninder Rai <harninder.rai@nxp.com>
5017 + *
5018 + * This file is dual-licensed: you can use it either under the terms
5019 + * of the GPLv2 or the X11 license, at your option. Note that this dual
5020 + * licensing only applies to this file, and not this project as a
5021 + * whole.
5022 + *
5023 + * a) This library is free software; you can redistribute it and/or
5024 + * modify it under the terms of the GNU General Public License as
5025 + * published by the Free Software Foundation; either version 2 of the
5026 + * License, or (at your option) any later version.
5027 + *
5028 + * This library is distributed in the hope that it will be useful,
5029 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5030 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5031 + * GNU General Public License for more details.
5032 + *
5033 + * Or, alternatively,
5034 + *
5035 + * b) Permission is hereby granted, free of charge, to any person
5036 + * obtaining a copy of this software and associated documentation
5037 + * files (the "Software"), to deal in the Software without
5038 + * restriction, including without limitation the rights to use,
5039 + * copy, modify, merge, publish, distribute, sublicense, and/or
5040 + * sell copies of the Software, and to permit persons to whom the
5041 + * Software is furnished to do so, subject to the following
5042 + * conditions:
5043 + *
5044 + * The above copyright notice and this permission notice shall be
5045 + * included in all copies or substantial portions of the Software.
5046 + *
5047 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
5048 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
5049 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
5050 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
5051 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
5052 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
5053 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
5054 + * OTHER DEALINGS IN THE SOFTWARE.
5055 + */
5056 +
5057 +/dts-v1/;
5058 +
5059 +#include "fsl-ls1088a.dtsi"
5060 +
5061 +/ {
5062 + model = "LS1088A QDS Board";
5063 + compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
5064 +};
5065 +
5066 +&i2c0 {
5067 + status = "okay";
5068 +
5069 + i2c-switch@77 {
5070 + compatible = "nxp,pca9547";
5071 + reg = <0x77>;
5072 + #address-cells = <1>;
5073 + #size-cells = <0>;
5074 +
5075 + i2c@2 {
5076 + #address-cells = <1>;
5077 + #size-cells = <0>;
5078 + reg = <0x2>;
5079 +
5080 + ina220@40 {
5081 + compatible = "ti,ina220";
5082 + reg = <0x40>;
5083 + shunt-resistor = <1000>;
5084 + };
5085 +
5086 + ina220@41 {
5087 + compatible = "ti,ina220";
5088 + reg = <0x41>;
5089 + shunt-resistor = <1000>;
5090 + };
5091 + };
5092 +
5093 + i2c@3 {
5094 + #address-cells = <1>;
5095 + #size-cells = <0>;
5096 + reg = <0x3>;
5097 +
5098 + temp-sensor@4c {
5099 + compatible = "adi,adt7461a";
5100 + reg = <0x4c>;
5101 + };
5102 +
5103 + rtc@51 {
5104 + compatible = "nxp,pcf2129";
5105 + reg = <0x51>;
5106 + /* IRQ10_B */
5107 + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
5108 + };
5109 +
5110 + eeprom@56 {
5111 + compatible = "atmel,24c512";
5112 + reg = <0x56>;
5113 + };
5114 +
5115 + eeprom@57 {
5116 + compatible = "atmel,24c512";
5117 + reg = <0x57>;
5118 + };
5119 + };
5120 + };
5121 +};
5122 +
5123 +&qspi {
5124 + status = "okay";
5125 + qflash0: s25fs512s@0 {
5126 + compatible = "spansion,m25p80";
5127 + #address-cells = <1>;
5128 + #size-cells = <1>;
5129 + spi-max-frequency = <20000000>;
5130 + m25p,fast-read;
5131 + reg = <0>;
5132 + };
5133 +
5134 + qflash1: s25fs512s@1 {
5135 + compatible = "spansion,m25p80";
5136 + #address-cells = <1>;
5137 + #size-cells = <1>;
5138 + spi-max-frequency = <20000000>;
5139 + m25p,fast-read;
5140 + reg = <1>;
5141 + };
5142 +};
5143 +
5144 +&ifc {
5145 + status = "okay";
5146 +
5147 + ranges = <0 0 0x5 0x80000000 0x08000000
5148 + 2 0 0x5 0x30000000 0x00010000
5149 + 3 0 0x5 0x20000000 0x00010000>;
5150 +
5151 + nor@0,0 {
5152 + compatible = "cfi-flash";
5153 + reg = <0x0 0x0 0x8000000>;
5154 + bank-width = <2>;
5155 + device-width = <1>;
5156 + };
5157 +
5158 + nand@2,0 {
5159 + compatible = "fsl,ifc-nand";
5160 + reg = <0x2 0x0 0x10000>;
5161 + };
5162 +
5163 + fpga: board-control@3,0 {
5164 + compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis";
5165 + reg = <0x3 0x0 0x0000100>;
5166 + };
5167 +};
5168 +
5169 +&duart0 {
5170 + status = "okay";
5171 +};
5172 +
5173 +&duart1 {
5174 + status = "okay";
5175 +};
5176 +
5177 +&esdhc {
5178 + status = "okay";
5179 +};
5180 +
5181 +&sata {
5182 + status = "okay";
5183 +};
5184 --- /dev/null
5185 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
5186 @@ -0,0 +1,236 @@
5187 +/*
5188 + * Device Tree file for NXP LS1088A RDB Board.
5189 + *
5190 + * Copyright 2017 NXP
5191 + *
5192 + * Harninder Rai <harninder.rai@nxp.com>
5193 + *
5194 + * This file is dual-licensed: you can use it either under the terms
5195 + * of the GPLv2 or the X11 license, at your option. Note that this dual
5196 + * licensing only applies to this file, and not this project as a
5197 + * whole.
5198 + *
5199 + * a) This library is free software; you can redistribute it and/or
5200 + * modify it under the terms of the GNU General Public License as
5201 + * published by the Free Software Foundation; either version 2 of the
5202 + * License, or (at your option) any later version.
5203 + *
5204 + * This library is distributed in the hope that it will be useful,
5205 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5206 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5207 + * GNU General Public License for more details.
5208 + *
5209 + * Or, alternatively,
5210 + *
5211 + * b) Permission is hereby granted, free of charge, to any person
5212 + * obtaining a copy of this software and associated documentation
5213 + * files (the "Software"), to deal in the Software without
5214 + * restriction, including without limitation the rights to use,
5215 + * copy, modify, merge, publish, distribute, sublicense, and/or
5216 + * sell copies of the Software, and to permit persons to whom the
5217 + * Software is furnished to do so, subject to the following
5218 + * conditions:
5219 + *
5220 + * The above copyright notice and this permission notice shall be
5221 + * included in all copies or substantial portions of the Software.
5222 + *
5223 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
5224 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
5225 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
5226 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
5227 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
5228 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
5229 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
5230 + * OTHER DEALINGS IN THE SOFTWARE.
5231 + */
5232 +
5233 +/dts-v1/;
5234 +
5235 +#include "fsl-ls1088a.dtsi"
5236 +
5237 +/ {
5238 + model = "L1088A RDB Board";
5239 + compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
5240 +};
5241 +
5242 +&i2c0 {
5243 + status = "okay";
5244 +
5245 + i2c-switch@77 {
5246 + compatible = "nxp,pca9547";
5247 + reg = <0x77>;
5248 + #address-cells = <1>;
5249 + #size-cells = <0>;
5250 +
5251 + i2c@2 {
5252 + #address-cells = <1>;
5253 + #size-cells = <0>;
5254 + reg = <0x2>;
5255 +
5256 + ina220@40 {
5257 + compatible = "ti,ina220";
5258 + reg = <0x40>;
5259 + shunt-resistor = <1000>;
5260 + };
5261 + };
5262 +
5263 + i2c@3 {
5264 + #address-cells = <1>;
5265 + #size-cells = <0>;
5266 + reg = <0x3>;
5267 +
5268 + temp-sensor@4c {
5269 + compatible = "adi,adt7461a";
5270 + reg = <0x4c>;
5271 + };
5272 +
5273 + rtc@51 {
5274 + compatible = "nxp,pcf2129";
5275 + reg = <0x51>;
5276 + /* IRQ10_B */
5277 + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
5278 + };
5279 + };
5280 + };
5281 +};
5282 +
5283 +&qspi {
5284 + status = "okay";
5285 + qflash0: s25fs512s@0 {
5286 + compatible = "spansion,m25p80";
5287 + #address-cells = <1>;
5288 + #size-cells = <1>;
5289 + m25p,fast-read;
5290 + spi-max-frequency = <20000000>;
5291 + reg = <0>;
5292 + };
5293 +
5294 + qflash1: s25fs512s@1 {
5295 + compatible = "spansion,m25p80";
5296 + #address-cells = <1>;
5297 + #size-cells = <1>;
5298 + m25p,fast-read;
5299 + spi-max-frequency = <20000000>;
5300 + reg = <1>;
5301 + };
5302 +};
5303 +
5304 +&ifc {
5305 + status = "okay";
5306 +
5307 + ranges = <0 0 0x5 0x30000000 0x00010000
5308 + 2 0 0x5 0x20000000 0x00010000>;
5309 +
5310 + nand@0,0 {
5311 + compatible = "fsl,ifc-nand";
5312 + reg = <0x0 0x0 0x10000>;
5313 + };
5314 +
5315 + fpga: board-control@2,0 {
5316 + compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
5317 + reg = <0x2 0x0 0x0000100>;
5318 + };
5319 +};
5320 +
5321 +&duart0 {
5322 + status = "okay";
5323 +};
5324 +
5325 +&duart1 {
5326 + status = "okay";
5327 +};
5328 +
5329 +&usb0 {
5330 + status = "okay";
5331 +};
5332 +
5333 +&usb1 {
5334 + status = "okay";
5335 +};
5336 +
5337 +&esdhc {
5338 + status = "okay";
5339 +};
5340 +
5341 +&sata {
5342 + status = "okay";
5343 +};
5344 +
5345 +&emdio1 {
5346 + /* Freescale F104 PHY1 */
5347 + mdio1_phy1: emdio1_phy@1 {
5348 + reg = <0x1c>;
5349 + phy-connection-type = "qsgmii";
5350 + };
5351 + mdio1_phy2: emdio1_phy@2 {
5352 + reg = <0x1d>;
5353 + phy-connection-type = "qsgmii";
5354 + };
5355 + mdio1_phy3: emdio1_phy@3 {
5356 + reg = <0x1e>;
5357 + phy-connection-type = "qsgmii";
5358 + };
5359 + mdio1_phy4: emdio1_phy@4 {
5360 + reg = <0x1f>;
5361 + phy-connection-type = "qsgmii";
5362 + };
5363 + /* F104 PHY2 */
5364 + mdio1_phy5: emdio1_phy@5 {
5365 + reg = <0x0c>;
5366 + phy-connection-type = "qsgmii";
5367 + };
5368 + mdio1_phy6: emdio1_phy@6 {
5369 + reg = <0x0d>;
5370 + phy-connection-type = "qsgmii";
5371 + };
5372 + mdio1_phy7: emdio1_phy@7 {
5373 + reg = <0x0e>;
5374 + phy-connection-type = "qsgmii";
5375 + };
5376 + mdio1_phy8: emdio1_phy@8 {
5377 + reg = <0x0f>;
5378 + phy-connection-type = "qsgmii";
5379 + };
5380 +};
5381 +
5382 +&emdio2 {
5383 + /* Aquantia AQR105 10G PHY */
5384 + mdio2_phy1: emdio2_phy@1 {
5385 + compatible = "ethernet-phy-ieee802.3-c45";
5386 + interrupts = <0 2 0x4>;
5387 + reg = <0x0>;
5388 + phy-connection-type = "xfi";
5389 + };
5390 +};
5391 +
5392 +/* DPMAC connections to external PHYs
5393 + * based on LS1088A RM RevC - $24.1.2 SerDes Options
5394 + */
5395 +/* DPMAC1 is 10G SFP+, fixed link */
5396 +&dpmac2 {
5397 + phy-handle = <&mdio2_phy1>;
5398 +};
5399 +&dpmac3 {
5400 + phy-handle = <&mdio1_phy5>;
5401 +};
5402 +&dpmac4 {
5403 + phy-handle = <&mdio1_phy6>;
5404 +};
5405 +&dpmac5 {
5406 + phy-handle = <&mdio1_phy7>;
5407 +};
5408 +&dpmac6 {
5409 + phy-handle = <&mdio1_phy8>;
5410 +};
5411 +&dpmac7 {
5412 + phy-handle = <&mdio1_phy1>;
5413 +};
5414 +&dpmac8 {
5415 + phy-handle = <&mdio1_phy2>;
5416 +};
5417 +&dpmac9 {
5418 + phy-handle = <&mdio1_phy3>;
5419 +};
5420 +&dpmac10 {
5421 + phy-handle = <&mdio1_phy4>;
5422 +};
5423 --- /dev/null
5424 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
5425 @@ -0,0 +1,825 @@
5426 +/*
5427 + * Device Tree Include file for NXP Layerscape-1088A family SoC.
5428 + *
5429 + * Copyright 2017 NXP
5430 + *
5431 + * Harninder Rai <harninder.rai@nxp.com>
5432 + *
5433 + * This file is dual-licensed: you can use it either under the terms
5434 + * of the GPLv2 or the X11 license, at your option. Note that this dual
5435 + * licensing only applies to this file, and not this project as a
5436 + * whole.
5437 + *
5438 + * a) This library is free software; you can redistribute it and/or
5439 + * modify it under the terms of the GNU General Public License as
5440 + * published by the Free Software Foundation; either version 2 of the
5441 + * License, or (at your option) any later version.
5442 + *
5443 + * This library is distributed in the hope that it will be useful,
5444 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5445 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5446 + * GNU General Public License for more details.
5447 + *
5448 + * Or, alternatively,
5449 + *
5450 + * b) Permission is hereby granted, free of charge, to any person
5451 + * obtaining a copy of this software and associated documentation
5452 + * files (the "Software"), to deal in the Software without
5453 + * restriction, including without limitation the rights to use,
5454 + * copy, modify, merge, publish, distribute, sublicense, and/or
5455 + * sell copies of the Software, and to permit persons to whom the
5456 + * Software is furnished to do so, subject to the following
5457 + * conditions:
5458 + *
5459 + * The above copyright notice and this permission notice shall be
5460 + * included in all copies or substantial portions of the Software.
5461 + *
5462 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
5463 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
5464 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
5465 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
5466 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
5467 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
5468 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
5469 + * OTHER DEALINGS IN THE SOFTWARE.
5470 + */
5471 +#include <dt-bindings/interrupt-controller/arm-gic.h>
5472 +#include <dt-bindings/thermal/thermal.h>
5473 +
5474 +/ {
5475 + compatible = "fsl,ls1088a";
5476 + interrupt-parent = <&gic>;
5477 + #address-cells = <2>;
5478 + #size-cells = <2>;
5479 +
5480 + aliases {
5481 + crypto = &crypto;
5482 + };
5483 +
5484 + cpus {
5485 + #address-cells = <1>;
5486 + #size-cells = <0>;
5487 +
5488 + /* We have 2 clusters having 4 Cortex-A53 cores each */
5489 + cpu0: cpu@0 {
5490 + device_type = "cpu";
5491 + compatible = "arm,cortex-a53";
5492 + reg = <0x0>;
5493 + clocks = <&clockgen 1 0>;
5494 + #cooling-cells = <2>;
5495 + cpu-idle-states = <&CPU_PH20>;
5496 + };
5497 +
5498 + cpu1: cpu@1 {
5499 + device_type = "cpu";
5500 + compatible = "arm,cortex-a53";
5501 + reg = <0x1>;
5502 + clocks = <&clockgen 1 0>;
5503 + cpu-idle-states = <&CPU_PH20>;
5504 + };
5505 +
5506 + cpu2: cpu@2 {
5507 + device_type = "cpu";
5508 + compatible = "arm,cortex-a53";
5509 + reg = <0x2>;
5510 + clocks = <&clockgen 1 0>;
5511 + cpu-idle-states = <&CPU_PH20>;
5512 + };
5513 +
5514 + cpu3: cpu@3 {
5515 + device_type = "cpu";
5516 + compatible = "arm,cortex-a53";
5517 + reg = <0x3>;
5518 + clocks = <&clockgen 1 0>;
5519 + cpu-idle-states = <&CPU_PH20>;
5520 + };
5521 +
5522 + cpu4: cpu@100 {
5523 + device_type = "cpu";
5524 + compatible = "arm,cortex-a53";
5525 + reg = <0x100>;
5526 + clocks = <&clockgen 1 1>;
5527 + #cooling-cells = <2>;
5528 + cpu-idle-states = <&CPU_PH20>;
5529 + };
5530 +
5531 + cpu5: cpu@101 {
5532 + device_type = "cpu";
5533 + compatible = "arm,cortex-a53";
5534 + reg = <0x101>;
5535 + clocks = <&clockgen 1 1>;
5536 + cpu-idle-states = <&CPU_PH20>;
5537 + };
5538 +
5539 + cpu6: cpu@102 {
5540 + device_type = "cpu";
5541 + compatible = "arm,cortex-a53";
5542 + reg = <0x102>;
5543 + clocks = <&clockgen 1 1>;
5544 + cpu-idle-states = <&CPU_PH20>;
5545 + };
5546 +
5547 + cpu7: cpu@103 {
5548 + device_type = "cpu";
5549 + compatible = "arm,cortex-a53";
5550 + reg = <0x103>;
5551 + clocks = <&clockgen 1 1>;
5552 + cpu-idle-states = <&CPU_PH20>;
5553 + };
5554 + };
5555 +
5556 + idle-states {
5557 + /*
5558 + * PSCI node is not added default, U-boot will add missing
5559 + * parts if it determines to use PSCI.
5560 + */
5561 + entry-method = "arm,psci";
5562 +
5563 + CPU_PH20: cpu-ph20 {
5564 + compatible = "arm,idle-state";
5565 + idle-state-name = "PH20";
5566 + arm,psci-suspend-param = <0x0>;
5567 + entry-latency-us = <1000>;
5568 + exit-latency-us = <1000>;
5569 + min-residency-us = <3000>;
5570 + };
5571 + };
5572 +
5573 + gic: interrupt-controller@6000000 {
5574 + compatible = "arm,gic-v3";
5575 + #interrupt-cells = <3>;
5576 + #address-cells = <2>;
5577 + #size-cells = <2>;
5578 + ranges;
5579 + interrupt-controller;
5580 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
5581 + <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
5582 + <0x0 0x0c0c0000 0 0x2000>, /* GICC */
5583 + <0x0 0x0c0d0000 0 0x1000>, /* GICH */
5584 + <0x0 0x0c0e0000 0 0x20000>; /* GICV */
5585 + interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
5586 +
5587 + its: gic-its@6020000 {
5588 + compatible = "arm,gic-v3-its";
5589 + msi-controller;
5590 + reg = <0x0 0x6020000 0 0x20000>;
5591 + };
5592 + };
5593 +
5594 + timer {
5595 + compatible = "arm,armv8-timer";
5596 + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
5597 + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
5598 + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
5599 + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
5600 + };
5601 +
5602 + fsl_mc: fsl-mc@80c000000 {
5603 + compatible = "fsl,qoriq-mc";
5604 + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
5605 + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
5606 + msi-parent = <&its>;
5607 + iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
5608 + #address-cells = <3>;
5609 + #size-cells = <1>;
5610 +
5611 + /*
5612 + * Region type 0x0 - MC portals
5613 + * Region type 0x1 - QBMAN portals
5614 + */
5615 + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
5616 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
5617 +
5618 + dpmacs {
5619 + #address-cells = <1>;
5620 + #size-cells = <0>;
5621 +
5622 + dpmac1: dpmac@1 {
5623 + compatible = "fsl,qoriq-mc-dpmac";
5624 + reg = <1>;
5625 + };
5626 + dpmac2: dpmac@2 {
5627 + compatible = "fsl,qoriq-mc-dpmac";
5628 + reg = <2>;
5629 + };
5630 + dpmac3: dpmac@3 {
5631 + compatible = "fsl,qoriq-mc-dpmac";
5632 + reg = <3>;
5633 + };
5634 + dpmac4: dpmac@4 {
5635 + compatible = "fsl,qoriq-mc-dpmac";
5636 + reg = <4>;
5637 + };
5638 + dpmac5: dpmac@5 {
5639 + compatible = "fsl,qoriq-mc-dpmac";
5640 + reg = <5>;
5641 + };
5642 + dpmac6: dpmac@6 {
5643 + compatible = "fsl,qoriq-mc-dpmac";
5644 + reg = <6>;
5645 + };
5646 + dpmac7: dpmac@7 {
5647 + compatible = "fsl,qoriq-mc-dpmac";
5648 + reg = <7>;
5649 + };
5650 + dpmac8: dpmac@8 {
5651 + compatible = "fsl,qoriq-mc-dpmac";
5652 + reg = <8>;
5653 + };
5654 + dpmac9: dpmac@9 {
5655 + compatible = "fsl,qoriq-mc-dpmac";
5656 + reg = <9>;
5657 + };
5658 + dpmac10: dpmac@10 {
5659 + compatible = "fsl,qoriq-mc-dpmac";
5660 + reg = <0xa>;
5661 + };
5662 + };
5663 +
5664 + };
5665 +
5666 + sysclk: sysclk {
5667 + compatible = "fixed-clock";
5668 + #clock-cells = <0>;
5669 + clock-frequency = <100000000>;
5670 + clock-output-names = "sysclk";
5671 + };
5672 +
5673 + dcfg: dcfg@1e00000 {
5674 + compatible = "fsl,ls1088a-dcfg", "syscon";
5675 + reg = <0x0 0x1e00000 0x0 0x10000>;
5676 + little-endian;
5677 + };
5678 +
5679 + rstcr: syscon@1e60000 {
5680 + compatible = "fsl,ls1088a-rstcr", "syscon";
5681 + reg = <0x0 0x1e60000 0x0 0x4>;
5682 + };
5683 +
5684 + reboot {
5685 + compatible = "syscon-reboot";
5686 + regmap = <&rstcr>;
5687 + offset = <0x0>;
5688 + mask = <0x02>;
5689 + };
5690 +
5691 +
5692 + soc {
5693 + compatible = "simple-bus";
5694 + #address-cells = <2>;
5695 + #size-cells = <2>;
5696 + ranges;
5697 +
5698 + clockgen: clocking@1300000 {
5699 + compatible = "fsl,ls1088a-clockgen";
5700 + reg = <0 0x1300000 0 0xa0000>;
5701 + #clock-cells = <2>;
5702 + clocks = <&sysclk>;
5703 + };
5704 +
5705 + tmu: tmu@1f80000 {
5706 + compatible = "fsl,qoriq-tmu";
5707 + reg = <0x0 0x1f80000 0x0 0x10000>;
5708 + interrupts = <0 23 0x4>;
5709 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
5710 + fsl,tmu-calibration =
5711 + /* Calibration data group 1 */
5712 + <0x00000000 0x00000026
5713 + 0x00000001 0x0000002d
5714 + 0x00000002 0x00000032
5715 + 0x00000003 0x00000039
5716 + 0x00000004 0x0000003f
5717 + 0x00000005 0x00000046
5718 + 0x00000006 0x0000004d
5719 + 0x00000007 0x00000054
5720 + 0x00000008 0x0000005a
5721 + 0x00000009 0x00000061
5722 + 0x0000000a 0x0000006a
5723 + 0x0000000b 0x00000071
5724 + /* Calibration data group 2 */
5725 + 0x00010000 0x00000025
5726 + 0x00010001 0x0000002c
5727 + 0x00010002 0x00000035
5728 + 0x00010003 0x0000003d
5729 + 0x00010004 0x00000045
5730 + 0x00010005 0x0000004e
5731 + 0x00010006 0x00000057
5732 + 0x00010007 0x00000061
5733 + 0x00010008 0x0000006b
5734 + 0x00010009 0x00000076
5735 + /* Calibration data group 3 */
5736 + 0x00020000 0x00000029
5737 + 0x00020001 0x00000033
5738 + 0x00020002 0x0000003d
5739 + 0x00020003 0x00000049
5740 + 0x00020004 0x00000056
5741 + 0x00020005 0x00000061
5742 + 0x00020006 0x0000006d
5743 + /* Calibration data group 4 */
5744 + 0x00030000 0x00000021
5745 + 0x00030001 0x0000002a
5746 + 0x00030002 0x0000003c
5747 + 0x00030003 0x0000004e>;
5748 + little-endian;
5749 + #thermal-sensor-cells = <1>;
5750 + };
5751 +
5752 + thermal-zones {
5753 + cpu_thermal: cpu-thermal {
5754 + polling-delay-passive = <1000>;
5755 + polling-delay = <5000>;
5756 + thermal-sensors = <&tmu 0>;
5757 +
5758 + trips {
5759 + cpu_alert: cpu-alert {
5760 + temperature = <85000>;
5761 + hysteresis = <2000>;
5762 + type = "passive";
5763 + };
5764 +
5765 + cpu_crit: cpu-crit {
5766 + temperature = <95000>;
5767 + hysteresis = <2000>;
5768 + type = "critical";
5769 + };
5770 + };
5771 +
5772 + cooling-maps {
5773 + map0 {
5774 + trip = <&cpu_alert>;
5775 + cooling-device =
5776 + <&cpu0 THERMAL_NO_LIMIT
5777 + THERMAL_NO_LIMIT>;
5778 + };
5779 + map1 {
5780 + trip = <&cpu_alert>;
5781 + cooling-device =
5782 + <&cpu4 THERMAL_NO_LIMIT
5783 + THERMAL_NO_LIMIT>;
5784 + };
5785 + };
5786 + };
5787 + };
5788 +
5789 + duart0: serial@21c0500 {
5790 + compatible = "fsl,ns16550", "ns16550a";
5791 + reg = <0x0 0x21c0500 0x0 0x100>;
5792 + clocks = <&clockgen 4 3>;
5793 + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
5794 + status = "disabled";
5795 + };
5796 +
5797 + duart1: serial@21c0600 {
5798 + compatible = "fsl,ns16550", "ns16550a";
5799 + reg = <0x0 0x21c0600 0x0 0x100>;
5800 + clocks = <&clockgen 4 3>;
5801 + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
5802 + status = "disabled";
5803 + };
5804 +
5805 + cluster1_core0_watchdog: wdt@c000000 {
5806 + compatible = "arm,sp805-wdt", "arm,primecell";
5807 + reg = <0x0 0xc000000 0x0 0x1000>;
5808 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5809 + clock-names = "apb_pclk", "wdog_clk";
5810 + };
5811 +
5812 + cluster1_core1_watchdog: wdt@c010000 {
5813 + compatible = "arm,sp805-wdt", "arm,primecell";
5814 + reg = <0x0 0xc010000 0x0 0x1000>;
5815 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5816 + clock-names = "apb_pclk", "wdog_clk";
5817 + };
5818 +
5819 + cluster1_core2_watchdog: wdt@c020000 {
5820 + compatible = "arm,sp805-wdt", "arm,primecell";
5821 + reg = <0x0 0xc020000 0x0 0x1000>;
5822 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5823 + clock-names = "apb_pclk", "wdog_clk";
5824 + };
5825 +
5826 + cluster1_core3_watchdog: wdt@c030000 {
5827 + compatible = "arm,sp805-wdt", "arm,primecell";
5828 + reg = <0x0 0xc030000 0x0 0x1000>;
5829 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5830 + clock-names = "apb_pclk", "wdog_clk";
5831 + };
5832 +
5833 + cluster2_core0_watchdog: wdt@c100000 {
5834 + compatible = "arm,sp805-wdt", "arm,primecell";
5835 + reg = <0x0 0xc100000 0x0 0x1000>;
5836 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5837 + clock-names = "apb_pclk", "wdog_clk";
5838 + };
5839 +
5840 + cluster2_core1_watchdog: wdt@c110000 {
5841 + compatible = "arm,sp805-wdt", "arm,primecell";
5842 + reg = <0x0 0xc110000 0x0 0x1000>;
5843 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5844 + clock-names = "apb_pclk", "wdog_clk";
5845 + };
5846 +
5847 + cluster2_core2_watchdog: wdt@c120000 {
5848 + compatible = "arm,sp805-wdt", "arm,primecell";
5849 + reg = <0x0 0xc120000 0x0 0x1000>;
5850 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5851 + clock-names = "apb_pclk", "wdog_clk";
5852 + };
5853 +
5854 + cluster2_core3_watchdog: wdt@c130000 {
5855 + compatible = "arm,sp805-wdt", "arm,primecell";
5856 + reg = <0x0 0xc130000 0x0 0x1000>;
5857 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5858 + clock-names = "apb_pclk", "wdog_clk";
5859 + };
5860 +
5861 + gpio0: gpio@2300000 {
5862 + compatible = "fsl,qoriq-gpio";
5863 + reg = <0x0 0x2300000 0x0 0x10000>;
5864 + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
5865 + gpio-controller;
5866 + #gpio-cells = <2>;
5867 + interrupt-controller;
5868 + #interrupt-cells = <2>;
5869 + };
5870 +
5871 + gpio1: gpio@2310000 {
5872 + compatible = "fsl,qoriq-gpio";
5873 + reg = <0x0 0x2310000 0x0 0x10000>;
5874 + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
5875 + gpio-controller;
5876 + #gpio-cells = <2>;
5877 + interrupt-controller;
5878 + #interrupt-cells = <2>;
5879 + };
5880 +
5881 + gpio2: gpio@2320000 {
5882 + compatible = "fsl,qoriq-gpio";
5883 + reg = <0x0 0x2320000 0x0 0x10000>;
5884 + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
5885 + gpio-controller;
5886 + #gpio-cells = <2>;
5887 + interrupt-controller;
5888 + #interrupt-cells = <2>;
5889 + };
5890 +
5891 + gpio3: gpio@2330000 {
5892 + compatible = "fsl,qoriq-gpio";
5893 + reg = <0x0 0x2330000 0x0 0x10000>;
5894 + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
5895 + gpio-controller;
5896 + #gpio-cells = <2>;
5897 + interrupt-controller;
5898 + #interrupt-cells = <2>;
5899 + };
5900 +
5901 + /* TODO: WRIOP (CCSR?) */
5902 + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
5903 + * E-MDIO1: 0x1_6000
5904 + */
5905 + compatible = "fsl,fman-memac-mdio";
5906 + reg = <0x0 0x8B96000 0x0 0x1000>;
5907 + device_type = "mdio";
5908 + little-endian; /* force the driver in LE mode */
5909 +
5910 + /* Not necessary on the QDS, but needed on the RDB */
5911 + #address-cells = <1>;
5912 + #size-cells = <0>;
5913 + };
5914 +
5915 + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
5916 + * E-MDIO2: 0x1_7000
5917 + */
5918 + compatible = "fsl,fman-memac-mdio";
5919 + reg = <0x0 0x8B97000 0x0 0x1000>;
5920 + device_type = "mdio";
5921 + little-endian; /* force the driver in LE mode */
5922 +
5923 + #address-cells = <1>;
5924 + #size-cells = <0>;
5925 + };
5926 +
5927 + ifc: ifc@2240000 {
5928 + compatible = "fsl,ifc", "simple-bus";
5929 + reg = <0x0 0x2240000 0x0 0x20000>;
5930 + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
5931 + little-endian;
5932 + #address-cells = <2>;
5933 + #size-cells = <1>;
5934 +
5935 + };
5936 +
5937 + ftm0: ftm0@2800000 {
5938 + compatible = "fsl,ls1088a-ftm";
5939 + reg = <0x0 0x2800000 0x0 0x10000>,
5940 + <0x0 0x1e34050 0x0 0x4>;
5941 + interrupts = <0 44 4>;
5942 + reg-names = "ftm", "FlexTimer1";
5943 + };
5944 +
5945 + i2c0: i2c@2000000 {
5946 + compatible = "fsl,vf610-i2c";
5947 + #address-cells = <1>;
5948 + #size-cells = <0>;
5949 + reg = <0x0 0x2000000 0x0 0x10000>;
5950 + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
5951 + clocks = <&clockgen 4 7>;
5952 + status = "disabled";
5953 + };
5954 +
5955 + i2c1: i2c@2010000 {
5956 + compatible = "fsl,vf610-i2c";
5957 + #address-cells = <1>;
5958 + #size-cells = <0>;
5959 + reg = <0x0 0x2010000 0x0 0x10000>;
5960 + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
5961 + clocks = <&clockgen 4 7>;
5962 + status = "disabled";
5963 + };
5964 +
5965 + i2c2: i2c@2020000 {
5966 + compatible = "fsl,vf610-i2c";
5967 + #address-cells = <1>;
5968 + #size-cells = <0>;
5969 + reg = <0x0 0x2020000 0x0 0x10000>;
5970 + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
5971 + clocks = <&clockgen 4 7>;
5972 + status = "disabled";
5973 + };
5974 +
5975 + i2c3: i2c@2030000 {
5976 + compatible = "fsl,vf610-i2c";
5977 + #address-cells = <1>;
5978 + #size-cells = <0>;
5979 + reg = <0x0 0x2030000 0x0 0x10000>;
5980 + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
5981 + clocks = <&clockgen 4 7>;
5982 + status = "disabled";
5983 + };
5984 +
5985 + qspi: quadspi@20c0000 {
5986 + compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
5987 + #address-cells = <1>;
5988 + #size-cells = <0>;
5989 + reg = <0x0 0x20c0000 0x0 0x10000>,
5990 + <0x0 0x20000000 0x0 0x10000000>;
5991 + reg-names = "QuadSPI", "QuadSPI-memory";
5992 + interrupts = <0 25 0x4>; /* Level high type */
5993 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5994 + clock-names = "qspi_en", "qspi";
5995 + fsl,qspi-has-second-chip;
5996 + };
5997 +
5998 + esdhc: esdhc@2140000 {
5999 + compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
6000 + reg = <0x0 0x2140000 0x0 0x10000>;
6001 + interrupts = <0 28 0x4>; /* Level high type */
6002 + clock-frequency = <0>;
6003 + voltage-ranges = <1800 1800 3300 3300>;
6004 + sdhci,auto-cmd12;
6005 + little-endian;
6006 + bus-width = <4>;
6007 + status = "disabled";
6008 + };
6009 +
6010 + usb0: usb3@3100000 {
6011 + compatible = "snps,dwc3";
6012 + reg = <0x0 0x3100000 0x0 0x10000>;
6013 + interrupts = <0 80 0x4>; /* Level high type */
6014 + dr_mode = "host";
6015 + configure-gfladj;
6016 + snps,dis_rxdet_inp3_quirk;
6017 + };
6018 +
6019 + usb1: usb3@3110000 {
6020 + compatible = "snps,dwc3";
6021 + reg = <0x0 0x3110000 0x0 0x10000>;
6022 + interrupts = <0 81 0x4>; /* Level high type */
6023 + dr_mode = "host";
6024 + configure-gfladj;
6025 + snps,dis_rxdet_inp3_quirk;
6026 + };
6027 +
6028 + sata: sata@3200000 {
6029 + compatible = "fsl,ls1088a-ahci";
6030 + reg = <0x0 0x3200000 0x0 0x10000>,
6031 + <0x7 0x100520 0x0 0x4>;
6032 + reg-names = "ahci", "sata-ecc";
6033 + interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
6034 + clocks = <&clockgen 4 3>;
6035 + dma-coherent;
6036 + status = "disabled";
6037 + };
6038 +
6039 + pcie@3400000 {
6040 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
6041 + "snps,dw-pcie";
6042 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
6043 + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
6044 + reg-names = "regs", "config";
6045 + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
6046 + interrupt-names = "aer";
6047 + #address-cells = <3>;
6048 + #size-cells = <2>;
6049 + device_type = "pci";
6050 + dma-coherent;
6051 + num-lanes = <4>;
6052 + bus-range = <0x0 0xff>;
6053 + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
6054 + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
6055 + msi-parent = <&its>;
6056 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
6057 + #interrupt-cells = <1>;
6058 + interrupt-map-mask = <0 0 0 7>;
6059 + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
6060 + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
6061 + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
6062 + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
6063 + };
6064 +
6065 + pcie@3500000 {
6066 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
6067 + "snps,dw-pcie";
6068 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
6069 + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
6070 + reg-names = "regs", "config";
6071 + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
6072 + interrupt-names = "aer";
6073 + #address-cells = <3>;
6074 + #size-cells = <2>;
6075 + device_type = "pci";
6076 + dma-coherent;
6077 + num-lanes = <4>;
6078 + bus-range = <0x0 0xff>;
6079 + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
6080 + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
6081 + msi-parent = <&its>;
6082 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
6083 + #interrupt-cells = <1>;
6084 + interrupt-map-mask = <0 0 0 7>;
6085 + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
6086 + <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
6087 + <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
6088 + <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
6089 + };
6090 +
6091 + pcie@3600000 {
6092 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
6093 + "snps,dw-pcie";
6094 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
6095 + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
6096 + reg-names = "regs", "config";
6097 + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
6098 + interrupt-names = "aer";
6099 + #address-cells = <3>;
6100 + #size-cells = <2>;
6101 + device_type = "pci";
6102 + dma-coherent;
6103 + num-lanes = <8>;
6104 + bus-range = <0x0 0xff>;
6105 + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
6106 + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
6107 + msi-parent = <&its>;
6108 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
6109 + #interrupt-cells = <1>;
6110 + interrupt-map-mask = <0 0 0 7>;
6111 + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
6112 + <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
6113 + <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
6114 + <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
6115 + };
6116 +
6117 + smmu: iommu@5000000 {
6118 + compatible = "arm,mmu-500";
6119 + reg = <0 0x5000000 0 0x800000>;
6120 + #global-interrupts = <12>;
6121 + #iommu-cells = <1>;
6122 + stream-match-mask = <0x7C00>;
6123 + interrupts = <0 13 4>, /* global secure fault */
6124 + <0 14 4>, /* combined secure interrupt */
6125 + <0 15 4>, /* global non-secure fault */
6126 + <0 16 4>, /* combined non-secure interrupt */
6127 + /* performance counter interrupts 0-7 */
6128 + <0 211 4>,
6129 + <0 212 4>,
6130 + <0 213 4>,
6131 + <0 214 4>,
6132 + <0 215 4>,
6133 + <0 216 4>,
6134 + <0 217 4>,
6135 + <0 218 4>,
6136 + /* per context interrupt, 64 interrupts */
6137 + <0 146 4>,
6138 + <0 147 4>,
6139 + <0 148 4>,
6140 + <0 149 4>,
6141 + <0 150 4>,
6142 + <0 151 4>,
6143 + <0 152 4>,
6144 + <0 153 4>,
6145 + <0 154 4>,
6146 + <0 155 4>,
6147 + <0 156 4>,
6148 + <0 157 4>,
6149 + <0 158 4>,
6150 + <0 159 4>,
6151 + <0 160 4>,
6152 + <0 161 4>,
6153 + <0 162 4>,
6154 + <0 163 4>,
6155 + <0 164 4>,
6156 + <0 165 4>,
6157 + <0 166 4>,
6158 + <0 167 4>,
6159 + <0 168 4>,
6160 + <0 169 4>,
6161 + <0 170 4>,
6162 + <0 171 4>,
6163 + <0 172 4>,
6164 + <0 173 4>,
6165 + <0 174 4>,
6166 + <0 175 4>,
6167 + <0 176 4>,
6168 + <0 177 4>,
6169 + <0 178 4>,
6170 + <0 179 4>,
6171 + <0 180 4>,
6172 + <0 181 4>,
6173 + <0 182 4>,
6174 + <0 183 4>,
6175 + <0 184 4>,
6176 + <0 185 4>,
6177 + <0 186 4>,
6178 + <0 187 4>,
6179 + <0 188 4>,
6180 + <0 189 4>,
6181 + <0 190 4>,
6182 + <0 191 4>,
6183 + <0 192 4>,
6184 + <0 193 4>,
6185 + <0 194 4>,
6186 + <0 195 4>,
6187 + <0 196 4>,
6188 + <0 197 4>,
6189 + <0 198 4>,
6190 + <0 199 4>,
6191 + <0 200 4>,
6192 + <0 201 4>,
6193 + <0 202 4>,
6194 + <0 203 4>,
6195 + <0 204 4>,
6196 + <0 205 4>,
6197 + <0 206 4>,
6198 + <0 207 4>,
6199 + <0 208 4>,
6200 + <0 209 4>;
6201 + };
6202 +
6203 + crypto: crypto@8000000 {
6204 + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
6205 + fsl,sec-era = <8>;
6206 + #address-cells = <1>;
6207 + #size-cells = <1>;
6208 + ranges = <0x0 0x00 0x8000000 0x100000>;
6209 + reg = <0x00 0x8000000 0x0 0x100000>;
6210 + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
6211 + dma-coherent;
6212 +
6213 + sec_jr0: jr@10000 {
6214 + compatible = "fsl,sec-v5.0-job-ring",
6215 + "fsl,sec-v4.0-job-ring";
6216 + reg = <0x10000 0x10000>;
6217 + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
6218 + };
6219 +
6220 + sec_jr1: jr@20000 {
6221 + compatible = "fsl,sec-v5.0-job-ring",
6222 + "fsl,sec-v4.0-job-ring";
6223 + reg = <0x20000 0x10000>;
6224 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
6225 + };
6226 +
6227 + sec_jr2: jr@30000 {
6228 + compatible = "fsl,sec-v5.0-job-ring",
6229 + "fsl,sec-v4.0-job-ring";
6230 + reg = <0x30000 0x10000>;
6231 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
6232 + };
6233 +
6234 + sec_jr3: jr@40000 {
6235 + compatible = "fsl,sec-v5.0-job-ring",
6236 + "fsl,sec-v4.0-job-ring";
6237 + reg = <0x40000 0x10000>;
6238 + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
6239 + };
6240 + };
6241 + };
6242 +
6243 + firmware {
6244 + optee {
6245 + compatible = "linaro,optee-tz";
6246 + method = "smc";
6247 + };
6248 + };
6249 +
6250 +};
6251 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
6252 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
6253 @@ -1,8 +1,10 @@
6254 /*
6255 * Device Tree file for Freescale LS2080a QDS Board.
6256 *
6257 - * Copyright (C) 2015, Freescale Semiconductor
6258 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
6259 + * Copyright 2017 NXP
6260 *
6261 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6262 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6263 *
6264 * This file is dual-licensed: you can use it either under the terms
6265 @@ -46,169 +48,76 @@
6266
6267 /dts-v1/;
6268
6269 -/include/ "fsl-ls2080a.dtsi"
6270 +#include "fsl-ls2080a.dtsi"
6271 +#include "fsl-ls208xa-qds.dtsi"
6272
6273 / {
6274 model = "Freescale Layerscape 2080a QDS Board";
6275 compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
6276
6277 - aliases {
6278 - serial0 = &serial0;
6279 - serial1 = &serial1;
6280 - };
6281 -
6282 chosen {
6283 stdout-path = "serial0:115200n8";
6284 };
6285 };
6286
6287 -&esdhc {
6288 - status = "okay";
6289 -};
6290 -
6291 &ifc {
6292 - status = "okay";
6293 - #address-cells = <2>;
6294 - #size-cells = <1>;
6295 - ranges = <0x0 0x0 0x5 0x80000000 0x08000000
6296 - 0x2 0x0 0x5 0x30000000 0x00010000
6297 - 0x3 0x0 0x5 0x20000000 0x00010000>;
6298 -
6299 - nor@0,0 {
6300 + boardctrl: board-control@3,0 {
6301 #address-cells = <1>;
6302 #size-cells = <1>;
6303 - compatible = "cfi-flash";
6304 - reg = <0x0 0x0 0x8000000>;
6305 - bank-width = <2>;
6306 - device-width = <1>;
6307 - };
6308 + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
6309 + reg = <3 0 0x300>; /* TODO check address */
6310 + ranges = <0 3 0 0x300>;
6311
6312 - nand@2,0 {
6313 - compatible = "fsl,ifc-nand";
6314 - reg = <0x2 0x0 0x10000>;
6315 - };
6316 + mdio_mux_emi1 {
6317 + compatible = "mdio-mux-mmioreg", "mdio-mux";
6318 + mdio-parent-bus = <&emdio1>;
6319 + reg = <0x54 1>; /* BRDCFG4 */
6320 + mux-mask = <0xe0>; /* EMI1_MDIO */
6321
6322 - cpld@3,0 {
6323 - reg = <0x3 0x0 0x10000>;
6324 - compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
6325 - };
6326 -};
6327 -
6328 -&i2c0 {
6329 - status = "okay";
6330 - pca9547@77 {
6331 - compatible = "nxp,pca9547";
6332 - reg = <0x77>;
6333 - #address-cells = <1>;
6334 - #size-cells = <0>;
6335 - i2c@0 {
6336 - #address-cells = <1>;
6337 + #address-cells=<1>;
6338 #size-cells = <0>;
6339 - reg = <0x00>;
6340 - rtc@68 {
6341 - compatible = "dallas,ds3232";
6342 - reg = <0x68>;
6343 - };
6344 - };
6345
6346 - i2c@2 {
6347 - #address-cells = <1>;
6348 - #size-cells = <0>;
6349 - reg = <0x02>;
6350 -
6351 - ina220@40 {
6352 - compatible = "ti,ina220";
6353 - reg = <0x40>;
6354 - shunt-resistor = <500>;
6355 - };
6356 -
6357 - ina220@41 {
6358 - compatible = "ti,ina220";
6359 - reg = <0x41>;
6360 - shunt-resistor = <1000>;
6361 - };
6362 - };
6363 -
6364 - i2c@3 {
6365 - #address-cells = <1>;
6366 - #size-cells = <0>;
6367 - reg = <0x3>;
6368 -
6369 - adt7481@4c {
6370 - compatible = "adi,adt7461";
6371 - reg = <0x4c>;
6372 + /* Child MDIO buses, one for each riser card:
6373 + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
6374 + * VSC8234 PHYs on the riser cards.
6375 + */
6376 +
6377 + mdio_mux3: mdio@60 {
6378 + reg = <0x60>;
6379 + #address-cells = <1>;
6380 + #size-cells = <0>;
6381 +
6382 + mdio0_phy12: mdio_phy0@1c {
6383 + reg = <0x1c>;
6384 + phy-connection-type = "sgmii";
6385 + };
6386 + mdio0_phy13: mdio_phy1@1d {
6387 + reg = <0x1d>;
6388 + phy-connection-type = "sgmii";
6389 + };
6390 + mdio0_phy14: mdio_phy2@1e {
6391 + reg = <0x1e>;
6392 + phy-connection-type = "sgmii";
6393 + };
6394 + mdio0_phy15: mdio_phy3@1f {
6395 + reg = <0x1f>;
6396 + phy-connection-type = "sgmii";
6397 + };
6398 };
6399 };
6400 };
6401 };
6402
6403 -&i2c1 {
6404 - status = "disabled";
6405 -};
6406 -
6407 -&i2c2 {
6408 - status = "disabled";
6409 -};
6410 -
6411 -&i2c3 {
6412 - status = "disabled";
6413 -};
6414 -
6415 -&dspi {
6416 - status = "okay";
6417 - dflash0: n25q128a {
6418 - #address-cells = <1>;
6419 - #size-cells = <1>;
6420 - compatible = "st,m25p80";
6421 - spi-max-frequency = <3000000>;
6422 - reg = <0>;
6423 - };
6424 - dflash1: sst25wf040b {
6425 - #address-cells = <1>;
6426 - #size-cells = <1>;
6427 - compatible = "st,m25p80";
6428 - spi-max-frequency = <3000000>;
6429 - reg = <1>;
6430 - };
6431 - dflash2: en25s64 {
6432 - #address-cells = <1>;
6433 - #size-cells = <1>;
6434 - compatible = "st,m25p80";
6435 - spi-max-frequency = <3000000>;
6436 - reg = <2>;
6437 - };
6438 -};
6439 -
6440 -&qspi {
6441 - status = "okay";
6442 - flash0: s25fl256s1@0 {
6443 - #address-cells = <1>;
6444 - #size-cells = <1>;
6445 - compatible = "st,m25p80";
6446 - spi-max-frequency = <20000000>;
6447 - reg = <0>;
6448 - };
6449 - flash2: s25fl256s1@2 {
6450 - #address-cells = <1>;
6451 - #size-cells = <1>;
6452 - compatible = "st,m25p80";
6453 - spi-max-frequency = <20000000>;
6454 - reg = <0>;
6455 - };
6456 -};
6457 -
6458 -&sata0 {
6459 - status = "okay";
6460 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
6461 +&dpmac9 {
6462 + phy-handle = <&mdio0_phy12>;
6463 };
6464 -
6465 -&sata1 {
6466 - status = "okay";
6467 +&dpmac10 {
6468 + phy-handle = <&mdio0_phy13>;
6469 };
6470 -
6471 -&usb0 {
6472 - status = "okay";
6473 +&dpmac11 {
6474 + phy-handle = <&mdio0_phy14>;
6475 };
6476 -
6477 -&usb1 {
6478 - status = "okay";
6479 +&dpmac12 {
6480 + phy-handle = <&mdio0_phy15>;
6481 };
6482 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
6483 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
6484 @@ -1,8 +1,10 @@
6485 /*
6486 * Device Tree file for Freescale LS2080a RDB Board.
6487 *
6488 - * Copyright (C) 2015, Freescale Semiconductor
6489 + * Copyright 2016 Freescale Semiconductor, Inc.
6490 + * Copyright 2017 NXP
6491 *
6492 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6493 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6494 *
6495 * This file is dual-licensed: you can use it either under the terms
6496 @@ -46,125 +48,94 @@
6497
6498 /dts-v1/;
6499
6500 -/include/ "fsl-ls2080a.dtsi"
6501 +#include "fsl-ls2080a.dtsi"
6502 +#include "fsl-ls208xa-rdb.dtsi"
6503
6504 / {
6505 model = "Freescale Layerscape 2080a RDB Board";
6506 compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
6507
6508 - aliases {
6509 - serial0 = &serial0;
6510 - serial1 = &serial1;
6511 - };
6512 -
6513 chosen {
6514 stdout-path = "serial1:115200n8";
6515 };
6516 };
6517
6518 -&esdhc {
6519 - status = "okay";
6520 -};
6521 -
6522 -&ifc {
6523 - status = "okay";
6524 - #address-cells = <2>;
6525 - #size-cells = <1>;
6526 - ranges = <0x0 0x0 0x5 0x80000000 0x08000000
6527 - 0x2 0x0 0x5 0x30000000 0x00010000
6528 - 0x3 0x0 0x5 0x20000000 0x00010000>;
6529 -
6530 - nor@0,0 {
6531 - #address-cells = <1>;
6532 - #size-cells = <1>;
6533 - compatible = "cfi-flash";
6534 - reg = <0x0 0x0 0x8000000>;
6535 - bank-width = <2>;
6536 - device-width = <1>;
6537 - };
6538 -
6539 - nand@2,0 {
6540 - compatible = "fsl,ifc-nand";
6541 - reg = <0x2 0x0 0x10000>;
6542 - };
6543 -
6544 - cpld@3,0 {
6545 - reg = <0x3 0x0 0x10000>;
6546 - compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
6547 - };
6548 -
6549 -};
6550 -
6551 -&i2c0 {
6552 - status = "okay";
6553 - pca9547@75 {
6554 - compatible = "nxp,pca9547";
6555 - reg = <0x75>;
6556 - #address-cells = <1>;
6557 - #size-cells = <0>;
6558 - status = "disabled";
6559 - i2c@1 {
6560 - #address-cells = <1>;
6561 - #size-cells = <0>;
6562 - reg = <0x01>;
6563 - rtc@68 {
6564 - compatible = "dallas,ds3232";
6565 - reg = <0x68>;
6566 - };
6567 - };
6568 -
6569 - i2c@3 {
6570 - #address-cells = <1>;
6571 - #size-cells = <0>;
6572 - reg = <0x3>;
6573 -
6574 - adt7481@4c {
6575 - compatible = "adi,adt7461";
6576 - reg = <0x4c>;
6577 - };
6578 - };
6579 - };
6580 -};
6581 -
6582 -&i2c1 {
6583 - status = "disabled";
6584 -};
6585 -
6586 -&i2c2 {
6587 - status = "disabled";
6588 -};
6589 -
6590 -&i2c3 {
6591 +&emdio1 {
6592 status = "disabled";
6593 + /* CS4340 PHYs */
6594 + mdio1_phy1: emdio1_phy@1 {
6595 + reg = <0x10>;
6596 + phy-connection-type = "xfi";
6597 + };
6598 + mdio1_phy2: emdio1_phy@2 {
6599 + reg = <0x11>;
6600 + phy-connection-type = "xfi";
6601 + };
6602 + mdio1_phy3: emdio1_phy@3 {
6603 + reg = <0x12>;
6604 + phy-connection-type = "xfi";
6605 + };
6606 + mdio1_phy4: emdio1_phy@4 {
6607 + reg = <0x13>;
6608 + phy-connection-type = "xfi";
6609 + };
6610 };
6611
6612 -&dspi {
6613 - status = "okay";
6614 - dflash0: n25q512a {
6615 - #address-cells = <1>;
6616 - #size-cells = <1>;
6617 - compatible = "st,m25p80";
6618 - spi-max-frequency = <3000000>;
6619 - reg = <0>;
6620 +&emdio2 {
6621 + /* AQR405 PHYs */
6622 + mdio2_phy1: emdio2_phy@1 {
6623 + compatible = "ethernet-phy-ieee802.3-c45";
6624 + interrupts = <0 1 0x4>; /* Level high type */
6625 + reg = <0x0>;
6626 + phy-connection-type = "xfi";
6627 + };
6628 + mdio2_phy2: emdio2_phy@2 {
6629 + compatible = "ethernet-phy-ieee802.3-c45";
6630 + interrupts = <0 2 0x4>; /* Level high type */
6631 + reg = <0x1>;
6632 + phy-connection-type = "xfi";
6633 + };
6634 + mdio2_phy3: emdio2_phy@3 {
6635 + compatible = "ethernet-phy-ieee802.3-c45";
6636 + interrupts = <0 4 0x4>; /* Level high type */
6637 + reg = <0x2>;
6638 + phy-connection-type = "xfi";
6639 + };
6640 + mdio2_phy4: emdio2_phy@4 {
6641 + compatible = "ethernet-phy-ieee802.3-c45";
6642 + interrupts = <0 5 0x4>; /* Level high type */
6643 + reg = <0x3>;
6644 + phy-connection-type = "xfi";
6645 };
6646 };
6647
6648 -&qspi {
6649 - status = "disabled";
6650 -};
6651 +/* Update DPMAC connections to external PHYs, under the assumption of
6652 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
6653 + */
6654 +/* Leave Cortina nodes commented out until driver is integrated
6655 + *&dpmac1 {
6656 + * phy-handle = <&mdio1_phy1>;
6657 + *};
6658 + *&dpmac2 {
6659 + * phy-handle = <&mdio1_phy2>;
6660 + *};
6661 + *&dpmac3 {
6662 + * phy-handle = <&mdio1_phy3>;
6663 + *};
6664 + *&dpmac4 {
6665 + * phy-handle = <&mdio1_phy4>;
6666 + *};
6667 + */
6668
6669 -&sata0 {
6670 - status = "okay";
6671 +&dpmac5 {
6672 + phy-handle = <&mdio2_phy1>;
6673 };
6674 -
6675 -&sata1 {
6676 - status = "okay";
6677 +&dpmac6 {
6678 + phy-handle = <&mdio2_phy2>;
6679 };
6680 -
6681 -&usb0 {
6682 - status = "okay";
6683 +&dpmac7 {
6684 + phy-handle = <&mdio2_phy3>;
6685 };
6686 -
6687 -&usb1 {
6688 - status = "okay";
6689 +&dpmac8 {
6690 + phy-handle = <&mdio2_phy4>;
6691 };
6692 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
6693 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
6694 @@ -1,7 +1,7 @@
6695 /*
6696 * Device Tree file for Freescale LS2080a software Simulator model
6697 *
6698 - * Copyright (C) 2014-2015, Freescale Semiconductor
6699 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
6700 *
6701 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6702 *
6703 @@ -46,17 +46,12 @@
6704
6705 /dts-v1/;
6706
6707 -/include/ "fsl-ls2080a.dtsi"
6708 +#include "fsl-ls2080a.dtsi"
6709
6710 / {
6711 model = "Freescale Layerscape 2080a software Simulator model";
6712 compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
6713
6714 - aliases {
6715 - serial0 = &serial0;
6716 - serial1 = &serial1;
6717 - };
6718 -
6719 ethernet@2210000 {
6720 compatible = "smsc,lan91c111";
6721 reg = <0x0 0x2210000 0x0 0x100>;
6722 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
6723 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
6724 @@ -1,8 +1,9 @@
6725 /*
6726 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6727 *
6728 - * Copyright (C) 2014-2015, Freescale Semiconductor
6729 + * Copyright 2014-2016 Freescale Semiconductor, Inc.
6730 *
6731 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6732 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6733 *
6734 * This file is dual-licensed: you can use it either under the terms
6735 @@ -44,696 +45,132 @@
6736 * OTHER DEALINGS IN THE SOFTWARE.
6737 */
6738
6739 -/ {
6740 - compatible = "fsl,ls2080a";
6741 - interrupt-parent = <&gic>;
6742 - #address-cells = <2>;
6743 - #size-cells = <2>;
6744 -
6745 - cpus {
6746 - #address-cells = <1>;
6747 - #size-cells = <0>;
6748 -
6749 - /*
6750 - * We expect the enable-method for cpu's to be "psci", but this
6751 - * is dependent on the SoC FW, which will fill this in.
6752 - *
6753 - * Currently supported enable-method is psci v0.2
6754 - */
6755 -
6756 - /* We have 4 clusters having 2 Cortex-A57 cores each */
6757 - cpu@0 {
6758 - device_type = "cpu";
6759 - compatible = "arm,cortex-a57";
6760 - reg = <0x0>;
6761 - clocks = <&clockgen 1 0>;
6762 - next-level-cache = <&cluster0_l2>;
6763 - };
6764 -
6765 - cpu@1 {
6766 - device_type = "cpu";
6767 - compatible = "arm,cortex-a57";
6768 - reg = <0x1>;
6769 - clocks = <&clockgen 1 0>;
6770 - next-level-cache = <&cluster0_l2>;
6771 - };
6772 -
6773 - cpu@100 {
6774 - device_type = "cpu";
6775 - compatible = "arm,cortex-a57";
6776 - reg = <0x100>;
6777 - clocks = <&clockgen 1 1>;
6778 - next-level-cache = <&cluster1_l2>;
6779 - };
6780 -
6781 - cpu@101 {
6782 - device_type = "cpu";
6783 - compatible = "arm,cortex-a57";
6784 - reg = <0x101>;
6785 - clocks = <&clockgen 1 1>;
6786 - next-level-cache = <&cluster1_l2>;
6787 - };
6788 -
6789 - cpu@200 {
6790 - device_type = "cpu";
6791 - compatible = "arm,cortex-a57";
6792 - reg = <0x200>;
6793 - clocks = <&clockgen 1 2>;
6794 - next-level-cache = <&cluster2_l2>;
6795 - };
6796 -
6797 - cpu@201 {
6798 - device_type = "cpu";
6799 - compatible = "arm,cortex-a57";
6800 - reg = <0x201>;
6801 - clocks = <&clockgen 1 2>;
6802 - next-level-cache = <&cluster2_l2>;
6803 - };
6804 -
6805 - cpu@300 {
6806 - device_type = "cpu";
6807 - compatible = "arm,cortex-a57";
6808 - reg = <0x300>;
6809 - clocks = <&clockgen 1 3>;
6810 - next-level-cache = <&cluster3_l2>;
6811 - };
6812 -
6813 - cpu@301 {
6814 - device_type = "cpu";
6815 - compatible = "arm,cortex-a57";
6816 - reg = <0x301>;
6817 - clocks = <&clockgen 1 3>;
6818 - next-level-cache = <&cluster3_l2>;
6819 - };
6820 -
6821 - cluster0_l2: l2-cache0 {
6822 - compatible = "cache";
6823 - };
6824 -
6825 - cluster1_l2: l2-cache1 {
6826 - compatible = "cache";
6827 - };
6828 -
6829 - cluster2_l2: l2-cache2 {
6830 - compatible = "cache";
6831 - };
6832 -
6833 - cluster3_l2: l2-cache3 {
6834 - compatible = "cache";
6835 - };
6836 - };
6837 -
6838 - memory@80000000 {
6839 - device_type = "memory";
6840 - reg = <0x00000000 0x80000000 0 0x80000000>;
6841 - /* DRAM space - 1, size : 2 GB DRAM */
6842 - };
6843 -
6844 - sysclk: sysclk {
6845 - compatible = "fixed-clock";
6846 - #clock-cells = <0>;
6847 - clock-frequency = <100000000>;
6848 - clock-output-names = "sysclk";
6849 - };
6850 -
6851 - gic: interrupt-controller@6000000 {
6852 - compatible = "arm,gic-v3";
6853 - reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
6854 - <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
6855 - <0x0 0x0c0c0000 0 0x2000>, /* GICC */
6856 - <0x0 0x0c0d0000 0 0x1000>, /* GICH */
6857 - <0x0 0x0c0e0000 0 0x20000>; /* GICV */
6858 - #interrupt-cells = <3>;
6859 - #address-cells = <2>;
6860 - #size-cells = <2>;
6861 - ranges;
6862 - interrupt-controller;
6863 - interrupts = <1 9 0x4>;
6864 -
6865 - its: gic-its@6020000 {
6866 - compatible = "arm,gic-v3-its";
6867 - msi-controller;
6868 - reg = <0x0 0x6020000 0 0x20000>;
6869 - };
6870 - };
6871 -
6872 - rstcr: syscon@1e60000 {
6873 - compatible = "fsl,ls2080a-rstcr", "syscon";
6874 - reg = <0x0 0x1e60000 0x0 0x4>;
6875 - };
6876 -
6877 - reboot {
6878 - compatible ="syscon-reboot";
6879 - regmap = <&rstcr>;
6880 - offset = <0x0>;
6881 - mask = <0x2>;
6882 - };
6883 -
6884 - timer {
6885 - compatible = "arm,armv8-timer";
6886 - interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
6887 - <1 14 4>, /* Physical Non-Secure PPI, active-low */
6888 - <1 11 4>, /* Virtual PPI, active-low */
6889 - <1 10 4>; /* Hypervisor PPI, active-low */
6890 - fsl,erratum-a008585;
6891 - };
6892 -
6893 - pmu {
6894 - compatible = "arm,armv8-pmuv3";
6895 - interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
6896 - };
6897 -
6898 - soc {
6899 - compatible = "simple-bus";
6900 - #address-cells = <2>;
6901 - #size-cells = <2>;
6902 - ranges;
6903 -
6904 - clockgen: clocking@1300000 {
6905 - compatible = "fsl,ls2080a-clockgen";
6906 - reg = <0 0x1300000 0 0xa0000>;
6907 - #clock-cells = <2>;
6908 - clocks = <&sysclk>;
6909 - };
6910 -
6911 - serial0: serial@21c0500 {
6912 - compatible = "fsl,ns16550", "ns16550a";
6913 - reg = <0x0 0x21c0500 0x0 0x100>;
6914 - clocks = <&clockgen 4 3>;
6915 - interrupts = <0 32 0x4>; /* Level high type */
6916 - };
6917 -
6918 - serial1: serial@21c0600 {
6919 - compatible = "fsl,ns16550", "ns16550a";
6920 - reg = <0x0 0x21c0600 0x0 0x100>;
6921 - clocks = <&clockgen 4 3>;
6922 - interrupts = <0 32 0x4>; /* Level high type */
6923 - };
6924 -
6925 - cluster1_core0_watchdog: wdt@c000000 {
6926 - compatible = "arm,sp805-wdt", "arm,primecell";
6927 - reg = <0x0 0xc000000 0x0 0x1000>;
6928 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6929 - clock-names = "apb_pclk", "wdog_clk";
6930 - };
6931 -
6932 - cluster1_core1_watchdog: wdt@c010000 {
6933 - compatible = "arm,sp805-wdt", "arm,primecell";
6934 - reg = <0x0 0xc010000 0x0 0x1000>;
6935 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6936 - clock-names = "apb_pclk", "wdog_clk";
6937 - };
6938 -
6939 - cluster2_core0_watchdog: wdt@c100000 {
6940 - compatible = "arm,sp805-wdt", "arm,primecell";
6941 - reg = <0x0 0xc100000 0x0 0x1000>;
6942 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6943 - clock-names = "apb_pclk", "wdog_clk";
6944 - };
6945 -
6946 - cluster2_core1_watchdog: wdt@c110000 {
6947 - compatible = "arm,sp805-wdt", "arm,primecell";
6948 - reg = <0x0 0xc110000 0x0 0x1000>;
6949 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6950 - clock-names = "apb_pclk", "wdog_clk";
6951 - };
6952 -
6953 - cluster3_core0_watchdog: wdt@c200000 {
6954 - compatible = "arm,sp805-wdt", "arm,primecell";
6955 - reg = <0x0 0xc200000 0x0 0x1000>;
6956 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6957 - clock-names = "apb_pclk", "wdog_clk";
6958 - };
6959 -
6960 - cluster3_core1_watchdog: wdt@c210000 {
6961 - compatible = "arm,sp805-wdt", "arm,primecell";
6962 - reg = <0x0 0xc210000 0x0 0x1000>;
6963 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6964 - clock-names = "apb_pclk", "wdog_clk";
6965 - };
6966 -
6967 - cluster4_core0_watchdog: wdt@c300000 {
6968 - compatible = "arm,sp805-wdt", "arm,primecell";
6969 - reg = <0x0 0xc300000 0x0 0x1000>;
6970 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6971 - clock-names = "apb_pclk", "wdog_clk";
6972 - };
6973 -
6974 - cluster4_core1_watchdog: wdt@c310000 {
6975 - compatible = "arm,sp805-wdt", "arm,primecell";
6976 - reg = <0x0 0xc310000 0x0 0x1000>;
6977 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6978 - clock-names = "apb_pclk", "wdog_clk";
6979 - };
6980 -
6981 - fsl_mc: fsl-mc@80c000000 {
6982 - compatible = "fsl,qoriq-mc";
6983 - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
6984 - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
6985 - msi-parent = <&its>;
6986 - #address-cells = <3>;
6987 - #size-cells = <1>;
6988 -
6989 - /*
6990 - * Region type 0x0 - MC portals
6991 - * Region type 0x1 - QBMAN portals
6992 - */
6993 - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
6994 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
6995 -
6996 - /*
6997 - * Define the maximum number of MACs present on the SoC.
6998 - */
6999 - dpmacs {
7000 - #address-cells = <1>;
7001 - #size-cells = <0>;
7002 -
7003 - dpmac1: dpmac@1 {
7004 - compatible = "fsl,qoriq-mc-dpmac";
7005 - reg = <0x1>;
7006 - };
7007 -
7008 - dpmac2: dpmac@2 {
7009 - compatible = "fsl,qoriq-mc-dpmac";
7010 - reg = <0x2>;
7011 - };
7012 -
7013 - dpmac3: dpmac@3 {
7014 - compatible = "fsl,qoriq-mc-dpmac";
7015 - reg = <0x3>;
7016 - };
7017 -
7018 - dpmac4: dpmac@4 {
7019 - compatible = "fsl,qoriq-mc-dpmac";
7020 - reg = <0x4>;
7021 - };
7022 -
7023 - dpmac5: dpmac@5 {
7024 - compatible = "fsl,qoriq-mc-dpmac";
7025 - reg = <0x5>;
7026 - };
7027 -
7028 - dpmac6: dpmac@6 {
7029 - compatible = "fsl,qoriq-mc-dpmac";
7030 - reg = <0x6>;
7031 - };
7032 -
7033 - dpmac7: dpmac@7 {
7034 - compatible = "fsl,qoriq-mc-dpmac";
7035 - reg = <0x7>;
7036 - };
7037 -
7038 - dpmac8: dpmac@8 {
7039 - compatible = "fsl,qoriq-mc-dpmac";
7040 - reg = <0x8>;
7041 - };
7042 -
7043 - dpmac9: dpmac@9 {
7044 - compatible = "fsl,qoriq-mc-dpmac";
7045 - reg = <0x9>;
7046 - };
7047 -
7048 - dpmac10: dpmac@a {
7049 - compatible = "fsl,qoriq-mc-dpmac";
7050 - reg = <0xa>;
7051 - };
7052 -
7053 - dpmac11: dpmac@b {
7054 - compatible = "fsl,qoriq-mc-dpmac";
7055 - reg = <0xb>;
7056 - };
7057 -
7058 - dpmac12: dpmac@c {
7059 - compatible = "fsl,qoriq-mc-dpmac";
7060 - reg = <0xc>;
7061 - };
7062 -
7063 - dpmac13: dpmac@d {
7064 - compatible = "fsl,qoriq-mc-dpmac";
7065 - reg = <0xd>;
7066 - };
7067 -
7068 - dpmac14: dpmac@e {
7069 - compatible = "fsl,qoriq-mc-dpmac";
7070 - reg = <0xe>;
7071 - };
7072 -
7073 - dpmac15: dpmac@f {
7074 - compatible = "fsl,qoriq-mc-dpmac";
7075 - reg = <0xf>;
7076 - };
7077 -
7078 - dpmac16: dpmac@10 {
7079 - compatible = "fsl,qoriq-mc-dpmac";
7080 - reg = <0x10>;
7081 - };
7082 - };
7083 - };
7084 -
7085 - smmu: iommu@5000000 {
7086 - compatible = "arm,mmu-500";
7087 - reg = <0 0x5000000 0 0x800000>;
7088 - #global-interrupts = <12>;
7089 - interrupts = <0 13 4>, /* global secure fault */
7090 - <0 14 4>, /* combined secure interrupt */
7091 - <0 15 4>, /* global non-secure fault */
7092 - <0 16 4>, /* combined non-secure interrupt */
7093 - /* performance counter interrupts 0-7 */
7094 - <0 211 4>, <0 212 4>,
7095 - <0 213 4>, <0 214 4>,
7096 - <0 215 4>, <0 216 4>,
7097 - <0 217 4>, <0 218 4>,
7098 - /* per context interrupt, 64 interrupts */
7099 - <0 146 4>, <0 147 4>,
7100 - <0 148 4>, <0 149 4>,
7101 - <0 150 4>, <0 151 4>,
7102 - <0 152 4>, <0 153 4>,
7103 - <0 154 4>, <0 155 4>,
7104 - <0 156 4>, <0 157 4>,
7105 - <0 158 4>, <0 159 4>,
7106 - <0 160 4>, <0 161 4>,
7107 - <0 162 4>, <0 163 4>,
7108 - <0 164 4>, <0 165 4>,
7109 - <0 166 4>, <0 167 4>,
7110 - <0 168 4>, <0 169 4>,
7111 - <0 170 4>, <0 171 4>,
7112 - <0 172 4>, <0 173 4>,
7113 - <0 174 4>, <0 175 4>,
7114 - <0 176 4>, <0 177 4>,
7115 - <0 178 4>, <0 179 4>,
7116 - <0 180 4>, <0 181 4>,
7117 - <0 182 4>, <0 183 4>,
7118 - <0 184 4>, <0 185 4>,
7119 - <0 186 4>, <0 187 4>,
7120 - <0 188 4>, <0 189 4>,
7121 - <0 190 4>, <0 191 4>,
7122 - <0 192 4>, <0 193 4>,
7123 - <0 194 4>, <0 195 4>,
7124 - <0 196 4>, <0 197 4>,
7125 - <0 198 4>, <0 199 4>,
7126 - <0 200 4>, <0 201 4>,
7127 - <0 202 4>, <0 203 4>,
7128 - <0 204 4>, <0 205 4>,
7129 - <0 206 4>, <0 207 4>,
7130 - <0 208 4>, <0 209 4>;
7131 - mmu-masters = <&fsl_mc 0x300 0>;
7132 - };
7133 -
7134 - dspi: dspi@2100000 {
7135 - status = "disabled";
7136 - compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
7137 - #address-cells = <1>;
7138 - #size-cells = <0>;
7139 - reg = <0x0 0x2100000 0x0 0x10000>;
7140 - interrupts = <0 26 0x4>; /* Level high type */
7141 - clocks = <&clockgen 4 3>;
7142 - clock-names = "dspi";
7143 - spi-num-chipselects = <5>;
7144 - bus-num = <0>;
7145 - };
7146 -
7147 - esdhc: esdhc@2140000 {
7148 - status = "disabled";
7149 - compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
7150 - reg = <0x0 0x2140000 0x0 0x10000>;
7151 - interrupts = <0 28 0x4>; /* Level high type */
7152 - clock-frequency = <0>; /* Updated by bootloader */
7153 - voltage-ranges = <1800 1800 3300 3300>;
7154 - sdhci,auto-cmd12;
7155 - little-endian;
7156 - bus-width = <4>;
7157 - };
7158 -
7159 - gpio0: gpio@2300000 {
7160 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
7161 - reg = <0x0 0x2300000 0x0 0x10000>;
7162 - interrupts = <0 36 0x4>; /* Level high type */
7163 - gpio-controller;
7164 - little-endian;
7165 - #gpio-cells = <2>;
7166 - interrupt-controller;
7167 - #interrupt-cells = <2>;
7168 - };
7169 -
7170 - gpio1: gpio@2310000 {
7171 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
7172 - reg = <0x0 0x2310000 0x0 0x10000>;
7173 - interrupts = <0 36 0x4>; /* Level high type */
7174 - gpio-controller;
7175 - little-endian;
7176 - #gpio-cells = <2>;
7177 - interrupt-controller;
7178 - #interrupt-cells = <2>;
7179 - };
7180 -
7181 - gpio2: gpio@2320000 {
7182 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
7183 - reg = <0x0 0x2320000 0x0 0x10000>;
7184 - interrupts = <0 37 0x4>; /* Level high type */
7185 - gpio-controller;
7186 - little-endian;
7187 - #gpio-cells = <2>;
7188 - interrupt-controller;
7189 - #interrupt-cells = <2>;
7190 - };
7191 -
7192 - gpio3: gpio@2330000 {
7193 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
7194 - reg = <0x0 0x2330000 0x0 0x10000>;
7195 - interrupts = <0 37 0x4>; /* Level high type */
7196 - gpio-controller;
7197 - little-endian;
7198 - #gpio-cells = <2>;
7199 - interrupt-controller;
7200 - #interrupt-cells = <2>;
7201 - };
7202 -
7203 - i2c0: i2c@2000000 {
7204 - status = "disabled";
7205 - compatible = "fsl,vf610-i2c";
7206 - #address-cells = <1>;
7207 - #size-cells = <0>;
7208 - reg = <0x0 0x2000000 0x0 0x10000>;
7209 - interrupts = <0 34 0x4>; /* Level high type */
7210 - clock-names = "i2c";
7211 - clocks = <&clockgen 4 3>;
7212 - };
7213 -
7214 - i2c1: i2c@2010000 {
7215 - status = "disabled";
7216 - compatible = "fsl,vf610-i2c";
7217 - #address-cells = <1>;
7218 - #size-cells = <0>;
7219 - reg = <0x0 0x2010000 0x0 0x10000>;
7220 - interrupts = <0 34 0x4>; /* Level high type */
7221 - clock-names = "i2c";
7222 - clocks = <&clockgen 4 3>;
7223 - };
7224 -
7225 - i2c2: i2c@2020000 {
7226 - status = "disabled";
7227 - compatible = "fsl,vf610-i2c";
7228 - #address-cells = <1>;
7229 - #size-cells = <0>;
7230 - reg = <0x0 0x2020000 0x0 0x10000>;
7231 - interrupts = <0 35 0x4>; /* Level high type */
7232 - clock-names = "i2c";
7233 - clocks = <&clockgen 4 3>;
7234 - };
7235 -
7236 - i2c3: i2c@2030000 {
7237 - status = "disabled";
7238 - compatible = "fsl,vf610-i2c";
7239 - #address-cells = <1>;
7240 - #size-cells = <0>;
7241 - reg = <0x0 0x2030000 0x0 0x10000>;
7242 - interrupts = <0 35 0x4>; /* Level high type */
7243 - clock-names = "i2c";
7244 - clocks = <&clockgen 4 3>;
7245 - };
7246 -
7247 - ifc: ifc@2240000 {
7248 - compatible = "fsl,ifc", "simple-bus";
7249 - reg = <0x0 0x2240000 0x0 0x20000>;
7250 - interrupts = <0 21 0x4>; /* Level high type */
7251 - little-endian;
7252 - #address-cells = <2>;
7253 - #size-cells = <1>;
7254 -
7255 - ranges = <0 0 0x5 0x80000000 0x08000000
7256 - 2 0 0x5 0x30000000 0x00010000
7257 - 3 0 0x5 0x20000000 0x00010000>;
7258 - };
7259 -
7260 - qspi: quadspi@20c0000 {
7261 - status = "disabled";
7262 - compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
7263 - #address-cells = <1>;
7264 - #size-cells = <0>;
7265 - reg = <0x0 0x20c0000 0x0 0x10000>,
7266 - <0x0 0x20000000 0x0 0x10000000>;
7267 - reg-names = "QuadSPI", "QuadSPI-memory";
7268 - interrupts = <0 25 0x4>; /* Level high type */
7269 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
7270 - clock-names = "qspi_en", "qspi";
7271 - };
7272 -
7273 - pcie@3400000 {
7274 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7275 - "snps,dw-pcie";
7276 - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
7277 - 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
7278 - reg-names = "regs", "config";
7279 - interrupts = <0 108 0x4>; /* Level high type */
7280 - interrupt-names = "intr";
7281 - #address-cells = <3>;
7282 - #size-cells = <2>;
7283 - device_type = "pci";
7284 - dma-coherent;
7285 - num-lanes = <4>;
7286 - bus-range = <0x0 0xff>;
7287 - ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
7288 - 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7289 - msi-parent = <&its>;
7290 - #interrupt-cells = <1>;
7291 - interrupt-map-mask = <0 0 0 7>;
7292 - interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
7293 - <0000 0 0 2 &gic 0 0 0 110 4>,
7294 - <0000 0 0 3 &gic 0 0 0 111 4>,
7295 - <0000 0 0 4 &gic 0 0 0 112 4>;
7296 - };
7297 -
7298 - pcie@3500000 {
7299 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7300 - "snps,dw-pcie";
7301 - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
7302 - 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
7303 - reg-names = "regs", "config";
7304 - interrupts = <0 113 0x4>; /* Level high type */
7305 - interrupt-names = "intr";
7306 - #address-cells = <3>;
7307 - #size-cells = <2>;
7308 - device_type = "pci";
7309 - dma-coherent;
7310 - num-lanes = <4>;
7311 - bus-range = <0x0 0xff>;
7312 - ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
7313 - 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7314 - msi-parent = <&its>;
7315 - #interrupt-cells = <1>;
7316 - interrupt-map-mask = <0 0 0 7>;
7317 - interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
7318 - <0000 0 0 2 &gic 0 0 0 115 4>,
7319 - <0000 0 0 3 &gic 0 0 0 116 4>,
7320 - <0000 0 0 4 &gic 0 0 0 117 4>;
7321 - };
7322 -
7323 - pcie@3600000 {
7324 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7325 - "snps,dw-pcie";
7326 - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
7327 - 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
7328 - reg-names = "regs", "config";
7329 - interrupts = <0 118 0x4>; /* Level high type */
7330 - interrupt-names = "intr";
7331 - #address-cells = <3>;
7332 - #size-cells = <2>;
7333 - device_type = "pci";
7334 - dma-coherent;
7335 - num-lanes = <8>;
7336 - bus-range = <0x0 0xff>;
7337 - ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
7338 - 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7339 - msi-parent = <&its>;
7340 - #interrupt-cells = <1>;
7341 - interrupt-map-mask = <0 0 0 7>;
7342 - interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
7343 - <0000 0 0 2 &gic 0 0 0 120 4>,
7344 - <0000 0 0 3 &gic 0 0 0 121 4>,
7345 - <0000 0 0 4 &gic 0 0 0 122 4>;
7346 - };
7347 -
7348 - pcie@3700000 {
7349 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7350 - "snps,dw-pcie";
7351 - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
7352 - 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
7353 - reg-names = "regs", "config";
7354 - interrupts = <0 123 0x4>; /* Level high type */
7355 - interrupt-names = "intr";
7356 - #address-cells = <3>;
7357 - #size-cells = <2>;
7358 - device_type = "pci";
7359 - dma-coherent;
7360 - num-lanes = <4>;
7361 - bus-range = <0x0 0xff>;
7362 - ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
7363 - 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7364 - msi-parent = <&its>;
7365 - #interrupt-cells = <1>;
7366 - interrupt-map-mask = <0 0 0 7>;
7367 - interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
7368 - <0000 0 0 2 &gic 0 0 0 125 4>,
7369 - <0000 0 0 3 &gic 0 0 0 126 4>,
7370 - <0000 0 0 4 &gic 0 0 0 127 4>;
7371 - };
7372 -
7373 - sata0: sata@3200000 {
7374 - status = "disabled";
7375 - compatible = "fsl,ls2080a-ahci";
7376 - reg = <0x0 0x3200000 0x0 0x10000>;
7377 - interrupts = <0 133 0x4>; /* Level high type */
7378 - clocks = <&clockgen 4 3>;
7379 - dma-coherent;
7380 - };
7381 -
7382 - sata1: sata@3210000 {
7383 - status = "disabled";
7384 - compatible = "fsl,ls2080a-ahci";
7385 - reg = <0x0 0x3210000 0x0 0x10000>;
7386 - interrupts = <0 136 0x4>; /* Level high type */
7387 - clocks = <&clockgen 4 3>;
7388 - dma-coherent;
7389 - };
7390 -
7391 - usb0: usb3@3100000 {
7392 - status = "disabled";
7393 - compatible = "snps,dwc3";
7394 - reg = <0x0 0x3100000 0x0 0x10000>;
7395 - interrupts = <0 80 0x4>; /* Level high type */
7396 - dr_mode = "host";
7397 - snps,quirk-frame-length-adjustment = <0x20>;
7398 - snps,dis_rxdet_inp3_quirk;
7399 - };
7400 -
7401 - usb1: usb3@3110000 {
7402 - status = "disabled";
7403 - compatible = "snps,dwc3";
7404 - reg = <0x0 0x3110000 0x0 0x10000>;
7405 - interrupts = <0 81 0x4>; /* Level high type */
7406 - dr_mode = "host";
7407 - snps,quirk-frame-length-adjustment = <0x20>;
7408 - snps,dis_rxdet_inp3_quirk;
7409 - };
7410 -
7411 - ccn@4000000 {
7412 - compatible = "arm,ccn-504";
7413 - reg = <0x0 0x04000000 0x0 0x01000000>;
7414 - interrupts = <0 12 4>;
7415 - };
7416 - };
7417 -
7418 - ddr1: memory-controller@1080000 {
7419 - compatible = "fsl,qoriq-memory-controller";
7420 - reg = <0x0 0x1080000 0x0 0x1000>;
7421 - interrupts = <0 17 0x4>;
7422 - little-endian;
7423 - };
7424 -
7425 - ddr2: memory-controller@1090000 {
7426 - compatible = "fsl,qoriq-memory-controller";
7427 - reg = <0x0 0x1090000 0x0 0x1000>;
7428 - interrupts = <0 18 0x4>;
7429 - little-endian;
7430 +#include "fsl-ls208xa.dtsi"
7431 +
7432 +&cpu {
7433 + cpu0: cpu@0 {
7434 + device_type = "cpu";
7435 + compatible = "arm,cortex-a57";
7436 + reg = <0x0>;
7437 + clocks = <&clockgen 1 0>;
7438 + next-level-cache = <&cluster0_l2>;
7439 + #cooling-cells = <2>;
7440 + };
7441 +
7442 + cpu1: cpu@1 {
7443 + device_type = "cpu";
7444 + compatible = "arm,cortex-a57";
7445 + reg = <0x1>;
7446 + clocks = <&clockgen 1 0>;
7447 + next-level-cache = <&cluster0_l2>;
7448 + };
7449 +
7450 + cpu2: cpu@100 {
7451 + device_type = "cpu";
7452 + compatible = "arm,cortex-a57";
7453 + reg = <0x100>;
7454 + clocks = <&clockgen 1 1>;
7455 + next-level-cache = <&cluster1_l2>;
7456 + #cooling-cells = <2>;
7457 + };
7458 +
7459 + cpu3: cpu@101 {
7460 + device_type = "cpu";
7461 + compatible = "arm,cortex-a57";
7462 + reg = <0x101>;
7463 + clocks = <&clockgen 1 1>;
7464 + next-level-cache = <&cluster1_l2>;
7465 + };
7466 +
7467 + cpu4: cpu@200 {
7468 + device_type = "cpu";
7469 + compatible = "arm,cortex-a57";
7470 + reg = <0x200>;
7471 + clocks = <&clockgen 1 2>;
7472 + next-level-cache = <&cluster2_l2>;
7473 + #cooling-cells = <2>;
7474 + };
7475 +
7476 + cpu5: cpu@201 {
7477 + device_type = "cpu";
7478 + compatible = "arm,cortex-a57";
7479 + reg = <0x201>;
7480 + clocks = <&clockgen 1 2>;
7481 + next-level-cache = <&cluster2_l2>;
7482 + };
7483 +
7484 + cpu6: cpu@300 {
7485 + device_type = "cpu";
7486 + compatible = "arm,cortex-a57";
7487 + reg = <0x300>;
7488 + clocks = <&clockgen 1 3>;
7489 + next-level-cache = <&cluster3_l2>;
7490 + #cooling-cells = <2>;
7491 + };
7492 +
7493 + cpu7: cpu@301 {
7494 + device_type = "cpu";
7495 + compatible = "arm,cortex-a57";
7496 + reg = <0x301>;
7497 + clocks = <&clockgen 1 3>;
7498 + next-level-cache = <&cluster3_l2>;
7499 };
7500 +
7501 + cluster0_l2: l2-cache0 {
7502 + compatible = "cache";
7503 + };
7504 +
7505 + cluster1_l2: l2-cache1 {
7506 + compatible = "cache";
7507 + };
7508 +
7509 + cluster2_l2: l2-cache2 {
7510 + compatible = "cache";
7511 + };
7512 +
7513 + cluster3_l2: l2-cache3 {
7514 + compatible = "cache";
7515 + };
7516 +};
7517 +
7518 +&usb0 {
7519 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
7520 + snps,dma-snooping;
7521 +};
7522 +
7523 +&usb1 {
7524 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
7525 + snps,dma-snooping;
7526 +};
7527 +
7528 +&pcie1 {
7529 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
7530 + 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
7531 +
7532 + ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
7533 + 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7534 +};
7535 +
7536 +&pcie2 {
7537 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
7538 + 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
7539 +
7540 + ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
7541 + 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7542 +};
7543 +
7544 +&pcie3 {
7545 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
7546 + 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
7547 +
7548 + ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
7549 + 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7550 +};
7551 +
7552 +&pcie4 {
7553 + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
7554 + 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
7555 +
7556 + ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
7557 + 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7558 };
7559 --- /dev/null
7560 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
7561 @@ -0,0 +1,161 @@
7562 +/*
7563 + * Device Tree file for NXP LS2081A RDB Board.
7564 + *
7565 + * Copyright 2017 NXP
7566 + *
7567 + * Priyanka Jain <priyanka.jain@nxp.com>
7568 + *
7569 + * This file is dual-licensed: you can use it either under the terms
7570 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7571 + * licensing only applies to this file, and not this project as a
7572 + * whole.
7573 + *
7574 + * a) This library is free software; you can redistribute it and/or
7575 + * modify it under the terms of the GNU General Public License as
7576 + * published by the Free Software Foundation; either version 2 of the
7577 + * License, or (at your option) any later version.
7578 + *
7579 + * This library is distributed in the hope that it will be useful,
7580 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7581 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7582 + * GNU General Public License for more details.
7583 + *
7584 + * Or, alternatively,
7585 + *
7586 + * b) Permission is hereby granted, free of charge, to any person
7587 + * obtaining a copy of this software and associated documentation
7588 + * files (the "Software"), to deal in the Software without
7589 + * restriction, including without limitation the rights to use,
7590 + * copy, modify, merge, publish, distribute, sublicense, and/or
7591 + * sell copies of the Software, and to permit persons to whom the
7592 + * Software is furnished to do so, subject to the following
7593 + * conditions:
7594 + *
7595 + * The above copyright notice and this permission notice shall be
7596 + * included in all copies or substantial portions of the Software.
7597 + *
7598 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7599 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7600 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7601 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7602 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7603 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7604 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7605 + * OTHER DEALINGS IN THE SOFTWARE.
7606 + */
7607 +
7608 +/dts-v1/;
7609 +
7610 +#include "fsl-ls2088a.dtsi"
7611 +
7612 +/ {
7613 + model = "NXP Layerscape 2081A RDB Board";
7614 + compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
7615 +
7616 + aliases {
7617 + serial0 = &serial0;
7618 + serial1 = &serial1;
7619 + };
7620 +
7621 + chosen {
7622 + stdout-path = "serial1:115200n8";
7623 + };
7624 +};
7625 +
7626 +&esdhc {
7627 + status = "okay";
7628 +};
7629 +
7630 +&ifc {
7631 + status = "disabled";
7632 +};
7633 +
7634 +&i2c0 {
7635 + status = "okay";
7636 + pca9547@75 {
7637 + compatible = "nxp,pca9547";
7638 + reg = <0x75>;
7639 + #address-cells = <1>;
7640 + #size-cells = <0>;
7641 + i2c@1 {
7642 + #address-cells = <1>;
7643 + #size-cells = <0>;
7644 + reg = <0x01>;
7645 + rtc@51 {
7646 + compatible = "nxp,pcf2129";
7647 + reg = <0x51>;
7648 + };
7649 + };
7650 +
7651 + i2c@2 {
7652 + #address-cells = <1>;
7653 + #size-cells = <0>;
7654 + reg = <0x02>;
7655 +
7656 + ina220@40 {
7657 + compatible = "ti,ina220";
7658 + reg = <0x40>;
7659 + shunt-resistor = <500>;
7660 + };
7661 + };
7662 +
7663 + i2c@3 {
7664 + #address-cells = <1>;
7665 + #size-cells = <0>;
7666 + reg = <0x3>;
7667 +
7668 + adt7481@4c {
7669 + compatible = "adi,adt7461";
7670 + reg = <0x4c>;
7671 + };
7672 + };
7673 + };
7674 +};
7675 +
7676 +&dspi {
7677 + status = "okay";
7678 + dflash0: n25q512a {
7679 + #address-cells = <1>;
7680 + #size-cells = <1>;
7681 + compatible = "st,m25p80";
7682 + spi-max-frequency = <3000000>;
7683 + reg = <0>;
7684 + };
7685 +};
7686 +
7687 +&qspi {
7688 + status = "okay";
7689 + fsl,qspi-has-second-chip;
7690 + flash0: s25fs512s@0 {
7691 + #address-cells = <1>;
7692 + #size-cells = <1>;
7693 + compatible = "spansion,m25p80";
7694 + m25p,fast-read;
7695 + spi-max-frequency = <20000000>;
7696 + reg = <0>;
7697 + };
7698 + flash1: s25fs512s@1 {
7699 + #address-cells = <1>;
7700 + #size-cells = <1>;
7701 + compatible = "spansion,m25p80";
7702 + m25p,fast-read;
7703 + spi-max-frequency = <20000000>;
7704 + reg = <1>;
7705 + };
7706 +};
7707 +
7708 +&sata0 {
7709 + status = "okay";
7710 +};
7711 +
7712 +&sata1 {
7713 + status = "okay";
7714 +};
7715 +
7716 +&usb0 {
7717 + status = "okay";
7718 +};
7719 +
7720 +&usb1 {
7721 + status = "okay";
7722 +};
7723 --- /dev/null
7724 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
7725 @@ -0,0 +1,162 @@
7726 +/*
7727 + * Device Tree file for Freescale LS2088A QDS Board.
7728 + *
7729 + * Copyright 2016 Freescale Semiconductor, Inc.
7730 + * Copyright 2017 NXP
7731 + *
7732 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7733 + *
7734 + * This file is dual-licensed: you can use it either under the terms
7735 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7736 + * licensing only applies to this file, and not this project as a
7737 + * whole.
7738 + *
7739 + * a) This library is free software; you can redistribute it and/or
7740 + * modify it under the terms of the GNU General Public License as
7741 + * published by the Free Software Foundation; either version 2 of the
7742 + * License, or (at your option) any later version.
7743 + *
7744 + * This library is distributed in the hope that it will be useful,
7745 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7746 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7747 + * GNU General Public License for more details.
7748 + *
7749 + * Or, alternatively,
7750 + *
7751 + * b) Permission is hereby granted, free of charge, to any person
7752 + * obtaining a copy of this software and associated documentation
7753 + * files (the "Software"), to deal in the Software without
7754 + * restriction, including without limitation the rights to use,
7755 + * copy, modify, merge, publish, distribute, sublicense, and/or
7756 + * sell copies of the Software, and to permit persons to whom the
7757 + * Software is furnished to do so, subject to the following
7758 + * conditions:
7759 + *
7760 + * The above copyright notice and this permission notice shall be
7761 + * included in all copies or substantial portions of the Software.
7762 + *
7763 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7764 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7765 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7766 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7767 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7768 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7769 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7770 + * OTHER DEALINGS IN THE SOFTWARE.
7771 + */
7772 +
7773 +/dts-v1/;
7774 +
7775 +#include "fsl-ls2088a.dtsi"
7776 +#include "fsl-ls208xa-qds.dtsi"
7777 +
7778 +/ {
7779 + model = "Freescale Layerscape 2088A QDS Board";
7780 + compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
7781 +
7782 + chosen {
7783 + stdout-path = "serial0:115200n8";
7784 + };
7785 +};
7786 +
7787 +&ifc {
7788 + boardctrl: board-control@3,0 {
7789 + #address-cells = <1>;
7790 + #size-cells = <1>;
7791 + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
7792 + reg = <3 0 0x300>; /* TODO check address */
7793 + ranges = <0 3 0 0x300>;
7794 +
7795 + mdio_mux_emi1 {
7796 + compatible = "mdio-mux-mmioreg", "mdio-mux";
7797 + mdio-parent-bus = <&emdio1>;
7798 + reg = <0x54 1>; /* BRDCFG4 */
7799 + mux-mask = <0xe0>; /* EMI1_MDIO */
7800 +
7801 + #address-cells=<1>;
7802 + #size-cells = <0>;
7803 +
7804 + /* Child MDIO buses, one for each riser card:
7805 + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
7806 + * VSC8234 PHYs on the riser cards.
7807 + */
7808 +
7809 + mdio_mux3: mdio@60 {
7810 + reg = <0x60>;
7811 + #address-cells = <1>;
7812 + #size-cells = <0>;
7813 +
7814 + mdio0_phy12: mdio_phy0@1c {
7815 + reg = <0x1c>;
7816 + phy-connection-type = "sgmii";
7817 + };
7818 + mdio0_phy13: mdio_phy1@1d {
7819 + reg = <0x1d>;
7820 + phy-connection-type = "sgmii";
7821 + };
7822 + mdio0_phy14: mdio_phy2@1e {
7823 + reg = <0x1e>;
7824 + phy-connection-type = "sgmii";
7825 + };
7826 + mdio0_phy15: mdio_phy3@1f {
7827 + reg = <0x1f>;
7828 + phy-connection-type = "sgmii";
7829 + };
7830 + };
7831 + };
7832 + };
7833 +};
7834 +
7835 +&pcs_mdio1 {
7836 + pcs_phy1: ethernet-phy@0 {
7837 + backplane-mode = "10gbase-kr";
7838 + compatible = "ethernet-phy-ieee802.3-c45";
7839 + reg = <0x0>;
7840 + fsl,lane-handle = <&serdes1>;
7841 + fsl,lane-reg = <0x9C0 0x40>;/* lane H */
7842 + };
7843 +};
7844 +
7845 +&pcs_mdio2 {
7846 + pcs_phy2: ethernet-phy@0 {
7847 + backplane-mode = "10gbase-kr";
7848 + compatible = "ethernet-phy-ieee802.3-c45";
7849 + reg = <0x0>;
7850 + fsl,lane-handle = <&serdes1>;
7851 + fsl,lane-reg = <0x980 0x40>;/* lane G */
7852 + };
7853 +};
7854 +
7855 +&pcs_mdio3 {
7856 + pcs_phy3: ethernet-phy@0 {
7857 + backplane-mode = "10gbase-kr";
7858 + compatible = "ethernet-phy-ieee802.3-c45";
7859 + reg = <0x0>;
7860 + fsl,lane-handle = <&serdes1>;
7861 + fsl,lane-reg = <0x940 0x40>;/* lane F */
7862 + };
7863 +};
7864 +
7865 +&pcs_mdio4 {
7866 + pcs_phy4: ethernet-phy@0 {
7867 + backplane-mode = "10gbase-kr";
7868 + compatible = "ethernet-phy-ieee802.3-c45";
7869 + reg = <0x0>;
7870 + fsl,lane-handle = <&serdes1>;
7871 + fsl,lane-reg = <0x900 0x40>;/* lane E */
7872 + };
7873 +};
7874 +
7875 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
7876 +&dpmac9 {
7877 + phy-handle = <&mdio0_phy12>;
7878 +};
7879 +&dpmac10 {
7880 + phy-handle = <&mdio0_phy13>;
7881 +};
7882 +&dpmac11 {
7883 + phy-handle = <&mdio0_phy14>;
7884 +};
7885 +&dpmac12 {
7886 + phy-handle = <&mdio0_phy15>;
7887 +};
7888 --- /dev/null
7889 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
7890 @@ -0,0 +1,140 @@
7891 +/*
7892 + * Device Tree file for Freescale LS2088A RDB Board.
7893 + *
7894 + * Copyright 2016 Freescale Semiconductor, Inc.
7895 + * Copyright 2017 NXP
7896 + *
7897 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7898 + *
7899 + * This file is dual-licensed: you can use it either under the terms
7900 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7901 + * licensing only applies to this file, and not this project as a
7902 + * whole.
7903 + *
7904 + * a) This library is free software; you can redistribute it and/or
7905 + * modify it under the terms of the GNU General Public License as
7906 + * published by the Free Software Foundation; either version 2 of the
7907 + * License, or (at your option) any later version.
7908 + *
7909 + * This library is distributed in the hope that it will be useful,
7910 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7911 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7912 + * GNU General Public License for more details.
7913 + *
7914 + * Or, alternatively,
7915 + *
7916 + * b) Permission is hereby granted, free of charge, to any person
7917 + * obtaining a copy of this software and associated documentation
7918 + * files (the "Software"), to deal in the Software without
7919 + * restriction, including without limitation the rights to use,
7920 + * copy, modify, merge, publish, distribute, sublicense, and/or
7921 + * sell copies of the Software, and to permit persons to whom the
7922 + * Software is furnished to do so, subject to the following
7923 + * conditions:
7924 + *
7925 + * The above copyright notice and this permission notice shall be
7926 + * included in all copies or substantial portions of the Software.
7927 + *
7928 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7929 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7930 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7931 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7932 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7933 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7934 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7935 + * OTHER DEALINGS IN THE SOFTWARE.
7936 + */
7937 +
7938 +/dts-v1/;
7939 +
7940 +#include "fsl-ls2088a.dtsi"
7941 +#include "fsl-ls208xa-rdb.dtsi"
7942 +
7943 +/ {
7944 + model = "Freescale Layerscape 2088A RDB Board";
7945 + compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
7946 +
7947 + chosen {
7948 + stdout-path = "serial1:115200n8";
7949 + };
7950 +};
7951 +
7952 +&emdio1 {
7953 + status = "disabled";
7954 + /* CS4340 PHYs */
7955 + mdio1_phy1: emdio1_phy@1 {
7956 + reg = <0x10>;
7957 + phy-connection-type = "xfi";
7958 + };
7959 + mdio1_phy2: emdio1_phy@2 {
7960 + reg = <0x11>;
7961 + phy-connection-type = "xfi";
7962 + };
7963 + mdio1_phy3: emdio1_phy@3 {
7964 + reg = <0x12>;
7965 + phy-connection-type = "xfi";
7966 + };
7967 + mdio1_phy4: emdio1_phy@4 {
7968 + reg = <0x13>;
7969 + phy-connection-type = "xfi";
7970 + };
7971 +};
7972 +
7973 +&emdio2 {
7974 + /* AQR405 PHYs */
7975 + mdio2_phy1: emdio2_phy@1 {
7976 + compatible = "ethernet-phy-ieee802.3-c45";
7977 + interrupts = <0 1 0x4>; /* Level high type */
7978 + reg = <0x0>;
7979 + phy-connection-type = "xfi";
7980 + };
7981 + mdio2_phy2: emdio2_phy@2 {
7982 + compatible = "ethernet-phy-ieee802.3-c45";
7983 + interrupts = <0 2 0x4>; /* Level high type */
7984 + reg = <0x1>;
7985 + phy-connection-type = "xfi";
7986 + };
7987 + mdio2_phy3: emdio2_phy@3 {
7988 + compatible = "ethernet-phy-ieee802.3-c45";
7989 + interrupts = <0 4 0x4>; /* Level high type */
7990 + reg = <0x2>;
7991 + phy-connection-type = "xfi";
7992 + };
7993 + mdio2_phy4: emdio2_phy@4 {
7994 + compatible = "ethernet-phy-ieee802.3-c45";
7995 + interrupts = <0 5 0x4>; /* Level high type */
7996 + reg = <0x3>;
7997 + phy-connection-type = "xfi";
7998 + };
7999 +};
8000 +
8001 +/* Update DPMAC connections to external PHYs, under the assumption of
8002 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
8003 + */
8004 +/* Leave Cortina PHYs commented out until proper driver is integrated
8005 + *&dpmac1 {
8006 + * phy-handle = <&mdio1_phy1>;
8007 + *};
8008 + *&dpmac2 {
8009 + * phy-handle = <&mdio1_phy2>;
8010 + *};
8011 + *&dpmac3 {
8012 + * phy-handle = <&mdio1_phy3>;
8013 + *};
8014 + *&dpmac4 {
8015 + * phy-handle = <&mdio1_phy4>;
8016 + *};
8017 + */
8018 +
8019 +&dpmac5 {
8020 + phy-handle = <&mdio2_phy1>;
8021 +};
8022 +&dpmac6 {
8023 + phy-handle = <&mdio2_phy2>;
8024 +};
8025 +&dpmac7 {
8026 + phy-handle = <&mdio2_phy3>;
8027 +};
8028 +&dpmac8 {
8029 + phy-handle = <&mdio2_phy4>;
8030 +};
8031 --- /dev/null
8032 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
8033 @@ -0,0 +1,195 @@
8034 +/*
8035 + * Device Tree Include file for Freescale Layerscape-2088A family SoC.
8036 + *
8037 + * Copyright 2016 Freescale Semiconductor, Inc.
8038 + * Copyright 2017 NXP
8039 + *
8040 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8041 + *
8042 + * This file is dual-licensed: you can use it either under the terms
8043 + * of the GPLv2 or the X11 license, at your option. Note that this dual
8044 + * licensing only applies to this file, and not this project as a
8045 + * whole.
8046 + *
8047 + * a) This library is free software; you can redistribute it and/or
8048 + * modify it under the terms of the GNU General Public License as
8049 + * published by the Free Software Foundation; either version 2 of the
8050 + * License, or (at your option) any later version.
8051 + *
8052 + * This library is distributed in the hope that it will be useful,
8053 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8054 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8055 + * GNU General Public License for more details.
8056 + *
8057 + * Or, alternatively,
8058 + *
8059 + * b) Permission is hereby granted, free of charge, to any person
8060 + * obtaining a copy of this software and associated documentation
8061 + * files (the "Software"), to deal in the Software without
8062 + * restriction, including without limitation the rights to use,
8063 + * copy, modify, merge, publish, distribute, sublicense, and/or
8064 + * sell copies of the Software, and to permit persons to whom the
8065 + * Software is furnished to do so, subject to the following
8066 + * conditions:
8067 + *
8068 + * The above copyright notice and this permission notice shall be
8069 + * included in all copies or substantial portions of the Software.
8070 + *
8071 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
8072 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
8073 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8074 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
8075 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
8076 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
8077 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
8078 + * OTHER DEALINGS IN THE SOFTWARE.
8079 + */
8080 +
8081 +#include "fsl-ls208xa.dtsi"
8082 +
8083 +&cpu {
8084 + cpu0: cpu@0 {
8085 + device_type = "cpu";
8086 + compatible = "arm,cortex-a72";
8087 + reg = <0x0>;
8088 + clocks = <&clockgen 1 0>;
8089 + next-level-cache = <&cluster0_l2>;
8090 + #cooling-cells = <2>;
8091 + cpu-idle-states = <&CPU_PH20>;
8092 + };
8093 +
8094 + cpu1: cpu@1 {
8095 + device_type = "cpu";
8096 + compatible = "arm,cortex-a72";
8097 + reg = <0x1>;
8098 + clocks = <&clockgen 1 0>;
8099 + next-level-cache = <&cluster0_l2>;
8100 + cpu-idle-states = <&CPU_PH20>;
8101 + };
8102 +
8103 + cpu2: cpu@100 {
8104 + device_type = "cpu";
8105 + compatible = "arm,cortex-a72";
8106 + reg = <0x100>;
8107 + clocks = <&clockgen 1 1>;
8108 + next-level-cache = <&cluster1_l2>;
8109 + #cooling-cells = <2>;
8110 + cpu-idle-states = <&CPU_PH20>;
8111 + };
8112 +
8113 + cpu3: cpu@101 {
8114 + device_type = "cpu";
8115 + compatible = "arm,cortex-a72";
8116 + reg = <0x101>;
8117 + clocks = <&clockgen 1 1>;
8118 + next-level-cache = <&cluster1_l2>;
8119 + cpu-idle-states = <&CPU_PH20>;
8120 + };
8121 +
8122 + cpu4: cpu@200 {
8123 + device_type = "cpu";
8124 + compatible = "arm,cortex-a72";
8125 + reg = <0x200>;
8126 + clocks = <&clockgen 1 2>;
8127 + next-level-cache = <&cluster2_l2>;
8128 + #cooling-cells = <2>;
8129 + cpu-idle-states = <&CPU_PH20>;
8130 + };
8131 +
8132 + cpu5: cpu@201 {
8133 + device_type = "cpu";
8134 + compatible = "arm,cortex-a72";
8135 + reg = <0x201>;
8136 + clocks = <&clockgen 1 2>;
8137 + next-level-cache = <&cluster2_l2>;
8138 + cpu-idle-states = <&CPU_PH20>;
8139 + };
8140 +
8141 + cpu6: cpu@300 {
8142 + device_type = "cpu";
8143 + compatible = "arm,cortex-a72";
8144 + reg = <0x300>;
8145 + clocks = <&clockgen 1 3>;
8146 + next-level-cache = <&cluster3_l2>;
8147 + #cooling-cells = <2>;
8148 + cpu-idle-states = <&CPU_PH20>;
8149 + };
8150 +
8151 + cpu7: cpu@301 {
8152 + device_type = "cpu";
8153 + compatible = "arm,cortex-a72";
8154 + reg = <0x301>;
8155 + clocks = <&clockgen 1 3>;
8156 + next-level-cache = <&cluster3_l2>;
8157 + cpu-idle-states = <&CPU_PH20>;
8158 + };
8159 +
8160 + idle-states {
8161 + /*
8162 + * PSCI node is not added default, U-boot will add missing
8163 + * parts if it determines to use PSCI.
8164 + */
8165 + entry-method = "arm,psci";
8166 +
8167 + CPU_PH20: cpu-ph20 {
8168 + compatible = "arm,idle-state";
8169 + idle-state-name = "PH20";
8170 + arm,psci-suspend-param = <0x0>;
8171 + entry-latency-us = <1000>;
8172 + exit-latency-us = <1000>;
8173 + min-residency-us = <3000>;
8174 + };
8175 + };
8176 +
8177 + cluster0_l2: l2-cache0 {
8178 + compatible = "cache";
8179 + };
8180 +
8181 + cluster1_l2: l2-cache1 {
8182 + compatible = "cache";
8183 + };
8184 +
8185 + cluster2_l2: l2-cache2 {
8186 + compatible = "cache";
8187 + };
8188 +
8189 + cluster3_l2: l2-cache3 {
8190 + compatible = "cache";
8191 + };
8192 +};
8193 +
8194 +&pcie1 {
8195 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
8196 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
8197 + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
8198 +
8199 + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
8200 + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
8201 +};
8202 +
8203 +&pcie2 {
8204 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
8205 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
8206 + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
8207 +
8208 + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
8209 + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
8210 +};
8211 +
8212 +&pcie3 {
8213 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
8214 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
8215 + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
8216 +
8217 + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
8218 + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
8219 +};
8220 +
8221 +&pcie4 {
8222 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
8223 + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
8224 + 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
8225 +
8226 + ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
8227 + 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
8228 +};
8229 --- /dev/null
8230 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
8231 @@ -0,0 +1,198 @@
8232 +/*
8233 + * Device Tree file for Freescale LS2080A QDS Board.
8234 + *
8235 + * Copyright 2016 Freescale Semiconductor, Inc.
8236 + * Copyright 2017 NXP
8237 + *
8238 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8239 + *
8240 + * This file is dual-licensed: you can use it either under the terms
8241 + * of the GPLv2 or the X11 license, at your option. Note that this dual
8242 + * licensing only applies to this file, and not this project as a
8243 + * whole.
8244 + *
8245 + * a) This library is free software; you can redistribute it and/or
8246 + * modify it under the terms of the GNU General Public License as
8247 + * published by the Free Software Foundation; either version 2 of the
8248 + * License, or (at your option) any later version.
8249 + *
8250 + * This library is distributed in the hope that it will be useful,
8251 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8252 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8253 + * GNU General Public License for more details.
8254 + *
8255 + * Or, alternatively,
8256 + *
8257 + * b) Permission is hereby granted, free of charge, to any person
8258 + * obtaining a copy of this software and associated documentation
8259 + * files (the "Software"), to deal in the Software without
8260 + * restriction, including without limitation the rights to use,
8261 + * copy, modify, merge, publish, distribute, sublicense, and/or
8262 + * sell copies of the Software, and to permit persons to whom the
8263 + * Software is furnished to do so, subject to the following
8264 + * conditions:
8265 + *
8266 + * The above copyright notice and this permission notice shall be
8267 + * included in all copies or substantial portions of the Software.
8268 + *
8269 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
8270 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
8271 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8272 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
8273 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
8274 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
8275 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
8276 + * OTHER DEALINGS IN THE SOFTWARE.
8277 + */
8278 +
8279 +&esdhc {
8280 + mmc-hs200-1_8v;
8281 + status = "okay";
8282 +};
8283 +
8284 +&ifc {
8285 + status = "okay";
8286 + #address-cells = <2>;
8287 + #size-cells = <1>;
8288 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
8289 + 0x2 0x0 0x5 0x30000000 0x00010000
8290 + 0x3 0x0 0x5 0x20000000 0x00010000>;
8291 +
8292 + nor@0,0 {
8293 + #address-cells = <1>;
8294 + #size-cells = <1>;
8295 + compatible = "cfi-flash";
8296 + reg = <0x0 0x0 0x8000000>;
8297 + bank-width = <2>;
8298 + device-width = <1>;
8299 + };
8300 +
8301 + nand@2,0 {
8302 + compatible = "fsl,ifc-nand";
8303 + reg = <0x2 0x0 0x10000>;
8304 + };
8305 +
8306 + cpld@3,0 {
8307 + reg = <0x3 0x0 0x10000>;
8308 + compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
8309 + };
8310 +};
8311 +
8312 +&i2c0 {
8313 + status = "okay";
8314 + pca9547@77 {
8315 + compatible = "nxp,pca9547";
8316 + reg = <0x77>;
8317 + #address-cells = <1>;
8318 + #size-cells = <0>;
8319 + i2c@0 {
8320 + #address-cells = <1>;
8321 + #size-cells = <0>;
8322 + reg = <0x00>;
8323 + rtc@68 {
8324 + compatible = "dallas,ds3232";
8325 + reg = <0x68>;
8326 + };
8327 + };
8328 +
8329 + i2c@2 {
8330 + #address-cells = <1>;
8331 + #size-cells = <0>;
8332 + reg = <0x02>;
8333 +
8334 + ina220@40 {
8335 + compatible = "ti,ina220";
8336 + reg = <0x40>;
8337 + shunt-resistor = <500>;
8338 + };
8339 +
8340 + ina220@41 {
8341 + compatible = "ti,ina220";
8342 + reg = <0x41>;
8343 + shunt-resistor = <1000>;
8344 + };
8345 + };
8346 +
8347 + i2c@3 {
8348 + #address-cells = <1>;
8349 + #size-cells = <0>;
8350 + reg = <0x3>;
8351 +
8352 + adt7481@4c {
8353 + compatible = "adi,adt7461";
8354 + reg = <0x4c>;
8355 + };
8356 + };
8357 + };
8358 +};
8359 +
8360 +&i2c1 {
8361 + status = "disabled";
8362 +};
8363 +
8364 +&i2c2 {
8365 + status = "disabled";
8366 +};
8367 +
8368 +&i2c3 {
8369 + status = "disabled";
8370 +};
8371 +
8372 +&dspi {
8373 + status = "okay";
8374 + dflash0: n25q128a {
8375 + #address-cells = <1>;
8376 + #size-cells = <1>;
8377 + compatible = "st,m25p80";
8378 + spi-max-frequency = <3000000>;
8379 + reg = <0>;
8380 + };
8381 + dflash1: sst25wf040b {
8382 + #address-cells = <1>;
8383 + #size-cells = <1>;
8384 + compatible = "st,m25p80";
8385 + spi-max-frequency = <3000000>;
8386 + reg = <1>;
8387 + };
8388 + dflash2: en25s64 {
8389 + #address-cells = <1>;
8390 + #size-cells = <1>;
8391 + compatible = "st,m25p80";
8392 + spi-max-frequency = <3000000>;
8393 + reg = <2>;
8394 + };
8395 +};
8396 +
8397 +&qspi {
8398 + status = "okay";
8399 + flash0: s25fl256s1@0 {
8400 + #address-cells = <1>;
8401 + #size-cells = <1>;
8402 + compatible = "st,m25p80";
8403 + spi-max-frequency = <20000000>;
8404 + reg = <0>;
8405 + };
8406 + flash2: s25fl256s1@2 {
8407 + #address-cells = <1>;
8408 + #size-cells = <1>;
8409 + compatible = "st,m25p80";
8410 + spi-max-frequency = <20000000>;
8411 + reg = <0>;
8412 + };
8413 +};
8414 +
8415 +&sata0 {
8416 + status = "okay";
8417 +};
8418 +
8419 +&sata1 {
8420 + status = "okay";
8421 +};
8422 +
8423 +&usb0 {
8424 + status = "okay";
8425 +};
8426 +
8427 +&usb1 {
8428 + status = "okay";
8429 +};
8430 --- /dev/null
8431 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
8432 @@ -0,0 +1,161 @@
8433 +/*
8434 + * Device Tree file for Freescale LS2080A RDB Board.
8435 + *
8436 + * Copyright 2016 Freescale Semiconductor, Inc.
8437 + * Copyright 2017 NXP
8438 + *
8439 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8440 + *
8441 + * This file is dual-licensed: you can use it either under the terms
8442 + * of the GPLv2 or the X11 license, at your option. Note that this dual
8443 + * licensing only applies to this file, and not this project as a
8444 + * whole.
8445 + *
8446 + * a) This library is free software; you can redistribute it and/or
8447 + * modify it under the terms of the GNU General Public License as
8448 + * published by the Free Software Foundation; either version 2 of the
8449 + * License, or (at your option) any later version.
8450 + *
8451 + * This library is distributed in the hope that it will be useful,
8452 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8453 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8454 + * GNU General Public License for more details.
8455 + *
8456 + * Or, alternatively,
8457 + *
8458 + * b) Permission is hereby granted, free of charge, to any person
8459 + * obtaining a copy of this software and associated documentation
8460 + * files (the "Software"), to deal in the Software without
8461 + * restriction, including without limitation the rights to use,
8462 + * copy, modify, merge, publish, distribute, sublicense, and/or
8463 + * sell copies of the Software, and to permit persons to whom the
8464 + * Software is furnished to do so, subject to the following
8465 + * conditions:
8466 + *
8467 + * The above copyright notice and this permission notice shall be
8468 + * included in all copies or substantial portions of the Software.
8469 + *
8470 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
8471 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
8472 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8473 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
8474 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
8475 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
8476 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
8477 + * OTHER DEALINGS IN THE SOFTWARE.
8478 + */
8479 +
8480 +&esdhc {
8481 + status = "okay";
8482 +};
8483 +
8484 +&ifc {
8485 + status = "okay";
8486 + #address-cells = <2>;
8487 + #size-cells = <1>;
8488 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
8489 + 0x2 0x0 0x5 0x30000000 0x00010000
8490 + 0x3 0x0 0x5 0x20000000 0x00010000>;
8491 +
8492 + nor@0,0 {
8493 + #address-cells = <1>;
8494 + #size-cells = <1>;
8495 + compatible = "cfi-flash";
8496 + reg = <0x0 0x0 0x8000000>;
8497 + bank-width = <2>;
8498 + device-width = <1>;
8499 + };
8500 +
8501 + nand@2,0 {
8502 + compatible = "fsl,ifc-nand";
8503 + reg = <0x2 0x0 0x10000>;
8504 + };
8505 +
8506 + cpld@3,0 {
8507 + reg = <0x3 0x0 0x10000>;
8508 + compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
8509 + };
8510 +
8511 +};
8512 +
8513 +&i2c0 {
8514 + status = "okay";
8515 + pca9547@75 {
8516 + compatible = "nxp,pca9547";
8517 + reg = <0x75>;
8518 + #address-cells = <1>;
8519 + #size-cells = <0>;
8520 + i2c-mux-never-disable;
8521 + i2c@1 {
8522 + #address-cells = <1>;
8523 + #size-cells = <0>;
8524 + reg = <0x01>;
8525 + rtc@68 {
8526 + compatible = "dallas,ds3232";
8527 + reg = <0x68>;
8528 + };
8529 + };
8530 +
8531 + i2c@3 {
8532 + #address-cells = <1>;
8533 + #size-cells = <0>;
8534 + reg = <0x3>;
8535 +
8536 + adt7481@4c {
8537 + compatible = "adi,adt7461";
8538 + reg = <0x4c>;
8539 + };
8540 + };
8541 + };
8542 +};
8543 +
8544 +&i2c1 {
8545 + status = "disabled";
8546 +};
8547 +
8548 +&i2c2 {
8549 + status = "disabled";
8550 +};
8551 +
8552 +&i2c3 {
8553 + status = "disabled";
8554 +};
8555 +
8556 +&dspi {
8557 + status = "okay";
8558 + dflash0: n25q512a {
8559 + #address-cells = <1>;
8560 + #size-cells = <1>;
8561 + compatible = "st,m25p80";
8562 + spi-max-frequency = <3000000>;
8563 + reg = <0>;
8564 + };
8565 +};
8566 +
8567 +&qspi {
8568 + status = "okay";
8569 + flash0: s25fs512s@0 {
8570 + #address-cells = <1>;
8571 + #size-cells = <1>;
8572 + compatible = "spansion,m25p80";
8573 + m25p,fast-read;
8574 + spi-max-frequency = <20000000>;
8575 + reg = <0>;
8576 + };
8577 +};
8578 +
8579 +&sata0 {
8580 + status = "okay";
8581 +};
8582 +
8583 +&sata1 {
8584 + status = "okay";
8585 +};
8586 +
8587 +&usb0 {
8588 + status = "okay";
8589 +};
8590 +
8591 +&usb1 {
8592 + status = "okay";
8593 +};
8594 --- /dev/null
8595 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
8596 @@ -0,0 +1,919 @@
8597 +/*
8598 + * Device Tree Include file for Freescale Layerscape-2080A family SoC.
8599 + *
8600 + * Copyright 2016 Freescale Semiconductor, Inc.
8601 + * Copyright 2017 NXP
8602 + *
8603 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8604 + *
8605 + * This file is dual-licensed: you can use it either under the terms
8606 + * of the GPLv2 or the X11 license, at your option. Note that this dual
8607 + * licensing only applies to this file, and not this project as a
8608 + * whole.
8609 + *
8610 + * a) This library is free software; you can redistribute it and/or
8611 + * modify it under the terms of the GNU General Public License as
8612 + * published by the Free Software Foundation; either version 2 of the
8613 + * License, or (at your option) any later version.
8614 + *
8615 + * This library is distributed in the hope that it will be useful,
8616 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8617 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8618 + * GNU General Public License for more details.
8619 + *
8620 + * Or, alternatively,
8621 + *
8622 + * b) Permission is hereby granted, free of charge, to any person
8623 + * obtaining a copy of this software and associated documentation
8624 + * files (the "Software"), to deal in the Software without
8625 + * restriction, including without limitation the rights to use,
8626 + * copy, modify, merge, publish, distribute, sublicense, and/or
8627 + * sell copies of the Software, and to permit persons to whom the
8628 + * Software is furnished to do so, subject to the following
8629 + * conditions:
8630 + *
8631 + * The above copyright notice and this permission notice shall be
8632 + * included in all copies or substantial portions of the Software.
8633 + *
8634 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
8635 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
8636 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8637 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
8638 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
8639 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
8640 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
8641 + * OTHER DEALINGS IN THE SOFTWARE.
8642 + */
8643 +
8644 +#include <dt-bindings/thermal/thermal.h>
8645 +#include <dt-bindings/interrupt-controller/arm-gic.h>
8646 +
8647 +/ {
8648 + compatible = "fsl,ls2080a";
8649 + interrupt-parent = <&gic>;
8650 + #address-cells = <2>;
8651 + #size-cells = <2>;
8652 +
8653 + aliases {
8654 + crypto = &crypto;
8655 + serial0 = &serial0;
8656 + serial1 = &serial1;
8657 + };
8658 +
8659 + cpu: cpus {
8660 + #address-cells = <1>;
8661 + #size-cells = <0>;
8662 + };
8663 +
8664 + memory@80000000 {
8665 + device_type = "memory";
8666 + reg = <0x00000000 0x80000000 0 0x80000000>;
8667 + /* DRAM space - 1, size : 2 GB DRAM */
8668 + };
8669 +
8670 + sysclk: sysclk {
8671 + compatible = "fixed-clock";
8672 + #clock-cells = <0>;
8673 + clock-frequency = <100000000>;
8674 + clock-output-names = "sysclk";
8675 + };
8676 +
8677 + gic: interrupt-controller@6000000 {
8678 + compatible = "arm,gic-v3";
8679 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
8680 + <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
8681 + <0x0 0x0c0c0000 0 0x2000>, /* GICC */
8682 + <0x0 0x0c0d0000 0 0x1000>, /* GICH */
8683 + <0x0 0x0c0e0000 0 0x20000>; /* GICV */
8684 + #interrupt-cells = <3>;
8685 + #address-cells = <2>;
8686 + #size-cells = <2>;
8687 + ranges;
8688 + interrupt-controller;
8689 + interrupts = <1 9 0x4>;
8690 +
8691 + its: gic-its@6020000 {
8692 + compatible = "arm,gic-v3-its";
8693 + msi-controller;
8694 + reg = <0x0 0x6020000 0 0x20000>;
8695 + };
8696 + };
8697 +
8698 + rstcr: syscon@1e60000 {
8699 + compatible = "fsl,ls2080a-rstcr", "syscon";
8700 + reg = <0x0 0x1e60000 0x0 0x4>;
8701 + };
8702 +
8703 + reboot {
8704 + compatible ="syscon-reboot";
8705 + regmap = <&rstcr>;
8706 + offset = <0x0>;
8707 + mask = <0x2>;
8708 + };
8709 +
8710 + timer {
8711 + compatible = "arm,armv8-timer";
8712 + interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
8713 + <1 14 4>, /* Physical Non-Secure PPI, active-low */
8714 + <1 11 4>, /* Virtual PPI, active-low */
8715 + <1 10 4>; /* Hypervisor PPI, active-low */
8716 + fsl,erratum-a008585;
8717 + };
8718 +
8719 + pmu {
8720 + compatible = "arm,armv8-pmuv3";
8721 + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
8722 + };
8723 +
8724 + soc {
8725 + compatible = "simple-bus";
8726 + #address-cells = <2>;
8727 + #size-cells = <2>;
8728 + ranges;
8729 +
8730 + clockgen: clocking@1300000 {
8731 + compatible = "fsl,ls2080a-clockgen";
8732 + reg = <0 0x1300000 0 0xa0000>;
8733 + #clock-cells = <2>;
8734 + clocks = <&sysclk>;
8735 + };
8736 +
8737 + dcfg: dcfg@1e00000 {
8738 + compatible = "fsl,ls2080a-dcfg", "syscon";
8739 + reg = <0x0 0x1e00000 0x0 0x10000>;
8740 + little-endian;
8741 + };
8742 +
8743 + tmu: tmu@1f80000 {
8744 + compatible = "fsl,qoriq-tmu";
8745 + reg = <0x0 0x1f80000 0x0 0x10000>;
8746 + interrupts = <0 23 0x4>;
8747 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
8748 + fsl,tmu-calibration = <0x00000000 0x00000026
8749 + 0x00000001 0x0000002d
8750 + 0x00000002 0x00000032
8751 + 0x00000003 0x00000039
8752 + 0x00000004 0x0000003f
8753 + 0x00000005 0x00000046
8754 + 0x00000006 0x0000004d
8755 + 0x00000007 0x00000054
8756 + 0x00000008 0x0000005a
8757 + 0x00000009 0x00000061
8758 + 0x0000000a 0x0000006a
8759 + 0x0000000b 0x00000071
8760 +
8761 + 0x00010000 0x00000025
8762 + 0x00010001 0x0000002c
8763 + 0x00010002 0x00000035
8764 + 0x00010003 0x0000003d
8765 + 0x00010004 0x00000045
8766 + 0x00010005 0x0000004e
8767 + 0x00010006 0x00000057
8768 + 0x00010007 0x00000061
8769 + 0x00010008 0x0000006b
8770 + 0x00010009 0x00000076
8771 +
8772 + 0x00020000 0x00000029
8773 + 0x00020001 0x00000033
8774 + 0x00020002 0x0000003d
8775 + 0x00020003 0x00000049
8776 + 0x00020004 0x00000056
8777 + 0x00020005 0x00000061
8778 + 0x00020006 0x0000006d
8779 +
8780 + 0x00030000 0x00000021
8781 + 0x00030001 0x0000002a
8782 + 0x00030002 0x0000003c
8783 + 0x00030003 0x0000004e>;
8784 + little-endian;
8785 + #thermal-sensor-cells = <1>;
8786 + };
8787 +
8788 + thermal-zones {
8789 + cpu_thermal: cpu-thermal {
8790 + polling-delay-passive = <1000>;
8791 + polling-delay = <5000>;
8792 +
8793 + thermal-sensors = <&tmu 4>;
8794 +
8795 + trips {
8796 + cpu_alert: cpu-alert {
8797 + temperature = <75000>;
8798 + hysteresis = <2000>;
8799 + type = "passive";
8800 + };
8801 + cpu_crit: cpu-crit {
8802 + temperature = <85000>;
8803 + hysteresis = <2000>;
8804 + type = "critical";
8805 + };
8806 + };
8807 +
8808 + cooling-maps {
8809 + map0 {
8810 + trip = <&cpu_alert>;
8811 + cooling-device =
8812 + <&cpu0 THERMAL_NO_LIMIT
8813 + THERMAL_NO_LIMIT>;
8814 + };
8815 + map1 {
8816 + trip = <&cpu_alert>;
8817 + cooling-device =
8818 + <&cpu2 THERMAL_NO_LIMIT
8819 + THERMAL_NO_LIMIT>;
8820 + };
8821 + map2 {
8822 + trip = <&cpu_alert>;
8823 + cooling-device =
8824 + <&cpu4 THERMAL_NO_LIMIT
8825 + THERMAL_NO_LIMIT>;
8826 + };
8827 + map3 {
8828 + trip = <&cpu_alert>;
8829 + cooling-device =
8830 + <&cpu6 THERMAL_NO_LIMIT
8831 + THERMAL_NO_LIMIT>;
8832 + };
8833 + };
8834 + };
8835 + };
8836 +
8837 + serial0: serial@21c0500 {
8838 + compatible = "fsl,ns16550", "ns16550a";
8839 + reg = <0x0 0x21c0500 0x0 0x100>;
8840 + clocks = <&clockgen 4 3>;
8841 + interrupts = <0 32 0x4>; /* Level high type */
8842 + };
8843 +
8844 + serial1: serial@21c0600 {
8845 + compatible = "fsl,ns16550", "ns16550a";
8846 + reg = <0x0 0x21c0600 0x0 0x100>;
8847 + clocks = <&clockgen 4 3>;
8848 + interrupts = <0 32 0x4>; /* Level high type */
8849 + };
8850 +
8851 + cluster1_core0_watchdog: wdt@c000000 {
8852 + compatible = "arm,sp805-wdt", "arm,primecell";
8853 + reg = <0x0 0xc000000 0x0 0x1000>;
8854 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8855 + clock-names = "apb_pclk", "wdog_clk";
8856 + };
8857 +
8858 + cluster1_core1_watchdog: wdt@c010000 {
8859 + compatible = "arm,sp805-wdt", "arm,primecell";
8860 + reg = <0x0 0xc010000 0x0 0x1000>;
8861 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8862 + clock-names = "apb_pclk", "wdog_clk";
8863 + };
8864 +
8865 + cluster2_core0_watchdog: wdt@c100000 {
8866 + compatible = "arm,sp805-wdt", "arm,primecell";
8867 + reg = <0x0 0xc100000 0x0 0x1000>;
8868 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8869 + clock-names = "apb_pclk", "wdog_clk";
8870 + };
8871 +
8872 + cluster2_core1_watchdog: wdt@c110000 {
8873 + compatible = "arm,sp805-wdt", "arm,primecell";
8874 + reg = <0x0 0xc110000 0x0 0x1000>;
8875 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8876 + clock-names = "apb_pclk", "wdog_clk";
8877 + };
8878 +
8879 + cluster3_core0_watchdog: wdt@c200000 {
8880 + compatible = "arm,sp805-wdt", "arm,primecell";
8881 + reg = <0x0 0xc200000 0x0 0x1000>;
8882 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8883 + clock-names = "apb_pclk", "wdog_clk";
8884 + };
8885 +
8886 + cluster3_core1_watchdog: wdt@c210000 {
8887 + compatible = "arm,sp805-wdt", "arm,primecell";
8888 + reg = <0x0 0xc210000 0x0 0x1000>;
8889 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8890 + clock-names = "apb_pclk", "wdog_clk";
8891 + };
8892 +
8893 + cluster4_core0_watchdog: wdt@c300000 {
8894 + compatible = "arm,sp805-wdt", "arm,primecell";
8895 + reg = <0x0 0xc300000 0x0 0x1000>;
8896 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8897 + clock-names = "apb_pclk", "wdog_clk";
8898 + };
8899 +
8900 + cluster4_core1_watchdog: wdt@c310000 {
8901 + compatible = "arm,sp805-wdt", "arm,primecell";
8902 + reg = <0x0 0xc310000 0x0 0x1000>;
8903 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8904 + clock-names = "apb_pclk", "wdog_clk";
8905 + };
8906 +
8907 + crypto: crypto@8000000 {
8908 + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
8909 + fsl,sec-era = <8>;
8910 + #address-cells = <1>;
8911 + #size-cells = <1>;
8912 + ranges = <0x0 0x00 0x8000000 0x100000>;
8913 + reg = <0x00 0x8000000 0x0 0x100000>;
8914 + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
8915 + dma-coherent;
8916 +
8917 + sec_jr0: jr@10000 {
8918 + compatible = "fsl,sec-v5.0-job-ring",
8919 + "fsl,sec-v4.0-job-ring";
8920 + reg = <0x10000 0x10000>;
8921 + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
8922 + };
8923 +
8924 + sec_jr1: jr@20000 {
8925 + compatible = "fsl,sec-v5.0-job-ring",
8926 + "fsl,sec-v4.0-job-ring";
8927 + reg = <0x20000 0x10000>;
8928 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
8929 + };
8930 +
8931 + sec_jr2: jr@30000 {
8932 + compatible = "fsl,sec-v5.0-job-ring",
8933 + "fsl,sec-v4.0-job-ring";
8934 + reg = <0x30000 0x10000>;
8935 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
8936 + };
8937 +
8938 + sec_jr3: jr@40000 {
8939 + compatible = "fsl,sec-v5.0-job-ring",
8940 + "fsl,sec-v4.0-job-ring";
8941 + reg = <0x40000 0x10000>;
8942 + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
8943 + };
8944 + };
8945 +
8946 + fsl_mc: fsl-mc@80c000000 {
8947 + compatible = "fsl,qoriq-mc";
8948 + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
8949 + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
8950 + msi-parent = <&its>;
8951 + iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
8952 + #address-cells = <3>;
8953 + #size-cells = <1>;
8954 +
8955 + /*
8956 + * Region type 0x0 - MC portals
8957 + * Region type 0x1 - QBMAN portals
8958 + */
8959 + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
8960 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
8961 +
8962 + /*
8963 + * Define the maximum number of MACs present on the SoC.
8964 + */
8965 + dpmacs {
8966 + #address-cells = <1>;
8967 + #size-cells = <0>;
8968 +
8969 + dpmac1: dpmac@1 {
8970 + compatible = "fsl,qoriq-mc-dpmac";
8971 + reg = <0x1>;
8972 + };
8973 +
8974 + dpmac2: dpmac@2 {
8975 + compatible = "fsl,qoriq-mc-dpmac";
8976 + reg = <0x2>;
8977 + };
8978 +
8979 + dpmac3: dpmac@3 {
8980 + compatible = "fsl,qoriq-mc-dpmac";
8981 + reg = <0x3>;
8982 + };
8983 +
8984 + dpmac4: dpmac@4 {
8985 + compatible = "fsl,qoriq-mc-dpmac";
8986 + reg = <0x4>;
8987 + };
8988 +
8989 + dpmac5: dpmac@5 {
8990 + compatible = "fsl,qoriq-mc-dpmac";
8991 + reg = <0x5>;
8992 + };
8993 +
8994 + dpmac6: dpmac@6 {
8995 + compatible = "fsl,qoriq-mc-dpmac";
8996 + reg = <0x6>;
8997 + };
8998 +
8999 + dpmac7: dpmac@7 {
9000 + compatible = "fsl,qoriq-mc-dpmac";
9001 + reg = <0x7>;
9002 + };
9003 +
9004 + dpmac8: dpmac@8 {
9005 + compatible = "fsl,qoriq-mc-dpmac";
9006 + reg = <0x8>;
9007 + };
9008 +
9009 + dpmac9: dpmac@9 {
9010 + compatible = "fsl,qoriq-mc-dpmac";
9011 + reg = <0x9>;
9012 + };
9013 +
9014 + dpmac10: dpmac@a {
9015 + compatible = "fsl,qoriq-mc-dpmac";
9016 + reg = <0xa>;
9017 + };
9018 +
9019 + dpmac11: dpmac@b {
9020 + compatible = "fsl,qoriq-mc-dpmac";
9021 + reg = <0xb>;
9022 + };
9023 +
9024 + dpmac12: dpmac@c {
9025 + compatible = "fsl,qoriq-mc-dpmac";
9026 + reg = <0xc>;
9027 + };
9028 +
9029 + dpmac13: dpmac@d {
9030 + compatible = "fsl,qoriq-mc-dpmac";
9031 + reg = <0xd>;
9032 + };
9033 +
9034 + dpmac14: dpmac@e {
9035 + compatible = "fsl,qoriq-mc-dpmac";
9036 + reg = <0xe>;
9037 + };
9038 +
9039 + dpmac15: dpmac@f {
9040 + compatible = "fsl,qoriq-mc-dpmac";
9041 + reg = <0xf>;
9042 + };
9043 +
9044 + dpmac16: dpmac@10 {
9045 + compatible = "fsl,qoriq-mc-dpmac";
9046 + reg = <0x10>;
9047 + };
9048 + };
9049 + };
9050 +
9051 + smmu: iommu@5000000 {
9052 + compatible = "arm,mmu-500";
9053 + reg = <0 0x5000000 0 0x800000>;
9054 + #global-interrupts = <12>;
9055 + #iommu-cells = <1>;
9056 + stream-match-mask = <0x7C00>;
9057 + interrupts = <0 13 4>, /* global secure fault */
9058 + <0 14 4>, /* combined secure interrupt */
9059 + <0 15 4>, /* global non-secure fault */
9060 + <0 16 4>, /* combined non-secure interrupt */
9061 + /* performance counter interrupts 0-7 */
9062 + <0 211 4>, <0 212 4>,
9063 + <0 213 4>, <0 214 4>,
9064 + <0 215 4>, <0 216 4>,
9065 + <0 217 4>, <0 218 4>,
9066 + /* per context interrupt, 64 interrupts */
9067 + <0 146 4>, <0 147 4>,
9068 + <0 148 4>, <0 149 4>,
9069 + <0 150 4>, <0 151 4>,
9070 + <0 152 4>, <0 153 4>,
9071 + <0 154 4>, <0 155 4>,
9072 + <0 156 4>, <0 157 4>,
9073 + <0 158 4>, <0 159 4>,
9074 + <0 160 4>, <0 161 4>,
9075 + <0 162 4>, <0 163 4>,
9076 + <0 164 4>, <0 165 4>,
9077 + <0 166 4>, <0 167 4>,
9078 + <0 168 4>, <0 169 4>,
9079 + <0 170 4>, <0 171 4>,
9080 + <0 172 4>, <0 173 4>,
9081 + <0 174 4>, <0 175 4>,
9082 + <0 176 4>, <0 177 4>,
9083 + <0 178 4>, <0 179 4>,
9084 + <0 180 4>, <0 181 4>,
9085 + <0 182 4>, <0 183 4>,
9086 + <0 184 4>, <0 185 4>,
9087 + <0 186 4>, <0 187 4>,
9088 + <0 188 4>, <0 189 4>,
9089 + <0 190 4>, <0 191 4>,
9090 + <0 192 4>, <0 193 4>,
9091 + <0 194 4>, <0 195 4>,
9092 + <0 196 4>, <0 197 4>,
9093 + <0 198 4>, <0 199 4>,
9094 + <0 200 4>, <0 201 4>,
9095 + <0 202 4>, <0 203 4>,
9096 + <0 204 4>, <0 205 4>,
9097 + <0 206 4>, <0 207 4>,
9098 + <0 208 4>, <0 209 4>;
9099 + };
9100 +
9101 + dspi: dspi@2100000 {
9102 + status = "disabled";
9103 + compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
9104 + #address-cells = <1>;
9105 + #size-cells = <0>;
9106 + reg = <0x0 0x2100000 0x0 0x10000>;
9107 + interrupts = <0 26 0x4>; /* Level high type */
9108 + clocks = <&clockgen 4 3>;
9109 + clock-names = "dspi";
9110 + spi-num-chipselects = <5>;
9111 + bus-num = <0>;
9112 + };
9113 +
9114 + esdhc: esdhc@2140000 {
9115 + status = "disabled";
9116 + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
9117 + reg = <0x0 0x2140000 0x0 0x10000>;
9118 + interrupts = <0 28 0x4>; /* Level high type */
9119 + clocks = <&clockgen 4 1>;
9120 + voltage-ranges = <1800 1800 3300 3300>;
9121 + sdhci,auto-cmd12;
9122 + little-endian;
9123 + bus-width = <4>;
9124 + };
9125 +
9126 + gpio0: gpio@2300000 {
9127 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
9128 + reg = <0x0 0x2300000 0x0 0x10000>;
9129 + interrupts = <0 36 0x4>; /* Level high type */
9130 + gpio-controller;
9131 + little-endian;
9132 + #gpio-cells = <2>;
9133 + interrupt-controller;
9134 + #interrupt-cells = <2>;
9135 + };
9136 +
9137 + gpio1: gpio@2310000 {
9138 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
9139 + reg = <0x0 0x2310000 0x0 0x10000>;
9140 + interrupts = <0 36 0x4>; /* Level high type */
9141 + gpio-controller;
9142 + little-endian;
9143 + #gpio-cells = <2>;
9144 + interrupt-controller;
9145 + #interrupt-cells = <2>;
9146 + };
9147 +
9148 + gpio2: gpio@2320000 {
9149 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
9150 + reg = <0x0 0x2320000 0x0 0x10000>;
9151 + interrupts = <0 37 0x4>; /* Level high type */
9152 + gpio-controller;
9153 + little-endian;
9154 + #gpio-cells = <2>;
9155 + interrupt-controller;
9156 + #interrupt-cells = <2>;
9157 + };
9158 +
9159 + gpio3: gpio@2330000 {
9160 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
9161 + reg = <0x0 0x2330000 0x0 0x10000>;
9162 + interrupts = <0 37 0x4>; /* Level high type */
9163 + gpio-controller;
9164 + little-endian;
9165 + #gpio-cells = <2>;
9166 + interrupt-controller;
9167 + #interrupt-cells = <2>;
9168 + };
9169 +
9170 + /* TODO: WRIOP (CCSR?) */
9171 + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
9172 + * E-MDIO1: 0x1_6000
9173 + */
9174 + compatible = "fsl,fman-memac-mdio";
9175 + reg = <0x0 0x8B96000 0x0 0x1000>;
9176 + device_type = "mdio"; /* TODO: is this necessary? */
9177 + little-endian; /* force the driver in LE mode */
9178 +
9179 + /* Not necessary on the QDS, but needed on the RDB */
9180 + #address-cells = <1>;
9181 + #size-cells = <0>;
9182 + };
9183 +
9184 + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
9185 + * E-MDIO2: 0x1_7000
9186 + */
9187 + compatible = "fsl,fman-memac-mdio";
9188 + reg = <0x0 0x8B97000 0x0 0x1000>;
9189 + device_type = "mdio"; /* TODO: is this necessary? */
9190 + little-endian; /* force the driver in LE mode */
9191 +
9192 + #address-cells = <1>;
9193 + #size-cells = <0>;
9194 + };
9195 +
9196 + pcs_mdio1: mdio@0x8c07000 {
9197 + compatible = "fsl,fman-memac-mdio";
9198 + reg = <0x0 0x8c07000 0x0 0x1000>;
9199 + device_type = "mdio";
9200 + little-endian;
9201 +
9202 + #address-cells = <1>;
9203 + #size-cells = <0>;
9204 + };
9205 +
9206 + pcs_mdio2: mdio@0x8c0b000 {
9207 + compatible = "fsl,fman-memac-mdio";
9208 + reg = <0x0 0x8c0b000 0x0 0x1000>;
9209 + device_type = "mdio";
9210 + little-endian;
9211 +
9212 + #address-cells = <1>;
9213 + #size-cells = <0>;
9214 + };
9215 +
9216 + pcs_mdio3: mdio@0x8c0f000 {
9217 + compatible = "fsl,fman-memac-mdio";
9218 + reg = <0x0 0x8c0f000 0x0 0x1000>;
9219 + device_type = "mdio";
9220 + little-endian;
9221 +
9222 + #address-cells = <1>;
9223 + #size-cells = <0>;
9224 + };
9225 +
9226 + pcs_mdio4: mdio@0x8c13000 {
9227 + compatible = "fsl,fman-memac-mdio";
9228 + reg = <0x0 0x8c13000 0x0 0x1000>;
9229 + device_type = "mdio";
9230 + little-endian;
9231 +
9232 + #address-cells = <1>;
9233 + #size-cells = <0>;
9234 + };
9235 +
9236 + pcs_mdio5: mdio@0x8c17000 {
9237 + status = "disabled";
9238 + compatible = "fsl,fman-memac-mdio";
9239 + reg = <0x0 0x8c17000 0x0 0x1000>;
9240 + device_type = "mdio";
9241 + little-endian;
9242 +
9243 + #address-cells = <1>;
9244 + #size-cells = <0>;
9245 + };
9246 +
9247 + pcs_mdio6: mdio@0x8c1b000 {
9248 + status = "disabled";
9249 + compatible = "fsl,fman-memac-mdio";
9250 + reg = <0x0 0x8c1b000 0x0 0x1000>;
9251 + device_type = "mdio";
9252 + little-endian;
9253 +
9254 + #address-cells = <1>;
9255 + #size-cells = <0>;
9256 + };
9257 +
9258 + pcs_mdio7: mdio@0x8c1f000 {
9259 + status = "disabled";
9260 + compatible = "fsl,fman-memac-mdio";
9261 + reg = <0x0 0x8c1f000 0x0 0x1000>;
9262 + device_type = "mdio";
9263 + little-endian;
9264 +
9265 + #address-cells = <1>;
9266 + #size-cells = <0>;
9267 + };
9268 +
9269 + pcs_mdio8: mdio@0x8c23000 {
9270 + status = "disabled";
9271 + compatible = "fsl,fman-memac-mdio";
9272 + reg = <0x0 0x8c23000 0x0 0x1000>;
9273 + device_type = "mdio";
9274 + little-endian;
9275 +
9276 + #address-cells = <1>;
9277 + #size-cells = <0>;
9278 + };
9279 +
9280 + i2c0: i2c@2000000 {
9281 + status = "disabled";
9282 + compatible = "fsl,vf610-i2c";
9283 + #address-cells = <1>;
9284 + #size-cells = <0>;
9285 + reg = <0x0 0x2000000 0x0 0x10000>;
9286 + interrupts = <0 34 0x4>; /* Level high type */
9287 + clock-names = "i2c";
9288 + clocks = <&clockgen 4 1>;
9289 + };
9290 +
9291 + i2c1: i2c@2010000 {
9292 + status = "disabled";
9293 + compatible = "fsl,vf610-i2c";
9294 + #address-cells = <1>;
9295 + #size-cells = <0>;
9296 + reg = <0x0 0x2010000 0x0 0x10000>;
9297 + interrupts = <0 34 0x4>; /* Level high type */
9298 + clock-names = "i2c";
9299 + clocks = <&clockgen 4 1>;
9300 + };
9301 +
9302 + i2c2: i2c@2020000 {
9303 + status = "disabled";
9304 + compatible = "fsl,vf610-i2c";
9305 + #address-cells = <1>;
9306 + #size-cells = <0>;
9307 + reg = <0x0 0x2020000 0x0 0x10000>;
9308 + interrupts = <0 35 0x4>; /* Level high type */
9309 + clock-names = "i2c";
9310 + clocks = <&clockgen 4 1>;
9311 + };
9312 +
9313 + i2c3: i2c@2030000 {
9314 + status = "disabled";
9315 + compatible = "fsl,vf610-i2c";
9316 + #address-cells = <1>;
9317 + #size-cells = <0>;
9318 + reg = <0x0 0x2030000 0x0 0x10000>;
9319 + interrupts = <0 35 0x4>; /* Level high type */
9320 + clock-names = "i2c";
9321 + clocks = <&clockgen 4 1>;
9322 + };
9323 +
9324 + ifc: ifc@2240000 {
9325 + compatible = "fsl,ifc", "simple-bus";
9326 + reg = <0x0 0x2240000 0x0 0x20000>;
9327 + interrupts = <0 21 0x4>; /* Level high type */
9328 + little-endian;
9329 + #address-cells = <2>;
9330 + #size-cells = <1>;
9331 +
9332 + ranges = <0 0 0x5 0x80000000 0x08000000
9333 + 2 0 0x5 0x30000000 0x00010000
9334 + 3 0 0x5 0x20000000 0x00010000>;
9335 + };
9336 +
9337 + qspi: quadspi@20c0000 {
9338 + status = "disabled";
9339 + compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
9340 + #address-cells = <1>;
9341 + #size-cells = <0>;
9342 + reg = <0x0 0x20c0000 0x0 0x10000>,
9343 + <0x0 0x20000000 0x0 0x10000000>;
9344 + reg-names = "QuadSPI", "QuadSPI-memory";
9345 + interrupts = <0 25 0x4>; /* Level high type */
9346 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
9347 + clock-names = "qspi_en", "qspi";
9348 + };
9349 +
9350 + pcie1: pcie@3400000 {
9351 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9352 + "snps,dw-pcie";
9353 + reg-names = "regs", "config";
9354 + interrupts = <0 108 0x4>; /* aer interrupt */
9355 + interrupt-names = "aer";
9356 + #address-cells = <3>;
9357 + #size-cells = <2>;
9358 + device_type = "pci";
9359 + dma-coherent;
9360 + num-lanes = <4>;
9361 + bus-range = <0x0 0xff>;
9362 + msi-parent = <&its>;
9363 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9364 + #interrupt-cells = <1>;
9365 + interrupt-map-mask = <0 0 0 7>;
9366 + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
9367 + <0000 0 0 2 &gic 0 0 0 110 4>,
9368 + <0000 0 0 3 &gic 0 0 0 111 4>,
9369 + <0000 0 0 4 &gic 0 0 0 112 4>;
9370 + };
9371 +
9372 + pcie2: pcie@3500000 {
9373 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9374 + "snps,dw-pcie";
9375 + reg-names = "regs", "config";
9376 + interrupts = <0 113 0x4>; /* aer interrupt */
9377 + interrupt-names = "aer";
9378 + #address-cells = <3>;
9379 + #size-cells = <2>;
9380 + device_type = "pci";
9381 + dma-coherent;
9382 + num-lanes = <4>;
9383 + bus-range = <0x0 0xff>;
9384 + msi-parent = <&its>;
9385 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9386 + #interrupt-cells = <1>;
9387 + interrupt-map-mask = <0 0 0 7>;
9388 + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
9389 + <0000 0 0 2 &gic 0 0 0 115 4>,
9390 + <0000 0 0 3 &gic 0 0 0 116 4>,
9391 + <0000 0 0 4 &gic 0 0 0 117 4>;
9392 + };
9393 +
9394 + pcie3: pcie@3600000 {
9395 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9396 + "snps,dw-pcie";
9397 + reg-names = "regs", "config";
9398 + interrupts = <0 118 0x4>; /* aer interrupt */
9399 + interrupt-names = "aer";
9400 + #address-cells = <3>;
9401 + #size-cells = <2>;
9402 + device_type = "pci";
9403 + dma-coherent;
9404 + num-lanes = <8>;
9405 + bus-range = <0x0 0xff>;
9406 + msi-parent = <&its>;
9407 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9408 + #interrupt-cells = <1>;
9409 + interrupt-map-mask = <0 0 0 7>;
9410 + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
9411 + <0000 0 0 2 &gic 0 0 0 120 4>,
9412 + <0000 0 0 3 &gic 0 0 0 121 4>,
9413 + <0000 0 0 4 &gic 0 0 0 122 4>;
9414 + };
9415 +
9416 + pcie4: pcie@3700000 {
9417 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9418 + "snps,dw-pcie";
9419 + reg-names = "regs", "config";
9420 + interrupts = <0 123 0x4>; /* aer interrupt */
9421 + interrupt-names = "aer";
9422 + #address-cells = <3>;
9423 + #size-cells = <2>;
9424 + device_type = "pci";
9425 + dma-coherent;
9426 + num-lanes = <4>;
9427 + bus-range = <0x0 0xff>;
9428 + msi-parent = <&its>;
9429 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9430 + #interrupt-cells = <1>;
9431 + interrupt-map-mask = <0 0 0 7>;
9432 + interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
9433 + <0000 0 0 2 &gic 0 0 0 125 4>,
9434 + <0000 0 0 3 &gic 0 0 0 126 4>,
9435 + <0000 0 0 4 &gic 0 0 0 127 4>;
9436 + };
9437 +
9438 + sata0: sata@3200000 {
9439 + status = "disabled";
9440 + compatible = "fsl,ls2080a-ahci";
9441 + reg = <0x0 0x3200000 0x0 0x10000>;
9442 + interrupts = <0 133 0x4>; /* Level high type */
9443 + clocks = <&clockgen 4 3>;
9444 + dma-coherent;
9445 + };
9446 +
9447 + sata1: sata@3210000 {
9448 + status = "disabled";
9449 + compatible = "fsl,ls2080a-ahci";
9450 + reg = <0x0 0x3210000 0x0 0x10000>;
9451 + interrupts = <0 136 0x4>; /* Level high type */
9452 + clocks = <&clockgen 4 3>;
9453 + dma-coherent;
9454 + };
9455 +
9456 + usb0: usb3@3100000 {
9457 + status = "disabled";
9458 + compatible = "snps,dwc3";
9459 + reg = <0x0 0x3100000 0x0 0x10000>;
9460 + interrupts = <0 80 0x4>; /* Level high type */
9461 + dr_mode = "host";
9462 + snps,quirk-frame-length-adjustment = <0x20>;
9463 + snps,dis_rxdet_inp3_quirk;
9464 + };
9465 +
9466 + usb1: usb3@3110000 {
9467 + status = "disabled";
9468 + compatible = "snps,dwc3";
9469 + reg = <0x0 0x3110000 0x0 0x10000>;
9470 + interrupts = <0 81 0x4>; /* Level high type */
9471 + dr_mode = "host";
9472 + snps,quirk-frame-length-adjustment = <0x20>;
9473 + snps,dis_rxdet_inp3_quirk;
9474 + };
9475 +
9476 + serdes1: serdes@1ea0000 {
9477 + reg = <0x0 0x1ea0000 0 0x00002000>;
9478 + };
9479 +
9480 + ccn@4000000 {
9481 + compatible = "arm,ccn-504";
9482 + reg = <0x0 0x04000000 0x0 0x01000000>;
9483 + interrupts = <0 12 4>;
9484 + };
9485 +
9486 + ftm0: ftm0@2800000 {
9487 + compatible = "fsl,ls208xa-ftm";
9488 + reg = <0x0 0x2800000 0x0 0x10000>,
9489 + <0x0 0x1e34050 0x0 0x4>;
9490 + interrupts = <0 44 4>;
9491 + reg-names = "ftm", "FlexTimer1";
9492 + };
9493 + };
9494 +
9495 + ddr1: memory-controller@1080000 {
9496 + compatible = "fsl,qoriq-memory-controller";
9497 + reg = <0x0 0x1080000 0x0 0x1000>;
9498 + interrupts = <0 17 0x4>;
9499 + little-endian;
9500 + };
9501 +
9502 + ddr2: memory-controller@1090000 {
9503 + compatible = "fsl,qoriq-memory-controller";
9504 + reg = <0x0 0x1090000 0x0 0x1000>;
9505 + interrupts = <0 18 0x4>;
9506 + little-endian;
9507 + };
9508 +
9509 + firmware {
9510 + optee {
9511 + compatible = "linaro,optee-tz";
9512 + method = "smc";
9513 + };
9514 + };
9515 +};
9516 --- /dev/null
9517 +++ b/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
9518 @@ -0,0 +1,81 @@
9519 +/*
9520 + * QorIQ BMan Portals device tree
9521 + *
9522 + * Copyright 2011-2016 Freescale Semiconductor Inc.
9523 + *
9524 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9525 + */
9526 +
9527 +&bportals {
9528 + #address-cells = <1>;
9529 + #size-cells = <1>;
9530 + compatible = "simple-bus";
9531 +
9532 + bman-portal@0 {
9533 + cell-index = <0>;
9534 + compatible = "fsl,bman-portal";
9535 + reg = <0x0 0x4000 0x4000000 0x4000>;
9536 + interrupts = <0 173 0x4>;
9537 + };
9538 +
9539 + bman-portal@10000 {
9540 + cell-index = <1>;
9541 + compatible = "fsl,bman-portal";
9542 + reg = <0x10000 0x4000 0x4010000 0x4000>;
9543 + interrupts = <0 175 0x4>;
9544 + };
9545 +
9546 + bman-portal@20000 {
9547 + cell-index = <2>;
9548 + compatible = "fsl,bman-portal";
9549 + reg = <0x20000 0x4000 0x4020000 0x4000>;
9550 + interrupts = <0 177 0x4>;
9551 + };
9552 +
9553 + bman-portal@30000 {
9554 + cell-index = <3>;
9555 + compatible = "fsl,bman-portal";
9556 + reg = <0x30000 0x4000 0x4030000 0x4000>;
9557 + interrupts = <0 179 0x4>;
9558 + };
9559 +
9560 + bman-portal@40000 {
9561 + cell-index = <4>;
9562 + compatible = "fsl,bman-portal";
9563 + reg = <0x40000 0x4000 0x4040000 0x4000>;
9564 + interrupts = <0 181 0x4>;
9565 + };
9566 +
9567 + bman-portal@50000 {
9568 + cell-index = <5>;
9569 + compatible = "fsl,bman-portal";
9570 + reg = <0x50000 0x4000 0x4050000 0x4000>;
9571 + interrupts = <0 183 0x4>;
9572 + };
9573 +
9574 + bman-portal@60000 {
9575 + cell-index = <6>;
9576 + compatible = "fsl,bman-portal";
9577 + reg = <0x60000 0x4000 0x4060000 0x4000>;
9578 + interrupts = <0 185 0x4>;
9579 + };
9580 +
9581 + bman-portal@70000 {
9582 + cell-index = <7>;
9583 + compatible = "fsl,bman-portal";
9584 + reg = <0x70000 0x4000 0x4070000 0x4000>;
9585 + interrupts = <0 187 0x4>;
9586 + };
9587 +
9588 + bman-portal@80000 {
9589 + cell-index = <8>;
9590 + compatible = "fsl,bman-portal";
9591 + reg = <0x80000 0x4000 0x4080000 0x4000>;
9592 + interrupts = <0 189 0x4>;
9593 + };
9594 +
9595 + bman-bpids@0 {
9596 + compatible = "fsl,bpid-range";
9597 + fsl,bpid-range = <32 32>;
9598 + };
9599 +};
9600 --- /dev/null
9601 +++ b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
9602 @@ -0,0 +1,73 @@
9603 +/*
9604 + * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ]
9605 + *
9606 + * Copyright 2012 - 2015 Freescale Semiconductor Inc.
9607 + *
9608 + * Redistribution and use in source and binary forms, with or without
9609 + * modification, are permitted provided that the following conditions are met:
9610 + * * Redistributions of source code must retain the above copyright
9611 + * notice, this list of conditions and the following disclaimer.
9612 + * * Redistributions in binary form must reproduce the above copyright
9613 + * notice, this list of conditions and the following disclaimer in the
9614 + * documentation and/or other materials provided with the distribution.
9615 + * * Neither the name of Freescale Semiconductor nor the
9616 + * names of its contributors may be used to endorse or promote products
9617 + * derived from this software without specific prior written permission.
9618 + *
9619 + *
9620 + * ALTERNATIVELY, this software may be distributed under the terms of the
9621 + * GNU General Public License ("GPL") as published by the Free Software
9622 + * Foundation, either version 2 of that License or (at your option) any
9623 + * later version.
9624 + *
9625 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
9626 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
9627 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
9628 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
9629 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9630 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
9631 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
9632 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9633 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
9634 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9635 + */
9636 +
9637 +fsldpaa: fsl,dpaa {
9638 + compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa";
9639 + ethernet@0 {
9640 + compatible = "fsl,dpa-ethernet";
9641 + fsl,fman-mac = <&enet0>;
9642 + dma-coherent;
9643 + };
9644 + ethernet@1 {
9645 + compatible = "fsl,dpa-ethernet";
9646 + fsl,fman-mac = <&enet1>;
9647 + dma-coherent;
9648 + };
9649 + ethernet@2 {
9650 + compatible = "fsl,dpa-ethernet";
9651 + fsl,fman-mac = <&enet2>;
9652 + dma-coherent;
9653 + };
9654 + ethernet@3 {
9655 + compatible = "fsl,dpa-ethernet";
9656 + fsl,fman-mac = <&enet3>;
9657 + dma-coherent;
9658 + };
9659 + ethernet@4 {
9660 + compatible = "fsl,dpa-ethernet";
9661 + fsl,fman-mac = <&enet4>;
9662 + dma-coherent;
9663 + };
9664 + ethernet@5 {
9665 + compatible = "fsl,dpa-ethernet";
9666 + fsl,fman-mac = <&enet5>;
9667 + dma-coherent;
9668 + };
9669 + ethernet@8 {
9670 + compatible = "fsl,dpa-ethernet";
9671 + fsl,fman-mac = <&enet6>;
9672 + dma-coherent;
9673 + };
9674 +};
9675 +
9676 --- /dev/null
9677 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
9678 @@ -0,0 +1,43 @@
9679 +/*
9680 + * QorIQ FMan v3 10g port #0 device tree
9681 + *
9682 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9683 + *
9684 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9685 + */
9686 +
9687 +fman@1a00000 {
9688 + fman0_rx_0x10: port@90000 {
9689 + cell-index = <0x10>;
9690 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
9691 + reg = <0x90000 0x1000>;
9692 + fsl,fman-10g-port;
9693 + };
9694 +
9695 + fman0_tx_0x30: port@b0000 {
9696 + cell-index = <0x30>;
9697 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
9698 + reg = <0xb0000 0x1000>;
9699 + fsl,fman-10g-port;
9700 + fsl,qman-channel-id = <0x800>;
9701 + };
9702 +
9703 + ethernet@f0000 {
9704 + cell-index = <0x8>;
9705 + compatible = "fsl,fman-memac";
9706 + reg = <0xf0000 0x1000>;
9707 + fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
9708 + pcsphy-handle = <&pcsphy6>;
9709 + };
9710 +
9711 + mdio@f1000 {
9712 + #address-cells = <1>;
9713 + #size-cells = <0>;
9714 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9715 + reg = <0xf1000 0x1000>;
9716 +
9717 + pcsphy6: ethernet-phy@0 {
9718 + reg = <0x0>;
9719 + };
9720 + };
9721 +};
9722 --- /dev/null
9723 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
9724 @@ -0,0 +1,43 @@
9725 +/*
9726 + * QorIQ FMan v3 10g port #1 device tree
9727 + *
9728 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9729 + *
9730 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9731 + */
9732 +
9733 +fman@1a00000 {
9734 + fman0_rx_0x11: port@91000 {
9735 + cell-index = <0x11>;
9736 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
9737 + reg = <0x91000 0x1000>;
9738 + fsl,fman-10g-port;
9739 + };
9740 +
9741 + fman0_tx_0x31: port@b1000 {
9742 + cell-index = <0x31>;
9743 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
9744 + reg = <0xb1000 0x1000>;
9745 + fsl,fman-10g-port;
9746 + fsl,qman-channel-id = <0x801>;
9747 + };
9748 +
9749 + ethernet@f2000 {
9750 + cell-index = <0x9>;
9751 + compatible = "fsl,fman-memac";
9752 + reg = <0xf2000 0x1000>;
9753 + fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
9754 + pcsphy-handle = <&pcsphy7>;
9755 + };
9756 +
9757 + mdio@f3000 {
9758 + #address-cells = <1>;
9759 + #size-cells = <0>;
9760 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9761 + reg = <0xf3000 0x1000>;
9762 +
9763 + pcsphy7: ethernet-phy@0 {
9764 + reg = <0x0>;
9765 + };
9766 + };
9767 +};
9768 --- /dev/null
9769 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
9770 @@ -0,0 +1,42 @@
9771 +/*
9772 + * QorIQ FMan v3 1g port #0 device tree
9773 + *
9774 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9775 + *
9776 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9777 + */
9778 +
9779 +fman@1a00000 {
9780 + fman0_rx_0x08: port@88000 {
9781 + cell-index = <0x8>;
9782 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9783 + reg = <0x88000 0x1000>;
9784 + };
9785 +
9786 + fman0_tx_0x28: port@a8000 {
9787 + cell-index = <0x28>;
9788 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9789 + reg = <0xa8000 0x1000>;
9790 + fsl,qman-channel-id = <0x802>;
9791 + };
9792 +
9793 + ethernet@e0000 {
9794 + cell-index = <0>;
9795 + compatible = "fsl,fman-memac";
9796 + reg = <0xe0000 0x1000>;
9797 + fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
9798 + ptp-timer = <&ptp_timer0>;
9799 + pcsphy-handle = <&pcsphy0>;
9800 + };
9801 +
9802 + mdio@e1000 {
9803 + #address-cells = <1>;
9804 + #size-cells = <0>;
9805 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9806 + reg = <0xe1000 0x1000>;
9807 +
9808 + pcsphy0: ethernet-phy@0 {
9809 + reg = <0x0>;
9810 + };
9811 + };
9812 +};
9813 --- /dev/null
9814 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
9815 @@ -0,0 +1,42 @@
9816 +/*
9817 + * QorIQ FMan v3 1g port #1 device tree
9818 + *
9819 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9820 + *
9821 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9822 + */
9823 +
9824 +fman@1a00000 {
9825 + fman0_rx_0x09: port@89000 {
9826 + cell-index = <0x9>;
9827 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9828 + reg = <0x89000 0x1000>;
9829 + };
9830 +
9831 + fman0_tx_0x29: port@a9000 {
9832 + cell-index = <0x29>;
9833 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9834 + reg = <0xa9000 0x1000>;
9835 + fsl,qman-channel-id = <0x803>;
9836 + };
9837 +
9838 + ethernet@e2000 {
9839 + cell-index = <1>;
9840 + compatible = "fsl,fman-memac";
9841 + reg = <0xe2000 0x1000>;
9842 + fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
9843 + ptp-timer = <&ptp_timer0>;
9844 + pcsphy-handle = <&pcsphy1>;
9845 + };
9846 +
9847 + mdio@e3000 {
9848 + #address-cells = <1>;
9849 + #size-cells = <0>;
9850 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9851 + reg = <0xe3000 0x1000>;
9852 +
9853 + pcsphy1: ethernet-phy@0 {
9854 + reg = <0x0>;
9855 + };
9856 + };
9857 +};
9858 --- /dev/null
9859 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
9860 @@ -0,0 +1,42 @@
9861 +/*
9862 + * QorIQ FMan v3 1g port #2 device tree
9863 + *
9864 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9865 + *
9866 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9867 + */
9868 +
9869 +fman@1a00000 {
9870 + fman0_rx_0x0a: port@8a000 {
9871 + cell-index = <0xa>;
9872 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9873 + reg = <0x8a000 0x1000>;
9874 + };
9875 +
9876 + fman0_tx_0x2a: port@aa000 {
9877 + cell-index = <0x2a>;
9878 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9879 + reg = <0xaa000 0x1000>;
9880 + fsl,qman-channel-id = <0x804>;
9881 + };
9882 +
9883 + ethernet@e4000 {
9884 + cell-index = <2>;
9885 + compatible = "fsl,fman-memac";
9886 + reg = <0xe4000 0x1000>;
9887 + fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
9888 + ptp-timer = <&ptp_timer0>;
9889 + pcsphy-handle = <&pcsphy2>;
9890 + };
9891 +
9892 + mdio@e5000 {
9893 + #address-cells = <1>;
9894 + #size-cells = <0>;
9895 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9896 + reg = <0xe5000 0x1000>;
9897 +
9898 + pcsphy2: ethernet-phy@0 {
9899 + reg = <0x0>;
9900 + };
9901 + };
9902 +};
9903 --- /dev/null
9904 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
9905 @@ -0,0 +1,42 @@
9906 +/*
9907 + * QorIQ FMan v3 1g port #3 device tree
9908 + *
9909 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9910 + *
9911 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9912 + */
9913 +
9914 +fman@1a00000 {
9915 + fman0_rx_0x0b: port@8b000 {
9916 + cell-index = <0xb>;
9917 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9918 + reg = <0x8b000 0x1000>;
9919 + };
9920 +
9921 + fman0_tx_0x2b: port@ab000 {
9922 + cell-index = <0x2b>;
9923 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9924 + reg = <0xab000 0x1000>;
9925 + fsl,qman-channel-id = <0x805>;
9926 + };
9927 +
9928 + ethernet@e6000 {
9929 + cell-index = <3>;
9930 + compatible = "fsl,fman-memac";
9931 + reg = <0xe6000 0x1000>;
9932 + fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
9933 + ptp-timer = <&ptp_timer0>;
9934 + pcsphy-handle = <&pcsphy3>;
9935 + };
9936 +
9937 + mdio@e7000 {
9938 + #address-cells = <1>;
9939 + #size-cells = <0>;
9940 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9941 + reg = <0xe7000 0x1000>;
9942 +
9943 + pcsphy3: ethernet-phy@0 {
9944 + reg = <0x0>;
9945 + };
9946 + };
9947 +};
9948 --- /dev/null
9949 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
9950 @@ -0,0 +1,42 @@
9951 +/*
9952 + * QorIQ FMan v3 1g port #4 device tree
9953 + *
9954 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9955 + *
9956 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9957 + */
9958 +
9959 +fman@1a00000 {
9960 + fman0_rx_0x0c: port@8c000 {
9961 + cell-index = <0xc>;
9962 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9963 + reg = <0x8c000 0x1000>;
9964 + };
9965 +
9966 + fman0_tx_0x2c: port@ac000 {
9967 + cell-index = <0x2c>;
9968 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9969 + reg = <0xac000 0x1000>;
9970 + fsl,qman-channel-id = <0x806>;
9971 + };
9972 +
9973 + ethernet@e8000 {
9974 + cell-index = <4>;
9975 + compatible = "fsl,fman-memac";
9976 + reg = <0xe8000 0x1000>;
9977 + fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
9978 + ptp-timer = <&ptp_timer0>;
9979 + pcsphy-handle = <&pcsphy4>;
9980 + };
9981 +
9982 + mdio@e9000 {
9983 + #address-cells = <1>;
9984 + #size-cells = <0>;
9985 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9986 + reg = <0xe9000 0x1000>;
9987 +
9988 + pcsphy4: ethernet-phy@0 {
9989 + reg = <0x0>;
9990 + };
9991 + };
9992 +};
9993 --- /dev/null
9994 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
9995 @@ -0,0 +1,42 @@
9996 +/*
9997 + * QorIQ FMan v3 1g port #5 device tree
9998 + *
9999 + * Copyright 2012-2015 Freescale Semiconductor Inc.
10000 + *
10001 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
10002 + */
10003 +
10004 +fman@1a00000 {
10005 + fman0_rx_0x0d: port@8d000 {
10006 + cell-index = <0xd>;
10007 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
10008 + reg = <0x8d000 0x1000>;
10009 + };
10010 +
10011 + fman0_tx_0x2d: port@ad000 {
10012 + cell-index = <0x2d>;
10013 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
10014 + reg = <0xad000 0x1000>;
10015 + fsl,qman-channel-id = <0x807>;
10016 + };
10017 +
10018 + ethernet@ea000 {
10019 + cell-index = <5>;
10020 + compatible = "fsl,fman-memac";
10021 + reg = <0xea000 0x1000>;
10022 + fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
10023 + ptp-timer = <&ptp_timer0>;
10024 + pcsphy-handle = <&pcsphy5>;
10025 + };
10026 +
10027 + mdio@eb000 {
10028 + #address-cells = <1>;
10029 + #size-cells = <0>;
10030 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
10031 + reg = <0xeb000 0x1000>;
10032 +
10033 + pcsphy5: ethernet-phy@0 {
10034 + reg = <0x0>;
10035 + };
10036 + };
10037 +};
10038 --- /dev/null
10039 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
10040 @@ -0,0 +1,47 @@
10041 +/*
10042 + * QorIQ FMan v3 OH ports device tree
10043 + *
10044 + * Copyright 2012-2015 Freescale Semiconductor Inc.
10045 + *
10046 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
10047 + */
10048 +
10049 +fman@1a00000 {
10050 +
10051 + fman0_oh1: port@82000 {
10052 + cell-index = <0>;
10053 + compatible = "fsl,fman-port-oh";
10054 + reg = <0x82000 0x1000>;
10055 + };
10056 +
10057 + fman0_oh2: port@83000 {
10058 + cell-index = <1>;
10059 + compatible = "fsl,fman-port-oh";
10060 + reg = <0x83000 0x1000>;
10061 + };
10062 +
10063 + fman0_oh3: port@84000 {
10064 + cell-index = <2>;
10065 + compatible = "fsl,fman-port-oh";
10066 + reg = <0x84000 0x1000>;
10067 + };
10068 +
10069 + fman0_oh4: port@85000 {
10070 + cell-index = <3>;
10071 + compatible = "fsl,fman-port-oh";
10072 + reg = <0x85000 0x1000>;
10073 + };
10074 +
10075 + fman0_oh5: port@86000 {
10076 + cell-index = <4>;
10077 + compatible = "fsl,fman-port-oh";
10078 + reg = <0x86000 0x1000>;
10079 + };
10080 +
10081 + fman0_oh6: port@87000 {
10082 + cell-index = <5>;
10083 + compatible = "fsl,fman-port-oh";
10084 + reg = <0x87000 0x1000>;
10085 + };
10086 +
10087 +};
10088 --- /dev/null
10089 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
10090 @@ -0,0 +1,130 @@
10091 +/*
10092 + * QorIQ FMan v3 device tree
10093 + *
10094 + * Copyright 2012-2015 Freescale Semiconductor Inc.
10095 + *
10096 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
10097 + */
10098 +
10099 +fman0: fman@1a00000 {
10100 + #address-cells = <1>;
10101 + #size-cells = <1>;
10102 + cell-index = <0>;
10103 + compatible = "fsl,fman";
10104 + ranges = <0x0 0x00 0x1a00000 0x100000>;
10105 + reg = <0x0 0x1a00000 0x0 0x100000>;
10106 + interrupts = <0 44 0x4>, <0 45 0x4>;
10107 + clocks = <&clockgen 3 0>;
10108 + clock-names = "fmanclk";
10109 + fsl,qman-channel-range = <0x800 0x10>;
10110 +
10111 + cc {
10112 + compatible = "fsl,fman-cc";
10113 + };
10114 +
10115 + muram@0 {
10116 + compatible = "fsl,fman-muram";
10117 + reg = <0x0 0x60000>;
10118 + };
10119 +
10120 + bmi@80000 {
10121 + compatible = "fsl,fman-bmi";
10122 + reg = <0x80000 0x400>;
10123 + };
10124 +
10125 + qmi@80400 {
10126 + compatible = "fsl,fman-qmi";
10127 + reg = <0x80400 0x400>;
10128 + };
10129 +
10130 + fman0_oh_0x2: port@82000 {
10131 + cell-index = <0x2>;
10132 + compatible = "fsl,fman-v3-port-oh";
10133 + reg = <0x82000 0x1000>;
10134 + fsl,qman-channel-id = <0x809>;
10135 + };
10136 +
10137 + fman0_oh_0x3: port@83000 {
10138 + cell-index = <0x3>;
10139 + compatible = "fsl,fman-v3-port-oh";
10140 + reg = <0x83000 0x1000>;
10141 + fsl,qman-channel-id = <0x80a>;
10142 + };
10143 +
10144 + fman0_oh_0x4: port@84000 {
10145 + cell-index = <0x4>;
10146 + compatible = "fsl,fman-v3-port-oh";
10147 + reg = <0x84000 0x1000>;
10148 + fsl,qman-channel-id = <0x80b>;
10149 + };
10150 +
10151 + fman0_oh_0x5: port@85000 {
10152 + cell-index = <0x5>;
10153 + compatible = "fsl,fman-v3-port-oh";
10154 + reg = <0x85000 0x1000>;
10155 + fsl,qman-channel-id = <0x80c>;
10156 + };
10157 +
10158 + fman0_oh_0x6: port@86000 {
10159 + cell-index = <0x6>;
10160 + compatible = "fsl,fman-v3-port-oh";
10161 + reg = <0x86000 0x1000>;
10162 + fsl,qman-channel-id = <0x80d>;
10163 + };
10164 +
10165 + fman0_oh_0x7: port@87000 {
10166 + cell-index = <0x7>;
10167 + compatible = "fsl,fman-v3-port-oh";
10168 + reg = <0x87000 0x1000>;
10169 + fsl,qman-channel-id = <0x80e>;
10170 + };
10171 +
10172 + policer@c0000 {
10173 + compatible = "fsl,fman-policer";
10174 + reg = <0xc0000 0x1000>;
10175 + };
10176 +
10177 + keygen@c1000 {
10178 + compatible = "fsl,fman-keygen";
10179 + reg = <0xc1000 0x1000>;
10180 + };
10181 +
10182 + dma@c2000 {
10183 + compatible = "fsl,fman-dma";
10184 + reg = <0xc2000 0x1000>;
10185 + };
10186 +
10187 + fpm@c3000 {
10188 + compatible = "fsl,fman-fpm";
10189 + reg = <0xc3000 0x1000>;
10190 + };
10191 +
10192 + parser@c7000 {
10193 + compatible = "fsl,fman-parser";
10194 + reg = <0xc7000 0x1000>;
10195 + };
10196 +
10197 + vsps@dc000 {
10198 + compatible = "fsl,fman-vsps";
10199 + reg = <0xdc000 0x1000>;
10200 + };
10201 +
10202 + mdio0: mdio@fc000 {
10203 + #address-cells = <1>;
10204 + #size-cells = <0>;
10205 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
10206 + reg = <0xfc000 0x1000>;
10207 + };
10208 +
10209 + xmdio0: mdio@fd000 {
10210 + #address-cells = <1>;
10211 + #size-cells = <0>;
10212 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
10213 + reg = <0xfd000 0x1000>;
10214 + };
10215 +
10216 + ptp_timer0: ptp-timer@fe000 {
10217 + compatible = "fsl,fman-ptp-timer", "fsl,fman-rtc";
10218 + reg = <0xfe000 0x1000>;
10219 + };
10220 +};
10221 --- /dev/null
10222 +++ b/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
10223 @@ -0,0 +1,104 @@
10224 +/*
10225 + * QorIQ QMan Portals device tree
10226 + *
10227 + * Copyright 2011-2016 Freescale Semiconductor Inc.
10228 + *
10229 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
10230 + */
10231 +
10232 +&qportals {
10233 + #address-cells = <1>;
10234 + #size-cells = <1>;
10235 + compatible = "simple-bus";
10236 +
10237 + qportal0: qman-portal@0 {
10238 + compatible = "fsl,qman-portal";
10239 + reg = <0x0 0x4000 0x4000000 0x4000>;
10240 + interrupts = <0 172 0x4>;
10241 + cell-index = <0>;
10242 + };
10243 +
10244 + qportal1: qman-portal@10000 {
10245 + compatible = "fsl,qman-portal";
10246 + reg = <0x10000 0x4000 0x4010000 0x4000>;
10247 + interrupts = <0 174 0x4>;
10248 + cell-index = <1>;
10249 + };
10250 +
10251 + qportal2: qman-portal@20000 {
10252 + compatible = "fsl,qman-portal";
10253 + reg = <0x20000 0x4000 0x4020000 0x4000>;
10254 + interrupts = <0 176 0x4>;
10255 + cell-index = <2>;
10256 + };
10257 +
10258 + qportal3: qman-portal@30000 {
10259 + compatible = "fsl,qman-portal";
10260 + reg = <0x30000 0x4000 0x4030000 0x4000>;
10261 + interrupts = <0 178 0x4>;
10262 + cell-index = <3>;
10263 + };
10264 +
10265 + qportal4: qman-portal@40000 {
10266 + compatible = "fsl,qman-portal";
10267 + reg = <0x40000 0x4000 0x4040000 0x4000>;
10268 + interrupts = <0 180 0x4>;
10269 + cell-index = <4>;
10270 + };
10271 +
10272 + qportal5: qman-portal@50000 {
10273 + compatible = "fsl,qman-portal";
10274 + reg = <0x50000 0x4000 0x4050000 0x4000>;
10275 + interrupts = <0 182 0x4>;
10276 + cell-index = <5>;
10277 + };
10278 +
10279 + qportal6: qman-portal@60000 {
10280 + compatible = "fsl,qman-portal";
10281 + reg = <0x60000 0x4000 0x4060000 0x4000>;
10282 + interrupts = <0 184 0x4>;
10283 + cell-index = <6>;
10284 + };
10285 +
10286 + qportal7: qman-portal@70000 {
10287 + compatible = "fsl,qman-portal";
10288 + reg = <0x70000 0x4000 0x4070000 0x4000>;
10289 + interrupts = <0 186 0x4>;
10290 + cell-index = <7>;
10291 + };
10292 +
10293 + qportal8: qman-portal@80000 {
10294 + compatible = "fsl,qman-portal";
10295 + reg = <0x80000 0x4000 0x4080000 0x4000>;
10296 + interrupts = <0 188 0x4>;
10297 + cell-index = <8>;
10298 + };
10299 +
10300 + qman-fqids@0 {
10301 + compatible = "fsl,fqid-range";
10302 + fsl,fqid-range = <256 256>;
10303 + };
10304 +
10305 + qman-fqids@1 {
10306 + compatible = "fsl,fqid-range";
10307 + fsl,fqid-range = <32768 32768>;
10308 + };
10309 +
10310 + qman-pools@0 {
10311 + compatible = "fsl,pool-channel-range";
10312 + fsl,pool-channel-range = <0x401 0xf>;
10313 + };
10314 +
10315 + qman-cgrids@0 {
10316 + compatible = "fsl,cgrid-range";
10317 + fsl,cgrid-range = <0 256>;
10318 + };
10319 +
10320 + qman-ceetm@0 {
10321 + compatible = "fsl,qman-ceetm";
10322 + fsl,ceetm-lfqid-range = <0xf00000 0x1000>;
10323 + fsl,ceetm-sp-range = <0 12>;
10324 + fsl,ceetm-lni-range = <0 8>;
10325 + fsl,ceetm-channel-range = <0 32>;
10326 + };
10327 +};
10328 --- a/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
10329 +++ b/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
10330 @@ -38,51 +38,61 @@
10331 compatible = "simple-bus";
10332
10333 bman-portal@0 {
10334 + cell-index = <0>;
10335 compatible = "fsl,bman-portal";
10336 reg = <0x0 0x4000>, <0x100000 0x1000>;
10337 interrupts = <105 2 0 0>;
10338 };
10339 bman-portal@4000 {
10340 + cell-index = <1>;
10341 compatible = "fsl,bman-portal";
10342 reg = <0x4000 0x4000>, <0x101000 0x1000>;
10343 interrupts = <107 2 0 0>;
10344 };
10345 bman-portal@8000 {
10346 + cell-index = <2>;
10347 compatible = "fsl,bman-portal";
10348 reg = <0x8000 0x4000>, <0x102000 0x1000>;
10349 interrupts = <109 2 0 0>;
10350 };
10351 bman-portal@c000 {
10352 + cell-index = <3>;
10353 compatible = "fsl,bman-portal";
10354 reg = <0xc000 0x4000>, <0x103000 0x1000>;
10355 interrupts = <111 2 0 0>;
10356 };
10357 bman-portal@10000 {
10358 + cell-index = <4>;
10359 compatible = "fsl,bman-portal";
10360 reg = <0x10000 0x4000>, <0x104000 0x1000>;
10361 interrupts = <113 2 0 0>;
10362 };
10363 bman-portal@14000 {
10364 + cell-index = <5>;
10365 compatible = "fsl,bman-portal";
10366 reg = <0x14000 0x4000>, <0x105000 0x1000>;
10367 interrupts = <115 2 0 0>;
10368 };
10369 bman-portal@18000 {
10370 + cell-index = <6>;
10371 compatible = "fsl,bman-portal";
10372 reg = <0x18000 0x4000>, <0x106000 0x1000>;
10373 interrupts = <117 2 0 0>;
10374 };
10375 bman-portal@1c000 {
10376 + cell-index = <7>;
10377 compatible = "fsl,bman-portal";
10378 reg = <0x1c000 0x4000>, <0x107000 0x1000>;
10379 interrupts = <119 2 0 0>;
10380 };
10381 bman-portal@20000 {
10382 + cell-index = <8>;
10383 compatible = "fsl,bman-portal";
10384 reg = <0x20000 0x4000>, <0x108000 0x1000>;
10385 interrupts = <121 2 0 0>;
10386 };
10387 bman-portal@24000 {
10388 + cell-index = <9>;
10389 compatible = "fsl,bman-portal";
10390 reg = <0x24000 0x4000>, <0x109000 0x1000>;
10391 interrupts = <123 2 0 0>;
10392 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
10393 +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
10394 @@ -35,14 +35,14 @@
10395 fman@400000 {
10396 fman0_rx_0x10: port@90000 {
10397 cell-index = <0x10>;
10398 - compatible = "fsl,fman-v3-port-rx";
10399 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
10400 reg = <0x90000 0x1000>;
10401 fsl,fman-10g-port;
10402 };
10403
10404 fman0_tx_0x30: port@b0000 {
10405 cell-index = <0x30>;
10406 - compatible = "fsl,fman-v3-port-tx";
10407 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
10408 reg = <0xb0000 0x1000>;
10409 fsl,fman-10g-port;
10410 };
10411 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
10412 +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
10413 @@ -35,14 +35,14 @@
10414 fman@400000 {
10415 fman0_rx_0x11: port@91000 {
10416 cell-index = <0x11>;
10417 - compatible = "fsl,fman-v3-port-rx";
10418 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
10419 reg = <0x91000 0x1000>;
10420 fsl,fman-10g-port;
10421 };
10422
10423 fman0_tx_0x31: port@b1000 {
10424 cell-index = <0x31>;
10425 - compatible = "fsl,fman-v3-port-tx";
10426 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
10427 reg = <0xb1000 0x1000>;
10428 fsl,fman-10g-port;
10429 };
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