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[openwrt/staging/wigyori.git] / target / linux / layerscape / patches-4.9 / 702-pci-support-layerscape.patch
1 From 9e6e0a53b29190dbd86a39304b59c3028f5b36c2 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 11:04:10 +0800
4 Subject: [PATCH] pci: support layerscape
5
6 This is a integrated patch for layerscape pcie support.
7
8 Signed-off-by: Po Liu <po.liu@nxp.com>
9 Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
10 Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
11 Signed-off-by: hongbo.wang <hongbo.wang@nxp.com>
12 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
13 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
14 Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
15 Signed-off-by: Christoph Hellwig <hch@lst.de>
16 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
17 ---
18 drivers/irqchip/irq-ls-scfg-msi.c | 257 +++++++--
19 drivers/pci/host/Makefile | 2 +-
20 drivers/pci/host/pci-layerscape-ep-debugfs.c | 758 +++++++++++++++++++++++++++
21 drivers/pci/host/pci-layerscape-ep.c | 309 +++++++++++
22 drivers/pci/host/pci-layerscape-ep.h | 115 ++++
23 drivers/pci/host/pci-layerscape.c | 38 +-
24 drivers/pci/host/pcie-designware.c | 6 +
25 drivers/pci/host/pcie-designware.h | 1 +
26 drivers/pci/pcie/portdrv_core.c | 181 +++----
27 include/linux/pci.h | 1 +
28 10 files changed, 1520 insertions(+), 148 deletions(-)
29 create mode 100644 drivers/pci/host/pci-layerscape-ep-debugfs.c
30 create mode 100644 drivers/pci/host/pci-layerscape-ep.c
31 create mode 100644 drivers/pci/host/pci-layerscape-ep.h
32
33 diff --git a/drivers/irqchip/irq-ls-scfg-msi.c b/drivers/irqchip/irq-ls-scfg-msi.c
34 index 02cca74c..57e3d900 100644
35 --- a/drivers/irqchip/irq-ls-scfg-msi.c
36 +++ b/drivers/irqchip/irq-ls-scfg-msi.c
37 @@ -17,13 +17,32 @@
38 #include <linux/irq.h>
39 #include <linux/irqchip/chained_irq.h>
40 #include <linux/irqdomain.h>
41 +#include <linux/of_irq.h>
42 #include <linux/of_pci.h>
43 #include <linux/of_platform.h>
44 #include <linux/spinlock.h>
45
46 -#define MSI_MAX_IRQS 32
47 -#define MSI_IBS_SHIFT 3
48 -#define MSIR 4
49 +#define MSI_IRQS_PER_MSIR 32
50 +#define MSI_MSIR_OFFSET 4
51 +
52 +#define MSI_LS1043V1_1_IRQS_PER_MSIR 8
53 +#define MSI_LS1043V1_1_MSIR_OFFSET 0x10
54 +
55 +struct ls_scfg_msi_cfg {
56 + u32 ibs_shift; /* Shift of interrupt bit select */
57 + u32 msir_irqs; /* The irq number per MSIR */
58 + u32 msir_base; /* The base address of MSIR */
59 +};
60 +
61 +struct ls_scfg_msir {
62 + struct ls_scfg_msi *msi_data;
63 + unsigned int index;
64 + unsigned int gic_irq;
65 + unsigned int bit_start;
66 + unsigned int bit_end;
67 + unsigned int srs; /* Shared interrupt register select */
68 + void __iomem *reg;
69 +};
70
71 struct ls_scfg_msi {
72 spinlock_t lock;
73 @@ -32,8 +51,11 @@ struct ls_scfg_msi {
74 struct irq_domain *msi_domain;
75 void __iomem *regs;
76 phys_addr_t msiir_addr;
77 - int irq;
78 - DECLARE_BITMAP(used, MSI_MAX_IRQS);
79 + struct ls_scfg_msi_cfg *cfg;
80 + u32 msir_num;
81 + struct ls_scfg_msir *msir;
82 + u32 irqs_num;
83 + unsigned long *used;
84 };
85
86 static struct irq_chip ls_scfg_msi_irq_chip = {
87 @@ -49,19 +71,56 @@ static struct msi_domain_info ls_scfg_msi_domain_info = {
88 .chip = &ls_scfg_msi_irq_chip,
89 };
90
91 +static int msi_affinity_flag = 1;
92 +
93 +static int __init early_parse_ls_scfg_msi(char *p)
94 +{
95 + if (p && strncmp(p, "no-affinity", 11) == 0)
96 + msi_affinity_flag = 0;
97 + else
98 + msi_affinity_flag = 1;
99 +
100 + return 0;
101 +}
102 +early_param("lsmsi", early_parse_ls_scfg_msi);
103 +
104 static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
105 {
106 struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data);
107
108 msg->address_hi = upper_32_bits(msi_data->msiir_addr);
109 msg->address_lo = lower_32_bits(msi_data->msiir_addr);
110 - msg->data = data->hwirq << MSI_IBS_SHIFT;
111 + msg->data = data->hwirq;
112 +
113 + if (msi_affinity_flag)
114 + msg->data |= cpumask_first(data->common->affinity);
115 }
116
117 static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
118 const struct cpumask *mask, bool force)
119 {
120 - return -EINVAL;
121 + struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(irq_data);
122 + u32 cpu;
123 +
124 + if (!msi_affinity_flag)
125 + return -EINVAL;
126 +
127 + if (!force)
128 + cpu = cpumask_any_and(mask, cpu_online_mask);
129 + else
130 + cpu = cpumask_first(mask);
131 +
132 + if (cpu >= msi_data->msir_num)
133 + return -EINVAL;
134 +
135 + if (msi_data->msir[cpu].gic_irq <= 0) {
136 + pr_warn("cannot bind the irq to cpu%d\n", cpu);
137 + return -EINVAL;
138 + }
139 +
140 + cpumask_copy(irq_data->common->affinity, mask);
141 +
142 + return IRQ_SET_MASK_OK;
143 }
144
145 static struct irq_chip ls_scfg_msi_parent_chip = {
146 @@ -81,8 +140,8 @@ static int ls_scfg_msi_domain_irq_alloc(struct irq_domain *domain,
147 WARN_ON(nr_irqs != 1);
148
149 spin_lock(&msi_data->lock);
150 - pos = find_first_zero_bit(msi_data->used, MSI_MAX_IRQS);
151 - if (pos < MSI_MAX_IRQS)
152 + pos = find_first_zero_bit(msi_data->used, msi_data->irqs_num);
153 + if (pos < msi_data->irqs_num)
154 __set_bit(pos, msi_data->used);
155 else
156 err = -ENOSPC;
157 @@ -106,7 +165,7 @@ static void ls_scfg_msi_domain_irq_free(struct irq_domain *domain,
158 int pos;
159
160 pos = d->hwirq;
161 - if (pos < 0 || pos >= MSI_MAX_IRQS) {
162 + if (pos < 0 || pos >= msi_data->irqs_num) {
163 pr_err("failed to teardown msi. Invalid hwirq %d\n", pos);
164 return;
165 }
166 @@ -123,15 +182,22 @@ static const struct irq_domain_ops ls_scfg_msi_domain_ops = {
167
168 static void ls_scfg_msi_irq_handler(struct irq_desc *desc)
169 {
170 - struct ls_scfg_msi *msi_data = irq_desc_get_handler_data(desc);
171 + struct ls_scfg_msir *msir = irq_desc_get_handler_data(desc);
172 + struct ls_scfg_msi *msi_data = msir->msi_data;
173 unsigned long val;
174 - int pos, virq;
175 + int pos, size, virq, hwirq;
176
177 chained_irq_enter(irq_desc_get_chip(desc), desc);
178
179 - val = ioread32be(msi_data->regs + MSIR);
180 - for_each_set_bit(pos, &val, MSI_MAX_IRQS) {
181 - virq = irq_find_mapping(msi_data->parent, (31 - pos));
182 + val = ioread32be(msir->reg);
183 +
184 + pos = msir->bit_start;
185 + size = msir->bit_end + 1;
186 +
187 + for_each_set_bit_from(pos, &val, size) {
188 + hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) |
189 + msir->srs;
190 + virq = irq_find_mapping(msi_data->parent, hwirq);
191 if (virq)
192 generic_handle_irq(virq);
193 }
194 @@ -143,7 +209,7 @@ static int ls_scfg_msi_domains_init(struct ls_scfg_msi *msi_data)
195 {
196 /* Initialize MSI domain parent */
197 msi_data->parent = irq_domain_add_linear(NULL,
198 - MSI_MAX_IRQS,
199 + msi_data->irqs_num,
200 &ls_scfg_msi_domain_ops,
201 msi_data);
202 if (!msi_data->parent) {
203 @@ -164,16 +230,118 @@ static int ls_scfg_msi_domains_init(struct ls_scfg_msi *msi_data)
204 return 0;
205 }
206
207 +static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int index)
208 +{
209 + struct ls_scfg_msir *msir;
210 + int virq, i, hwirq;
211 +
212 + virq = platform_get_irq(msi_data->pdev, index);
213 + if (virq <= 0)
214 + return -ENODEV;
215 +
216 + msir = &msi_data->msir[index];
217 + msir->index = index;
218 + msir->msi_data = msi_data;
219 + msir->gic_irq = virq;
220 + msir->reg = msi_data->regs + msi_data->cfg->msir_base + 4 * index;
221 +
222 + if (msi_data->cfg->msir_irqs == MSI_LS1043V1_1_IRQS_PER_MSIR) {
223 + msir->bit_start = 32 - ((msir->index + 1) *
224 + MSI_LS1043V1_1_IRQS_PER_MSIR);
225 + msir->bit_end = msir->bit_start +
226 + MSI_LS1043V1_1_IRQS_PER_MSIR - 1;
227 + } else {
228 + msir->bit_start = 0;
229 + msir->bit_end = msi_data->cfg->msir_irqs - 1;
230 + }
231 +
232 + irq_set_chained_handler_and_data(msir->gic_irq,
233 + ls_scfg_msi_irq_handler,
234 + msir);
235 +
236 + if (msi_affinity_flag) {
237 + /* Associate MSIR interrupt to the cpu */
238 + irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
239 + msir->srs = 0; /* This value is determined by the CPU */
240 + } else
241 + msir->srs = index;
242 +
243 + /* Release the hwirqs corresponding to this MSIR */
244 + if (!msi_affinity_flag || msir->index == 0) {
245 + for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
246 + hwirq = i << msi_data->cfg->ibs_shift | msir->index;
247 + bitmap_clear(msi_data->used, hwirq, 1);
248 + }
249 + }
250 +
251 + return 0;
252 +}
253 +
254 +static int ls_scfg_msi_teardown_hwirq(struct ls_scfg_msir *msir)
255 +{
256 + struct ls_scfg_msi *msi_data = msir->msi_data;
257 + int i, hwirq;
258 +
259 + if (msir->gic_irq > 0)
260 + irq_set_chained_handler_and_data(msir->gic_irq, NULL, NULL);
261 +
262 + for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
263 + hwirq = i << msi_data->cfg->ibs_shift | msir->index;
264 + bitmap_set(msi_data->used, hwirq, 1);
265 + }
266 +
267 + return 0;
268 +}
269 +
270 +static struct ls_scfg_msi_cfg ls1021_msi_cfg = {
271 + .ibs_shift = 3,
272 + .msir_irqs = MSI_IRQS_PER_MSIR,
273 + .msir_base = MSI_MSIR_OFFSET,
274 +};
275 +
276 +static struct ls_scfg_msi_cfg ls1046_msi_cfg = {
277 + .ibs_shift = 2,
278 + .msir_irqs = MSI_IRQS_PER_MSIR,
279 + .msir_base = MSI_MSIR_OFFSET,
280 +};
281 +
282 +static struct ls_scfg_msi_cfg ls1043_v1_1_msi_cfg = {
283 + .ibs_shift = 2,
284 + .msir_irqs = MSI_LS1043V1_1_IRQS_PER_MSIR,
285 + .msir_base = MSI_LS1043V1_1_MSIR_OFFSET,
286 +};
287 +
288 +static const struct of_device_id ls_scfg_msi_id[] = {
289 + /* The following two misspelled compatibles are obsolete */
290 + { .compatible = "fsl,1s1021a-msi", .data = &ls1021_msi_cfg},
291 + { .compatible = "fsl,1s1043a-msi", .data = &ls1021_msi_cfg},
292 +
293 + { .compatible = "fsl,ls1012a-msi", .data = &ls1021_msi_cfg },
294 + { .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg },
295 + { .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg },
296 + { .compatible = "fsl,ls1043a-v1.1-msi", .data = &ls1043_v1_1_msi_cfg },
297 + { .compatible = "fsl,ls1046a-msi", .data = &ls1046_msi_cfg },
298 + {},
299 +};
300 +MODULE_DEVICE_TABLE(of, ls_scfg_msi_id);
301 +
302 static int ls_scfg_msi_probe(struct platform_device *pdev)
303 {
304 + const struct of_device_id *match;
305 struct ls_scfg_msi *msi_data;
306 struct resource *res;
307 - int ret;
308 + int i, ret;
309 +
310 + match = of_match_device(ls_scfg_msi_id, &pdev->dev);
311 + if (!match)
312 + return -ENODEV;
313
314 msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL);
315 if (!msi_data)
316 return -ENOMEM;
317
318 + msi_data->cfg = (struct ls_scfg_msi_cfg *) match->data;
319 +
320 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
321 msi_data->regs = devm_ioremap_resource(&pdev->dev, res);
322 if (IS_ERR(msi_data->regs)) {
323 @@ -182,23 +350,48 @@ static int ls_scfg_msi_probe(struct platform_device *pdev)
324 }
325 msi_data->msiir_addr = res->start;
326
327 - msi_data->irq = platform_get_irq(pdev, 0);
328 - if (msi_data->irq <= 0) {
329 - dev_err(&pdev->dev, "failed to get MSI irq\n");
330 - return -ENODEV;
331 - }
332 -
333 msi_data->pdev = pdev;
334 spin_lock_init(&msi_data->lock);
335
336 + msi_data->irqs_num = MSI_IRQS_PER_MSIR *
337 + (1 << msi_data->cfg->ibs_shift);
338 + msi_data->used = devm_kcalloc(&pdev->dev,
339 + BITS_TO_LONGS(msi_data->irqs_num),
340 + sizeof(*msi_data->used),
341 + GFP_KERNEL);
342 + if (!msi_data->used)
343 + return -ENOMEM;
344 + /*
345 + * Reserve all the hwirqs
346 + * The available hwirqs will be released in ls1_msi_setup_hwirq()
347 + */
348 + bitmap_set(msi_data->used, 0, msi_data->irqs_num);
349 +
350 + msi_data->msir_num = of_irq_count(pdev->dev.of_node);
351 +
352 + if (msi_affinity_flag) {
353 + u32 cpu_num;
354 +
355 + cpu_num = num_possible_cpus();
356 + if (msi_data->msir_num >= cpu_num)
357 + msi_data->msir_num = cpu_num;
358 + else
359 + msi_affinity_flag = 0;
360 + }
361 +
362 + msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num,
363 + sizeof(*msi_data->msir),
364 + GFP_KERNEL);
365 + if (!msi_data->msir)
366 + return -ENOMEM;
367 +
368 + for (i = 0; i < msi_data->msir_num; i++)
369 + ls_scfg_msi_setup_hwirq(msi_data, i);
370 +
371 ret = ls_scfg_msi_domains_init(msi_data);
372 if (ret)
373 return ret;
374
375 - irq_set_chained_handler_and_data(msi_data->irq,
376 - ls_scfg_msi_irq_handler,
377 - msi_data);
378 -
379 platform_set_drvdata(pdev, msi_data);
380
381 return 0;
382 @@ -207,8 +400,10 @@ static int ls_scfg_msi_probe(struct platform_device *pdev)
383 static int ls_scfg_msi_remove(struct platform_device *pdev)
384 {
385 struct ls_scfg_msi *msi_data = platform_get_drvdata(pdev);
386 + int i;
387
388 - irq_set_chained_handler_and_data(msi_data->irq, NULL, NULL);
389 + for (i = 0; i < msi_data->msir_num; i++)
390 + ls_scfg_msi_teardown_hwirq(&msi_data->msir[i]);
391
392 irq_domain_remove(msi_data->msi_domain);
393 irq_domain_remove(msi_data->parent);
394 @@ -218,12 +413,6 @@ static int ls_scfg_msi_remove(struct platform_device *pdev)
395 return 0;
396 }
397
398 -static const struct of_device_id ls_scfg_msi_id[] = {
399 - { .compatible = "fsl,1s1021a-msi", },
400 - { .compatible = "fsl,1s1043a-msi", },
401 - {},
402 -};
403 -
404 static struct platform_driver ls_scfg_msi_driver = {
405 .driver = {
406 .name = "ls-scfg-msi",
407 diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
408 index 084cb498..88e87704 100644
409 --- a/drivers/pci/host/Makefile
410 +++ b/drivers/pci/host/Makefile
411 @@ -17,7 +17,7 @@ obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
412 obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
413 obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
414 obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o
415 -obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
416 +obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o pci-layerscape-ep-debugfs.o
417 obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
418 obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
419 obj-$(CONFIG_PCIE_IPROC_MSI) += pcie-iproc-msi.o
420 diff --git a/drivers/pci/host/pci-layerscape-ep-debugfs.c b/drivers/pci/host/pci-layerscape-ep-debugfs.c
421 new file mode 100644
422 index 00000000..5f4870ba
423 --- /dev/null
424 +++ b/drivers/pci/host/pci-layerscape-ep-debugfs.c
425 @@ -0,0 +1,758 @@
426 +/*
427 + * PCIe Endpoint driver for Freescale Layerscape SoCs
428 + *
429 + * Copyright (C) 2015 Freescale Semiconductor.
430 + *
431 + * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
432 + *
433 + * This program is free software; you can redistribute it and/or modify
434 + * it under the terms of the GNU General Public License version 2 as
435 + * published by the Free Software Foundation.
436 + */
437 +
438 +#include <linux/kernel.h>
439 +#include <linux/module.h>
440 +#include <linux/debugfs.h>
441 +#include <linux/time.h>
442 +#include <linux/uaccess.h>
443 +#include <linux/kthread.h>
444 +#include <linux/slab.h>
445 +#include <linux/dmaengine.h>
446 +#include <linux/dma-mapping.h>
447 +#include <linux/freezer.h>
448 +
449 +#include <linux/completion.h>
450 +
451 +#include "pci-layerscape-ep.h"
452 +
453 +#define PCIE_ATU_INDEX3 (0x3 << 0)
454 +#define PCIE_ATU_INDEX2 (0x2 << 0)
455 +#define PCIE_ATU_INDEX1 (0x1 << 0)
456 +#define PCIE_ATU_INDEX0 (0x0 << 0)
457 +
458 +#define PCIE_BAR0_SIZE (4 * 1024) /* 4K */
459 +#define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */
460 +#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
461 +#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
462 +#define PCIE_MSI_OB_SIZE (4 * 1024) /* 4K */
463 +
464 +#define PCIE_MSI_MSG_ADDR_OFF 0x54
465 +#define PCIE_MSI_MSG_DATA_OFF 0x5c
466 +
467 +enum test_type {
468 + TEST_TYPE_DMA,
469 + TEST_TYPE_MEMCPY
470 +};
471 +
472 +enum test_dirt {
473 + TEST_DIRT_READ,
474 + TEST_DIRT_WRITE
475 +};
476 +
477 +enum test_status {
478 + TEST_IDLE,
479 + TEST_BUSY
480 +};
481 +
482 +struct ls_ep_test {
483 + struct ls_ep_dev *ep;
484 + void __iomem *cfg;
485 + void __iomem *buf;
486 + void __iomem *out;
487 + void __iomem *msi;
488 + dma_addr_t cfg_addr;
489 + dma_addr_t buf_addr;
490 + dma_addr_t out_addr;
491 + dma_addr_t bus_addr;
492 + dma_addr_t msi_addr;
493 + u64 msi_msg_addr;
494 + u16 msi_msg_data;
495 + struct task_struct *thread;
496 + spinlock_t lock;
497 + struct completion done;
498 + u32 len;
499 + int loop;
500 + char data;
501 + enum test_dirt dirt;
502 + enum test_type type;
503 + enum test_status status;
504 + u64 result; /* Mbps */
505 + char cmd[256];
506 +};
507 +
508 +static int ls_pcie_ep_trigger_msi(struct ls_ep_test *test)
509 +{
510 + if (!test->msi)
511 + return -EINVAL;
512 +
513 + iowrite32(test->msi_msg_data, test->msi);
514 +
515 + return 0;
516 +}
517 +
518 +static int ls_pcie_ep_test_try_run(struct ls_ep_test *test)
519 +{
520 + int ret;
521 +
522 + spin_lock(&test->lock);
523 + if (test->status == TEST_IDLE) {
524 + test->status = TEST_BUSY;
525 + ret = 0;
526 + } else
527 + ret = -EBUSY;
528 + spin_unlock(&test->lock);
529 +
530 + return ret;
531 +}
532 +
533 +static void ls_pcie_ep_test_done(struct ls_ep_test *test)
534 +{
535 + spin_lock(&test->lock);
536 + test->status = TEST_IDLE;
537 + spin_unlock(&test->lock);
538 +}
539 +
540 +static void ls_pcie_ep_test_dma_cb(void *arg)
541 +{
542 + struct ls_ep_test *test = arg;
543 +
544 + complete(&test->done);
545 +}
546 +
547 +static int ls_pcie_ep_test_dma(struct ls_ep_test *test)
548 +{
549 + dma_cap_mask_t mask;
550 + struct dma_chan *chan;
551 + struct dma_device *dma_dev;
552 + dma_addr_t src, dst;
553 + enum dma_data_direction direction;
554 + enum dma_ctrl_flags dma_flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
555 + struct timespec start, end, period;
556 + int i = 0;
557 +
558 + dma_cap_zero(mask);
559 + dma_cap_set(DMA_MEMCPY, mask);
560 +
561 + chan = dma_request_channel(mask, NULL, test);
562 + if (!chan) {
563 + pr_err("failed to request dma channel\n");
564 + return -EINVAL;
565 + }
566 +
567 + memset(test->buf, test->data, test->len);
568 +
569 + if (test->dirt == TEST_DIRT_WRITE) {
570 + src = test->buf_addr;
571 + dst = test->out_addr;
572 + direction = DMA_TO_DEVICE;
573 + } else {
574 + src = test->out_addr;
575 + dst = test->buf_addr;
576 + direction = DMA_FROM_DEVICE;
577 + }
578 +
579 + dma_dev = chan->device;
580 + dma_flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
581 +
582 + dma_sync_single_for_device(&test->ep->dev, test->buf_addr,
583 + test->len, direction);
584 +
585 + set_freezable();
586 +
587 + getrawmonotonic(&start);
588 + while (!kthread_should_stop() && (i < test->loop)) {
589 + struct dma_async_tx_descriptor *dma_desc;
590 + dma_cookie_t dma_cookie = {0};
591 + unsigned long tmo;
592 + int status;
593 +
594 + init_completion(&test->done);
595 +
596 + dma_desc = dma_dev->device_prep_dma_memcpy(chan,
597 + dst, src,
598 + test->len,
599 + dma_flags);
600 + if (!dma_desc) {
601 + pr_err("DMA desc constr failed...\n");
602 + goto _err;
603 + }
604 +
605 + dma_desc->callback = ls_pcie_ep_test_dma_cb;
606 + dma_desc->callback_param = test;
607 + dma_cookie = dmaengine_submit(dma_desc);
608 +
609 + if (dma_submit_error(dma_cookie)) {
610 + pr_err("DMA submit error....\n");
611 + goto _err;
612 + }
613 +
614 + /* Trigger the transaction */
615 + dma_async_issue_pending(chan);
616 +
617 + tmo = wait_for_completion_timeout(&test->done,
618 + msecs_to_jiffies(5 * test->len));
619 + if (tmo == 0) {
620 + pr_err("Self-test copy timed out, disabling\n");
621 + goto _err;
622 + }
623 +
624 + status = dma_async_is_tx_complete(chan, dma_cookie,
625 + NULL, NULL);
626 + if (status != DMA_COMPLETE) {
627 + pr_err("got completion callback, but status is %s\n",
628 + status == DMA_ERROR ? "error" : "in progress");
629 + goto _err;
630 + }
631 +
632 + i++;
633 + }
634 +
635 + getrawmonotonic(&end);
636 + period = timespec_sub(end, start);
637 + test->result = test->len * 8ULL * i * 1000;
638 + do_div(test->result, period.tv_sec * 1000 * 1000 * 1000 + period.tv_nsec);
639 + dma_release_channel(chan);
640 +
641 + return 0;
642 +
643 +_err:
644 + dma_release_channel(chan);
645 + test->result = 0;
646 + return -EINVAL;
647 +}
648 +
649 +static int ls_pcie_ep_test_cpy(struct ls_ep_test *test)
650 +{
651 + void *dst, *src;
652 + struct timespec start, end, period;
653 + int i = 0;
654 +
655 + memset(test->buf, test->data, test->len);
656 +
657 + if (test->dirt == TEST_DIRT_WRITE) {
658 + dst = test->out;
659 + src = test->buf;
660 + } else {
661 + dst = test->buf;
662 + src = test->out;
663 + }
664 +
665 + getrawmonotonic(&start);
666 + while (!kthread_should_stop() && i < test->loop) {
667 + memcpy(dst, src, test->len);
668 + i++;
669 + }
670 + getrawmonotonic(&end);
671 +
672 + period = timespec_sub(end, start);
673 + test->result = test->len * 8ULL * i * 1000;
674 + do_div(test->result, period.tv_sec * 1000 * 1000 * 1000 + period.tv_nsec);
675 +
676 + return 0;
677 +}
678 +
679 +int ls_pcie_ep_test_thread(void *arg)
680 +{
681 + int ret;
682 +
683 + struct ls_ep_test *test = arg;
684 +
685 + if (test->type == TEST_TYPE_DMA)
686 + ret = ls_pcie_ep_test_dma(test);
687 + else
688 + ret = ls_pcie_ep_test_cpy(test);
689 +
690 + if (ret) {
691 + pr_err("\n%s \ttest failed\n",
692 + test->cmd);
693 + test->result = 0;
694 + } else
695 + pr_err("\n%s \tthroughput:%lluMbps\n",
696 + test->cmd, test->result);
697 +
698 + ls_pcie_ep_test_done(test);
699 +
700 + ls_pcie_ep_trigger_msi(test);
701 +
702 + do_exit(0);
703 +}
704 +
705 +static int ls_pcie_ep_free_test(struct ls_ep_dev *ep)
706 +{
707 + struct ls_ep_test *test = ep->driver_data;
708 +
709 + if (!test)
710 + return 0;
711 +
712 + if (test->status == TEST_BUSY) {
713 + kthread_stop(test->thread);
714 + dev_info(&ep->dev,
715 + "test is running please wait and run again\n");
716 + return -EBUSY;
717 + }
718 +
719 + if (test->buf)
720 + free_pages((unsigned long)test->buf,
721 + get_order(PCIE_BAR4_SIZE));
722 +
723 + if (test->cfg)
724 + free_pages((unsigned long)test->cfg,
725 + get_order(PCIE_BAR2_SIZE));
726 +
727 + if (test->out)
728 + iounmap(test->out);
729 +
730 + kfree(test);
731 + ep->driver_data = NULL;
732 +
733 + return 0;
734 +}
735 +
736 +static int ls_pcie_ep_init_test(struct ls_ep_dev *ep, u64 bus_addr)
737 +{
738 + struct ls_pcie *pcie = ep->pcie;
739 + struct ls_ep_test *test = ep->driver_data;
740 + int err;
741 +
742 + if (test) {
743 + dev_info(&ep->dev,
744 + "Please use 'free' to remove the exiting test\n");
745 + return -EBUSY;
746 + }
747 +
748 + test = kzalloc(sizeof(*test), GFP_KERNEL);
749 + if (!test)
750 + return -ENOMEM;
751 + ep->driver_data = test;
752 + test->ep = ep;
753 + spin_lock_init(&test->lock);
754 + test->status = TEST_IDLE;
755 +
756 + test->buf = dma_alloc_coherent(pcie->dev, get_order(PCIE_BAR4_SIZE),
757 + &test->buf_addr,
758 + GFP_KERNEL);
759 + if (!test->buf) {
760 + dev_info(&ep->dev, "failed to get mem for bar4\n");
761 + err = -ENOMEM;
762 + goto _err;
763 + }
764 +
765 + test->cfg = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
766 + get_order(PCIE_BAR2_SIZE));
767 + if (!test->cfg) {
768 + dev_info(&ep->dev, "failed to get mem for bar4\n");
769 + err = -ENOMEM;
770 + goto _err;
771 + }
772 + test->cfg_addr = virt_to_phys(test->cfg);
773 +
774 + test->out_addr = pcie->out_base;
775 + test->out = ioremap(test->out_addr, PCIE_BAR4_SIZE);
776 + if (!test->out) {
777 + dev_info(&ep->dev, "failed to map out\n");
778 + err = -ENOMEM;
779 + goto _err;
780 + }
781 +
782 + test->bus_addr = bus_addr;
783 +
784 + test->msi_addr = test->out_addr + PCIE_BAR4_SIZE;
785 + test->msi = ioremap(test->msi_addr, PCIE_MSI_OB_SIZE);
786 + if (!test->msi)
787 + dev_info(&ep->dev, "failed to map MSI outbound region\n");
788 +
789 + test->msi_msg_addr = ioread32(pcie->dbi + PCIE_MSI_MSG_ADDR_OFF) |
790 + (((u64)ioread32(pcie->dbi + PCIE_MSI_MSG_ADDR_OFF + 4)) << 32);
791 + test->msi_msg_data = ioread16(pcie->dbi + PCIE_MSI_MSG_DATA_OFF);
792 +
793 + ls_pcie_ep_dev_cfg_enable(ep);
794 +
795 + /* outbound iATU for memory */
796 + ls_pcie_iatu_outbound_set(pcie, 0, PCIE_ATU_TYPE_MEM,
797 + test->out_addr, bus_addr, PCIE_BAR4_SIZE);
798 + /* outbound iATU for MSI */
799 + ls_pcie_iatu_outbound_set(pcie, 1, PCIE_ATU_TYPE_MEM,
800 + test->msi_addr, test->msi_msg_addr,
801 + PCIE_MSI_OB_SIZE);
802 +
803 + /* ATU 0 : INBOUND : map BAR0 */
804 + ls_pcie_iatu_inbound_set(pcie, 0, 0, test->cfg_addr);
805 + /* ATU 2 : INBOUND : map BAR2 */
806 + ls_pcie_iatu_inbound_set(pcie, 2, 2, test->cfg_addr);
807 + /* ATU 3 : INBOUND : map BAR4 */
808 + ls_pcie_iatu_inbound_set(pcie, 3, 4, test->buf_addr);
809 +
810 + return 0;
811 +
812 +_err:
813 + ls_pcie_ep_free_test(ep);
814 + return err;
815 +}
816 +
817 +static int ls_pcie_ep_start_test(struct ls_ep_dev *ep, char *cmd)
818 +{
819 + struct ls_ep_test *test = ep->driver_data;
820 + enum test_type type;
821 + enum test_dirt dirt;
822 + u32 cnt, len, loop;
823 + unsigned int data;
824 + char dirt_str[2];
825 + int ret;
826 +
827 + if (strncmp(cmd, "dma", 3) == 0)
828 + type = TEST_TYPE_DMA;
829 + else
830 + type = TEST_TYPE_MEMCPY;
831 +
832 + cnt = sscanf(&cmd[4], "%1s %u %u %x", dirt_str, &len, &loop, &data);
833 + if (cnt != 4) {
834 + dev_info(&ep->dev, "format error %s", cmd);
835 + dev_info(&ep->dev, "dma/cpy <r/w> <packet_size> <loop> <data>\n");
836 + return -EINVAL;
837 + }
838 +
839 + if (strncmp(dirt_str, "r", 1) == 0)
840 + dirt = TEST_DIRT_READ;
841 + else
842 + dirt = TEST_DIRT_WRITE;
843 +
844 + if (len > PCIE_BAR4_SIZE) {
845 + dev_err(&ep->dev, "max len is %d", PCIE_BAR4_SIZE);
846 + return -EINVAL;
847 + }
848 +
849 + if (!test) {
850 + dev_err(&ep->dev, "Please first run init command\n");
851 + return -EINVAL;
852 + }
853 +
854 + if (ls_pcie_ep_test_try_run(test)) {
855 + dev_err(&ep->dev, "There is already a test running\n");
856 + return -EINVAL;
857 + }
858 +
859 + test->len = len;
860 + test->loop = loop;
861 + test->type = type;
862 + test->data = (char)data;
863 + test->dirt = dirt;
864 + strcpy(test->cmd, cmd);
865 + test->thread = kthread_run(ls_pcie_ep_test_thread, test,
866 + "pcie ep test");
867 + if (IS_ERR(test->thread)) {
868 + dev_err(&ep->dev, "fork failed for pcie ep test\n");
869 + ls_pcie_ep_test_done(test);
870 + ret = PTR_ERR(test->thread);
871 + }
872 +
873 + return ret;
874 +}
875 +
876 +
877 +/**
878 + * ls_pcie_reg_ops_read - read for regs data
879 + * @filp: the opened file
880 + * @buffer: where to write the data for the user to read
881 + * @count: the size of the user's buffer
882 + * @ppos: file position offset
883 + **/
884 +static ssize_t ls_pcie_ep_dbg_regs_read(struct file *filp, char __user *buffer,
885 + size_t count, loff_t *ppos)
886 +{
887 + struct ls_ep_dev *ep = filp->private_data;
888 + struct ls_pcie *pcie = ep->pcie;
889 + char *buf;
890 + int desc = 0, i, len;
891 +
892 + buf = kmalloc(4 * 1024, GFP_KERNEL);
893 + if (!buf)
894 + return -ENOMEM;
895 +
896 + ls_pcie_ep_dev_cfg_enable(ep);
897 +
898 + desc += sprintf(buf + desc, "%s", "reg info:");
899 + for (i = 0; i < 0x200; i += 4) {
900 + if (i % 16 == 0)
901 + desc += sprintf(buf + desc, "\n%08x:", i);
902 + desc += sprintf(buf + desc, " %08x", readl(pcie->dbi + i));
903 + }
904 +
905 + desc += sprintf(buf + desc, "\n%s", "outbound iATU info:\n");
906 + for (i = 0; i < 6; i++) {
907 + writel(PCIE_ATU_REGION_OUTBOUND | i,
908 + pcie->dbi + PCIE_ATU_VIEWPORT);
909 + desc += sprintf(buf + desc, "iATU%d", i);
910 + desc += sprintf(buf + desc, "\tLOWER PHYS 0x%08x\n",
911 + readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
912 + desc += sprintf(buf + desc, "\tUPPER PHYS 0x%08x\n",
913 + readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
914 + desc += sprintf(buf + desc, "\tLOWER BUS 0x%08x\n",
915 + readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
916 + desc += sprintf(buf + desc, "\tUPPER BUS 0x%08x\n",
917 + readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
918 + desc += sprintf(buf + desc, "\tLIMIT 0x%08x\n",
919 + readl(pcie->dbi + PCIE_ATU_LIMIT));
920 + desc += sprintf(buf + desc, "\tCR1 0x%08x\n",
921 + readl(pcie->dbi + PCIE_ATU_CR1));
922 + desc += sprintf(buf + desc, "\tCR2 0x%08x\n",
923 + readl(pcie->dbi + PCIE_ATU_CR2));
924 + }
925 +
926 + desc += sprintf(buf + desc, "\n%s", "inbound iATU info:\n");
927 + for (i = 0; i < 6; i++) {
928 + writel(PCIE_ATU_REGION_INBOUND | i,
929 + pcie->dbi + PCIE_ATU_VIEWPORT);
930 + desc += sprintf(buf + desc, "iATU%d", i);
931 + desc += sprintf(buf + desc, "\tLOWER BUS 0x%08x\n",
932 + readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
933 + desc += sprintf(buf + desc, "\tUPPER BUSs 0x%08x\n",
934 + readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
935 + desc += sprintf(buf + desc, "\tLOWER PHYS 0x%08x\n",
936 + readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
937 + desc += sprintf(buf + desc, "\tUPPER PHYS 0x%08x\n",
938 + readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
939 + desc += sprintf(buf + desc, "\tLIMIT 0x%08x\n",
940 + readl(pcie->dbi + PCIE_ATU_LIMIT));
941 + desc += sprintf(buf + desc, "\tCR1 0x%08x\n",
942 + readl(pcie->dbi + PCIE_ATU_CR1));
943 + desc += sprintf(buf + desc, "\tCR2 0x%08x\n",
944 + readl(pcie->dbi + PCIE_ATU_CR2));
945 + }
946 +
947 + len = simple_read_from_buffer(buffer, count, ppos, buf, desc);
948 + kfree(buf);
949 +
950 + return len;
951 +}
952 +
953 +/**
954 + * ls_pcie_ep_dbg_regs_write - write into regs datum
955 + * @filp: the opened file
956 + * @buffer: where to find the user's data
957 + * @count: the length of the user's data
958 + * @ppos: file position offset
959 + **/
960 +static ssize_t ls_pcie_ep_dbg_regs_write(struct file *filp,
961 + const char __user *buffer,
962 + size_t count, loff_t *ppos)
963 +{
964 + struct ls_ep_dev *ep = filp->private_data;
965 + struct ls_pcie *pcie = ep->pcie;
966 + char buf[256];
967 +
968 + if (count >= sizeof(buf))
969 + return -ENOSPC;
970 +
971 + memset(buf, 0, sizeof(buf));
972 +
973 + if (copy_from_user(buf, buffer, count))
974 + return -EFAULT;
975 +
976 + ls_pcie_ep_dev_cfg_enable(ep);
977 +
978 + if (strncmp(buf, "reg", 3) == 0) {
979 + u32 reg, value;
980 + int cnt;
981 +
982 + cnt = sscanf(&buf[3], "%x %x", &reg, &value);
983 + if (cnt == 2) {
984 + writel(value, pcie->dbi + reg);
985 + value = readl(pcie->dbi + reg);
986 + dev_info(&ep->dev, "reg 0x%08x: 0x%08x\n",
987 + reg, value);
988 + } else {
989 + dev_info(&ep->dev, "reg <reg> <value>\n");
990 + }
991 + } else if (strncmp(buf, "atu", 3) == 0) {
992 + /* to do */
993 + dev_info(&ep->dev, " Not support atu command\n");
994 + } else {
995 + dev_info(&ep->dev, "Unknown command %s\n", buf);
996 + dev_info(&ep->dev, "Available commands:\n");
997 + dev_info(&ep->dev, " reg <reg> <value>\n");
998 + }
999 +
1000 + return count;
1001 +}
1002 +
1003 +static const struct file_operations ls_pcie_ep_dbg_regs_fops = {
1004 + .owner = THIS_MODULE,
1005 + .open = simple_open,
1006 + .read = ls_pcie_ep_dbg_regs_read,
1007 + .write = ls_pcie_ep_dbg_regs_write,
1008 +};
1009 +
1010 +static ssize_t ls_pcie_ep_dbg_test_read(struct file *filp,
1011 + char __user *buffer,
1012 + size_t count, loff_t *ppos)
1013 +{
1014 + struct ls_ep_dev *ep = filp->private_data;
1015 + struct ls_ep_test *test = ep->driver_data;
1016 + char buf[512];
1017 + int desc = 0, len;
1018 +
1019 + if (!test) {
1020 + dev_info(&ep->dev, " there is NO test\n");
1021 + return 0;
1022 + }
1023 +
1024 + if (test->status != TEST_IDLE) {
1025 + dev_info(&ep->dev, "test %s is running\n", test->cmd);
1026 + return 0;
1027 + }
1028 +
1029 + desc = sprintf(buf, "MSI ADDR:0x%llx MSI DATA:0x%x\n",
1030 + test->msi_msg_addr, test->msi_msg_data);
1031 +
1032 + desc += sprintf(buf + desc, "%s throughput:%lluMbps\n",
1033 + test->cmd, test->result);
1034 +
1035 + len = simple_read_from_buffer(buffer, count, ppos,
1036 + buf, desc);
1037 +
1038 + return len;
1039 +}
1040 +
1041 +static ssize_t ls_pcie_ep_dbg_test_write(struct file *filp,
1042 + const char __user *buffer,
1043 + size_t count, loff_t *ppos)
1044 +{
1045 + struct ls_ep_dev *ep = filp->private_data;
1046 + char buf[256];
1047 +
1048 + if (count >= sizeof(buf))
1049 + return -ENOSPC;
1050 +
1051 + memset(buf, 0, sizeof(buf));
1052 +
1053 + if (copy_from_user(buf, buffer, count))
1054 + return -EFAULT;
1055 +
1056 + if (strncmp(buf, "init", 4) == 0) {
1057 + int i = 4;
1058 + u64 bus_addr;
1059 +
1060 + while (buf[i] == ' ')
1061 + i++;
1062 +
1063 + if (kstrtou64(&buf[i], 0, &bus_addr))
1064 + dev_info(&ep->dev, "command: init <bus_addr>\n");
1065 + else {
1066 + if (ls_pcie_ep_init_test(ep, bus_addr))
1067 + dev_info(&ep->dev, "failed to init test\n");
1068 + }
1069 + } else if (strncmp(buf, "free", 4) == 0)
1070 + ls_pcie_ep_free_test(ep);
1071 + else if (strncmp(buf, "dma", 3) == 0 ||
1072 + strncmp(buf, "cpy", 3) == 0)
1073 + ls_pcie_ep_start_test(ep, buf);
1074 + else {
1075 + dev_info(&ep->dev, "Unknown command: %s\n", buf);
1076 + dev_info(&ep->dev, "Available commands:\n");
1077 + dev_info(&ep->dev, "\tinit <bus_addr>\n");
1078 + dev_info(&ep->dev, "\t<dma/cpy> <r/w> <packet_size> <loop>\n");
1079 + dev_info(&ep->dev, "\tfree\n");
1080 + }
1081 +
1082 + return count;
1083 +}
1084 +
1085 +static const struct file_operations ls_pcie_ep_dbg_test_fops = {
1086 + .owner = THIS_MODULE,
1087 + .open = simple_open,
1088 + .read = ls_pcie_ep_dbg_test_read,
1089 + .write = ls_pcie_ep_dbg_test_write,
1090 +};
1091 +
1092 +static ssize_t ls_pcie_ep_dbg_dump_read(struct file *filp,
1093 + char __user *buffer,
1094 + size_t count, loff_t *ppos)
1095 +{
1096 + struct ls_ep_dev *ep = filp->private_data;
1097 + struct ls_ep_test *test = ep->driver_data;
1098 + char *buf;
1099 + int desc = 0, i, len;
1100 +
1101 + buf = kmalloc(4 * 1024, GFP_KERNEL);
1102 + if (!buf)
1103 + return -ENOMEM;
1104 +
1105 + if (!test) {
1106 + dev_info(&ep->dev, " there is NO test\n");
1107 + kfree(buf);
1108 + return 0;
1109 + }
1110 +
1111 + desc += sprintf(buf + desc, "%s", "dump info:");
1112 + for (i = 0; i < 256; i += 4) {
1113 + if (i % 16 == 0)
1114 + desc += sprintf(buf + desc, "\n%08x:", i);
1115 + desc += sprintf(buf + desc, " %08x", readl(test->buf + i));
1116 + }
1117 +
1118 + desc += sprintf(buf + desc, "\n");
1119 + len = simple_read_from_buffer(buffer, count, ppos, buf, desc);
1120 +
1121 + kfree(buf);
1122 +
1123 + return len;
1124 +}
1125 +
1126 +static const struct file_operations ls_pcie_ep_dbg_dump_fops = {
1127 + .owner = THIS_MODULE,
1128 + .open = simple_open,
1129 + .read = ls_pcie_ep_dbg_dump_read,
1130 +};
1131 +
1132 +static int ls_pcie_ep_dev_dbgfs_init(struct ls_ep_dev *ep)
1133 +{
1134 + struct ls_pcie *pcie = ep->pcie;
1135 + struct dentry *pfile;
1136 +
1137 + ls_pcie_ep_dev_cfg_enable(ep);
1138 +
1139 + ep->dir = debugfs_create_dir(dev_name(&ep->dev), pcie->dir);
1140 + if (!ep->dir)
1141 + return -ENOMEM;
1142 +
1143 + pfile = debugfs_create_file("regs", 0600, ep->dir, ep,
1144 + &ls_pcie_ep_dbg_regs_fops);
1145 + if (!pfile)
1146 + dev_info(&ep->dev, "debugfs regs for failed\n");
1147 +
1148 + pfile = debugfs_create_file("test", 0600, ep->dir, ep,
1149 + &ls_pcie_ep_dbg_test_fops);
1150 + if (!pfile)
1151 + dev_info(&ep->dev, "debugfs test for failed\n");
1152 +
1153 + pfile = debugfs_create_file("dump", 0600, ep->dir, ep,
1154 + &ls_pcie_ep_dbg_dump_fops);
1155 + if (!pfile)
1156 + dev_info(&ep->dev, "debugfs dump for failed\n");
1157 +
1158 + return 0;
1159 +}
1160 +
1161 +int ls_pcie_ep_dbgfs_init(struct ls_pcie *pcie)
1162 +{
1163 + struct ls_ep_dev *ep;
1164 +
1165 + pcie->dir = debugfs_create_dir(dev_name(pcie->dev), NULL);
1166 + if (!pcie->dir)
1167 + return -ENOMEM;
1168 +
1169 + list_for_each_entry(ep, &pcie->ep_list, node)
1170 + ls_pcie_ep_dev_dbgfs_init(ep);
1171 +
1172 + return 0;
1173 +}
1174 +
1175 +int ls_pcie_ep_dbgfs_remove(struct ls_pcie *pcie)
1176 +{
1177 + debugfs_remove_recursive(pcie->dir);
1178 + return 0;
1179 +}
1180 +
1181 +MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
1182 +MODULE_DESCRIPTION("Freescale Layerscape PCIe EP controller driver");
1183 +MODULE_LICENSE("GPL v2");
1184 diff --git a/drivers/pci/host/pci-layerscape-ep.c b/drivers/pci/host/pci-layerscape-ep.c
1185 new file mode 100644
1186 index 00000000..8f1cca6e
1187 --- /dev/null
1188 +++ b/drivers/pci/host/pci-layerscape-ep.c
1189 @@ -0,0 +1,309 @@
1190 +/*
1191 + * PCIe Endpoint driver for Freescale Layerscape SoCs
1192 + *
1193 + * Copyright (C) 2015 Freescale Semiconductor.
1194 + *
1195 + * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
1196 + *
1197 + * This program is free software; you can redistribute it and/or modify
1198 + * it under the terms of the GNU General Public License version 2 as
1199 + * published by the Free Software Foundation.
1200 + */
1201 +
1202 +#include <linux/kernel.h>
1203 +#include <linux/delay.h>
1204 +#include <linux/interrupt.h>
1205 +#include <linux/module.h>
1206 +#include <linux/of_pci.h>
1207 +#include <linux/of_platform.h>
1208 +#include <linux/of_irq.h>
1209 +#include <linux/of_address.h>
1210 +#include <linux/pci.h>
1211 +#include <linux/platform_device.h>
1212 +#include <linux/resource.h>
1213 +#include <linux/debugfs.h>
1214 +#include <linux/time.h>
1215 +#include <linux/uaccess.h>
1216 +
1217 +#include "pci-layerscape-ep.h"
1218 +
1219 +struct ls_ep_dev *
1220 +ls_pci_ep_find(struct ls_pcie *pcie, int dev_id)
1221 +{
1222 + struct ls_ep_dev *ep;
1223 +
1224 + list_for_each_entry(ep, &pcie->ep_list, node) {
1225 + if (ep->dev_id == dev_id)
1226 + return ep;
1227 + }
1228 +
1229 + return NULL;
1230 +}
1231 +
1232 +static void ls_pcie_try_cfg2(struct ls_pcie *pcie, int pf, int vf)
1233 +{
1234 + if (pcie->sriov)
1235 + writel(PCIE_LCTRL0_VAL(pf, vf),
1236 + pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0);
1237 +}
1238 +
1239 +static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
1240 +{
1241 + u32 header_type = 0;
1242 +
1243 + header_type = readl(pcie->dbi + (PCI_HEADER_TYPE & ~0x3));
1244 + header_type = (header_type >> 16) & 0x7f;
1245 +
1246 + return header_type == PCI_HEADER_TYPE_BRIDGE;
1247 +}
1248 +
1249 +void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
1250 + u64 cpu_addr, u64 pci_addr, u32 size)
1251 +{
1252 + writel(PCIE_ATU_REGION_OUTBOUND | idx,
1253 + pcie->dbi + PCIE_ATU_VIEWPORT);
1254 + writel(lower_32_bits(cpu_addr),
1255 + pcie->dbi + PCIE_ATU_LOWER_BASE);
1256 + writel(upper_32_bits(cpu_addr),
1257 + pcie->dbi + PCIE_ATU_UPPER_BASE);
1258 + writel(lower_32_bits(cpu_addr + size - 1),
1259 + pcie->dbi + PCIE_ATU_LIMIT);
1260 + writel(lower_32_bits(pci_addr),
1261 + pcie->dbi + PCIE_ATU_LOWER_TARGET);
1262 + writel(upper_32_bits(pci_addr),
1263 + pcie->dbi + PCIE_ATU_UPPER_TARGET);
1264 + writel(type, pcie->dbi + PCIE_ATU_CR1);
1265 + writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2);
1266 +}
1267 +
1268 +/* Use bar match mode and MEM type as default */
1269 +void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx,
1270 + int bar, u64 phys)
1271 +{
1272 + writel(PCIE_ATU_REGION_INBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
1273 + writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_TARGET);
1274 + writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
1275 + writel(PCIE_ATU_TYPE_MEM, pcie->dbi + PCIE_ATU_CR1);
1276 + writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
1277 + PCIE_ATU_BAR_NUM(bar), pcie->dbi + PCIE_ATU_CR2);
1278 +}
1279 +
1280 +void ls_pcie_ep_dev_cfg_enable(struct ls_ep_dev *ep)
1281 +{
1282 + ls_pcie_try_cfg2(ep->pcie, ep->pf_idx, ep->vf_idx);
1283 +}
1284 +
1285 +void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
1286 +{
1287 + if (size < 4 * 1024)
1288 + return;
1289 +
1290 + switch (bar) {
1291 + case 0:
1292 + writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
1293 + break;
1294 + case 1:
1295 + writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
1296 + break;
1297 + case 2:
1298 + writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
1299 + writel(0, bar_base + PCI_BASE_ADDRESS_3);
1300 + break;
1301 + case 4:
1302 + writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
1303 + writel(0, bar_base + PCI_BASE_ADDRESS_5);
1304 + break;
1305 + default:
1306 + break;
1307 + }
1308 +}
1309 +
1310 +void ls_pcie_ep_dev_setup_bar(struct ls_ep_dev *ep, int bar, u32 size)
1311 +{
1312 + struct ls_pcie *pcie = ep->pcie;
1313 + void *bar_base;
1314 +
1315 + if (size < 4 * 1024)
1316 + return;
1317 +
1318 + if (pcie->sriov)
1319 + bar_base = pcie->dbi;
1320 + else
1321 + bar_base = pcie->dbi + PCIE_NO_SRIOV_BAR_BASE;
1322 +
1323 + ls_pcie_ep_dev_cfg_enable(ep);
1324 + ls_pcie_ep_setup_bar(bar_base, bar, size);
1325 +}
1326 +
1327 +static int ls_pcie_ep_dev_init(struct ls_pcie *pcie, int pf_idx, int vf_idx)
1328 +{
1329 + struct ls_ep_dev *ep;
1330 +
1331 + ep = devm_kzalloc(pcie->dev, sizeof(*ep), GFP_KERNEL);
1332 + if (!ep)
1333 + return -ENOMEM;
1334 +
1335 + ep->pcie = pcie;
1336 + ep->pf_idx = pf_idx;
1337 + ep->vf_idx = vf_idx;
1338 + if (vf_idx)
1339 + ep->dev_id = pf_idx + 4 + 4 * (vf_idx - 1);
1340 + else
1341 + ep->dev_id = pf_idx;
1342 +
1343 + if (ep->vf_idx)
1344 + dev_set_name(&ep->dev, "pf%d-vf%d",
1345 + ep->pf_idx,
1346 + ep->vf_idx);
1347 + else
1348 + dev_set_name(&ep->dev, "pf%d",
1349 + ep->pf_idx);
1350 +
1351 + list_add_tail(&ep->node, &pcie->ep_list);
1352 +
1353 + return 0;
1354 +}
1355 +
1356 +static int ls_pcie_ep_init(struct ls_pcie *pcie)
1357 +{
1358 + u32 sriov_header;
1359 + int pf, vf, i, j;
1360 +
1361 + sriov_header = readl(pcie->dbi + PCIE_SRIOV_POS);
1362 +
1363 + if (PCI_EXT_CAP_ID(sriov_header) == PCI_EXT_CAP_ID_SRIOV) {
1364 + pcie->sriov = PCIE_SRIOV_POS;
1365 + pf = PCIE_PF_NUM;
1366 + vf = PCIE_VF_NUM;
1367 + } else {
1368 + pcie->sriov = 0;
1369 + pf = 1;
1370 + vf = 0;
1371 + }
1372 +
1373 + for (i = 0; i < pf; i++) {
1374 + for (j = 0; j <= vf; j++)
1375 + ls_pcie_ep_dev_init(pcie, i, j);
1376 + }
1377 +
1378 + return 0;
1379 +}
1380 +
1381 +static struct ls_pcie_ep_drvdata ls1043_drvdata = {
1382 + .lut_offset = 0x10000,
1383 + .ltssm_shift = 24,
1384 + .lut_dbg = 0x7fc,
1385 +};
1386 +
1387 +static struct ls_pcie_ep_drvdata ls1046_drvdata = {
1388 + .lut_offset = 0x80000,
1389 + .ltssm_shift = 24,
1390 + .lut_dbg = 0x407fc,
1391 +};
1392 +
1393 +static struct ls_pcie_ep_drvdata ls2080_drvdata = {
1394 + .lut_offset = 0x80000,
1395 + .ltssm_shift = 0,
1396 + .lut_dbg = 0x7fc,
1397 +};
1398 +
1399 +static const struct of_device_id ls_pcie_ep_of_match[] = {
1400 + { .compatible = "fsl,ls1021a-pcie", },
1401 + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
1402 + { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
1403 + { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
1404 + { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
1405 + { },
1406 +};
1407 +MODULE_DEVICE_TABLE(of, ls_pcie_ep_of_match);
1408 +
1409 +static int ls_pcie_ep_probe(struct platform_device *pdev)
1410 +{
1411 + struct ls_pcie *pcie;
1412 + struct resource *dbi_base, *cfg_res;
1413 + const struct of_device_id *match;
1414 + int ret;
1415 +
1416 + match = of_match_device(ls_pcie_ep_of_match, &pdev->dev);
1417 + if (!match)
1418 + return -ENODEV;
1419 +
1420 + pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
1421 + if (!pcie)
1422 + return -ENOMEM;
1423 +
1424 + pcie->dev = &pdev->dev;
1425 + INIT_LIST_HEAD(&pcie->ep_list);
1426 +
1427 + dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1428 + pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
1429 + if (IS_ERR(pcie->dbi)) {
1430 + dev_err(&pdev->dev, "missing *regs* space\n");
1431 + return PTR_ERR(pcie->dbi);
1432 + }
1433 +
1434 + pcie->drvdata = match->data;
1435 + pcie->lut = pcie->dbi + pcie->drvdata->lut_offset;
1436 +
1437 + if (ls_pcie_is_bridge(pcie))
1438 + return -ENODEV;
1439 +
1440 + dev_info(pcie->dev, "in EP mode\n");
1441 +
1442 + cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
1443 + if (cfg_res)
1444 + pcie->out_base = cfg_res->start;
1445 + else {
1446 + dev_err(&pdev->dev, "missing *config* space\n");
1447 + return -ENODEV;
1448 + }
1449 +
1450 + ret = ls_pcie_ep_init(pcie);
1451 + if (ret)
1452 + return ret;
1453 +
1454 + ls_pcie_ep_dbgfs_init(pcie);
1455 +
1456 + platform_set_drvdata(pdev, pcie);
1457 +
1458 + return 0;
1459 +}
1460 +
1461 +static int ls_pcie_ep_dev_remove(struct ls_ep_dev *ep)
1462 +{
1463 + list_del(&ep->node);
1464 +
1465 + return 0;
1466 +}
1467 +
1468 +static int ls_pcie_ep_remove(struct platform_device *pdev)
1469 +{
1470 + struct ls_pcie *pcie = platform_get_drvdata(pdev);
1471 + struct ls_ep_dev *ep, *tmp;
1472 +
1473 + if (!pcie)
1474 + return 0;
1475 +
1476 + ls_pcie_ep_dbgfs_remove(pcie);
1477 +
1478 + list_for_each_entry_safe(ep, tmp, &pcie->ep_list, node)
1479 + ls_pcie_ep_dev_remove(ep);
1480 +
1481 + return 0;
1482 +}
1483 +
1484 +static struct platform_driver ls_pcie_ep_driver = {
1485 + .driver = {
1486 + .name = "ls-pcie-ep",
1487 + .owner = THIS_MODULE,
1488 + .of_match_table = ls_pcie_ep_of_match,
1489 + },
1490 + .probe = ls_pcie_ep_probe,
1491 + .remove = ls_pcie_ep_remove,
1492 +};
1493 +
1494 +module_platform_driver(ls_pcie_ep_driver);
1495 +
1496 +MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
1497 +MODULE_DESCRIPTION("Freescale Layerscape PCIe EP driver");
1498 +MODULE_LICENSE("GPL v2");
1499 diff --git a/drivers/pci/host/pci-layerscape-ep.h b/drivers/pci/host/pci-layerscape-ep.h
1500 new file mode 100644
1501 index 00000000..990c0ff5
1502 --- /dev/null
1503 +++ b/drivers/pci/host/pci-layerscape-ep.h
1504 @@ -0,0 +1,115 @@
1505 +/*
1506 + * PCIe Endpoint driver for Freescale Layerscape SoCs
1507 + *
1508 + * Copyright (C) 2015 Freescale Semiconductor.
1509 + *
1510 + * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
1511 + *
1512 + * This program is free software; you can redistribute it and/or modify
1513 + * it under the terms of the GNU General Public License version 2 as
1514 + * published by the Free Software Foundation.
1515 + */
1516 +
1517 +
1518 +#ifndef _PCIE_LAYERSCAPE_EP_H
1519 +#define _PCIE_LAYERSCAPE_EP_H
1520 +
1521 +#include <linux/device.h>
1522 +
1523 +/* Synopsis specific PCIE configuration registers */
1524 +#define PCIE_ATU_VIEWPORT 0x900
1525 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
1526 +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
1527 +#define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
1528 +#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
1529 +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
1530 +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
1531 +#define PCIE_ATU_CR1 0x904
1532 +#define PCIE_ATU_TYPE_MEM (0x0 << 0)
1533 +#define PCIE_ATU_TYPE_IO (0x2 << 0)
1534 +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
1535 +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
1536 +#define PCIE_ATU_CR2 0x908
1537 +#define PCIE_ATU_ENABLE (0x1 << 31)
1538 +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
1539 +#define PCIE_ATU_LOWER_BASE 0x90C
1540 +#define PCIE_ATU_UPPER_BASE 0x910
1541 +#define PCIE_ATU_LIMIT 0x914
1542 +#define PCIE_ATU_LOWER_TARGET 0x918
1543 +#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
1544 +#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
1545 +#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
1546 +#define PCIE_ATU_UPPER_TARGET 0x91C
1547 +
1548 +/* PEX internal configuration registers */
1549 +#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
1550 +
1551 +/* PEX LUT registers */
1552 +#define PCIE_LUT_BASE 0x80000
1553 +#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug register */
1554 +
1555 +#define PCIE_LUT_LCTRL0 0x7F8
1556 +
1557 +#define PCIE_ATU_BAR_NUM(bar) ((bar) << 8)
1558 +#define PCIE_LCTRL0_CFG2_ENABLE (1 << 31)
1559 +#define PCIE_LCTRL0_VF(vf) ((vf) << 22)
1560 +#define PCIE_LCTRL0_PF(pf) ((pf) << 16)
1561 +#define PCIE_LCTRL0_VF_ACTIVE (1 << 21)
1562 +#define PCIE_LCTRL0_VAL(pf, vf) (PCIE_LCTRL0_PF(pf) | \
1563 + PCIE_LCTRL0_VF(vf) | \
1564 + ((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \
1565 + PCIE_LCTRL0_CFG2_ENABLE)
1566 +
1567 +#define PCIE_NO_SRIOV_BAR_BASE 0x1000
1568 +
1569 +#define PCIE_SRIOV_POS 0x178
1570 +#define PCIE_PF_NUM 2
1571 +#define PCIE_VF_NUM 64
1572 +
1573 +struct ls_pcie_ep_drvdata {
1574 + u32 lut_offset;
1575 + u32 ltssm_shift;
1576 + u32 lut_dbg;
1577 +};
1578 +
1579 +struct ls_pcie {
1580 + struct list_head ep_list;
1581 + struct device *dev;
1582 + struct dentry *dir;
1583 + const struct ls_pcie_ep_drvdata *drvdata;
1584 + void __iomem *dbi;
1585 + void __iomem *lut;
1586 + phys_addr_t out_base;
1587 + int sriov;
1588 + int index;
1589 +};
1590 +
1591 +struct ls_ep_dev {
1592 + struct list_head node;
1593 + struct ls_pcie *pcie;
1594 + struct device dev;
1595 + struct dentry *dir;
1596 + int pf_idx;
1597 + int vf_idx;
1598 + int dev_id;
1599 + void *driver_data;
1600 +};
1601 +
1602 +struct ls_ep_dev *ls_pci_ep_find(struct ls_pcie *pcie, int dev_id);
1603 +
1604 +void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
1605 + u64 cpu_addr, u64 pci_addr, u32 size);
1606 +
1607 +/* Use bar match mode and MEM type as default */
1608 +void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx,
1609 + int bar, u64 phys);
1610 +
1611 +void ls_pcie_ep_dev_setup_bar(struct ls_ep_dev *ep, int bar, u32 size);
1612 +
1613 +
1614 +void ls_pcie_ep_dev_cfg_enable(struct ls_ep_dev *ep);
1615 +
1616 +int ls_pcie_ep_dbgfs_init(struct ls_pcie *pcie);
1617 +int ls_pcie_ep_dbgfs_remove(struct ls_pcie *pcie);
1618 +
1619 +#endif /* _PCIE_LAYERSCAPE_EP_H */
1620 diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c
1621 index 65370799..7ce32ff0 100644
1622 --- a/drivers/pci/host/pci-layerscape.c
1623 +++ b/drivers/pci/host/pci-layerscape.c
1624 @@ -35,12 +35,14 @@
1625 #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
1626 #define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
1627
1628 -/* PEX LUT registers */
1629 -#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */
1630 +#define PCIE_IATU_NUM 6
1631 +
1632 +static void ls_pcie_host_init(struct pcie_port *pp);
1633
1634 struct ls_pcie_drvdata {
1635 u32 lut_offset;
1636 u32 ltssm_shift;
1637 + u32 lut_dbg;
1638 struct pcie_host_ops *ops;
1639 };
1640
1641 @@ -86,6 +88,14 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
1642 iowrite32(val, pcie->pp.dbi_base + PCIE_STRFMR1);
1643 }
1644
1645 +static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie)
1646 +{
1647 + int i;
1648 +
1649 + for (i = 0; i < PCIE_IATU_NUM; i++)
1650 + dw_pcie_disable_outbound_atu(&pcie->pp, i);
1651 +}
1652 +
1653 static int ls1021_pcie_link_up(struct pcie_port *pp)
1654 {
1655 u32 state;
1656 @@ -134,7 +144,7 @@ static int ls_pcie_link_up(struct pcie_port *pp)
1657 struct ls_pcie *pcie = to_ls_pcie(pp);
1658 u32 state;
1659
1660 - state = (ioread32(pcie->lut + PCIE_LUT_DBG) >>
1661 + state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
1662 pcie->drvdata->ltssm_shift) &
1663 LTSSM_STATE_MASK;
1664
1665 @@ -153,6 +163,9 @@ static void ls_pcie_host_init(struct pcie_port *pp)
1666 ls_pcie_clear_multifunction(pcie);
1667 ls_pcie_drop_msg_tlp(pcie);
1668 iowrite32(0, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
1669 +
1670 + ls_pcie_disable_outbound_atus(pcie);
1671 + dw_pcie_setup_rc(pp);
1672 }
1673
1674 static int ls_pcie_msi_host_init(struct pcie_port *pp,
1675 @@ -196,20 +209,39 @@ static struct ls_pcie_drvdata ls1021_drvdata = {
1676 static struct ls_pcie_drvdata ls1043_drvdata = {
1677 .lut_offset = 0x10000,
1678 .ltssm_shift = 24,
1679 + .lut_dbg = 0x7fc,
1680 + .ops = &ls_pcie_host_ops,
1681 +};
1682 +
1683 +static struct ls_pcie_drvdata ls1046_drvdata = {
1684 + .lut_offset = 0x80000,
1685 + .ltssm_shift = 24,
1686 + .lut_dbg = 0x407fc,
1687 .ops = &ls_pcie_host_ops,
1688 };
1689
1690 static struct ls_pcie_drvdata ls2080_drvdata = {
1691 .lut_offset = 0x80000,
1692 .ltssm_shift = 0,
1693 + .lut_dbg = 0x7fc,
1694 + .ops = &ls_pcie_host_ops,
1695 +};
1696 +
1697 +static struct ls_pcie_drvdata ls2088_drvdata = {
1698 + .lut_offset = 0x80000,
1699 + .ltssm_shift = 0,
1700 + .lut_dbg = 0x407fc,
1701 .ops = &ls_pcie_host_ops,
1702 };
1703
1704 static const struct of_device_id ls_pcie_of_match[] = {
1705 + { .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata },
1706 { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
1707 { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
1708 + { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
1709 { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
1710 { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
1711 + { .compatible = "fsl,ls2088a-pcie", .data = &ls2088_drvdata },
1712 { },
1713 };
1714
1715 diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
1716 index af8f6e92..2358e049 100644
1717 --- a/drivers/pci/host/pcie-designware.c
1718 +++ b/drivers/pci/host/pcie-designware.c
1719 @@ -478,6 +478,12 @@ int dw_pcie_wait_for_link(struct pcie_port *pp)
1720 return -ETIMEDOUT;
1721 }
1722
1723 +void dw_pcie_disable_outbound_atu(struct pcie_port *pp, int index)
1724 +{
1725 + dw_pcie_writel_rc(pp, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_OUTBOUND | index);
1726 + dw_pcie_writel_rc(pp, PCIE_ATU_CR2, 0);
1727 +}
1728 +
1729 int dw_pcie_link_up(struct pcie_port *pp)
1730 {
1731 u32 val;
1732 diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
1733 index a567ea28..4e6672b2 100644
1734 --- a/drivers/pci/host/pcie-designware.h
1735 +++ b/drivers/pci/host/pcie-designware.h
1736 @@ -82,5 +82,6 @@ int dw_pcie_wait_for_link(struct pcie_port *pp);
1737 int dw_pcie_link_up(struct pcie_port *pp);
1738 void dw_pcie_setup_rc(struct pcie_port *pp);
1739 int dw_pcie_host_init(struct pcie_port *pp);
1740 +void dw_pcie_disable_outbound_atu(struct pcie_port *pp, int index);
1741
1742 #endif /* _PCIE_DESIGNWARE_H */
1743 diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
1744 index e9270b40..1bad877a 100644
1745 --- a/drivers/pci/pcie/portdrv_core.c
1746 +++ b/drivers/pci/pcie/portdrv_core.c
1747 @@ -44,52 +44,30 @@ static void release_pcie_device(struct device *dev)
1748 }
1749
1750 /**
1751 - * pcie_port_msix_add_entry - add entry to given array of MSI-X entries
1752 - * @entries: Array of MSI-X entries
1753 - * @new_entry: Index of the entry to add to the array
1754 - * @nr_entries: Number of entries already in the array
1755 + * pcibios_check_service_irqs - check irqs in the device tree
1756 + * @dev: PCI Express port to handle
1757 + * @irqs: Array of irqs to populate
1758 + * @mask: Bitmask of port capabilities returned by get_port_device_capability()
1759 + *
1760 + * Return value: 0 means no service irqs in the device tree
1761 *
1762 - * Return value: Position of the added entry in the array
1763 */
1764 -static int pcie_port_msix_add_entry(
1765 - struct msix_entry *entries, int new_entry, int nr_entries)
1766 +int __weak pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
1767 {
1768 - int j;
1769 -
1770 - for (j = 0; j < nr_entries; j++)
1771 - if (entries[j].entry == new_entry)
1772 - return j;
1773 -
1774 - entries[j].entry = new_entry;
1775 - return j;
1776 + return 0;
1777 }
1778
1779 /**
1780 * pcie_port_enable_msix - try to set up MSI-X as interrupt mode for given port
1781 * @dev: PCI Express port to handle
1782 - * @vectors: Array of interrupt vectors to populate
1783 + * @irqs: Array of interrupt vectors to populate
1784 * @mask: Bitmask of port capabilities returned by get_port_device_capability()
1785 *
1786 * Return value: 0 on success, error code on failure
1787 */
1788 -static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
1789 +static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask)
1790 {
1791 - struct msix_entry *msix_entries;
1792 - int idx[PCIE_PORT_DEVICE_MAXSERVICES];
1793 - int nr_entries, status, pos, i, nvec;
1794 - u16 reg16;
1795 - u32 reg32;
1796 -
1797 - nr_entries = pci_msix_vec_count(dev);
1798 - if (nr_entries < 0)
1799 - return nr_entries;
1800 - BUG_ON(!nr_entries);
1801 - if (nr_entries > PCIE_PORT_MAX_MSIX_ENTRIES)
1802 - nr_entries = PCIE_PORT_MAX_MSIX_ENTRIES;
1803 -
1804 - msix_entries = kzalloc(sizeof(*msix_entries) * nr_entries, GFP_KERNEL);
1805 - if (!msix_entries)
1806 - return -ENOMEM;
1807 + int nr_entries, entry, nvec = 0;
1808
1809 /*
1810 * Allocate as many entries as the port wants, so that we can check
1811 @@ -97,20 +75,13 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
1812 * equal to the number of entries this port actually uses, we'll happily
1813 * go through without any tricks.
1814 */
1815 - for (i = 0; i < nr_entries; i++)
1816 - msix_entries[i].entry = i;
1817 -
1818 - status = pci_enable_msix_exact(dev, msix_entries, nr_entries);
1819 - if (status)
1820 - goto Exit;
1821 -
1822 - for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1823 - idx[i] = -1;
1824 - status = -EIO;
1825 - nvec = 0;
1826 + nr_entries = pci_alloc_irq_vectors(dev, 1, PCIE_PORT_MAX_MSIX_ENTRIES,
1827 + PCI_IRQ_MSIX);
1828 + if (nr_entries < 0)
1829 + return nr_entries;
1830
1831 if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP)) {
1832 - int entry;
1833 + u16 reg16;
1834
1835 /*
1836 * The code below follows the PCI Express Base Specification 2.0
1837 @@ -125,18 +96,16 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
1838 pcie_capability_read_word(dev, PCI_EXP_FLAGS, &reg16);
1839 entry = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9;
1840 if (entry >= nr_entries)
1841 - goto Error;
1842 + goto out_free_irqs;
1843
1844 - i = pcie_port_msix_add_entry(msix_entries, entry, nvec);
1845 - if (i == nvec)
1846 - nvec++;
1847 + irqs[PCIE_PORT_SERVICE_PME_SHIFT] = pci_irq_vector(dev, entry);
1848 + irqs[PCIE_PORT_SERVICE_HP_SHIFT] = pci_irq_vector(dev, entry);
1849
1850 - idx[PCIE_PORT_SERVICE_PME_SHIFT] = i;
1851 - idx[PCIE_PORT_SERVICE_HP_SHIFT] = i;
1852 + nvec = max(nvec, entry + 1);
1853 }
1854
1855 if (mask & PCIE_PORT_SERVICE_AER) {
1856 - int entry;
1857 + u32 reg32, pos;
1858
1859 /*
1860 * The code below follows Section 7.10.10 of the PCI Express
1861 @@ -151,13 +120,11 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
1862 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &reg32);
1863 entry = reg32 >> 27;
1864 if (entry >= nr_entries)
1865 - goto Error;
1866 + goto out_free_irqs;
1867
1868 - i = pcie_port_msix_add_entry(msix_entries, entry, nvec);
1869 - if (i == nvec)
1870 - nvec++;
1871 + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = pci_irq_vector(dev, entry);
1872
1873 - idx[PCIE_PORT_SERVICE_AER_SHIFT] = i;
1874 + nvec = max(nvec, entry + 1);
1875 }
1876
1877 /*
1878 @@ -165,41 +132,54 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
1879 * what we have. Otherwise, the port has some extra entries not for the
1880 * services we know and we need to work around that.
1881 */
1882 - if (nvec == nr_entries) {
1883 - status = 0;
1884 - } else {
1885 + if (nvec != nr_entries) {
1886 /* Drop the temporary MSI-X setup */
1887 - pci_disable_msix(dev);
1888 + pci_free_irq_vectors(dev);
1889
1890 /* Now allocate the MSI-X vectors for real */
1891 - status = pci_enable_msix_exact(dev, msix_entries, nvec);
1892 - if (status)
1893 - goto Exit;
1894 + nr_entries = pci_alloc_irq_vectors(dev, nvec, nvec,
1895 + PCI_IRQ_MSIX);
1896 + if (nr_entries < 0)
1897 + return nr_entries;
1898 }
1899
1900 - for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1901 - vectors[i] = idx[i] >= 0 ? msix_entries[idx[i]].vector : -1;
1902 -
1903 - Exit:
1904 - kfree(msix_entries);
1905 - return status;
1906 + return 0;
1907
1908 - Error:
1909 - pci_disable_msix(dev);
1910 - goto Exit;
1911 +out_free_irqs:
1912 + pci_free_irq_vectors(dev);
1913 + return -EIO;
1914 }
1915
1916 /**
1917 - * init_service_irqs - initialize irqs for PCI Express port services
1918 + * pcie_init_service_irqs - initialize irqs for PCI Express port services
1919 * @dev: PCI Express port to handle
1920 * @irqs: Array of irqs to populate
1921 * @mask: Bitmask of port capabilities returned by get_port_device_capability()
1922 *
1923 * Return value: Interrupt mode associated with the port
1924 */
1925 -static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
1926 +static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
1927 {
1928 - int i, irq = -1;
1929 + unsigned flags = PCI_IRQ_LEGACY | PCI_IRQ_MSI;
1930 + int ret, i;
1931 + int irq = -1;
1932 +
1933 + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1934 + irqs[i] = -1;
1935 +
1936 + /* Check if some platforms owns independent irq pins for AER/PME etc.
1937 + * Some platforms may own independent AER/PME interrupts and set
1938 + * them in the device tree file.
1939 + */
1940 + ret = pcibios_check_service_irqs(dev, irqs, mask);
1941 + if (ret) {
1942 + if (dev->irq)
1943 + irq = dev->irq;
1944 + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1945 + if (irqs[i] == -1 && i != PCIE_PORT_SERVICE_VC_SHIFT)
1946 + irqs[i] = irq;
1947 + return 0;
1948 + }
1949
1950 /*
1951 * If MSI cannot be used for PCIe PME or hotplug, we have to use
1952 @@ -207,41 +187,25 @@ static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
1953 */
1954 if (((mask & PCIE_PORT_SERVICE_PME) && pcie_pme_no_msi()) ||
1955 ((mask & PCIE_PORT_SERVICE_HP) && pciehp_no_msi())) {
1956 - if (dev->irq)
1957 - irq = dev->irq;
1958 - goto no_msi;
1959 + flags &= ~PCI_IRQ_MSI;
1960 + } else {
1961 + /* Try to use MSI-X if supported */
1962 + if (!pcie_port_enable_msix(dev, irqs, mask))
1963 + return 0;
1964 }
1965
1966 - /* Try to use MSI-X if supported */
1967 - if (!pcie_port_enable_msix(dev, irqs, mask))
1968 - return 0;
1969 -
1970 - /*
1971 - * We're not going to use MSI-X, so try MSI and fall back to INTx.
1972 - * If neither MSI/MSI-X nor INTx available, try other interrupt. On
1973 - * some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
1974 - */
1975 - if (!pci_enable_msi(dev) || dev->irq)
1976 - irq = dev->irq;
1977 + ret = pci_alloc_irq_vectors(dev, 1, 1, flags);
1978 + if (ret < 0)
1979 + return -ENODEV;
1980
1981 - no_msi:
1982 - for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1983 - irqs[i] = irq;
1984 - irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
1985 + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
1986 + if (i != PCIE_PORT_SERVICE_VC_SHIFT)
1987 + irqs[i] = pci_irq_vector(dev, 0);
1988 + }
1989
1990 - if (irq < 0)
1991 - return -ENODEV;
1992 return 0;
1993 }
1994
1995 -static void cleanup_service_irqs(struct pci_dev *dev)
1996 -{
1997 - if (dev->msix_enabled)
1998 - pci_disable_msix(dev);
1999 - else if (dev->msi_enabled)
2000 - pci_disable_msi(dev);
2001 -}
2002 -
2003 /**
2004 * get_port_device_capability - discover capabilities of a PCI Express port
2005 * @dev: PCI Express port to examine
2006 @@ -378,7 +342,7 @@ int pcie_port_device_register(struct pci_dev *dev)
2007 * that can be used in the absence of irqs. Allow them to determine
2008 * if that is to be used.
2009 */
2010 - status = init_service_irqs(dev, irqs, capabilities);
2011 + status = pcie_init_service_irqs(dev, irqs, capabilities);
2012 if (status) {
2013 capabilities &= PCIE_PORT_SERVICE_VC | PCIE_PORT_SERVICE_HP;
2014 if (!capabilities)
2015 @@ -401,7 +365,7 @@ int pcie_port_device_register(struct pci_dev *dev)
2016 return 0;
2017
2018 error_cleanup_irqs:
2019 - cleanup_service_irqs(dev);
2020 + pci_free_irq_vectors(dev);
2021 error_disable:
2022 pci_disable_device(dev);
2023 return status;
2024 @@ -469,7 +433,7 @@ static int remove_iter(struct device *dev, void *data)
2025 void pcie_port_device_remove(struct pci_dev *dev)
2026 {
2027 device_for_each_child(&dev->dev, NULL, remove_iter);
2028 - cleanup_service_irqs(dev);
2029 + pci_free_irq_vectors(dev);
2030 pci_disable_device(dev);
2031 }
2032
2033 @@ -499,7 +463,6 @@ static int pcie_port_probe_service(struct device *dev)
2034 if (status)
2035 return status;
2036
2037 - dev_printk(KERN_DEBUG, dev, "service driver %s loaded\n", driver->name);
2038 get_device(dev);
2039 return 0;
2040 }
2041 @@ -524,8 +487,6 @@ static int pcie_port_remove_service(struct device *dev)
2042 pciedev = to_pcie_device(dev);
2043 driver = to_service_driver(dev->driver);
2044 if (driver && driver->remove) {
2045 - dev_printk(KERN_DEBUG, dev, "unloading service driver %s\n",
2046 - driver->name);
2047 driver->remove(pciedev);
2048 put_device(dev);
2049 }
2050 diff --git a/include/linux/pci.h b/include/linux/pci.h
2051 index 1b711796..6738d816 100644
2052 --- a/include/linux/pci.h
2053 +++ b/include/linux/pci.h
2054 @@ -1823,6 +1823,7 @@ void pcibios_release_device(struct pci_dev *dev);
2055 void pcibios_penalize_isa_irq(int irq, int active);
2056 int pcibios_alloc_irq(struct pci_dev *dev);
2057 void pcibios_free_irq(struct pci_dev *dev);
2058 +int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask);
2059
2060 #ifdef CONFIG_HIBERNATE_CALLBACKS
2061 extern struct dev_pm_ops pcibios_pm_ops;
2062 --
2063 2.14.1
2064
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