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[openwrt/staging/wigyori.git] / target / linux / mediatek / patches-4.19 / 0004-clk-mediatek-add-clock-support-for-MT7629-SoC.patch
1 From 3b5e748615e714711220b2a95d19bd25a037db09 Mon Sep 17 00:00:00 2001
2 From: Ryder Lee <ryder.lee@mediatek.com>
3 Date: Mon, 5 Nov 2018 16:43:55 +0800
4 Subject: [PATCH] clk: mediatek: add clock support for MT7629 SoC
5
6 Add all supported clocks exported from every susbystem found on MT7629 SoC.
7
8 Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
9 Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
10 Acked-by: Rob Herring <robh@kernel.org>
11 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
12 ---
13 drivers/clk/mediatek/Kconfig | 23 +
14 drivers/clk/mediatek/Makefile | 3 +
15 drivers/clk/mediatek/clk-mt7629-eth.c | 159 ++++++
16 drivers/clk/mediatek/clk-mt7629-hif.c | 156 ++++++
17 drivers/clk/mediatek/clk-mt7629.c | 723 +++++++++++++++++++++++++
18 include/dt-bindings/clock/mt7629-clk.h | 203 +++++++
19 6 files changed, 1267 insertions(+)
20 create mode 100644 drivers/clk/mediatek/clk-mt7629-eth.c
21 create mode 100644 drivers/clk/mediatek/clk-mt7629-hif.c
22 create mode 100644 drivers/clk/mediatek/clk-mt7629.c
23 create mode 100644 include/dt-bindings/clock/mt7629-clk.h
24
25 diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
26 index 3dd1dab92223..53edade25a1d 100644
27 --- a/drivers/clk/mediatek/Kconfig
28 +++ b/drivers/clk/mediatek/Kconfig
29 @@ -178,6 +178,29 @@ config COMMON_CLK_MT7622_AUDSYS
30 This driver supports MediaTek MT7622 AUDSYS clocks providing
31 to audio consumers such as I2S and TDM.
32
33 +config COMMON_CLK_MT7629
34 + bool "Clock driver for MediaTek MT7629"
35 + depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
36 + select COMMON_CLK_MEDIATEK
37 + default ARCH_MEDIATEK && ARM
38 + ---help---
39 + This driver supports MediaTek MT7629 basic clocks and clocks
40 + required for various periperals found on MediaTek.
41 +
42 +config COMMON_CLK_MT7629_ETHSYS
43 + bool "Clock driver for MediaTek MT7629 ETHSYS"
44 + depends on COMMON_CLK_MT7629
45 + ---help---
46 + This driver add support for clocks for Ethernet and SGMII
47 + required on MediaTek MT7629 SoC.
48 +
49 +config COMMON_CLK_MT7629_HIFSYS
50 + bool "Clock driver for MediaTek MT7629 HIFSYS"
51 + depends on COMMON_CLK_MT7629
52 + ---help---
53 + This driver supports MediaTek MT7629 HIFSYS clocks providing
54 + to PCI-E and USB.
55 +
56 config COMMON_CLK_MT8135
57 bool "Clock driver for MediaTek MT8135"
58 depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
59 diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
60 index 844b55d2770d..ee4410ff43ab 100644
61 --- a/drivers/clk/mediatek/Makefile
62 +++ b/drivers/clk/mediatek/Makefile
63 @@ -26,5 +26,8 @@ obj-$(CONFIG_COMMON_CLK_MT7622) += clk-mt7622.o
64 obj-$(CONFIG_COMMON_CLK_MT7622_ETHSYS) += clk-mt7622-eth.o
65 obj-$(CONFIG_COMMON_CLK_MT7622_HIFSYS) += clk-mt7622-hif.o
66 obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o
67 +obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
68 +obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
69 +obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
70 obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
71 obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
72 diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c
73 new file mode 100644
74 index 000000000000..88279d0ea1a7
75 --- /dev/null
76 +++ b/drivers/clk/mediatek/clk-mt7629-eth.c
77 @@ -0,0 +1,159 @@
78 +// SPDX-License-Identifier: GPL-2.0
79 +/*
80 + * Copyright (C) 2018 MediaTek Inc.
81 + * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
82 + * Ryder Lee <ryder.lee@mediatek.com>
83 + */
84 +
85 +#include <linux/clk-provider.h>
86 +#include <linux/of.h>
87 +#include <linux/of_address.h>
88 +#include <linux/of_device.h>
89 +#include <linux/platform_device.h>
90 +
91 +#include "clk-mtk.h"
92 +#include "clk-gate.h"
93 +
94 +#include <dt-bindings/clock/mt7629-clk.h>
95 +
96 +#define GATE_ETH(_id, _name, _parent, _shift) { \
97 + .id = _id, \
98 + .name = _name, \
99 + .parent_name = _parent, \
100 + .regs = &eth_cg_regs, \
101 + .shift = _shift, \
102 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
103 + }
104 +
105 +static const struct mtk_gate_regs eth_cg_regs = {
106 + .set_ofs = 0x30,
107 + .clr_ofs = 0x30,
108 + .sta_ofs = 0x30,
109 +};
110 +
111 +static const struct mtk_gate eth_clks[] = {
112 + GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "eth2pll", 6),
113 + GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
114 + GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
115 + GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
116 + GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 16),
117 +};
118 +
119 +static const struct mtk_gate_regs sgmii_cg_regs = {
120 + .set_ofs = 0xE4,
121 + .clr_ofs = 0xE4,
122 + .sta_ofs = 0xE4,
123 +};
124 +
125 +#define GATE_SGMII(_id, _name, _parent, _shift) { \
126 + .id = _id, \
127 + .name = _name, \
128 + .parent_name = _parent, \
129 + .regs = &sgmii_cg_regs, \
130 + .shift = _shift, \
131 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
132 + }
133 +
134 +static const struct mtk_gate sgmii_clks[2][4] = {
135 + {
136 + GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en",
137 + "ssusb_tx250m", 2),
138 + GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en",
139 + "ssusb_eq_rx250m", 3),
140 + GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
141 + "ssusb_cdr_ref", 4),
142 + GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
143 + "ssusb_cdr_fb", 5),
144 + }, {
145 + GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en1",
146 + "ssusb_tx250m", 2),
147 + GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en1",
148 + "ssusb_eq_rx250m", 3),
149 + GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref1",
150 + "ssusb_cdr_ref", 4),
151 + GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb1",
152 + "ssusb_cdr_fb", 5),
153 + }
154 +};
155 +
156 +static int clk_mt7629_ethsys_init(struct platform_device *pdev)
157 +{
158 + struct clk_onecell_data *clk_data;
159 + struct device_node *node = pdev->dev.of_node;
160 + int r;
161 +
162 + clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
163 +
164 + mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data);
165 +
166 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
167 + if (r)
168 + dev_err(&pdev->dev,
169 + "could not register clock provider: %s: %d\n",
170 + pdev->name, r);
171 +
172 + mtk_register_reset_controller(node, 1, 0x34);
173 +
174 + return r;
175 +}
176 +
177 +static int clk_mt7629_sgmiisys_init(struct platform_device *pdev)
178 +{
179 + struct clk_onecell_data *clk_data;
180 + struct device_node *node = pdev->dev.of_node;
181 + static int id;
182 + int r;
183 +
184 + clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
185 +
186 + mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK,
187 + clk_data);
188 +
189 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
190 + if (r)
191 + dev_err(&pdev->dev,
192 + "could not register clock provider: %s: %d\n",
193 + pdev->name, r);
194 +
195 + return r;
196 +}
197 +
198 +static const struct of_device_id of_match_clk_mt7629_eth[] = {
199 + {
200 + .compatible = "mediatek,mt7629-ethsys",
201 + .data = clk_mt7629_ethsys_init,
202 + }, {
203 + .compatible = "mediatek,mt7629-sgmiisys",
204 + .data = clk_mt7629_sgmiisys_init,
205 + }, {
206 + /* sentinel */
207 + }
208 +};
209 +
210 +static int clk_mt7629_eth_probe(struct platform_device *pdev)
211 +{
212 + int (*clk_init)(struct platform_device *);
213 + int r;
214 +
215 + clk_init = of_device_get_match_data(&pdev->dev);
216 + if (!clk_init)
217 + return -EINVAL;
218 +
219 + r = clk_init(pdev);
220 + if (r)
221 + dev_err(&pdev->dev,
222 + "could not register clock provider: %s: %d\n",
223 + pdev->name, r);
224 +
225 + return r;
226 +}
227 +
228 +static struct platform_driver clk_mt7629_eth_drv = {
229 + .probe = clk_mt7629_eth_probe,
230 + .driver = {
231 + .name = "clk-mt7629-eth",
232 + .of_match_table = of_match_clk_mt7629_eth,
233 + },
234 +};
235 +
236 +builtin_platform_driver(clk_mt7629_eth_drv);
237 diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c
238 new file mode 100644
239 index 000000000000..5c5b37207afb
240 --- /dev/null
241 +++ b/drivers/clk/mediatek/clk-mt7629-hif.c
242 @@ -0,0 +1,156 @@
243 +// SPDX-License-Identifier: GPL-2.0
244 +/*
245 + * Copyright (C) 2018 MediaTek Inc.
246 + * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
247 + * Ryder Lee <ryder.lee@mediatek.com>
248 + */
249 +
250 +#include <linux/clk-provider.h>
251 +#include <linux/of.h>
252 +#include <linux/of_address.h>
253 +#include <linux/of_device.h>
254 +#include <linux/platform_device.h>
255 +
256 +#include "clk-mtk.h"
257 +#include "clk-gate.h"
258 +
259 +#include <dt-bindings/clock/mt7629-clk.h>
260 +
261 +#define GATE_PCIE(_id, _name, _parent, _shift) { \
262 + .id = _id, \
263 + .name = _name, \
264 + .parent_name = _parent, \
265 + .regs = &pcie_cg_regs, \
266 + .shift = _shift, \
267 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
268 + }
269 +
270 +#define GATE_SSUSB(_id, _name, _parent, _shift) { \
271 + .id = _id, \
272 + .name = _name, \
273 + .parent_name = _parent, \
274 + .regs = &ssusb_cg_regs, \
275 + .shift = _shift, \
276 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
277 + }
278 +
279 +static const struct mtk_gate_regs pcie_cg_regs = {
280 + .set_ofs = 0x30,
281 + .clr_ofs = 0x30,
282 + .sta_ofs = 0x30,
283 +};
284 +
285 +static const struct mtk_gate_regs ssusb_cg_regs = {
286 + .set_ofs = 0x30,
287 + .clr_ofs = 0x30,
288 + .sta_ofs = 0x30,
289 +};
290 +
291 +static const struct mtk_gate ssusb_clks[] = {
292 + GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
293 + "to_u2_phy_1p", 0),
294 + GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
295 + GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
296 + GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
297 + GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "to_usb3_mcu", 7),
298 + GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "to_usb3_dma", 8),
299 +};
300 +
301 +static const struct mtk_gate pcie_clks[] = {
302 + GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
303 + GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
304 + GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "from_top_ahb", 14),
305 + GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "from_top_axi", 15),
306 + GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
307 + GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
308 + GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
309 + GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
310 + GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "from_top_ahb", 20),
311 + GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "from_top_axi", 21),
312 + GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
313 + GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
314 +};
315 +
316 +static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
317 +{
318 + struct clk_onecell_data *clk_data;
319 + struct device_node *node = pdev->dev.of_node;
320 + int r;
321 +
322 + clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
323 +
324 + mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
325 + clk_data);
326 +
327 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
328 + if (r)
329 + dev_err(&pdev->dev,
330 + "could not register clock provider: %s: %d\n",
331 + pdev->name, r);
332 +
333 + mtk_register_reset_controller(node, 1, 0x34);
334 +
335 + return r;
336 +}
337 +
338 +static int clk_mt7629_pciesys_init(struct platform_device *pdev)
339 +{
340 + struct clk_onecell_data *clk_data;
341 + struct device_node *node = pdev->dev.of_node;
342 + int r;
343 +
344 + clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
345 +
346 + mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
347 + clk_data);
348 +
349 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
350 + if (r)
351 + dev_err(&pdev->dev,
352 + "could not register clock provider: %s: %d\n",
353 + pdev->name, r);
354 +
355 + mtk_register_reset_controller(node, 1, 0x34);
356 +
357 + return r;
358 +}
359 +
360 +static const struct of_device_id of_match_clk_mt7629_hif[] = {
361 + {
362 + .compatible = "mediatek,mt7629-pciesys",
363 + .data = clk_mt7629_pciesys_init,
364 + }, {
365 + .compatible = "mediatek,mt7629-ssusbsys",
366 + .data = clk_mt7629_ssusbsys_init,
367 + }, {
368 + /* sentinel */
369 + }
370 +};
371 +
372 +static int clk_mt7629_hif_probe(struct platform_device *pdev)
373 +{
374 + int (*clk_init)(struct platform_device *);
375 + int r;
376 +
377 + clk_init = of_device_get_match_data(&pdev->dev);
378 + if (!clk_init)
379 + return -EINVAL;
380 +
381 + r = clk_init(pdev);
382 + if (r)
383 + dev_err(&pdev->dev,
384 + "could not register clock provider: %s: %d\n",
385 + pdev->name, r);
386 +
387 + return r;
388 +}
389 +
390 +static struct platform_driver clk_mt7629_hif_drv = {
391 + .probe = clk_mt7629_hif_probe,
392 + .driver = {
393 + .name = "clk-mt7629-hif",
394 + .of_match_table = of_match_clk_mt7629_hif,
395 + },
396 +};
397 +
398 +builtin_platform_driver(clk_mt7629_hif_drv);
399 diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
400 new file mode 100644
401 index 000000000000..200ba147bbc6
402 --- /dev/null
403 +++ b/drivers/clk/mediatek/clk-mt7629.c
404 @@ -0,0 +1,723 @@
405 +// SPDX-License-Identifier: GPL-2.0
406 +/*
407 + * Copyright (C) 2018 MediaTek Inc.
408 + * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
409 + * Ryder Lee <ryder.lee@mediatek.com>
410 + */
411 +
412 +#include <linux/clk.h>
413 +#include <linux/clk-provider.h>
414 +#include <linux/of.h>
415 +#include <linux/of_address.h>
416 +#include <linux/of_device.h>
417 +#include <linux/platform_device.h>
418 +
419 +#include "clk-mtk.h"
420 +#include "clk-gate.h"
421 +#include "clk-cpumux.h"
422 +
423 +#include <dt-bindings/clock/mt7629-clk.h>
424 +
425 +#define MT7629_PLL_FMAX (2500UL * MHZ)
426 +#define CON0_MT7629_RST_BAR BIT(24)
427 +
428 +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
429 + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
430 + _pcw_shift, _div_table, _parent_name) { \
431 + .id = _id, \
432 + .name = _name, \
433 + .reg = _reg, \
434 + .pwr_reg = _pwr_reg, \
435 + .en_mask = _en_mask, \
436 + .flags = _flags, \
437 + .rst_bar_mask = CON0_MT7629_RST_BAR, \
438 + .fmax = MT7629_PLL_FMAX, \
439 + .pcwbits = _pcwbits, \
440 + .pd_reg = _pd_reg, \
441 + .pd_shift = _pd_shift, \
442 + .tuner_reg = _tuner_reg, \
443 + .pcw_reg = _pcw_reg, \
444 + .pcw_shift = _pcw_shift, \
445 + .div_table = _div_table, \
446 + .parent_name = _parent_name, \
447 + }
448 +
449 +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
450 + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
451 + _pcw_shift) \
452 + PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
453 + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
454 + NULL, "clk20m")
455 +
456 +#define GATE_APMIXED(_id, _name, _parent, _shift) { \
457 + .id = _id, \
458 + .name = _name, \
459 + .parent_name = _parent, \
460 + .regs = &apmixed_cg_regs, \
461 + .shift = _shift, \
462 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
463 + }
464 +
465 +#define GATE_INFRA(_id, _name, _parent, _shift) { \
466 + .id = _id, \
467 + .name = _name, \
468 + .parent_name = _parent, \
469 + .regs = &infra_cg_regs, \
470 + .shift = _shift, \
471 + .ops = &mtk_clk_gate_ops_setclr, \
472 + }
473 +
474 +#define GATE_PERI0(_id, _name, _parent, _shift) { \
475 + .id = _id, \
476 + .name = _name, \
477 + .parent_name = _parent, \
478 + .regs = &peri0_cg_regs, \
479 + .shift = _shift, \
480 + .ops = &mtk_clk_gate_ops_setclr, \
481 + }
482 +
483 +#define GATE_PERI1(_id, _name, _parent, _shift) { \
484 + .id = _id, \
485 + .name = _name, \
486 + .parent_name = _parent, \
487 + .regs = &peri1_cg_regs, \
488 + .shift = _shift, \
489 + .ops = &mtk_clk_gate_ops_setclr, \
490 + }
491 +
492 +static DEFINE_SPINLOCK(mt7629_clk_lock);
493 +
494 +static const char * const axi_parents[] = {
495 + "clkxtal",
496 + "syspll1_d2",
497 + "syspll_d5",
498 + "syspll1_d4",
499 + "univpll_d5",
500 + "univpll2_d2",
501 + "univpll_d7",
502 + "dmpll_ck"
503 +};
504 +
505 +static const char * const mem_parents[] = {
506 + "clkxtal",
507 + "dmpll_ck"
508 +};
509 +
510 +static const char * const ddrphycfg_parents[] = {
511 + "clkxtal",
512 + "syspll1_d8"
513 +};
514 +
515 +static const char * const eth_parents[] = {
516 + "clkxtal",
517 + "syspll1_d2",
518 + "univpll1_d2",
519 + "syspll1_d4",
520 + "univpll_d5",
521 + "sgmiipll_d2",
522 + "univpll_d7",
523 + "dmpll_ck"
524 +};
525 +
526 +static const char * const pwm_parents[] = {
527 + "clkxtal",
528 + "univpll2_d4"
529 +};
530 +
531 +static const char * const f10m_ref_parents[] = {
532 + "clkxtal",
533 + "sgmiipll_d2"
534 +};
535 +
536 +static const char * const nfi_infra_parents[] = {
537 + "clkxtal",
538 + "clkxtal",
539 + "clkxtal",
540 + "clkxtal",
541 + "clkxtal",
542 + "clkxtal",
543 + "univpll2_d8",
544 + "univpll3_d4",
545 + "syspll1_d8",
546 + "univpll1_d8",
547 + "syspll4_d2",
548 + "syspll2_d4",
549 + "univpll2_d4",
550 + "univpll3_d2",
551 + "syspll1_d4",
552 + "syspll_d7"
553 +};
554 +
555 +static const char * const flash_parents[] = {
556 + "clkxtal",
557 + "univpll_d80_d4",
558 + "syspll2_d8",
559 + "syspll3_d4",
560 + "univpll3_d4",
561 + "univpll1_d8",
562 + "syspll2_d4",
563 + "univpll2_d4"
564 +};
565 +
566 +static const char * const uart_parents[] = {
567 + "clkxtal",
568 + "univpll2_d8"
569 +};
570 +
571 +static const char * const spi0_parents[] = {
572 + "clkxtal",
573 + "syspll3_d2",
574 + "clkxtal",
575 + "syspll2_d4",
576 + "syspll4_d2",
577 + "univpll2_d4",
578 + "univpll1_d8",
579 + "clkxtal"
580 +};
581 +
582 +static const char * const spi1_parents[] = {
583 + "clkxtal",
584 + "syspll3_d2",
585 + "clkxtal",
586 + "syspll4_d4",
587 + "syspll4_d2",
588 + "univpll2_d4",
589 + "univpll1_d8",
590 + "clkxtal"
591 +};
592 +
593 +static const char * const msdc30_0_parents[] = {
594 + "clkxtal",
595 + "univpll2_d16",
596 + "univ48m"
597 +};
598 +
599 +static const char * const msdc30_1_parents[] = {
600 + "clkxtal",
601 + "univpll2_d16",
602 + "univ48m",
603 + "syspll2_d4",
604 + "univpll2_d4",
605 + "syspll_d7",
606 + "syspll2_d2",
607 + "univpll2_d2"
608 +};
609 +
610 +static const char * const ap2wbmcu_parents[] = {
611 + "clkxtal",
612 + "syspll1_d2",
613 + "univ48m",
614 + "syspll1_d8",
615 + "univpll2_d4",
616 + "syspll_d7",
617 + "syspll2_d2",
618 + "univpll2_d2"
619 +};
620 +
621 +static const char * const audio_parents[] = {
622 + "clkxtal",
623 + "syspll3_d4",
624 + "syspll4_d4",
625 + "syspll1_d16"
626 +};
627 +
628 +static const char * const aud_intbus_parents[] = {
629 + "clkxtal",
630 + "syspll1_d4",
631 + "syspll4_d2",
632 + "dmpll_d4"
633 +};
634 +
635 +static const char * const pmicspi_parents[] = {
636 + "clkxtal",
637 + "syspll1_d8",
638 + "syspll3_d4",
639 + "syspll1_d16",
640 + "univpll3_d4",
641 + "clkxtal",
642 + "univpll2_d4",
643 + "dmpll_d8"
644 +};
645 +
646 +static const char * const scp_parents[] = {
647 + "clkxtal",
648 + "syspll1_d8",
649 + "univpll2_d2",
650 + "univpll2_d4"
651 +};
652 +
653 +static const char * const atb_parents[] = {
654 + "clkxtal",
655 + "syspll1_d2",
656 + "syspll_d5"
657 +};
658 +
659 +static const char * const hif_parents[] = {
660 + "clkxtal",
661 + "syspll1_d2",
662 + "univpll1_d2",
663 + "syspll1_d4",
664 + "univpll_d5",
665 + "clk_null",
666 + "univpll_d7"
667 +};
668 +
669 +static const char * const sata_parents[] = {
670 + "clkxtal",
671 + "univpll2_d4"
672 +};
673 +
674 +static const char * const usb20_parents[] = {
675 + "clkxtal",
676 + "univpll3_d4",
677 + "syspll1_d8"
678 +};
679 +
680 +static const char * const aud1_parents[] = {
681 + "clkxtal"
682 +};
683 +
684 +static const char * const irrx_parents[] = {
685 + "clkxtal",
686 + "syspll4_d16"
687 +};
688 +
689 +static const char * const crypto_parents[] = {
690 + "clkxtal",
691 + "univpll_d3",
692 + "univpll1_d2",
693 + "syspll1_d2",
694 + "univpll_d5",
695 + "syspll_d5",
696 + "univpll2_d2",
697 + "syspll_d2"
698 +};
699 +
700 +static const char * const gpt10m_parents[] = {
701 + "clkxtal",
702 + "clkxtal_d4"
703 +};
704 +
705 +static const char * const peribus_ck_parents[] = {
706 + "syspll1_d8",
707 + "syspll1_d4"
708 +};
709 +
710 +static const char * const infra_mux1_parents[] = {
711 + "clkxtal",
712 + "armpll",
713 + "main_core_en",
714 + "armpll"
715 +};
716 +
717 +static const struct mtk_gate_regs apmixed_cg_regs = {
718 + .set_ofs = 0x8,
719 + .clr_ofs = 0x8,
720 + .sta_ofs = 0x8,
721 +};
722 +
723 +static const struct mtk_gate_regs infra_cg_regs = {
724 + .set_ofs = 0x40,
725 + .clr_ofs = 0x44,
726 + .sta_ofs = 0x48,
727 +};
728 +
729 +static const struct mtk_gate_regs peri0_cg_regs = {
730 + .set_ofs = 0x8,
731 + .clr_ofs = 0x10,
732 + .sta_ofs = 0x18,
733 +};
734 +
735 +static const struct mtk_gate_regs peri1_cg_regs = {
736 + .set_ofs = 0xC,
737 + .clr_ofs = 0x14,
738 + .sta_ofs = 0x1C,
739 +};
740 +
741 +static const struct mtk_pll_data plls[] = {
742 + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
743 + 0, 21, 0x0204, 24, 0, 0x0204, 0),
744 + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
745 + HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
746 + PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
747 + HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
748 + PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
749 + 0, 21, 0x0300, 1, 0, 0x0304, 0),
750 + PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
751 + 0, 21, 0x0314, 1, 0, 0x0318, 0),
752 + PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
753 + 0, 21, 0x0358, 1, 0, 0x035C, 0),
754 +};
755 +
756 +static const struct mtk_gate apmixed_clks[] = {
757 + GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
758 +};
759 +
760 +static const struct mtk_gate infra_clks[] = {
761 + GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "hd_faxi", 0),
762 + GATE_INFRA(CLK_INFRA_TRNG_PD, "infra_trng_pd", "hd_faxi", 2),
763 + GATE_INFRA(CLK_INFRA_DEVAPC_PD, "infra_devapc_pd", "hd_faxi", 4),
764 + GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "infrao_10m", 18),
765 + GATE_INFRA(CLK_INFRA_SEJ_PD, "infra_sej_pd", "infrao_10m", 19),
766 +};
767 +
768 +static const struct mtk_fixed_clk top_fixed_clks[] = {
769 + FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
770 + 31250000),
771 + FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
772 + 31250000),
773 + FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
774 + 125000000),
775 + FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
776 + 125000000),
777 + FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
778 + 250000000),
779 + FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
780 + 250000000),
781 + FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
782 + 33333333),
783 + FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
784 + 50000000),
785 + FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
786 + 50000000),
787 + FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
788 + 50000000),
789 +};
790 +
791 +static const struct mtk_fixed_factor top_divs[] = {
792 + FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
793 + FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
794 + FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
795 + FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
796 + FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
797 + FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
798 + FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
799 + FACTOR(CLK_TOP_PWM_QTR_26M, "pwm_qtr_26m", "clkxtal", 1, 1),
800 + FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "cpum_tck", 1, 1),
801 + FACTOR(CLK_TOP_TO_USB3_DA_TOP, "to_usb3_da_top", "clkxtal", 1, 1),
802 + FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
803 + FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
804 + FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "mempll", 1, 4),
805 + FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "mempll", 1, 8),
806 + FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
807 + FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
808 + FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
809 + FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
810 + FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32),
811 + FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6),
812 + FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
813 + FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
814 + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
815 + FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
816 + FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
817 + FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
818 + FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
819 + FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
820 + FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
821 + FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
822 + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
823 + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
824 + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
825 + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
826 + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
827 + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
828 + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
829 + FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
830 + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
831 + FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
832 + FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
833 + FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
834 + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
835 + FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
836 + FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
837 + FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
838 + FACTOR(CLK_TOP_CLKXTAL_D4, "clkxtal_d4", "clkxtal", 1, 4),
839 + FACTOR(CLK_TOP_HD_FAXI, "hd_faxi", "axi_sel", 1, 1),
840 + FACTOR(CLK_TOP_FAXI, "faxi", "axi_sel", 1, 1),
841 + FACTOR(CLK_TOP_F_FAUD_INTBUS, "f_faud_intbus", "aud_intbus_sel", 1, 1),
842 + FACTOR(CLK_TOP_AP2WBHIF_HCLK, "ap2wbhif_hclk", "syspll1_d8", 1, 1),
843 + FACTOR(CLK_TOP_10M_INFRAO, "infrao_10m", "gpt10m_sel", 1, 1),
844 + FACTOR(CLK_TOP_MSDC30_1, "msdc30_1", "msdc30_1_sel", 1, 1),
845 + FACTOR(CLK_TOP_SPI, "spi", "spi0_sel", 1, 1),
846 + FACTOR(CLK_TOP_SF, "sf", "nfi_infra_sel", 1, 1),
847 + FACTOR(CLK_TOP_FLASH, "flash", "flash_sel", 1, 1),
848 + FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "sata_sel", 1, 4),
849 + FACTOR(CLK_TOP_TO_USB3_MCU, "to_usb3_mcu", "axi_sel", 1, 1),
850 + FACTOR(CLK_TOP_TO_USB3_DMA, "to_usb3_dma", "hif_sel", 1, 1),
851 + FACTOR(CLK_TOP_FROM_TOP_AHB, "from_top_ahb", "axi_sel", 1, 1),
852 + FACTOR(CLK_TOP_FROM_TOP_AXI, "from_top_axi", "hif_sel", 1, 1),
853 + FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1),
854 + FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1),
855 +};
856 +
857 +static const struct mtk_gate peri_clks[] = {
858 + /* PERI0 */
859 + GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "pwm_qtr_26m", 2),
860 + GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "pwm_qtr_26m", 3),
861 + GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "pwm_qtr_26m", 4),
862 + GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "pwm_qtr_26m", 5),
863 + GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "pwm_qtr_26m", 6),
864 + GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "pwm_qtr_26m", 7),
865 + GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "pwm_qtr_26m", 8),
866 + GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "pwm_qtr_26m", 9),
867 + GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "faxi", 12),
868 + GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1", 14),
869 + GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "faxi", 17),
870 + GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "faxi", 18),
871 + GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "faxi", 19),
872 + GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "faxi", 20),
873 + GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "faxi", 22),
874 + GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "faxi", 23),
875 + GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi", 28),
876 + GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "sf", 29),
877 + GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "faxi", 30),
878 + GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "faxi", 31),
879 + /* PERI1 */
880 + GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash", 1),
881 +};
882 +
883 +static struct mtk_composite infra_muxes[] = {
884 + /* INFRA_TOPCKGEN_CKMUXSEL */
885 + MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000,
886 + 2, 2),
887 +};
888 +
889 +static struct mtk_composite top_muxes[] = {
890 + /* CLK_CFG_0 */
891 + MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
892 + 0x040, 0, 3, 7),
893 + MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
894 + 0x040, 8, 1, 15),
895 + MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
896 + 0x040, 16, 1, 23),
897 + MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
898 + 0x040, 24, 3, 31),
899 + /* CLK_CFG_1 */
900 + MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
901 + 0x050, 0, 2, 7),
902 + MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
903 + 0x050, 8, 1, 15),
904 + MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
905 + 0x050, 16, 4, 23),
906 + MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
907 + 0x050, 24, 3, 31),
908 + /* CLK_CFG_2 */
909 + MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
910 + 0x060, 0, 1, 7),
911 + MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
912 + 0x060, 8, 3, 15),
913 + MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
914 + 0x060, 16, 3, 23),
915 + MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
916 + 0x060, 24, 3, 31),
917 + /* CLK_CFG_3 */
918 + MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
919 + 0x070, 0, 3, 7),
920 + MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
921 + 0x070, 8, 3, 15),
922 + MUX_GATE(CLK_TOP_AP2WBMCU_SEL, "ap2wbmcu_sel", ap2wbmcu_parents,
923 + 0x070, 16, 3, 23),
924 + MUX_GATE(CLK_TOP_AP2WBHIF_SEL, "ap2wbhif_sel", ap2wbmcu_parents,
925 + 0x070, 24, 3, 31),
926 + /* CLK_CFG_4 */
927 + MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
928 + 0x080, 0, 2, 7),
929 + MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
930 + 0x080, 8, 2, 15),
931 + MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
932 + 0x080, 16, 3, 23),
933 + MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
934 + 0x080, 24, 2, 31),
935 + /* CLK_CFG_5 */
936 + MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
937 + 0x090, 0, 2, 7),
938 + MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", hif_parents,
939 + 0x090, 8, 3, 15),
940 + MUX_GATE(CLK_TOP_SATA_SEL, "sata_sel", sata_parents,
941 + 0x090, 16, 1, 23),
942 + MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
943 + 0x090, 24, 2, 31),
944 + /* CLK_CFG_6 */
945 + MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
946 + 0x0A0, 0, 1, 7),
947 + MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud1_parents,
948 + 0x0A0, 8, 1, 15),
949 + MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", irrx_parents,
950 + 0x0A0, 16, 1, 23),
951 + MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", irrx_parents,
952 + 0x0A0, 24, 1, 31),
953 + /* CLK_CFG_7 */
954 + MUX_GATE(CLK_TOP_SATA_MCU_SEL, "sata_mcu_sel", scp_parents,
955 + 0x0B0, 0, 2, 7),
956 + MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, "pcie0_mcu_sel", scp_parents,
957 + 0x0B0, 8, 2, 15),
958 + MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, "pcie1_mcu_sel", scp_parents,
959 + 0x0B0, 16, 2, 23),
960 + MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, "ssusb_mcu_sel", scp_parents,
961 + 0x0B0, 24, 2, 31),
962 + /* CLK_CFG_8 */
963 + MUX_GATE(CLK_TOP_CRYPTO_SEL, "crypto_sel", crypto_parents,
964 + 0x0C0, 0, 3, 7),
965 + MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, "sgmii_ref_1_sel", f10m_ref_parents,
966 + 0x0C0, 8, 1, 15),
967 + MUX_GATE(CLK_TOP_10M_SEL, "gpt10m_sel", gpt10m_parents,
968 + 0x0C0, 16, 1, 23),
969 +};
970 +
971 +static struct mtk_composite peri_muxes[] = {
972 + /* PERI_GLOBALCON_CKSEL */
973 + MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
974 +};
975 +
976 +static int mtk_topckgen_init(struct platform_device *pdev)
977 +{
978 + struct clk_onecell_data *clk_data;
979 + void __iomem *base;
980 + struct device_node *node = pdev->dev.of_node;
981 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
982 +
983 + base = devm_ioremap_resource(&pdev->dev, res);
984 + if (IS_ERR(base))
985 + return PTR_ERR(base);
986 +
987 + clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
988 +
989 + mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
990 + clk_data);
991 +
992 + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
993 + clk_data);
994 +
995 + mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
996 + base, &mt7629_clk_lock, clk_data);
997 +
998 + clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]);
999 + clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]);
1000 + clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
1001 +
1002 + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1003 +}
1004 +
1005 +static int mtk_infrasys_init(struct platform_device *pdev)
1006 +{
1007 + struct device_node *node = pdev->dev.of_node;
1008 + struct clk_onecell_data *clk_data;
1009 + int r;
1010 +
1011 + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1012 +
1013 + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1014 + clk_data);
1015 +
1016 + mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
1017 + clk_data);
1018 +
1019 + r = of_clk_add_provider(node, of_clk_src_onecell_get,
1020 + clk_data);
1021 + if (r)
1022 + return r;
1023 +
1024 + return 0;
1025 +}
1026 +
1027 +static int mtk_pericfg_init(struct platform_device *pdev)
1028 +{
1029 + struct clk_onecell_data *clk_data;
1030 + void __iomem *base;
1031 + int r;
1032 + struct device_node *node = pdev->dev.of_node;
1033 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1034 +
1035 + base = devm_ioremap_resource(&pdev->dev, res);
1036 + if (IS_ERR(base))
1037 + return PTR_ERR(base);
1038 +
1039 + clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
1040 +
1041 + mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
1042 + clk_data);
1043 +
1044 + mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
1045 + &mt7629_clk_lock, clk_data);
1046 +
1047 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1048 + if (r)
1049 + return r;
1050 +
1051 + clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
1052 +
1053 + return 0;
1054 +}
1055 +
1056 +static int mtk_apmixedsys_init(struct platform_device *pdev)
1057 +{
1058 + struct clk_onecell_data *clk_data;
1059 + struct device_node *node = pdev->dev.of_node;
1060 +
1061 + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1062 + if (!clk_data)
1063 + return -ENOMEM;
1064 +
1065 + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
1066 + clk_data);
1067 +
1068 + mtk_clk_register_gates(node, apmixed_clks,
1069 + ARRAY_SIZE(apmixed_clks), clk_data);
1070 +
1071 + clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
1072 + clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]);
1073 +
1074 + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1075 +}
1076 +
1077 +
1078 +static const struct of_device_id of_match_clk_mt7629[] = {
1079 + {
1080 + .compatible = "mediatek,mt7629-apmixedsys",
1081 + .data = mtk_apmixedsys_init,
1082 + }, {
1083 + .compatible = "mediatek,mt7629-infracfg",
1084 + .data = mtk_infrasys_init,
1085 + }, {
1086 + .compatible = "mediatek,mt7629-topckgen",
1087 + .data = mtk_topckgen_init,
1088 + }, {
1089 + .compatible = "mediatek,mt7629-pericfg",
1090 + .data = mtk_pericfg_init,
1091 + }, {
1092 + /* sentinel */
1093 + }
1094 +};
1095 +
1096 +static int clk_mt7629_probe(struct platform_device *pdev)
1097 +{
1098 + int (*clk_init)(struct platform_device *);
1099 + int r;
1100 +
1101 + clk_init = of_device_get_match_data(&pdev->dev);
1102 + if (!clk_init)
1103 + return -EINVAL;
1104 +
1105 + r = clk_init(pdev);
1106 + if (r)
1107 + dev_err(&pdev->dev,
1108 + "could not register clock provider: %s: %d\n",
1109 + pdev->name, r);
1110 +
1111 + return r;
1112 +}
1113 +
1114 +static struct platform_driver clk_mt7629_drv = {
1115 + .probe = clk_mt7629_probe,
1116 + .driver = {
1117 + .name = "clk-mt7629",
1118 + .of_match_table = of_match_clk_mt7629,
1119 + },
1120 +};
1121 +
1122 +static int clk_mt7629_init(void)
1123 +{
1124 + return platform_driver_register(&clk_mt7629_drv);
1125 +}
1126 +
1127 +arch_initcall(clk_mt7629_init);
1128 diff --git a/include/dt-bindings/clock/mt7629-clk.h b/include/dt-bindings/clock/mt7629-clk.h
1129 new file mode 100644
1130 index 000000000000..ad8e6d7f0154
1131 --- /dev/null
1132 +++ b/include/dt-bindings/clock/mt7629-clk.h
1133 @@ -0,0 +1,203 @@
1134 +/* SPDX-License-Identifier: GPL-2.0 */
1135 +/*
1136 + * Copyright (C) 2018 MediaTek Inc.
1137 + */
1138 +
1139 +#ifndef _DT_BINDINGS_CLK_MT7629_H
1140 +#define _DT_BINDINGS_CLK_MT7629_H
1141 +
1142 +/* TOPCKGEN */
1143 +#define CLK_TOP_TO_U2_PHY 0
1144 +#define CLK_TOP_TO_U2_PHY_1P 1
1145 +#define CLK_TOP_PCIE0_PIPE_EN 2
1146 +#define CLK_TOP_PCIE1_PIPE_EN 3
1147 +#define CLK_TOP_SSUSB_TX250M 4
1148 +#define CLK_TOP_SSUSB_EQ_RX250M 5
1149 +#define CLK_TOP_SSUSB_CDR_REF 6
1150 +#define CLK_TOP_SSUSB_CDR_FB 7
1151 +#define CLK_TOP_SATA_ASIC 8
1152 +#define CLK_TOP_SATA_RBC 9
1153 +#define CLK_TOP_TO_USB3_SYS 10
1154 +#define CLK_TOP_P1_1MHZ 11
1155 +#define CLK_TOP_4MHZ 12
1156 +#define CLK_TOP_P0_1MHZ 13
1157 +#define CLK_TOP_ETH_500M 14
1158 +#define CLK_TOP_TXCLK_SRC_PRE 15
1159 +#define CLK_TOP_RTC 16
1160 +#define CLK_TOP_PWM_QTR_26M 17
1161 +#define CLK_TOP_CPUM_TCK_IN 18
1162 +#define CLK_TOP_TO_USB3_DA_TOP 19
1163 +#define CLK_TOP_MEMPLL 20
1164 +#define CLK_TOP_DMPLL 21
1165 +#define CLK_TOP_DMPLL_D4 22
1166 +#define CLK_TOP_DMPLL_D8 23
1167 +#define CLK_TOP_SYSPLL_D2 24
1168 +#define CLK_TOP_SYSPLL1_D2 25
1169 +#define CLK_TOP_SYSPLL1_D4 26
1170 +#define CLK_TOP_SYSPLL1_D8 27
1171 +#define CLK_TOP_SYSPLL1_D16 28
1172 +#define CLK_TOP_SYSPLL2_D2 29
1173 +#define CLK_TOP_SYSPLL2_D4 30
1174 +#define CLK_TOP_SYSPLL2_D8 31
1175 +#define CLK_TOP_SYSPLL_D5 32
1176 +#define CLK_TOP_SYSPLL3_D2 33
1177 +#define CLK_TOP_SYSPLL3_D4 34
1178 +#define CLK_TOP_SYSPLL_D7 35
1179 +#define CLK_TOP_SYSPLL4_D2 36
1180 +#define CLK_TOP_SYSPLL4_D4 37
1181 +#define CLK_TOP_SYSPLL4_D16 38
1182 +#define CLK_TOP_UNIVPLL 39
1183 +#define CLK_TOP_UNIVPLL1_D2 40
1184 +#define CLK_TOP_UNIVPLL1_D4 41
1185 +#define CLK_TOP_UNIVPLL1_D8 42
1186 +#define CLK_TOP_UNIVPLL_D3 43
1187 +#define CLK_TOP_UNIVPLL2_D2 44
1188 +#define CLK_TOP_UNIVPLL2_D4 45
1189 +#define CLK_TOP_UNIVPLL2_D8 46
1190 +#define CLK_TOP_UNIVPLL2_D16 47
1191 +#define CLK_TOP_UNIVPLL_D5 48
1192 +#define CLK_TOP_UNIVPLL3_D2 49
1193 +#define CLK_TOP_UNIVPLL3_D4 50
1194 +#define CLK_TOP_UNIVPLL3_D16 51
1195 +#define CLK_TOP_UNIVPLL_D7 52
1196 +#define CLK_TOP_UNIVPLL_D80_D4 53
1197 +#define CLK_TOP_UNIV48M 54
1198 +#define CLK_TOP_SGMIIPLL_D2 55
1199 +#define CLK_TOP_CLKXTAL_D4 56
1200 +#define CLK_TOP_HD_FAXI 57
1201 +#define CLK_TOP_FAXI 58
1202 +#define CLK_TOP_F_FAUD_INTBUS 59
1203 +#define CLK_TOP_AP2WBHIF_HCLK 60
1204 +#define CLK_TOP_10M_INFRAO 61
1205 +#define CLK_TOP_MSDC30_1 62
1206 +#define CLK_TOP_SPI 63
1207 +#define CLK_TOP_SF 64
1208 +#define CLK_TOP_FLASH 65
1209 +#define CLK_TOP_TO_USB3_REF 66
1210 +#define CLK_TOP_TO_USB3_MCU 67
1211 +#define CLK_TOP_TO_USB3_DMA 68
1212 +#define CLK_TOP_FROM_TOP_AHB 69
1213 +#define CLK_TOP_FROM_TOP_AXI 70
1214 +#define CLK_TOP_PCIE1_MAC_EN 71
1215 +#define CLK_TOP_PCIE0_MAC_EN 72
1216 +#define CLK_TOP_AXI_SEL 73
1217 +#define CLK_TOP_MEM_SEL 74
1218 +#define CLK_TOP_DDRPHYCFG_SEL 75
1219 +#define CLK_TOP_ETH_SEL 76
1220 +#define CLK_TOP_PWM_SEL 77
1221 +#define CLK_TOP_F10M_REF_SEL 78
1222 +#define CLK_TOP_NFI_INFRA_SEL 79
1223 +#define CLK_TOP_FLASH_SEL 80
1224 +#define CLK_TOP_UART_SEL 81
1225 +#define CLK_TOP_SPI0_SEL 82
1226 +#define CLK_TOP_SPI1_SEL 83
1227 +#define CLK_TOP_MSDC50_0_SEL 84
1228 +#define CLK_TOP_MSDC30_0_SEL 85
1229 +#define CLK_TOP_MSDC30_1_SEL 86
1230 +#define CLK_TOP_AP2WBMCU_SEL 87
1231 +#define CLK_TOP_AP2WBHIF_SEL 88
1232 +#define CLK_TOP_AUDIO_SEL 89
1233 +#define CLK_TOP_AUD_INTBUS_SEL 90
1234 +#define CLK_TOP_PMICSPI_SEL 91
1235 +#define CLK_TOP_SCP_SEL 92
1236 +#define CLK_TOP_ATB_SEL 93
1237 +#define CLK_TOP_HIF_SEL 94
1238 +#define CLK_TOP_SATA_SEL 95
1239 +#define CLK_TOP_U2_SEL 96
1240 +#define CLK_TOP_AUD1_SEL 97
1241 +#define CLK_TOP_AUD2_SEL 98
1242 +#define CLK_TOP_IRRX_SEL 99
1243 +#define CLK_TOP_IRTX_SEL 100
1244 +#define CLK_TOP_SATA_MCU_SEL 101
1245 +#define CLK_TOP_PCIE0_MCU_SEL 102
1246 +#define CLK_TOP_PCIE1_MCU_SEL 103
1247 +#define CLK_TOP_SSUSB_MCU_SEL 104
1248 +#define CLK_TOP_CRYPTO_SEL 105
1249 +#define CLK_TOP_SGMII_REF_1_SEL 106
1250 +#define CLK_TOP_10M_SEL 107
1251 +#define CLK_TOP_NR_CLK 108
1252 +
1253 +/* INFRACFG */
1254 +#define CLK_INFRA_MUX1_SEL 0
1255 +#define CLK_INFRA_DBGCLK_PD 1
1256 +#define CLK_INFRA_TRNG_PD 2
1257 +#define CLK_INFRA_DEVAPC_PD 3
1258 +#define CLK_INFRA_APXGPT_PD 4
1259 +#define CLK_INFRA_SEJ_PD 5
1260 +#define CLK_INFRA_NR_CLK 6
1261 +
1262 +/* PERICFG */
1263 +#define CLK_PERIBUS_SEL 0
1264 +#define CLK_PERI_PWM1_PD 1
1265 +#define CLK_PERI_PWM2_PD 2
1266 +#define CLK_PERI_PWM3_PD 3
1267 +#define CLK_PERI_PWM4_PD 4
1268 +#define CLK_PERI_PWM5_PD 5
1269 +#define CLK_PERI_PWM6_PD 6
1270 +#define CLK_PERI_PWM7_PD 7
1271 +#define CLK_PERI_PWM_PD 8
1272 +#define CLK_PERI_AP_DMA_PD 9
1273 +#define CLK_PERI_MSDC30_1_PD 10
1274 +#define CLK_PERI_UART0_PD 11
1275 +#define CLK_PERI_UART1_PD 12
1276 +#define CLK_PERI_UART2_PD 13
1277 +#define CLK_PERI_UART3_PD 14
1278 +#define CLK_PERI_BTIF_PD 15
1279 +#define CLK_PERI_I2C0_PD 16
1280 +#define CLK_PERI_SPI0_PD 17
1281 +#define CLK_PERI_SNFI_PD 18
1282 +#define CLK_PERI_NFI_PD 19
1283 +#define CLK_PERI_NFIECC_PD 20
1284 +#define CLK_PERI_FLASH_PD 21
1285 +#define CLK_PERI_NR_CLK 22
1286 +
1287 +/* APMIXEDSYS */
1288 +#define CLK_APMIXED_ARMPLL 0
1289 +#define CLK_APMIXED_MAINPLL 1
1290 +#define CLK_APMIXED_UNIV2PLL 2
1291 +#define CLK_APMIXED_ETH1PLL 3
1292 +#define CLK_APMIXED_ETH2PLL 4
1293 +#define CLK_APMIXED_SGMIPLL 5
1294 +#define CLK_APMIXED_MAIN_CORE_EN 6
1295 +#define CLK_APMIXED_NR_CLK 7
1296 +
1297 +/* SSUSBSYS */
1298 +#define CLK_SSUSB_U2_PHY_1P_EN 0
1299 +#define CLK_SSUSB_U2_PHY_EN 1
1300 +#define CLK_SSUSB_REF_EN 2
1301 +#define CLK_SSUSB_SYS_EN 3
1302 +#define CLK_SSUSB_MCU_EN 4
1303 +#define CLK_SSUSB_DMA_EN 5
1304 +#define CLK_SSUSB_NR_CLK 6
1305 +
1306 +/* PCIESYS */
1307 +#define CLK_PCIE_P1_AUX_EN 0
1308 +#define CLK_PCIE_P1_OBFF_EN 1
1309 +#define CLK_PCIE_P1_AHB_EN 2
1310 +#define CLK_PCIE_P1_AXI_EN 3
1311 +#define CLK_PCIE_P1_MAC_EN 4
1312 +#define CLK_PCIE_P1_PIPE_EN 5
1313 +#define CLK_PCIE_P0_AUX_EN 6
1314 +#define CLK_PCIE_P0_OBFF_EN 7
1315 +#define CLK_PCIE_P0_AHB_EN 8
1316 +#define CLK_PCIE_P0_AXI_EN 9
1317 +#define CLK_PCIE_P0_MAC_EN 10
1318 +#define CLK_PCIE_P0_PIPE_EN 11
1319 +#define CLK_PCIE_NR_CLK 12
1320 +
1321 +/* ETHSYS */
1322 +#define CLK_ETH_FE_EN 0
1323 +#define CLK_ETH_GP2_EN 1
1324 +#define CLK_ETH_GP1_EN 2
1325 +#define CLK_ETH_GP0_EN 3
1326 +#define CLK_ETH_ESW_EN 4
1327 +#define CLK_ETH_NR_CLK 5
1328 +
1329 +/* SGMIISYS */
1330 +#define CLK_SGMII_TX_EN 0
1331 +#define CLK_SGMII_RX_EN 1
1332 +#define CLK_SGMII_CDR_REF 2
1333 +#define CLK_SGMII_CDR_FB 3
1334 +#define CLK_SGMII_NR_CLK 4
1335 +
1336 +#endif /* _DT_BINDINGS_CLK_MT7629_H */
1337 --
1338 2.21.0
1339
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